JP2003243389A - Semiconductor device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high reliability without causing any increase in the dielectric constant. <P>SOLUTION: An insulation film 8 of an insulation material containing no oxygen is formed selectively on a metallization 2 containing Cu buried in a trench 4 of an interlayer insulation film 3. The insulation material containing no oxygen is at least one kind selected from SiN or SiC. The fabrication method comprises a step for forming a metallization containing Cu by filling the trench of the interlayer insulation film with a metal containing Cu, and a step for forming an insulation film of an insulation material containing no oxygen selectively on the metallization containing Cu. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a metal wiring containing Cu and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an Al-based alloy has been used as a material for fine wiring of a high-density integrated circuit (hereinafter referred to as a semiconductor device) formed on a semiconductor wafer. However, as the wiring becomes finer, the parasitic resistance of the wiring
Since the circuit delay due to the parasitic capacitance becomes dominant, the use of Cu as a wiring material, which has lower resistance and lower capacitance than the Al-based alloy and realizes high reliability, is under study. Cu
Has a low specific resistance of 1.8 μΩcm, which is advantageous for speeding up a semiconductor device and has an electromigration resistance of A.
It is expected to be used as a next-generation material because it is one digit higher than the l-based alloy.

In the wiring formation using Cu, the so-called damascene method is used because dry etching of Cu is generally not easy. This is because, for example, a predetermined groove is formed in advance in an interlayer insulating film made of silicon oxide, a wiring material (Cu) is embedded in the groove, and then surplus wiring material is subjected to chemical mechanical polishing (Chemical Mechanical P
polishing: Hereinafter referred to as CMP. ), And a wiring is formed. Furthermore, the connection hole (V
There is also known a dual damascene method in which after the formation of (ia) and a wiring groove (Trench), the wiring material is embedded at once and the surplus wiring material is removed by CMP.

Since Cu is a material that is extremely easy to diffuse into the interlayer insulating film, a barrier film functioning as a Cu diffusion preventing film is formed in advance by coating the bottom and side walls of the groove, and then Cu is formed. And a wiring is formed by CMP.

By the way, Cu wiring is generally used in a multi-layered structure, but since there is no barrier film on the surface of the Cu wiring immediately after CMP, a cap functioning as a Cu diffusion preventing layer is formed before the upper layer wiring is formed. Form a film. At this time, since Cu is easily oxidized in an atmosphere containing oxygen even at a low temperature of 150 ° C.,
A silicon nitride film (SiN), a silicon carbide film (SiC), or the like, which is a material containing no oxygen, is formed on the surfaces of the Cu wiring and the interlayer insulating film and used as a cap film.

[0006]

However, since silicon nitride (SiN) and silicon carbide (SiC) have a larger relative dielectric constant than silicon oxide (SiO ₂ ), Cu
There is an inconvenience that the effective dielectric constant of the semiconductor device having the wiring becomes high and the RC delay of the semiconductor device becomes large. Therefore, for the Cu wiring surface after CMP,
A method of selectively coating with an alloy such as cobalt tungsten phosphorus (CoWP) is considered to be advantageous.

As a method for forming a cap film made of an alloy such as cobalt tungsten phosphorus (CoWP), there is, for example, an electroless plating method. As disclosed in US Pat. No. 5,695,810, cobalt tungsten is used with a Cu surface as a catalyst. A method of forming a cap film made of phosphorus (CoWP) has been proposed. In addition, JP-A-9-3072
As disclosed in Japanese Patent Laid-Open No. 34-34, a method has been proposed in which the Cu surface is replaced with palladium (Pd) by displacement plating with palladium (Pd), and electroless plating is performed using the substituted palladium (Pd) as a catalyst nucleus. ing.

However, although the cap film made of CoWP functions sufficiently as a Cu diffusion preventing film,
There is a problem of poor oxidation resistance. In particular, when an interlayer insulating film made of a material containing oxygen such as SiO ₂ or SiOC is formed in the next step, for example, in order to form an upper layer wiring on the Cu wiring to form a multi-layered wiring, the temperature is high. Therefore, the surface of the cap film made of CoWP is oxidized to generate cobalt oxide. The cobalt oxide generated as a result of the oxidation is present between the bottom of the via that connects to the Cu wiring in the upper layer and the Cu wiring in the lower layer, thereby increasing the via resistance and insulating the wiring from each other. This causes various problems such as a decrease in adhesion with the via and peeling between the cap film and the bottom of the via, which causes a great decrease in reliability of the semiconductor device.

Therefore, the present invention has been proposed in order to solve such a conventional problem, and a semiconductor device and a manufacturing method thereof which can realize high reliability without causing an increase in relative permittivity. The purpose is to provide.

[0010]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention is provided with an insulating material containing no oxygen on a metal wiring containing Cu embedded in a groove portion of an interlayer insulating film. The insulating film is formed selectively.

Further, in the method of manufacturing a semiconductor device according to the present invention, a metal containing Cu is embedded in the groove portion of the interlayer insulating film to form C.
a wiring forming step of forming a metal wiring containing u, and Cu
And an insulating film forming step of selectively forming an insulating film made of an insulating material containing no oxygen on the metal wiring containing.

In the semiconductor device as described above, since the insulating film made of the insulating material containing no oxygen is selectively formed on the metal wiring containing Cu, diffusion of Cu from the metal wiring containing Cu is prevented. In addition, oxidation of the metal wiring containing Cu, which is the base of the insulating film, is prevented.

Further, since this insulating film is selectively formed only on the metal wiring containing Cu, even if a material having a high relative dielectric constant is used as the insulating material containing no oxygen, it is effective by these. The increase in the dielectric constant is dramatically suppressed as compared with the conventional technology. Furthermore, when an insulating material containing no oxygen is formed on the entire surface of the semiconductor device, film stress is applied to the entire surface of the base, causing film peeling. However, in the present invention, it is selectively formed on the wiring containing Cu. Therefore, the film stress is reduced and the film peeling can be avoided.

Since the insulating film made of an insulating material containing no oxygen has hydrofluoric acid resistance, a hydrofluoric acid solution treatment for removing residual Cu atoms on the interlayer insulating film was performed in a later step. Even in the case, it does not disappear due to etching. Therefore, even when the hydrofluoric acid solution treatment is performed, it reliably functions as a diffusion preventing layer of Cu atoms into the interlayer insulating film.

[0015]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to the present invention will be described in detail below with reference to the drawings. It should be noted that the drawings used in the following description may show the characteristic parts in an enlarged manner in order to clearly show the characteristics of the respective parts, and the dimensional ratios of the respective members are not always the same as the actual ones. Absent. Further, in the following, the constitution and materials of each film constituting the semiconductor device will be exemplified, but the present invention is not limited to the exemplified semiconductor device, and the constitution of each film depending on a desired purpose or performance. You can select the material and material.

<First Embodiment> As shown in FIG. 1, for example, a semiconductor device targeted by the present invention has a device such as a transistor (not shown) formed on a substrate 1 in advance. A metal wiring (hereinafter, referred to as Cu wiring) 2 containing Cu is embedded in a groove portion 4 provided in the interlayer insulating film 3. A barrier film 6 having a Cu diffusion preventing function is formed between the side wall and the bottom of the groove 4, that is, between the Cu wiring 2 and the interlayer insulating film 3. Also, the substrate 1
An etch stopper film 7 made of, for example, SiN or SiC is formed on the upper surface of the etch stopper film 7, and Cu from the Cu wiring 2 to the substrate 1 is formed.
Prevent spread.

Further, in the semiconductor device of the present invention, the insulating film 8 made of an insulating material containing no oxygen is selectively formed on the Cu wiring 2. The insulating film 8 made of an insulating material containing no oxygen is made of at least one insulating material selected from, for example, SiN and SiC, and has an extremely excellent oxidation resistance and a Cu diffusion preventing function.

In the present invention, since the insulating film 8 is selectively formed on the Cu wiring 2, diffusion of Cu from the Cu wiring 2 is prevented. In addition, the insulating film 8 is also effective in preventing the oxidation of the Cu wiring 2 having extremely poor oxidation resistance.

Since the insulating film 8 is selectively formed only on the Cu wiring 2, a material having a high relative permittivity such as SiN or SiC (having a relative permittivity of respectively) is used as an insulating material containing no oxygen. 8 and 5),
Compared with the conventional technique in which these materials are formed as a cap film on the entire surface of the semiconductor device, an effective increase in the dielectric constant can be suppressed. As a result, it is possible to minimize the increase in RC delay of the semiconductor device.

Further, in a conventional semiconductor device in which an insulating material containing no oxygen is formed on the entire surface of the semiconductor device to form a cap film, film stress is applied to the entire surface of the underlayer, which causes film peeling. On the other hand, in the present invention, since the insulating film 8 made of an insulating material containing no oxygen is formed only on the Cu wiring 2, film stress is reduced,
The trouble of film peeling can be avoided.

By the way, the applicant of the present invention formed a pattern on the Cu wiring.
To prevent oxidation of the formed cap film made of CoWP
For this reason, in Japanese Patent Application No. 2000-224884,
Then, a cap film made of CoWP is formed on the Cu wiring.
After that, the surface of CoWP is SiH _Four, Si_TwoH₆To gas
Proposed a method of forming a CoSi film by exposure.
It However, the method of forming the CoSi film is
It has chemical resistance but does not have hydrofluoric acid (HF) resistance.
To remove residual Cu atoms on the interlayer insulating film,
When the F solution treatment is applied, it is the CoSi film or the lower layer.
The cap film made of CoWP disappears due to etching
Resulting in. As a result, C disappears due to the disappearance of the cap film itself.
Since it is impossible to prevent the diffusion of u, it is necessary to provide a hydrofluoric acid solution treatment.
Semiconductor devices cannot be manufactured in the manufacturing process
The inconvenience occurs.

However, according to the present invention, since the insulating film 8 made of an insulating material containing no oxygen has excellent hydrofluoric acid resistance, even when the hydrofluoric acid solution treatment is performed during the semiconductor device manufacturing process, the hydrofluoric acid resistance is improved. Therefore, it is not etched by the hydrofluoric acid solution. Accordingly, in this semiconductor device, the insulating film 8 does not disappear even when hydrofluoric acid (HF) solution treatment is included in the manufacturing process for the purpose of removing residual Cu atoms on the interlayer insulating film, for example. , Because it exerts a good Cu diffusion prevention function,
It is possible to realize a semiconductor device in which the diffusion of Cu is surely prevented.

A method of manufacturing the semiconductor device according to the present invention as described above will be described below.

<1> Etch stopper film forming step First, as shown in FIG. 2, CVD (Chem) is formed on the substrate 1.
The etch stopper film 7 is formed by depositing a material such as SiC, SiN or the like by the ICP method. As an example, a mixed gas of trimethylsilane and N ₂ O was used as a source gas, and a SiC film was formed to a thickness of 50 nm by the CVD method.

<2> Interlayer Insulating Film Forming Step Next, as shown in FIG. 3, an interlayer insulating film 3 made of, for example, SiOC is formed on the entire surface of the etch stopper film 7 by the CVD method. The film formation of the interlayer insulating film 3 can be performed in the same chamber following the film formation of the etch stopper film 7 which is the previous step. Further, as the interlayer insulating film 3, Si is used.
Not limited to OC, a known oxide such as SiO ₂ or an organic material such as a low dielectric constant material may be used. As an example, a mixed gas of trimethylsilane and NH ₃ was used as a raw material gas, and SiOC was formed to a film thickness of 500 nm by a CVD method following the film formation of the etch stopper film 7.

<3> Wiring Groove Forming Step Next, as shown in FIG. 4, the groove portion 4 for forming wiring in the interlayer insulating film 3 is patterned by photolithography and dry etching.

<4> Barrier Film and Cu Seed Film Forming Step Next, as shown in FIG. 5, a barrier film 6 made of, for example, TaN for preventing diffusion of Cu into the interlayer insulating film 3 is formed.
VD (Physical Vapor Deposition)
ion) method, and subsequently, a Cu seed film (not shown) is formed by the PVD method. As the barrier film 6, besides TaN, a material having an excellent barrier property against Cu such as Ta, TiN, and WN can be used. The Cu seed film serves as a conductive layer when Cu is formed by an electrolytic plating method in the next Cu embedding step. The barrier film 6 and the Cu seed film may be formed by the CVD method. The thickness of each film is preferably 50 nm or less for the barrier film 6 and 200 nm or less for the Cu seed film, although it depends on the design rule. As an example,
A barrier film 6 made of TaN was formed to a thickness of 30 nm, and a Cu seed film was formed to a thickness of 150 nm.

<5> Cu Embedding Step Next, as shown in FIG. 6, Cu is embedded by electrolytic plating to form a Cu wiring 2. In this Cu embedding step, the electrolytic plating method is widely adopted, but the present invention is not limited to this, and for example, the CVD method does not pose any problem. The film thickness varies depending on the depth of the groove portion 4, but as a guide, it is preferably 2.0 μm or less. As an example, the film formation amount was set to 1 μm.

<6> CMP polishing step Next, as shown in FIG. 7, Cu is left only in the groove portions 4. A commonly applied technique is polishing by CMP. In this step, it is necessary to finish the polishing on the surface of the interlayer insulating film 3 so that the wiring material is left only in the groove portion 4. Further, the polishing is controlled so that these wiring materials do not remain on the interlayer insulating film 3. It is preferable. In the polishing process by CMP, two or more kinds of materials of Cu and the barrier film must be removed by polishing, and therefore it is necessary to control the polishing liquid (slurry), polishing conditions, etc. depending on the material to be polished. Therefore, polishing in multiple steps may be necessary.

<7> Insulating Film Forming Step Next, as shown in FIG. 8, Cu wiring 2 and interlayer insulating film 3 are formed.
A film of, for example, SiC is formed on the entire surface of the substrate by the CVD method. In practice, a mixed gas of trimethylsilane and N ₂ O was used as a source gas, and the film was formed with a film thickness of 50 nm.

<8> Insulating Film Processing Step Next, the SiC film formed in the previous step is processed by photolithography and subsequent dry etching.
The processing pattern at this time is the same as the pattern of the groove portion 4 in the <3> wiring groove forming step. As a result, the insulating film 8 is selectively formed only on the groove portion 4, that is, on the Cu wiring 2.
Are left, and the semiconductor device as shown in FIG. 1 is obtained.

By repeating the above process, the via 9 and the upper Cu wiring 10 as shown in FIG. 9 are provided, and the upper surface of the upper Cu wiring 10 is selectively covered with the insulating film 8. Thus, a semiconductor device having multilayer wiring can be manufactured.

<Second Embodiment> Next, a second embodiment will be described. In the following, the same members as those described above will be denoted by the same reference numerals and detailed description thereof will be omitted.

The semiconductor device of the second embodiment is shown in FIG.
2, the cap film 11 having a Cu diffusion preventing function is selectively formed on the Cu wiring 2, and the insulating film 8 made of an insulating material containing no oxygen is selectively formed on the cap film 11. Has been done. That is, the semiconductor device of the second embodiment has a structure in which the cap film 11 is interposed between the Cu wiring 2 and the insulating film 8.

Here, as the cap film 11, a cobalt alloy or a nickel alloy can be used.
P, CoB, CoW, CoMo, CoWP, CoWB,
CoMoP, CoMoB, NiWP, NiWB, NiM
oP, NiMoB, etc. are mentioned. Moreover, the thing which alloyed both Co and Ni, the combination which alloyed both W and Mo, etc. can be mentioned. W or Mo to C
The effect of preventing Cu diffusion is increased by adding O or Ni. Further, Pd formed by displacement plating, silicide thereof (CoSi, NiSi, PdSi), or the like is also possible. Further, P and B, which are secondarily mixed in by the electroless plating, also form the deposited Co and Ni into a fine crystal structure and contribute to the Cu diffusion preventing effect.

In the semiconductor device shown in FIG. 10, since the insulating film 8 is selectively formed on the cap film 11, the cap film 11 is reliably prevented from being oxidized. Therefore, for example, when a wiring is further formed in the upper layer via the via, the adhesion between the via and the cap film 11 is deteriorated, or the oxidized cap film 11 increases the via resistance. The inconvenience resulting from the oxidation of 11 is avoided, and the reliability is improved.

Further, since the insulating film 8 is selectively formed only on the Cu wiring 2 and the cap film 11, a material having a high relative permittivity such as SiN or SiC (compared to the relative dielectric constant) is used as an insulating material containing no oxygen. The dielectric constants are 8 and 5, respectively.)
Even in the case of using, the effective increase in the dielectric constant can be suppressed as compared with the conventional technique in which these materials are formed as a cap film on the entire surface of the semiconductor device. As a result, the semiconductor device R
The increase in C delay can be minimized.

Further, in the conventional semiconductor device in which an insulating material containing no oxygen is formed on the entire surface of the semiconductor device to form the cap film, film stress is applied to the entire surface of the underlayer, which causes film peeling. On the other hand, in the present invention, since the insulating film 8 made of an insulating material containing no oxygen is formed only on the Cu wiring 2 and the cap film 11, the film stress is reduced and the problem of film peeling is reduced. It can be avoided.

Further, since the insulating film 8 made of an insulating material containing no oxygen has excellent hydrofluoric acid resistance, even when the hydrofluoric acid solution treatment is performed during the semiconductor device manufacturing process, the hydrofluoric acid resistance causes the hydrofluoric acid resistance. Does not etch with solution. As a result, in this semiconductor device, the insulating film 8 is protected even when a hydrofluoric acid (HF) solution treatment is included in the manufacturing process for the purpose of removing residual Cu atoms on the interlayer insulating film, for example, so that the cap film is protected. Since 11 does not disappear and a good Cu diffusion preventing function is exhibited, it is possible to realize a semiconductor device in which Cu diffusion is surely prevented.

Further, in the present embodiment, the cap film 1
Since 1 functions as a copper diffusion preventing layer of the Cu wiring 2, the film thickness of the insulating film 8 is improved in hydrofluoric acid resistance when a hydrofluoric acid solution treatment for removing residual Cu atoms on the interlayer insulating film 3 is performed. Can be realized, and can be set to 10 nm or less, for example. In particular, the thickness of the insulating film 8 is 5 nm or more and 10 nm
The following is preferable, and by setting it within this range, an effective increase in the dielectric constant of the semiconductor device can be suppressed. When the film thickness of the insulating film 8 is less than 5 nm, the hydrofluoric acid resistance becomes insufficient, and conversely, when the film thickness exceeds 10 nm, the dielectric constant may increase. By thus providing the cap film 11, the insulating film 8 made of an insulating material that does not contain oxygen can be made thinner, so that the effective dielectric constant is increased as compared with the semiconductor device described in the first embodiment. It can be drastically suppressed, and the effect of suppressing the increase in RC delay of the semiconductor device can be more reliably obtained.

A method of manufacturing the above semiconductor device will be described. First, as in the case of the above-described first embodiment, the process of <1> to <6> is performed, and
The Cu wiring 2 is embedded in the groove 4 as shown in FIG.

<9> Cap Film Forming Step Next, in order to remove the natural oxide film formed on the Cu wiring 2 after the polishing step by CMP, the cap film is treated with a weakly acidic aqueous solution such as 1% HF, and the like. As shown in FIG. 11, the cap film 11 is formed on the Cu wiring 2 by the electroless plating method. By adopting the electroless plating method, the cap film 11 can be selectively formed only on the Cu wiring 2.
The step of etching the cap film can be omitted. In order to form the cap film 11 on the Cu wiring 2 by the electroless plating method, the surface of the Cu wiring 2 must be subjected to a catalyst activation treatment using Pd, which is a metal having a high catalytic property. The pretreatment method is as follows.

(1) Degreasing treatment: Alkali degreasing improves the wettability of the surface.

(2) Acid treatment: Neutralize with 2-3% hydrochloric acid, etc., and at the same time remove oxidized Cu on the surface.

(3) Pd substitution treatment: The outermost surface of the metal wiring is substituted with Pd using a hydrochloric acid solution of PdCl ₂ to form a catalytically active layer. This is to use the difference in ionization tendency of dissimilar metals in displacement plating. Since Cu is an electrochemically base metal compared to Pd, the electrons emitted by dissolution in the solution are transferred to Pd, which is the noble metal in the solution, and Pd is formed on the Cu surface of the base metal. It Therefore, Pd is not replaced on the oxide film, for example, TEOS (tetraethoxysilane). The metal to be replaced may be platinum, gold, rhodium or the like. An example of conditions when Pd displacement plating is actually performed is shown below.

Treatment solution: PdCl ₂ aqueous solution, HCl Treatment time: 2 minutes Temperature: 30 ° C. pH: 1.3

(4) Pure water rinse

In the above pretreatment, (1) degreasing treatment and (2) acid treatment may be carried out as necessary. Further, as the treatment methods in the above (1) degreasing treatment, (2) acid treatment, and (3) Pd substitution treatment, there can be mentioned spin treatment using a spin coater, paddle treatment, and further dipping treatment. .

Next, a Co alloy film or Ni was formed on the surface to be plated which was catalytically activated by the above Pd by electroless plating.
An alloy film or the like is formed as the cap film 11. As described above, Pd of the catalyst activation layer is replaced only on the surface of Cu,
Electroless plating proceeds only where Pd is present.
Therefore, the cap film 11 can be selectively formed only on Cu (metal wiring).

<10> Insulating Film Forming Step Next, as shown in FIG. 12, SiC, for example, is formed on the entire surfaces of the cap film 11 and the interlayer insulating film 3 by the CVD method. In practice, trimethylsilane and N are used as raw material gases.
_A film having a thickness of 5 nm was formed using a mixed gas of ₂ O.

<12> Insulating Film Processing Step Next, the SiC film formed in the previous step is processed by photolithography and subsequent dry etching.
The processing pattern at this time is the same as the pattern of the groove portion 4 in the <3> wiring groove forming step. As a result, the insulating film 8 selectively remains only on the groove portion 4, that is, on the cap film 11, and the semiconductor device as shown in FIG. 10 is obtained.

By repeating the above process, the via 9 and the upper layer Cu as shown in FIG. 13 are obtained.
Insulating film 8 is selectively formed on cap film 11 which has wiring 10 and is formed on upper Cu wiring 10.
A semiconductor device with multi-layer wiring can be manufactured.

It should be noted that the present invention is not limited to the above description, and can be modified as appropriate without departing from the gist of the present invention. For example, the combination of the protective film and the interlayer insulating film is not limited to the above-mentioned combination of SiC / SiOC, but may be the combination of SiN / SiO ₂ . Further, as a material for forming the interlayer insulating film,
Other low dielectric constant materials may be used.

Further, either a damascene process or a dual damascene process can be applied to the wiring forming process.

[0055]

As is apparent from the above description, according to the present invention, since the insulating film made of the insulating material containing no oxygen is selectively formed on the metal wiring containing Cu, Cu
It is possible to provide a highly reliable semiconductor device in which Cu is surely prevented from diffusing from a metal wiring containing The insulating film made of an insulating material containing no oxygen is Cu
Since it is formed only on the metal wiring containing, it is possible to provide a semiconductor device in which an effective increase in the dielectric constant is suppressed and the RC delay is small.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of an essential part showing an example of a semiconductor device to which the present invention is applied.

FIG. 2 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device and showing an etch stopper film forming step.

FIG. 3 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device and showing an interlayer insulating film forming step.

FIG. 4 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device, showing a wiring groove forming step in an interlayer insulating film.

FIG. 5 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device, showing a step of forming a barrier film and a Cu seed film.

FIG. 6 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device and showing a Cu filling step.

FIG. 7 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device and showing a CMP polishing step.

FIG. 8 is a schematic cross-sectional view showing an example of a wiring forming process in a semiconductor device, showing an insulating film forming step.

FIG. 9 is a schematic cross-sectional view of an essential part showing an example of a semiconductor device having multilayer wiring to which the present invention is applied.

FIG. 10 is a schematic cross-sectional view of an essential part showing another example of the semiconductor device to which the present invention is applied.

FIG. 11 shows another example of the wiring forming process in the semiconductor device, and is a schematic cross-sectional view showing a cap film forming step.

FIG. 12 shows another example of the wiring forming process in the semiconductor device, and is a schematic cross-sectional view showing an insulating film forming step.

FIG. 13 is a schematic cross-sectional view of a main part showing another example of a semiconductor device having multilayer wiring to which the present invention is applied.

[Explanation of symbols]

1 substrate 2 Cu wiring 3 Interlayer insulation film 4 groove 6 Barrier film 7 Etch stopper film 8 insulating film 9 beer 10 Cu wiring 11 Cap film

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Segawa             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Hiroshi Horikoshi             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F term (reference) 5F033 HH07 HH11 HH15 HH21 HH32                       HH33 HH34 KK07 KK11 KK15                       KK21 KK32 KK33 KK34 MM01                       MM05 MM12 MM13 PP06 PP14                       PP27 PP28 QQ11 QQ25 QQ48                       RR01 RR04 RR06 SS01 SS03                       SS11 XX20 XX24 XX27 XX28

Claims (17)

[Claims] 1. A semiconductor device, wherein an insulating film made of an insulating material containing no oxygen is selectively formed on a metal wiring containing Cu embedded in a groove portion of an interlayer insulating film. 2. The insulating material containing no oxygen is Si
The semiconductor device according to claim 1, wherein the semiconductor device is at least one selected from N and SiC. 3. The semiconductor device according to claim 1, wherein a cap film having a Cu diffusion preventing function is selectively formed between the metal wiring containing Cu and the insulating film. 4. The semiconductor device according to claim 3, wherein the cap film is made of at least one selected from a Co alloy and a Ni alloy. 5. The Co alloy or Ni alloy is W, M
5. The semiconductor device according to claim 4, containing at least one selected from o, P, and B. 6. The insulating film having a thickness of 5 nm or more and 10 nm
The semiconductor device according to claim 3, wherein: 7. The second interlayer insulating film made of a material containing oxygen is further formed on the insulating film made of an insulating material containing no oxygen.
The semiconductor device described. 8. The semiconductor device according to claim 7, wherein the semiconductor device is a multi-layer wiring having a via and a metal wiring buried in the groove of the second interlayer insulating film. 9. A wiring forming step of forming a metal wiring containing Cu by burying a metal containing Cu in a groove portion of an interlayer insulating film, and selecting an insulating film made of an insulating material containing no oxygen in the metal wiring containing Cu. A method of manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the insulating film forming step, the insulating film is formed by photolithography and etching an insulating material containing no oxygen. 11. The oxygen-free insulating material is S
10. The method for manufacturing a semiconductor device according to claim 9, wherein the method is at least one selected from iN and SiC. 12. The manufacturing of a semiconductor device according to claim 9, wherein a cap film having a Cu diffusion preventing function is selectively formed between the metal wiring containing Cu and the insulating film. Method. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the cap film is made of at least one selected from a Co alloy and a Ni alloy. 14. The Co alloy or Ni alloy is W, M
14. The method of manufacturing a semiconductor device according to claim 13, further comprising at least one selected from o, P and B. 15. The insulating film having a thickness of 5 nm or more and 10 n or more.
13. The method for manufacturing a semiconductor device according to claim 12, wherein the number is m or less. 16. A second layer formed of a material further containing oxygen on the insulating film formed of an insulating material not containing oxygen.
10. The method for manufacturing a semiconductor device according to claim 9, wherein the interlayer insulating film is formed. 17. The method of manufacturing a semiconductor device according to claim 16, wherein a via and a metal wiring are formed in the second interlayer insulating film to form a multilayer wiring.