JP2003139820A - Multi-chip module and its inter-chip connection test method - Google Patents

Abstract

(57) [Problem] To determine the quality of connection between chips of common wiring in a chip-on-chip type multi-chip module.
Do it more easily. SOLUTION: First and second semiconductor chips 10, 20
Are electrically connected to each other via a connection pad 15 and a conductive connection member 16. First
The external input / output pads 11 of the first semiconductor chip 10
The second external input / output pad 12 is connected to the common wiring 13 through the connection pad 15 and the connection member 16.
It is connected to the common wiring 14 of the second semiconductor chip 20.
However, the first and second external input / output pads 11, 12
Are not connected to each other in the first semiconductor chip 10. The first and second external input / output pads 11, 1
By applying a probe to 2 and measuring the impedance between its pads, the quality of the connection between chips between the common wirings 13 and 14 is determined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module configured by electrically connecting connection pads to a plurality of semiconductor chips, and a chip-to-chip connection test method therefor. Particularly, when a common wiring such as a power wiring exists in each semiconductor chip, the present invention relates to a connection test configuration and method between the common wirings.

[0002]

2. Description of the Related Art In recent years, the concept of a one-chip system LSI having a plurality of functions formed on a common substrate has been proposed, and various proposals have been made as a method for designing such a system LSI. Especially 1-chip system LS
The advantage of I is that a high-performance and multi-functional device can be realized by integrating various functional components such as memories such as DRAM and SRAM, logic circuits, analog circuits, etc. in one semiconductor chip. However, such a system LSI faces the following problems in forming a device.

The first problem is that increasing the scale of the system LSI requires more development power, and the manufacturing yield decreases as the chip area increases, so that the manufacturing cost of the device increases. is there.

The second problem is that it is difficult to match the manufacturing process of a different device such as a DRAM or FLASH memory with the manufacturing process of pure CMOS, and the manufacturing process is started up at the same time as the manufacturing process of pure CMOS. Is very difficult. Therefore, the manufacturing process for mounting different types of devices is delayed from the development of the most advanced pure CMOS manufacturing process by about 1 to 2 years, so that it is impossible to supply and supply the products in a timely manner according to the market needs.

In order to deal with each of the above problems, for example, Japanese Patent Laid-Open No. 58-92230 proposes a chip-on-chip type system LSI configured by modularizing a plurality of semiconductor chips. This chip-on-chip type multi-chip module technology includes a connection pad electrode provided on the upper surface of a bonding semiconductor chip (hereinafter, referred to as a parent chip), and a bonding target semiconductor chip (hereinafter, a child chip). (Referred to as)) is formed on the bump with a connection pad electrode provided on the upper surface, and the connection pad electrodes are bonded to each other between the two chips to electrically connect the semiconductor chips to each other to thereby form a plurality of semiconductor chips. This is a technology for modularizing one into one.

This chip-on-chip type system LSI
Since the functions are distributed over a plurality of semiconductor chips as compared with the one-chip system LSI, each semiconductor chip can be downsized and the yield of each semiconductor chip can be improved. Further, even different types of devices having different process generations can be easily modularized, so that it becomes possible to have multiple functions. In addition, compared to other multi-module technologies, system LSIs based on chip-on-chip multi-chip module technologies require extremely short wiring lengths for the interface between parent and child chips, enabling high-speed interfaces. It is possible to realize the same performance as the inter-block interface in the conventional 1-chip system LSI.

[0007]

However, the above-described chip-on-chip type multi-chip module technology is an important technology that replaces the conventional one-chip system LSI, but has the following problems.

That is, with the spread of chip-on-chip type multi-chip module technology in the future, it is expected that the manufacturer of semiconductor chips and the mounter who carries out multi-chip module mounting will be different. In the conventional test method, that is, the total function test for judging the quality of the entire multi-chip module, it is not possible to judge whether it is an internal failure of the semiconductor chip or a failure due to a connection failure between the semiconductor chips in the mounting process, and the mutual contractor The responsibility between them cannot be clarified. Therefore, in the future, it is desired to propose a connection test configuration for easily and inexpensively performing the quality determination in the mounting process, that is, the quality determination of the connection between the semiconductor chips.

Conventionally, an example of a connection test between semiconductor chips is disclosed in Japanese Patent Laid-Open No. 2000-258494. The operation will be described with reference to FIG. This figure shows a chip-on-chip type multi-chip module 100 configured by connecting a first semiconductor chip 110 and a second semiconductor chip 120 via an anisotropic conductive film P1.

In the above publication, the multi-chip module 1
00, for example, the wiring pad of the semiconductor chip 110
A wiring pad connected to the wiring pad C1-1 of the semiconductor chip 110 in order to inspect an electrical connection state by the anisotropic conductive film P1 between C1-1 and the wiring pad C1-2 of the other semiconductor chip 120. C2-1 is newly provided, and the newly provided wiring pad C2 is provided on the semiconductor chip 120.
-1 is newly provided with a wiring pad C2-2, and the original wiring pad C1-2 of the semiconductor chip 120 and the newly provided wiring pad C2-2 are respectively provided as connection pads B.
1, B2 and bonding wires W1, W2 to connect to external terminals (probe inspection pads) T1, T2. Then, when inspecting the connection state by the anisotropic conductive film P1, the quality of the electrical connection state is determined by measuring the impedance between the external terminals T1 and T2.

However, in the above-mentioned conventional configuration, in order to judge the quality of the connection between the two connection pads C1-1 and C1-2 at one place at most, the two connection pads C2-1,
C2-2 is required and 2 for further probing inspection
Requires individual probe test pads T1, T2. In general, the probe inspection pad is extremely large in comparison with the area of the chip-on-chip type connection pad, and if the number of signals between chips is several hundred to several thousand, the probe inspection pad has the conventional structure. Since the number of pads for use requires twice the number of signals between chips, the present technology can no longer be applied due to the problems of an increase in the area of the probe inspection pad and the complexity of the probing inspection device.

Further, in the case of inspecting the electrical connection state between the individual independent connection pads, the conventional inspection method as described above can be adopted. For example, common use is made between parent and child chips. Regarding the common wiring such as the power supply wiring, the connection state cannot be easily inspected and determined by the above-described conventional techniques. Because such common wiring is common in the parent and child chips, as the name implies,
For example, if a probe inspection pad cannot be specially provided on the child chip, even if two probe inspection pads are provided on the parent chip side, both probe inspection pads will have one common wiring in the parent chip. This is because there is a case where it is not possible to inspect the electrical connection between the parent and child chips of the common wiring.

The present invention has been made in view of the above problems, and an object thereof is to provide a multi-chip module capable of judging the quality of electrical connection between semiconductor chips without increasing the area of each semiconductor chip, and the same. It is to provide a connection test method between semiconductor chips, and particularly to provide an inter-chip connection test method for common wirings such as power supply wirings provided in at least two semiconductor chips.

[0014]

In order to achieve the above object, according to the present invention, two special pads are provided on one semiconductor chip, and a common wiring of the two semiconductor chips is provided between the two pads. Form a state in which they are electrically connected through the pads for connecting the chips and the conductive connecting member.

That is, a multi-chip module according to a first aspect of the present invention includes a plurality of semiconductor chips having a plurality of connecting pads, and the connecting pads are electrically connected between the semiconductor chips via a conductive connecting member. Of the plurality of semiconductor chips, the first and second semiconductor chips each have a common wiring, and the common wiring of the first semiconductor chip is a common wiring. And the common wiring of the second semiconductor chip are mutually connected through a plurality of the connection pads,
At least the first and second semiconductor chips are provided on the first semiconductor chip.
External input / output pads are provided, the first external input / output pads are connected to a common wiring of the first semiconductor chip, and the second external input / output pads are at least one for connection. The first external input / output pad and the second external input / output pad are connected to each other in the common wiring of the second semiconductor chip via a pad, and are connected to each other in the first semiconductor chip. It is not characterized.

The invention according to claim 2 is the multichip module according to claim 1, characterized in that the first and second common wirings are power wirings or ground wirings.

Further, the invention according to claim 3 is the multi-chip module according to claim 1 or 2, wherein the first and second external input / output pads are the first and second semiconductor chips. The common wirings are connected to each other when the connection between the chips is good.

In addition, an inter-chip connection test method for a multi-chip module according to a fourth aspect of the present invention is the inter-chip connection test method for a multi-chip module according to the first aspect, wherein the first and second An impedance between the first external input / output pad and the second external input / output pad is measured when determining whether the connection between the common wirings of the semiconductor chips is good or bad.

As described above, in the invention described in claims 1 to 4, the first and second semiconductor chips include common wirings, and the common wirings are connected to each other through the connection pad and the conductive connection member. In this case, the first external input / output pad connected to the common wiring of the first semiconductor chip is connected to the common wiring of the second semiconductor chip through the connection pad and the conductive connecting member. Since the second external input / output pads that are present are not connected in the first semiconductor chip, the first and second semiconductor chip pads are connected between the first and second external input / output pads. Both common wirings are connected via the connecting pad and the conductive connecting member which connect them to each other. Therefore, by measuring the impedance between the first and second input / output pads, it is possible to determine the quality of the electrical connection state between the common wirings of the first and second semiconductor chips. Become.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows the overall structure of a chip-on-chip type multi-chip module according to a first embodiment of the present invention. The figure shows an example of a configuration in which two semiconductor chips each have a common wiring.

In FIG. 1, 10 is a first semiconductor chip and 20 is a second semiconductor chip. Each of the first and second semiconductor chips 10 and 20 has an internal circuit 17. The internal circuit 17 of the first semiconductor chip 10 is provided with the common wiring 13, and the internal circuit 17 of the second semiconductor chip 20 is provided with the common wiring 14. The common wirings 13 and 14 of the first and second semiconductor chips 10 and 20 are, for example, power supply wirings. The common wirings 13 and 14 may be ground wirings or common signal wirings.

The first and second semiconductor chips 10 and 2
0 has a large number of connection pads 15 respectively, and the large number of connection pads 15 are connected to each other by a conductive connection member 16 formed of, for example, a solder bump or the like, and the first and second semiconductor chips 10 are connected. , 20 are electrically connected to form a multi-chip module. In the figure, the common wiring 13 of the first semiconductor chip 10 and the common wiring 14 of the second semiconductor chip 20 are connected to each other by five connection pads 15.
And electrically connected to each other via the conductive connecting member 16.

The first semiconductor chip 10 has a first external input / output pad 11 arranged at the left end in the drawing, and a second external input / output pad 12 arranged at the right end in the drawing.
The first external input / output pad 11 is connected to the common wiring 13 of the first semiconductor chip 10. Meanwhile, the second
The external input / output pad 12 of the wiring 18 and the connecting pad 15 and the conductive connecting member 1 arranged at the right end in the figure.
It is electrically connected to the common wiring 14 of the second semiconductor chip 20 via 6. As can be seen from FIG. 1, a first external input / output pad 11 and a second external input / output pad 12
And are not electrically connected to each other in the first semiconductor chip 10.

In the present embodiment, the common wiring 13 in the first semiconductor chip 10 connected to the first external input / output pad 11 and the wiring connected to the second external input / output pad 12 are connected. 18 is not connected in the first semiconductor chip 10. With such a configuration, the common wiring 13 of the first semiconductor chip 10 and the second semiconductor chip 20 are provided between the first external input / output pad 11 and the second external input / output pad 12. The common wiring 14, the connection pad 15 and the conductive connection member 16 connecting them are always present.

Therefore, the common wiring 1 of each of the semiconductor chips 10 and 20 of the chip-on-chip type multi-chip module
When conducting an electrical connection test between chips 3 and 14,
As shown in FIG. 2, a probe 19 is applied to each of the first and second external input / output pads 11 and 12, and the impedance between the pads 11 and 12 is measured. It is possible to test the quality of the connection state between chips of each other.

When performing the chip-to-chip connection test between the common wirings 13 and 14 as described above, an appropriate voltage is applied between the first external input / output pad 11 and the second external input / output pad 12. It is possible to measure the impedance by applying and measuring the flowing current.

Further, when the multichip module shown in FIG. 1 is normally operated, the first and second external input / output pads 11 and 12 have the same potential terminal in the multichip module. External input / output pad 1
The 1 and 12 may be connected to each other outside the multichip module. Therefore, if the inter-chip connection state is good after the chip-to-chip connection state pass / fail test, if the first and second external input / output pads 11 and 12 are connected outside the multi-chip module, The effect that the total impedance of the common wirings 13 and 14 is lowered is produced. Therefore, the second external input / output pad 12 has an effect that it can be used effectively not only during the quality determination test of the inter-chip connection state but also after the test.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
An embodiment will be described. FIG. 3 shows the overall configuration of the chip-on-chip type multi-chip module of this embodiment.

In the figure, the second semiconductor chip of the first semiconductor chip 10 is
The wiring 18 connected to the external input / output pad 12 of
The common wiring 14 of the semiconductor chip 20 is a plurality of (three in the figure) connecting pads 15 and conductive connecting members 16.
It illustrates the case where they are connected via. Also in this case, the wiring 18 connected to the second external input / output pad 12 and the common wiring 13 are not electrically connected in the first semiconductor chip 10,
Similar to the first embodiment, it is possible to perform a pass / fail judgment test of the electrical connection between the chips of the common wirings 13 and 14.

Further, after the quality judgment test of the electrical connection between the chips, the first and second external input / output pads 11 and 1 are provided.
If the two are connected outside the multi-chip module, the effect of lowering the total impedance of the common wirings 13 and 14 is produced, and the second external input / output pad 12 is used for a pass / fail judgment test of the electrical connection between the chips. It can be used effectively after testing instead of just using it.

As described above, in the chip-on-chip type multi-chip module in which the common wirings 13 and 14 exist between the semiconductor chips 10 and 20, it is judged whether the common wirings 13 and 14 are connected to each other or not. Since the test for performing the measurement can be performed by measuring the impedance between the first external input / output pad 11 and the second external input / output pad 12, the number of probing pads required for the measurement is 2 Very few as individual. Therefore, the semiconductor chip 1
There is almost no increase in the area of 0 or 20. Moreover, the probing pads 11 and 12 used in the pass / fail judgment test of the inter-chip connection of the common wirings 13 and 14 can be used as they are in actual use. Furthermore, since this is a simple test method in which the impedance between the two external input / output pads 11 and 12 is measured, there is an effect that the time and test cost required for the chip-to-chip connection test of common wires can be made extremely small.

In the above description, the multi-chip module is composed of the two semiconductor chips 10 and 20, but the present invention is not limited to this, and the multi-chip module is composed of three or more semiconductor chips. Of course, it is okay. In this case, for at least two semiconductor chips among those semiconductor chips, the first
Alternatively, it suffices to have the configuration of the second embodiment.

[0034]

As described above, according to the multi-chip module and the inter-chip connection test method of the present invention, the common wirings of the semiconductor chips can be connected to each other without increasing the area of the semiconductor chips. There is an effect that it is possible to determine the quality of the connection between chips.

[Brief description of drawings]

FIG. 1 is a sectional view showing a circuit configuration of a chip-on-chip type multi-chip module according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state during a quality determination test of an electrical connection state between common wirings of the multi-chip module.

FIG. 3 is a sectional view showing a circuit configuration of a chip-on-chip type multi-chip module according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a connection test configuration of a conventional chip-on-chip type multi-chip module.

[Explanation of symbols]

10 First semiconductor chip 20 Second semiconductor chip 11 First external input / output pad 12 Second external input / output pad 13, 14 Common wiring 15 pad for connection 16 connection bumps 17 Internal circuit 18 connection wiring 19 probes

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masayoshi Kinoshita             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 2G014 AA01 AB59 AC18                 2G132 AA14 AD15 AK07 AL09

Claims (4)

[Claims] 1. A multi-chip module comprising a plurality of semiconductor chips having a plurality of connecting pads, wherein the connecting pads are electrically connected to each other between the semiconductor chips via a conductive connecting member. A common wiring is provided in each of the first and second semiconductor chips of the plurality of semiconductor chips, and the common wiring of the first semiconductor chip and the common wiring of the second semiconductor chip are different from each other. Connected to each other via a plurality of the connection pads, and at least the first and second semiconductor chips are provided on the first semiconductor chip.
External input / output pads are provided, the first external input / output pads are connected to a common wiring of the first semiconductor chip, and the second external input / output pads are at least one for connection. The first external input / output pad and the second external input / output pad are connected to each other via the pad to the common wiring of the second semiconductor chip, and are connected to each other in the first semiconductor chip. Multi-chip module characterized by not being. 2. The multichip module according to claim 1, wherein the first and second common wirings are power wirings or ground wirings. 3. The first and second external input / output pads are connected to each other when common interconnection between the common wirings of the first and second semiconductor chips is good. The multichip module according to claim 1 or 2, characterized in that: 4. The inter-chip connection test method for a multi-chip module according to claim 1, wherein in determining whether the inter-chip connection between common wires of the first and second semiconductor chips is good or bad, An inter-chip connection test method for a multi-chip module, which comprises measuring an impedance between an external input / output pad and the second external input / output pad.