JP2003133712A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JP2003133712A JP2003133712A JP2001322657A JP2001322657A JP2003133712A JP 2003133712 A JP2003133712 A JP 2003133712A JP 2001322657 A JP2001322657 A JP 2001322657A JP 2001322657 A JP2001322657 A JP 2001322657A JP 2003133712 A JP2003133712 A JP 2003133712A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- solder resist
- resist layer
- layer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体素子および
受動素子を実装するための回路基板に関する。
【０００２】
【従来の技術】従来、半導体素子や受動素子を実装する
ための回路基板は、セラミック等からなる絶縁基板の上
下主面に形成される回路パターンの電気的導通を取るた
めにビアホール，スルーホール等の貫通導体が設けられ
る。この貫通導体は、例えば一般に以下の３種類の方法
により形成される。
【０００３】（１）セラミック等の絶縁基板を焼結させ
る前に、セラミックグリーンシート状態で貫通孔を設
け、この貫通孔に金属ペーストを注入して同時焼結させ
る同時焼結法。
【０００４】（２）セラミック等の絶縁基板を焼結後、
レーザ法またはブラスト法等によって貫通孔を形成し、
その後導電性ペースト等を貫通孔に注入し、熱硬化させ
る導電性ペースト法。
【０００５】（３）セラミック等の絶縁基板を焼結後、
レーザ法またはブラスト法等によって貫通孔を形成し、
その後絶縁基板の両主面にスパッタリング法、メッキ法
等により導電性の薄膜を成膜することで、貫通孔の内面
の薄膜を介して両主面の電気的導通を取るオープンホー
ル法。
【０００６】また、従来、半導体素子をフリップチップ
法により実装する回路基板には、上記（１）の同時焼結
法または（２）の導電性ペースト注入法により形成され
た貫通導体が用いられてきた。それは、（３）のオープ
ンホール法にて形成した回路基板の場合、貫通孔の内面
の薄膜を介して両主面の導通を取っており、貫通孔内に
何も埋め込まれていないため、回路基板を半導体素子収
納用パッケージ（以下、半導体パッケージという）等に
半田等によって実装した際、下側主面の余分な半田が貫
通孔を通って上側主面に這い上がり、上側主面の回路パ
ターンをショートさせるという問題を起こしやすいため
である。
【０００７】近年、半導体素子のファインピッチ化、即
ち電極間隔や配線間隔の微細化が進み、半導体素子を実
装する回路基板に対してもファインピッチ化が求められ
るようになってきた。
【０００８】
【発明が解決しようとする課題】しかしながら、上記従
来の（１）の同時焼結法によって形成した回路基板の場
合、セラミックグリーンシートの状態で貫通孔を形成
し、金属ペーストを印刷した後焼結させるため、この焼
結により絶縁基板が収縮する。従来、この収縮を見込ん
でセラミックグリーンシートを製品としての絶縁基板よ
りも大きく形成していたが、焼結による収縮にバラツキ
が生じるため、電極や配線の設計値からの位置ずれ、電
極間隔や配線間隔の設計値からのずれが生じて、ファイ
ンピッチ化が困難であるという問題があった。
【０００９】また、従来の（２）の導電性ペースト注入
法によって形成した回路基板の場合、ファインピッチ化
させるために貫通孔の径を小さくすると、貫通孔のアス
ペクト比（絶縁基板の厚みに対する貫通孔の径の比）が
小さくなり、導電性ペーストが貫通孔に入りにくくな
り、導通不良を起こしやすいという問題があった。さら
に、貫通孔に導電ペーストが完全に埋まってないと、貫
通孔の導体内に空隙が発生し、その空隙がその後の熱工
程等で膨張して貫通導体の導体に膨れが発生するという
問題があった。
【００１０】従って、本発明は上記事情に鑑みて完成さ
れたものであり、その目的は、ファインピッチ化された
半導体素子をフリップチップ法によって実装できる回路
基板を提供することにある。
【００１１】
【課題を解決するための手段】本発明の回路基板は、絶
縁基板の主面に形成された回路パターンと、該回路パタ
ーンの電極パッドに設けられた導体バンプと、前記回路
パターン内に設けられ、太さが０．５ｍｍ以下の貫通孔
の内面に導体層が形成された貫通導体とを具備して成
り、前記回路パターンに前記導体バンプを介して半導体
素子および受動素子が電気的に接続される回路基板であ
って、前記半導体素子に接続される前記導体バンプはそ
の周囲にＣｒ，Ｔｉ，Ｔａおよびこれらの窒化物のうち
の少なくとも一種から成る第一の半田レジスト層が形成
され、前記受動素子に接続される前記導体バンプはその
周囲に前記第一の半田レジスト層およびその上に積層さ
れた樹脂から成る第二の半田レジスト層が形成されてお
り、前記貫通導体は前記導体層上に前記第一の半田レジ
スト層および前記第二の半田レジスト層が順次積層され
ていることを特徴とする。
【００１２】本発明は、上記の構成により、貫通導体は
貫通孔の内面に導体層が形成されその導体層を介して絶
縁基板の上下主面の回路パターンが導通されるスルーホ
ールとなっているため、貫通孔は焼結後の絶縁基板にレ
ーザ法やブラスト法等により形成することができ、その
結果、位置精度が良く微小な径の貫通孔を形成すること
ができる。即ち、ファインピッチ化された半導体素子を
実装するのに好適な回路基板となる。
【００１３】また、半導体素子と電気的に接続される導
体バンプは、その周囲にＣｒ，Ｔｉ，Ｔａおよびこれら
の窒化物のうちの少なくとも一種から成る第一の半田レ
ジスト層が形成されているため、導体バンプの周囲から
半田が流れ出さず、導体バンプを確実に半導体素子に接
続することができ、また間隔の狭い隣接する導体バンプ
同士が短絡するのを防ぐことができるため、ファインピ
ッチ化された半導体素子をフリップチップ法によって正
確に実装することができる。また、第一の半田レジスト
層を形成した後に導体バンプを形成することができ、そ
の場合、第一の半田レジスト層によって囲まれる、導体
バンプが形成される面積を一定にすることで、半田の表
面張力により導体バンプの高さを一定に保つことができ
る。
【００１４】さらに、受動素子に接続される導体バンプ
は、その周囲に第一の半田レジスト層とその上に積層さ
れた樹脂から成る第二の半田レジスト層が形成されてい
るため、受動素子を強固に接続するための大きな導体バ
ンプの半田が周囲に流れ出さす、回路パターンがショー
トすることを防ぐことができる。
【００１５】加えて、貫通導体は、その内面の導体層上
に第一の半田レジスト層および第二の半田レジスト層が
順次積層されているため、回路基板を半導体パッケージ
等に収容し半田等によって実装した際、下側主面の余分
な半田等が貫通導体を通って上側主面に這い上がること
を防ぐことができる。
【００１６】
【発明の実施の形態】本発明の回路基板について以下に
詳細に説明する。図１（ａ）は本発明の回路基板の平面
図、図１（ｂ）は（ａ）のＡ−Ａ’線における断面図で
ある。同図において、１はセラミックス等からなる絶縁
基板、２は絶縁基板１に設けられたスルーホールタイプ
の貫通導体、３は複数の導電性の薄膜を積層して成る回
路パターン、４は回路パターン３の電極パッドに形成さ
れた導体バンプ、５は導体バンプ４の周囲に形成された
Ｃｒ，Ｔｉ，Ｔａおよびこれらの窒化物のうちの少なく
とも一種から成る第一の半田レジスト層、６は第一の半
田レジスト層５の上に積層された樹脂から成る第二の半
田レジスト層である。７は半導体素子が実装される領
域、８は抵抗素子，コンデンサ素子，インダクタ素子等
の受動素子が実装される領域を示す。
【００１７】本発明の回路基板は、絶縁基板１の主面に
形成された回路パターン３と、回路パターン３の電極パ
ッドに設けられた導体バンプ４と、回路パターン３内に
設けられ、太さが０．５ｍｍ以下の貫通孔の内面に導体
層が形成された貫通導体２とを具備して成り、回路パタ
ーン３に導体バンプ４を介して半導体素子および受動素
子が電気的に接続されるものである。そして、半導体素
子に接続される導体バンプ４はその周囲にＣｒ，Ｔｉ，
Ｔａおよびこれらの窒化物のうちの少なくとも一種から
成る第一の半田レジスト層５が形成され、受動素子に接
続される導体バンプ４はその周囲に第一の半田レジスト
層５およびその上に積層された樹脂から成る第二の半田
レジスト層６が形成されており、貫通導体２は導体層上
に第一の半田レジスト層５および第二の半田レジスト層
６が順次積層されている。
【００１８】本発明の絶縁基板１は、酸化アルミニウム
（Ａｌ2Ｏ3）質焼結体、ムライト（３Ａｌ2Ｏ3・２Ｓｉ
Ｏ2）質焼結体、窒化アルミニウム（ＡｌＮ）質焼結
体、炭化珪素（ＳｉＣ）質焼結体、ガラスセラミック焼
結体等のセラミック焼結体から成る。例えば、酸化アル
ミニウム質焼結体から成る場合、酸化アルミニウム、酸
化珪素（ＳｉＯ2）、酸化マグネシウム（ＭｇＯ）、酸
化カルシウム（ＣａＯ）等の原材料粉末に適当な有機溶
剤、溶媒を添加混合して泥漿状と成し、これをドクター
ブレード法等によってセラミックグリーンシートを形成
し、しかる後、セラミックグリーンシートに適当な打ち
抜き加工を施し、所定の形状と成して約１６００℃程度
の高温で焼成することによって製作される。
【００１９】絶縁基板１に設けられる貫通導体２を成す
貫通孔は、回路基板の回路パターン３の配線や電極のフ
ァインピッチ化のためにその太さ（貫通孔の断面形状が
円形の場合は直径に相当）は０．５ｍｍ以下が必要であ
り、炭酸ガスレーザやＹＡＧレーザ等を用いたレーザ法
や、サンドブラスト法等によって形成される。貫通孔の
太さは小さいほどよいが、１０μｍ未満では、貫通孔を
形成する際に除去されるべき絶縁基板１の部位が十分に
除去できなくなり、貫通孔が未開通の状態になりやすい
ので、１０μｍ以上とするのがよい。なお、貫通孔の断
面形状は円形、楕円形、多角形等の種々の形状とし得
る。
【００２０】また、貫通導体２を成す貫通孔の内面に形
成される導体層および回路パターン３は、例えば密着金
属層、拡散防止層および主導体層を順次積層させた３層
構造を有している。
【００２１】密着金属層は、Ｔｉ，Ｃｒ，Ｔａ，Ｎｂ，
Ｔａ2Ｎ，Ｎｉ−Ｃｒ合金等のうち少なくとも１種より
成るのがよく、蒸着法、スパッタリング法、イオンプレ
ーティング法等の薄膜形成法により被着され、フォトリ
ソグラフィ法により所定のパターンに形成される。密着
金属層の厚さは０．０１〜０．２μｍ程度が良く、０．
０１μｍ未満では、絶縁基板１の表面に強固に被着する
ことが困難となり、０．２μｍを超えると、成膜時の内
部応力によって剥離が生じ易くなる。
【００２２】拡散防止層は、Ｐｔ，Ｐｄ，Ｒｈ，Ｒｕ，
Ｎｉ，Ｎｉ−Ｃｒ合金，Ｔｉ−Ｗ合金等のうち少なくと
も１種より成るのがよく、その厚さは０．０５〜１μｍ
程度が好ましい。０．０５μｍ未満では、ピンホール等
の欠陥が発生して拡散防止層としての機能を果たし難く
なり、１μｍを超えると、成膜時の内部応力によって剥
離が生じ易くなる。また、回路基板が熱負荷の小さい状
態（５０℃以下の環境温度）で使用される場合は、拡散
防止層を設けなくてもよい。
【００２３】主導体層は、Ａｕ，Ａｇ，Ｃｕ等のうち少
なくとも１種より成るのがよく、その厚さは０．１〜５
μｍ程度がよい。０．１μｍ未満では、電気抵抗が大き
くなる傾向にあり、５μｍを超えると、成膜時の内部応
力により剥離を生じ易くなる。また、Ｃｕを用いる場合
は、表面酸化防止のためにメッキ法によりＮｉ層とＡｕ
層を順次形成するのがよい。
【００２４】貫通導体２の導体層および回路パターン３
としてＡｌを用いる場合は、上記のような３層構造では
なく、１層のみで形成することが可能である。Ａｌの厚
さは０．１〜５μｍ程度がよく、０．１μｍ未満では電
気抵抗が大きくなる傾向にあり、５μｍを超えると成膜
時の内部応力により剥離を生じ易くなる。
【００２５】導体バンプ４は、印刷法、めっき法、また
はスーパーソルダー法と呼ばれる有機溶剤中に半田を溶
解させた導体ペーストを被着させる方法等で形成され
る。導体バンプ４としては、Ｐｂ−Ｓｎ共晶半田が用い
られるが、Ｐｂは環境汚染の問題があるため、Ｐｂフリ
ーのＳｎ−Ａｇ半田、Ｓｎ−Ａｇ−Ｂｉ半田等を用いる
のが好ましい。
【００２６】導体バンプ４の周囲に形成されるＣｒ，Ｔ
ｉ，Ｔａおよびこれらの窒化物のうちの少なくとも一種
から成る第一の半田レジスト層５は、フォトリソグラフ
ィ法およびエッチング法によって精度よくパターン形成
されるため、その後形成する導体バンプ４形成用の半田
が流れ出さず、半田レジスト層５との界面で表面張力が
働くため、導体バンプ４の大きさおよび高さを一定にす
ることができる。第一の半田レジスト層５は、例えば密
着金属層と同様の金属からなり、その厚みも密着金属層
と同様である。
【００２７】樹脂からなる第二の半田レジスト層６は、
ポリイミド系樹脂、ＢＣＢ（ベンゾシクロブテン）系樹
脂、エポキシ系樹脂等からなる。第二の半田レジスト層
６の厚みは１〜５０μｍ程度がよく、１μｍ未満の場
合、回路パターン３上に半田が流れ出てショートが発生
し易くなり、５０μｍを超えると、第二の半田レジスト
層６を硬化させた際に硬化収縮によって絶縁基板１に反
りを発生させてしまい、半導体素子を良好に実装できな
くなる。
【００２８】また、第一の半田レジスト層５を用いず
に、半導体素子接続用の導体バンプ４および受動素子接
続用の導体バンプ４の周囲に第二の半田レジスト層６を
形成した場合、第二の半田レジスト層６は、フォトリソ
グラフィ法によって回路パターン３の電極パッドを除く
絶縁基板１の略全面に形成されるが、フォトリソグラフ
ィ法の現像工程で溶解される第二の半田レジスト層６が
完全に溶解されず、電極パッド上に残留し、特に半導体
素子接続用の微小な導体バンプ４において接続性が劣化
することがある。一方、本発明の場合、半導体素子接続
用の導体バンプ４の周囲には第一の半田レジスト層５を
形成しているため、有機物が電極パッド上部に残留する
ことがないことから接続信頼性の高い回路基板を提供す
ることができる。
【００２９】導体バンプ４をスーパーソルダー法と呼ば
れる有機溶剤中に半田を溶解させた導体ペーストを被着
させる方法で形成した場合、貫通導体２の内面および絶
縁基板１の主面との接続部が第一の半田レジスト層５と
第二の半田レジスト層６とによって二重に覆われてお
り、半田濡れ性のよい回路パターン３が露出していない
ので、誤って半田が付着することがない。即ち、回路パ
ターン３の電極パッド以外に半田が付着すると、フリッ
プチップ法によって半導体素子を実装する際に半導体素
子が傾いたりして良好な実装ができなくなるが、本発明
ではこのような不具合が発生しない。
【００３０】なお、本発明は上記実施の形態に限定され
るものではなく、本発明の要旨を逸脱しない範囲内にお
いて種々の変更を行うことは何等差し支えない。
【００３１】
【発明の効果】本発明の回路基板は、絶縁基板の主面に
形成された回路パターンと、回路パターンの電極パッド
に設けられた導体バンプと、回路パターン内に設けら
れ、太さが０．５ｍｍ以下の貫通孔の内面に導体層が形
成された貫通導体とを具備して成り、回路パターンに導
体バンプを介して半導体素子および受動素子が電気的に
接続される回路基板であって、半導体素子に接続される
導体バンプはその周囲にＣｒ，Ｔｉ，Ｔａおよびこれら
の窒化物のうちの少なくとも一種から成る第一の半田レ
ジスト層が形成され、受動素子に接続される導体バンプ
はその周囲に第一の半田レジスト層およびその上に積層
された樹脂から成る第二の半田レジスト層が形成されて
おり、貫通導体は導体層上に第一の半田レジスト層およ
び第二の半田レジスト層が順次積層されていることによ
り、貫通導体は貫通孔の内面に導体層が形成されその導
体層を介して絶縁基板の上下主面の回路パターンが導通
されるスルーホールとなっているため、貫通孔は焼結後
の絶縁基板にレーザ法やブラスト法等により形成するこ
とができ、その結果、位置精度が良く微小な径の貫通孔
を形成することができる。即ち、ファインピッチ化され
た半導体素子を実装するのに好適な回路基板となる。
【００３２】また、半導体素子と電気的に接続される導
体バンプは、その周囲にＣｒ，Ｔｉ，Ｔａおよびこれら
の窒化物のうちの少なくとも一種から成る第一の半田レ
ジスト層が形成されているため、導体バンプの周囲から
半田が流れ出さず、導体バンプを確実に半導体素子に接
続することができ、また間隔の狭い隣接する導体バンプ
同士が短絡するのを防ぐことができるため、ファインピ
ッチ化された半導体素子をフリップチップ法によって正
確に実装することができる。また、第一の半田レジスト
層を形成した後に導体バンプを形成することができ、そ
の場合、第一の半田レジスト層によって囲まれる、導体
バンプが形成される面積を一定にすることで、半田の表
面張力により導体バンプの高さを一定に保つことができ
る。
【００３３】さらに、受動素子に接続される導体バンプ
は、その周囲に第一の半田レジスト層およびその上に積
層された樹脂から成る第二の半田レジスト層が形成され
ているため、受動素子を強固に接続するための大きな導
体バンプの半田が周囲に流れ出さす、回路パターンがシ
ョートすることを防ぐことができる。
【００３４】加えて、貫通導体は、その内面の導体層上
に第一の半田レジスト層および第二の半田レジスト層が
順次積層されているため、回路基板を半導体パッケージ
等に収容し半田等によって実装した際、下側主面の余分
な半田等が貫通導体を通って上側主面に這い上がること
を防ぐことができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for mounting semiconductor elements and passive elements. 2. Description of the Related Art Conventionally, a circuit board for mounting a semiconductor element or a passive element has a via hole or a via hole for electrically connecting a circuit pattern formed on upper and lower main surfaces of an insulating substrate made of ceramic or the like. A through conductor such as a through hole is provided. This through conductor is generally formed, for example, by the following three methods. (1) A co-sintering method in which a through hole is provided in the form of a ceramic green sheet before a ceramic or other insulating substrate is sintered, and a metal paste is injected into the through hole and simultaneously sintered. (2) After sintering an insulating substrate such as a ceramic,
Form a through hole by laser method or blast method, etc.
Then, a conductive paste method is used in which a conductive paste or the like is injected into the through holes and thermally cured. (3) After sintering an insulating substrate such as a ceramic,
Form a through hole by laser method or blast method, etc.
An open hole method in which a conductive thin film is formed on both main surfaces of the insulating substrate by a sputtering method, a plating method, or the like, so that electrical continuity between the two main surfaces is formed through the thin film on the inner surface of the through hole. Conventionally, a through-conductor formed by the simultaneous sintering method (1) or the conductive paste injection method (2) has been used for a circuit board on which a semiconductor element is mounted by a flip chip method. Was. This is because, in the case of the circuit board formed by the open hole method of (3), conduction is established between both main surfaces through the thin film on the inner surface of the through hole, and nothing is embedded in the through hole. When the substrate is mounted on a semiconductor element storage package (hereinafter, referred to as a semiconductor package) or the like with solder or the like, excess solder on the lower main surface climbs up to the upper main surface through the through-hole, and the circuit pattern on the upper main surface. This is likely to cause a problem of short-circuiting. In recent years, fine pitches of semiconductor elements, that is, finer pitches of electrodes and wirings have been advanced, and fine pitches have also been required for circuit boards on which semiconductor elements are mounted. [0008] However, in the case of the circuit board formed by the conventional simultaneous sintering method (1), through holes are formed in the state of ceramic green sheets, and a metal paste is printed. Because of post-sintering, the sintering causes the insulating substrate to shrink. Conventionally, ceramic green sheets were formed larger than the insulating substrate as a product in anticipation of this shrinkage.However, since shrinkage due to sintering may vary, misalignment of electrodes and wiring from design values, electrode spacing and wiring There has been a problem that a deviation from the designed value of the interval occurs, and it is difficult to achieve a fine pitch. Further, in the case of the circuit board formed by the conventional conductive paste injection method of (2), when the diameter of the through hole is reduced in order to make the pitch fine, the aspect ratio of the through hole (through hole thickness relative to the thickness of the insulating substrate) is reduced. (The ratio of the diameters of the holes) becomes small, and the conductive paste hardly enters the through-holes. Furthermore, if the conductive paste is not completely buried in the through-hole, a void is generated in the conductor of the through-hole, and the void expands in a subsequent heat process or the like, causing the conductor of the through-conductor to swell. there were. Accordingly, the present invention has been completed in view of the above circumstances, and an object of the present invention is to provide a circuit board on which a semiconductor element having a fine pitch can be mounted by a flip chip method. According to the present invention, there is provided a circuit board comprising: a circuit pattern formed on a main surface of an insulating substrate; conductive bumps provided on electrode pads of the circuit pattern; And a through conductor having a conductor layer formed on the inner surface of a through hole having a thickness of 0.5 mm or less, and a semiconductor element and a passive element are electrically connected to the circuit pattern via the conductor bump. A first solder resist layer made of at least one of Cr, Ti, Ta and nitrides thereof is formed around the conductor bump connected to the semiconductor element. Wherein the conductor bumps connected to the passive elements are formed around the first solder resist layer and a second solder resist layer made of resin laminated thereon, The through conductor is characterized in that the first solder resist layer and the second solder resist layer are sequentially laminated on the conductor layer. According to the present invention, with the above configuration, the through conductor is a through hole in which a conductor layer is formed on the inner surface of the through hole and circuit patterns on the upper and lower main surfaces of the insulating substrate are conducted through the conductor layer. Therefore, the through-hole can be formed on the insulating substrate after sintering by a laser method, a blast method, or the like, and as a result, a through-hole having a good positional accuracy and a small diameter can be formed. That is, a circuit board suitable for mounting a semiconductor element having a fine pitch is obtained. In addition, since the conductor bump electrically connected to the semiconductor element has a first solder resist layer made of at least one of Cr, Ti, Ta and their nitride formed around the conductor bump. Since the solder does not flow out from the periphery of the conductor bumps, the conductor bumps can be reliably connected to the semiconductor element, and short-circuiting between adjacent conductor bumps with a small gap can be prevented, so that a fine pitch is obtained. The semiconductor device can be accurately mounted by the flip chip method. In addition, the conductor bumps can be formed after the first solder resist layer is formed. In this case, the area of the conductor bumps formed by the first solder resist layer, which is surrounded by the first solder resist layer, is kept constant. The height of the conductor bump can be kept constant by the surface tension. Further, since the conductor bump connected to the passive element has a first solder resist layer and a second solder resist layer made of resin laminated thereon on the periphery thereof, the passive element can be used as a conductive bump. It is possible to prevent the solder of the large conductor bump for the strong connection from flowing out to the surroundings and to prevent the circuit pattern from being short-circuited. In addition, the through conductor has a first solder resist layer and a second solder resist layer sequentially laminated on a conductor layer on the inner surface thereof, so that the circuit board is housed in a semiconductor package or the like and soldered. When mounted, excess solder or the like on the lower main surface can be prevented from creeping up to the upper main surface through the through conductor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit board according to the present invention will be described in detail below. FIG. 1A is a plan view of a circuit board of the present invention, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. In the figure, 1 is an insulating substrate made of ceramics or the like, 2 is a through-hole type through conductor provided on the insulating substrate 1, 3 is a circuit pattern formed by laminating a plurality of conductive thin films, and 4 is a circuit pattern 3. 5 is a first solder resist layer made of at least one of Cr, Ti, Ta and nitrides formed around the conductive bump 4, and 6 is a first solder resist layer formed around the conductive bump 4. This is a second solder resist layer made of a resin laminated on the solder resist layer 5. Reference numeral 7 denotes a region where a semiconductor element is mounted, and reference numeral 8 denotes a region where a passive element such as a resistance element, a capacitor element, and an inductor element is mounted. The circuit board of the present invention has a circuit pattern 3 formed on the main surface of the insulating substrate 1, conductor bumps 4 provided on the electrode pads of the circuit pattern 3, and a circuit board 3 provided in the circuit pattern 3. Comprising a through conductor 2 having a conductor layer formed on the inner surface of a through hole of 0.5 mm or less, and a semiconductor element and a passive element being electrically connected to a circuit pattern 3 via a conductor bump 4. It is. The conductor bumps 4 connected to the semiconductor element are surrounded by Cr, Ti,
A first solder resist layer 5 made of at least one of Ta and these nitrides is formed, and a conductor bump 4 connected to a passive element is laminated therearound with the first solder resist layer 5 and laminated thereon. A second solder resist layer 6 made of a resin is formed, and the through conductor 2 has a first solder resist layer 5 and a second solder resist layer 6 sequentially laminated on the conductor layer. The insulating substrate 1 of the present invention is made of an aluminum oxide (Al 2 O 3 ) sintered body, mullite (3Al 2 O 3 .2Si).
It is made of a ceramic sintered body such as an O 2 ) sintered body, an aluminum nitride (AlN) based sintered body, a silicon carbide (SiC) based sintered body, and a glass ceramic sintered body. For example, in the case of a sintered body of aluminum oxide, a suitable organic solvent and a solvent are added to a raw material powder such as aluminum oxide, silicon oxide (SiO 2 ), magnesium oxide (MgO), and calcium oxide (CaO), and the mixture is mixed. A ceramic green sheet is formed by a doctor blade method or the like, and then the ceramic green sheet is appropriately punched, formed into a predetermined shape, and fired at a high temperature of about 1600 ° C. Produced by The through-holes forming the through conductors 2 provided in the insulating substrate 1 have a thickness (for example, if the cross-sectional shape of the through-hole is circular, the diameter of the through-hole is circular if the cross-sectional shape of the through-hole is circular). Needs to be 0.5 mm or less, and is formed by a laser method using a carbon dioxide gas laser, a YAG laser, or the like, a sand blast method, or the like. The thickness of the through hole is preferably as small as possible. However, if the thickness is less than 10 μm, the portion of the insulating substrate 1 to be removed when forming the through hole cannot be sufficiently removed, and the through hole tends to be in an unopened state. The thickness is preferably 10 μm or more. Note that the cross-sectional shape of the through hole may be various shapes such as a circle, an ellipse, and a polygon. The conductor layer and the circuit pattern 3 formed on the inner surface of the through hole forming the through conductor 2 have, for example, a three-layer structure in which an adhesion metal layer, a diffusion prevention layer and a main conductor layer are sequentially laminated. I have. The adhesion metal layer is made of Ti, Cr, Ta, Nb,
It is preferably made of at least one of Ta 2 N, Ni—Cr alloy, etc., and is formed by a thin film forming method such as an evaporation method, a sputtering method, an ion plating method, and formed in a predetermined pattern by a photolithography method. You. The thickness of the adhesion metal layer is preferably about 0.01 to 0.2 μm.
When the thickness is less than 01 μm, it is difficult to firmly adhere to the surface of the insulating substrate 1, and when the thickness exceeds 0.2 μm, separation easily occurs due to internal stress during film formation. The diffusion preventing layer is made of Pt, Pd, Rh, Ru,
Ni, Ni-Cr alloy, Ti-W alloy or the like, and preferably has a thickness of 0.05 to 1 µm.
The degree is preferred. When the thickness is less than 0.05 μm, defects such as pinholes are generated and it is difficult to function as a diffusion prevention layer. When the thickness is more than 1 μm, separation easily occurs due to internal stress during film formation. When the circuit board is used in a state where the thermal load is small (an environmental temperature of 50 ° C. or less), the diffusion preventing layer may not be provided. The main conductor layer is preferably made of at least one of Au, Ag, Cu and the like, and has a thickness of 0.1 to 5 mm.
About μm is good. If it is less than 0.1 μm, the electrical resistance tends to increase, and if it exceeds 5 μm, peeling tends to occur due to internal stress during film formation. When Cu is used, the Ni layer and Au are plated by a plating method to prevent surface oxidation.
Preferably, the layers are formed sequentially. Conductive layer of through conductor 2 and circuit pattern 3
When Al is used, it is possible to form only one layer instead of the three-layer structure as described above. The thickness of Al is preferably about 0.1 to 5 μm, and if it is less than 0.1 μm, the electrical resistance tends to increase. If it exceeds 5 μm, peeling tends to occur due to internal stress during film formation. The conductor bumps 4 are formed by a printing method, a plating method, a method of applying a conductor paste obtained by dissolving solder in an organic solvent called a super solder method, or the like. As the conductor bump 4, Pb-Sn eutectic solder is used. However, since Pb has a problem of environmental pollution, it is preferable to use Pb-free Sn-Ag solder, Sn-Ag-Bi solder, or the like. Cr, T formed around the conductor bump 4
Since the first solder resist layer 5 made of at least one of i, Ta and these nitrides is precisely patterned by photolithography and etching, the solder for forming the conductor bumps 4 to be formed thereafter is not used. Since the surface does not flow out and a surface tension acts on the interface with the solder resist layer 5, the size and height of the conductive bump 4 can be made constant. The first solder resist layer 5 is made of, for example, the same metal as the adhesive metal layer, and has the same thickness as the adhesive metal layer. The second solder resist layer 6 made of resin is
It is made of a polyimide resin, a BCB (benzocyclobutene) resin, an epoxy resin, or the like. The thickness of the second solder resist layer 6 is preferably about 1 to 50 μm, and if it is less than 1 μm, the solder flows out onto the circuit pattern 3 to easily cause a short circuit, and if it exceeds 50 μm, the second solder resist layer 6 Curing causes the insulating substrate 1 to warp due to curing shrinkage, which makes it impossible to mount a semiconductor element satisfactorily. In the case where the second solder resist layer 6 is formed around the conductor bumps 4 for connecting semiconductor elements and the conductor bumps 4 for connecting passive elements without using the first solder resist layer 5, The second solder resist layer 6 is formed on substantially the entire surface of the insulating substrate 1 except for the electrode pads of the circuit pattern 3 by photolithography. It may not be completely dissolved and remains on the electrode pad, and the connectivity may be deteriorated, especially in the case of the minute conductive bumps 4 for connecting the semiconductor element. On the other hand, in the case of the present invention, since the first solder resist layer 5 is formed around the conductor bump 4 for connecting the semiconductor element, no organic matter remains on the upper part of the electrode pad. A high circuit board can be provided. When the conductor bumps 4 are formed by applying a conductor paste obtained by dissolving solder in an organic solvent called a super solder method, the connection between the inner surface of the through conductor 2 and the main surface of the insulating substrate 1 is reduced. Since the circuit pattern 3 having good solder wettability is doubly covered by the first solder resist layer 5 and the second solder resist layer 6 and is not exposed, solder does not accidentally adhere. That is, if solder adheres to the circuit pattern 3 other than the electrode pad, the semiconductor element is inclined when mounting the semiconductor element by the flip-chip method, and good mounting cannot be performed. do not do. It should be noted that the present invention is not limited to the above-described embodiment, and that various changes may be made without departing from the scope of the present invention. The circuit board of the present invention has a circuit pattern formed on the main surface of an insulating substrate, a conductive bump provided on an electrode pad of the circuit pattern, a circuit board provided in the circuit pattern, and a thickness. And a through conductor in which a conductor layer is formed on the inner surface of a through hole of 0.5 mm or less, and a semiconductor element and a passive element are electrically connected to a circuit pattern via a conductor bump. The conductor bump connected to the semiconductor element has a first solder resist layer formed of at least one of Cr, Ti, Ta and nitrides formed around the conductor bump, and the conductor bump connected to the passive element is A first solder resist layer and a second solder resist layer made of resin laminated on the first solder resist layer are formed around the first solder resist layer. The through-conductor is formed as a through-hole through which a conductor layer is formed on the inner surface of the through-hole and the circuit patterns on the upper and lower main surfaces of the insulating substrate are conducted through the conductor layer. Therefore, the through-hole can be formed on the insulating substrate after sintering by a laser method, a blast method, or the like, and as a result, a through-hole with a good positional accuracy and a small diameter can be formed. That is, a circuit board suitable for mounting a semiconductor element having a fine pitch is obtained. The conductor bump electrically connected to the semiconductor element has a first solder resist layer made of at least one of Cr, Ti, Ta and their nitride formed around the conductor bump. Since the solder does not flow out from the periphery of the conductor bumps, the conductor bumps can be reliably connected to the semiconductor element, and short-circuiting between adjacent conductor bumps with a small gap can be prevented, so that a fine pitch is obtained. The semiconductor device can be accurately mounted by the flip chip method. In addition, the conductor bumps can be formed after the first solder resist layer is formed. In this case, the area of the conductor bumps formed by the first solder resist layer, which is surrounded by the first solder resist layer, is kept constant. The height of the conductor bump can be kept constant by the surface tension. Further, the conductor bump connected to the passive element has a first solder resist layer and a second solder resist layer made of a resin laminated thereon on the periphery thereof. It is possible to prevent the solder of the large conductor bump for the strong connection from flowing out to the surroundings and to prevent the circuit pattern from being short-circuited. In addition, the through conductor has a first solder resist layer and a second solder resist layer sequentially laminated on a conductor layer on the inner surface thereof. When mounted, excess solder or the like on the lower main surface can be prevented from creeping up to the upper main surface through the through conductor.
【図面の簡単な説明】
【図１】（ａ）は本発明の回路基板の平面図、（ｂ）は
（ａ）のＡ−Ａ'線における断面図である。
【符号の説明】
１：絶縁基板
２：貫通導体
３：回路パターン
４：導体バンプ
５：第一の半田レジスト層
６：第二の半田レジスト層BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a plan view of a circuit board according to the present invention, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. [Description of Signs] 1: Insulating substrate 2: Through conductor 3: Circuit pattern 4: Conductor bump 5: First solder resist layer 6: Second solder resist layer
Claims (1)
ンと、該回路パターンの電極パッドに設けられた導体バ
ンプと、前記回路パターン内に設けられ、太さが０．５
ｍｍ以下の貫通孔の内面に導体層が形成された貫通導体
とを具備して成り、前記回路パターンに前記導体バンプ
を介して半導体素子および受動素子が電気的に接続され
る回路基板であって、前記半導体素子に接続される前記
導体バンプはその周囲にＣｒ，Ｔｉ，Ｔａおよびこれら
の窒化物のうちの少なくとも一種から成る第一の半田レ
ジスト層が形成され、前記受動素子に接続される前記導
体バンプはその周囲に前記第一の半田レジスト層および
その上に積層された樹脂から成る第二の半田レジスト層
が形成されており、前記貫通導体は前記導体層上に前記
第一の半田レジスト層および前記第二の半田レジスト層
が順次積層されていることを特徴とする回路基板。Claims: 1. A circuit pattern formed on a main surface of an insulating substrate, a conductor bump provided on an electrode pad of the circuit pattern, and a thickness of 0 mm provided in the circuit pattern. .5
a through conductor having a conductor layer formed on the inner surface of a through hole having a diameter of not more than 1 mm, wherein a semiconductor element and a passive element are electrically connected to the circuit pattern via the conductor bump. A first solder resist layer made of at least one of Cr, Ti, Ta and nitrides thereof is formed around the conductor bump connected to the semiconductor element, and the conductive bump is connected to the passive element; The conductor bumps are formed around the first solder resist layer and a second solder resist layer made of resin laminated thereon, and the through conductor is formed on the conductor layer by the first solder resist layer. A circuit board, wherein a layer and the second solder resist layer are sequentially laminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001322657A JP3934906B2 (en) | 2001-10-19 | 2001-10-19 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001322657A JP3934906B2 (en) | 2001-10-19 | 2001-10-19 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003133712A true JP2003133712A (en) | 2003-05-09 |
| JP3934906B2 JP3934906B2 (en) | 2007-06-20 |
Family
ID=19139672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001322657A Expired - Lifetime JP3934906B2 (en) | 2001-10-19 | 2001-10-19 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3934906B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100736635B1 (en) | 2006-02-09 | 2007-07-06 | 삼성전기주식회사 | Bare chip embedded pcb and method of the same |
| JP2011146569A (en) * | 2010-01-15 | 2011-07-28 | Mitsubishi Electric Corp | Ceramic circuit board |
| JP2011176188A (en) * | 2010-02-25 | 2011-09-08 | Kyocera Corp | Glass ceramic wiring board |
-
2001
- 2001-10-19 JP JP2001322657A patent/JP3934906B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100736635B1 (en) | 2006-02-09 | 2007-07-06 | 삼성전기주식회사 | Bare chip embedded pcb and method of the same |
| JP2011146569A (en) * | 2010-01-15 | 2011-07-28 | Mitsubishi Electric Corp | Ceramic circuit board |
| JP2011176188A (en) * | 2010-02-25 | 2011-09-08 | Kyocera Corp | Glass ceramic wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3934906B2 (en) | 2007-06-20 |
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