JP2003133741A - Multilayered printed wiring board having filled-via structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buildup multilayered printed wiring board that has a filled-via structure and is excellent in surface smoothness and connection reliability. SOLUTION: This multilayered printed wiring board is constituted by alternately laminating conductor circuits and interlayer resin insulating layers upon another. The insulating layers have openings. In each opening, a via hole which is filled up with a plated material and has a flat surface is formed so that the surface of the hole is flushed with that of the conductor circuit positioned in the same layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention proposes a build-up multilayer printed wiring board having a filled via structure capable of forming a fine pattern and having excellent surface smoothness and connection reliability.

[0002]

2. Description of the Related Art A build-up multilayer printed wiring board is one in which conductor circuits and interlayer resin insulation layers are alternately laminated, and a conductor circuit in a lower layer and a conductor circuit in an upper layer are opened in the interlayer insulation layer. It is electrically connected by a so-called via hole provided with a plating film.

In such a build-up multilayer printed wiring board, the via hole is generally formed by coating the inner surface of the opening of the interlayer insulating layer with a plating film. However, due to defective plating deposition or heat cycle. There was a problem that disconnection is likely to occur. Therefore, recently, a method of filling the opening with plating to form a filled via hole has been adopted. For example, Japanese Patent Laid-Open No. 2-188992
Japanese Patent Laid-Open No. 3-3298 and Japanese Patent Laid-Open No. 7-34048 have drawings that disclose the filled via holes.

However, such a filled via hole still has another problem that a depression is formed on the surface thereof. When the interlayer resin insulation layer was formed on the upper layer, the dent on the surface of the filled via hole also caused a dent on the surface, which eventually caused disconnection or mounting failure.

It is also possible to apply the interlayer resin a plurality of times to flatten the surface of the filled via hole. However, the thickness of the interlayer resin insulation layer immediately above the recess of the via hole is different from that on other conductor circuits. It becomes thicker than the thickness of the interlayer resin layer. Therefore, if an opening is provided in the interlayer resin insulation layer by exposure, development, or laser light, there is a problem that resin residue occurs and the connection reliability of the via hole is reduced. Especially in mass production, when opening the interlayer resin insulation layer,
Since it is difficult to change the exposure and development conditions on the via hole and on the other conductor circuits, such resin residue is likely to occur.

In order to solve such a problem, Japanese Patent Laid-Open No. 9-3
In Japanese Patent No. 12472 and the like, a build-up multilayer printed wiring board having a filled via hole is proposed. In this multilayer printed wiring board, the thickness of the conductor circuit is set to 1/2 or more of the diameter of the via hole to fill the via hole so that the height of the conductor circuit is the same as the height of the via hole.

However, in such a build-up multilayer printed wiring board, the conductor circuit becomes thicker than the via hole diameter. Therefore, it is necessary to increase the thickness of the plating resist, and as a result, it is difficult to expose and develop, and there is a problem that a fine pattern cannot be formed. Further, as in the example of JP-A-9-312472, when a conductor circuit is formed by etching after forming a conductor film, a fine pattern is formed by etching because the conductor circuit is thick. There was a problem that I could not.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a build-up multilayer printed wiring board having a filled via structure capable of forming a fine pattern and having excellent surface smoothness and connection reliability.

[0009]

Means for Solving the Problems As a result of intensive research aimed at realizing the above-mentioned object, the inventors have conceived an invention having the following essential requirements. ． It is a build-up multilayer printed wiring board (that is, conductor circuits are laminated via an interlayer resin insulation layer). ． The via holes must be filled with plating. ． The surface of the via hole is flat. ． The surface of the via hole and the surface of another conductor circuit located on the same layer as the via hole are at the same height. ． The thickness of the conductor circuit must be less than half the diameter of the via hole.

That is, the multilayer printed wiring board according to the present invention is a multilayer printed wiring board in which conductor circuits and interlayer resin insulation layers are alternately laminated, wherein the interlayer resin insulation layer comprises:
An opening is provided, and a flat via hole having a surface filled with plating is formed in the opening with the same surface height as other conductor circuits located in the same layer as the via hole. The conductor circuit is characterized in that its thickness is less than 1/2 of the via hole diameter. here,
The via hole diameter in the present invention means the opening diameter at the upper end of the via hole opening.

In such a multilayer printed wiring board of the present invention, (1) it is more desirable that the surfaces of the via holes and the conductor circuits are roughened. The reason for this is to improve the adhesion with the upper interlayer resin insulation layer. (2) It is more desirable that the inner wall surface of the opening provided in the interlayer resin insulation layer is roughened. The reason for this is to improve the adhesion with the via hole formed in the opening. (3) The conductor circuit on the lower layer side (inner layer pad) to which the via hole is connected has a roughened surface, and it is more desirable that the conductor circuit is connected to the via hole through the roughened surface. is there. The reason for this is to improve the adhesion between the via hole and the inner layer pad (lower layer conductor circuit).

In particular, in the constitution of the combination of (2) and (3), the inner layer pad adheres to the interlayer resin insulation layer, and the via hole also adheres to the interlayer resin insulation layer. , The inner layer pad and the via hole are completely integrated.

Further, in the multilayer printed wiring board of the present invention, (4) it is more desirable that another via hole is formed on the via hole. The reason for this is that the dead space of the wiring due to the via hole can be eliminated and a higher density can be achieved. (5) It is more desirable that the interlayer resin insulation layer in which the via hole is formed is made of a composite of a thermoplastic resin and a thermosetting resin, or a thermoplastic resin. The reason for this is that the filled via hole formed by filling the plating has a large stress generated during the heat cycle, and cracks easily occur in the interlayer resin insulation layer made of a normal thermosetting resin. A thermosetting resin,
Alternatively, the interlayer resin insulating layer made of only the thermoplastic resin has high toughness and can reliably suppress cracks. (6) The ratio of (diameter of via hole) / (thickness of interlayer resin insulation layer) is 1 to 4, and the thickness of the conductor circuit is 25.
It is more desirable that the thickness is less than μm. The reason for this is that a fine pattern is easily formed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A multilayer printed wiring board according to the present invention in which conductor circuits and interlayer resin insulation layers are alternately laminated is provided with an opening in the interlayer resin insulation layer, and the opening is plated. A flat via hole having a flat surface is formed with the same surface height as that of another conductor circuit located in the same layer as the via hole. It is characterized in that it is less than 1/2 of the diameter.

According to the configuration of the present invention as described above, Since the via hole is filled with the plating, the deposition failure of the plating and the disconnection failure due to the heat cycle are less likely to occur as compared with the case where the opening is covered with the plating film. ． Since there is no dent on the surface in the via hole portion and the surface flatness of the interlayer resin insulating layer is excellent, disconnection due to the dent and mounting failure of the IC chip or the like are less likely to occur. ． The thickness of the via hole and the interlayer resin insulation layer on the conductor circuit becomes uniform, and the resin residue when forming the opening is reduced. ． Since the thickness of the conductor circuit is less than 1/2 of the diameter of the via hole, the thickness of the conductor circuit does not become thick even when the via hole is filled with plating, and the plating resist can be made thin, resulting in a fine pattern. Can be formed.

In the present invention as described above, it is preferable that a roughened surface is formed on the inner wall surface of the opening of the interlayer resin insulation layer. The reason for this is to improve the adhesion between the via hole formed of the filling plating and the interlayer resin insulation layer.

In the multilayer printed wiring board of the present invention, it is preferable that the via holes are electrically connected through the roughening layer provided on the surface of the lower conductor circuit. As a result, the roughened layer improves the adhesion between the conductor circuit and the via hole, so that peeling occurs at the interface between the conductor circuit and the via hole even under high temperature and high humidity conditions such as PCT and heat cycle conditions. Hard to do.

When the roughened layer is formed on the side surface of the conductor circuit, the contact between the side surface of the conductor circuit and the interlayer resin insulation layer is insufficient, and the interface between these surfaces serves as a starting point to vertically face the interlayer resin insulation layer. It is advantageous in that cracks that occur can be suppressed.

The thickness of the roughening layer formed on the surface of such a conductor circuit is preferably 1 to 10 μm. The reason for this is that if it is too thick, it causes interlayer short-circuiting, and if it is too thin, the adhesion to the adherend becomes low. As the roughening treatment for forming this roughened layer, the surface of the conductor circuit is subjected to oxidation (blackening) -reduction treatment, spray treatment with a mixed aqueous solution of an organic acid and a cupric complex, or copper-nickel. -Phosphorus needle alloy plating is preferable.

Among these treatments, in the method of oxidation (blackening) -reduction treatment, NaOH (20 g / l), NaClO ₂ (50 g
/ L), Na ₃ PO ₄ (15.0 g / l) in an oxidizing bath (blackening bath), Na
OH (2.7 g / l) and NaBH ₄ (1.0 g / l) are used as the reducing bath.

Further, a mixed aqueous solution of an organic acid-cupric acid complex
In the treatment used, oxygen coexistence such as spraying and bubbling
Under the conditions, it works as follows, and it is the lower conductor circuit such as copper.
Melt the metal foil. Cu + Cu (II) A_n→ 2Cu (I) A_{n / 2} 2Cu (I) A_{n / 2}+ N / 4O₂+ NAH (Airray
2) Cu (II) A_n+ N / 2H₂O However, A is a complexing agent (acts as a chelating agent), and n is
It is a place.

The cupric complex used in this treatment is preferably a cupric complex of an azole. This cupric complex of azoles acts as an oxidizing agent for oxidizing metallic copper and the like. As azoles, diazole, triazole,
Tetrazole is good. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable. The content of the cupric complex of the azoles is preferably 1 to 15% by weight.
This is because if it is within this range, the solubility and stability are excellent.

The organic acid is added to dissolve copper oxide. Specific examples include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, apple. At least one selected from acid and sulfamic acid is preferable. The content of this organic acid is 0.1-30
Weight% is good. This is for maintaining the solubility of the oxidized copper and ensuring the dissolution stability. The generated cuprous complex is dissolved by the action of an acid, is combined with oxygen to form a cupric complex, and contributes to the oxidation of copper again.

In order to assist the dissolution of copper and the oxidizing action of azoles, halogen ions such as fluorine ion, chlorine ion and bromine ion are added to the etching solution containing the organic acid-cupric acid complex. Good. This halogen ion can be supplied by adding hydrochloric acid, sodium chloride or the like. The amount of halogen ions is preferably 0.01 to 20% by weight. This is because if it is within this range, the formed roughening layer has excellent adhesion to the interlayer resin insulating layer.

The etchant containing the organic acid-cupric acid complex is prepared by dissolving the cupric complex of an azole and the organic acid (halogen ion as necessary) in water.

Further, in the plating treatment of a needle-shaped alloy of copper-nickel-phosphorus, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l, boric acid 10-40 g / l, surfactant
It is desirable to use a plating bath having a liquid composition of 0.01 to 10 g / l.

In the multilayer printed wiring board of the present invention, it is preferable that another via hole is formed on the filled via hole. As a result, another via hole can be formed immediately above the via hole, so that the dead space of the wiring due to the via hole and the like can be eliminated and the wiring density can be increased.

In the present invention, a thermosetting resin, a thermoplastic resin, or a composite of a thermosetting resin and a thermoplastic resin can be used as the interlayer resin insulation layer. Particularly in the present invention, it is preferable to use a composite of a thermosetting resin and a thermoplastic resin as the interlayer resin insulating layer in which the via hole is formed. As the thermosetting resin, epoxy resin, polyimide resin, phenol resin, thermosetting polyphenylene ether (PPE) or the like can be used. As the thermoplastic resin, polytetrafluoroethylene (PTF
Fluorine resin such as E), polyethylene terephthalate (P
ET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyetherimide (PEI), polyphenylene sulfone (PPES), tetrafluoroethylene 6 fluorine Propylene copolymer (FEP), tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene naphthalate (PEN), polyether ether ketone (PEE)
K), polyolefin resin, etc. can be used. Examples of the composite of thermosetting resin and thermoplastic resin include epoxy resin-PES, epoxy resin-PSF, epoxy resin-PP.
S, epoxy resin-PPES or the like can be used.

In the present invention, as the interlayer resin insulation layer,
It is desirable to use a composite of a cloth of fluororesin fibers and a thermosetting resin filled in the voids of the cloth. This is because such a composite has a low dielectric constant and excellent shape stability. In this case, as the thermosetting resin, it is desirable to use at least one selected from epoxy resin, polyimide resin, polyamide resin, and phenol resin. As the cloth of fluororesin fiber, it is desirable to use cloth or non-woven cloth woven of the fibers. The non-woven fabric is manufactured by forming a short fiber or a long fiber of a fluororesin fiber together with a binder into a sheet, and heating the sheet to fuse the fibers to each other.

In the present invention, an adhesive for electroless plating can be used as the interlayer resin insulation layer. As the adhesive for electroless plating, heat-resistant resin particles soluble in a cured acid or an oxidant are dispersed in an uncured heat-resistant resin that is hardly soluble in an acid or an oxidant by the curing treatment. Is best. The reason for this is that the heat-resistant resin particles are dissolved and removed by treatment with an acid or an oxidizing agent, and a roughened surface composed of octopus-like anchors can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include heat-resistant resin powder having an average particle size of 10 μm or less, and an average particle size of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a mixture of heat-resistant resin powder having an average particle size of 2 to 10 μm and heat-resistant resin powder having an average particle size of 2 μm or less, and an average particle size of 2 to 10 μm
Pseudo particles formed by adhering at least one of a heat-resistant resin powder having an average particle size of 2 μm or less and an inorganic powder on the surface of the heat-resistant resin powder of 0.1 to 0.8 μm
A mixture of the heat-resistant resin powder and the heat-resistant resin powder having an average particle size of more than 0.8 μm and less than 2 μm, the average particle size of 0.1 to 1.
It is desirable to use at least one selected from 0 μm heat-resistant resin powder. This is because they can form more complex anchors. As the heat resistant resin used in the adhesive for electroless plating, the above-mentioned thermosetting resin, thermoplastic resin, or a composite of thermosetting resin and thermoplastic resin can be used. Particularly in the present invention, it is preferable to use a composite of a thermosetting resin and a thermoplastic resin.

Next, one method for manufacturing the multilayer printed wiring board of the present invention will be described. (1) First, a wiring board having an inner layer copper pattern formed on the surface of a core board is manufactured. The copper pattern is formed on the core substrate by etching the copper clad laminate, or
A method for forming an adhesive layer for electroless plating on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate, roughening the adhesive layer surface to a roughened surface, and performing electroless plating on the surface. Alternatively, the so-called semi-additive method (electroless plating is applied to the entire roughened surface to form a plating resist, electrolytic plating is applied to the non-plating resist forming portion, the plating resist is removed, and etching treatment is performed to perform electrolytic plating. Method for forming a conductor circuit including a film and an electroless plated film).

Further, if necessary, a roughening layer made of copper-nickel-phosphorus is formed on the copper pattern surface (the surface of the lower conductor circuit) of the wiring board. This roughened layer is formed by electroless plating. The liquid composition of this electroless plating solution has a copper ion concentration, a nickel ion concentration, and a hypophosphite ion concentration of 2.2 × 10 ^-2 to 4.1 × 10 ^-2 mol /
1, 2.2 × 10 ^-3 to 4.1 × 10 ^-3 mol / l, 0.20 to 0.25 mol
/ L is desirable. This is because the crystal structure of the coating film deposited in this range has a needle-like structure and is excellent in the anchor effect. In addition to the above compounds, complexing agents and additives may be added to this electroless plating aqueous solution. As the method for forming the roughened layer, as described above, the roughened surface is formed by the treatment of copper-nickel-phosphorus needle-like alloy plating, the oxidation-reduction treatment, and the treatment of etching the copper surface along the grain boundaries. There are ways.

A through hole is formed in the core substrate, and the wiring layers on the front surface and the back surface can be electrically connected through the through hole. Further, resin may be filled between the through holes and the conductor circuits of the core substrate to ensure the flatness.

(2) Next, an interlayer resin insulation layer is formed on the wiring board prepared in the above (1). Particularly in the present invention, it is desirable to use an adhesive for electroless plating using a composite of a thermosetting resin and a thermoplastic resin as a resin matrix as an interlayer resin insulating material forming a via hole.

(3) After drying the adhesive layer for electroless plating formed in (2) above, an opening for forming a via hole is provided. In the case of a photosensitive resin, it is exposed and developed and then heat-cured, and in the case of a thermosetting resin, it is heat-cured and then laser-processed to form a via hole in the adhesive layer. Provide an opening. At this time, the ratio of (diameter of via hole) / (thickness of interlayer resin insulating layer) is preferably 1 to 4. The reason is that the ratio is 1
This is because if the ratio is less than this, the electrolytic plating solution does not enter the opening and plating does not deposit in the opening. On the other hand, if the ratio exceeds 4, the degree of plating filling of the opening deteriorates.

(4) Next, the epoxy resin particles existing on the surface of the hardened adhesive layer are decomposed or dissolved by an acid or an oxidizing agent and removed, and the surface of the adhesive layer is roughened. Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and it is particularly preferable to use organic acids. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is unlikely to corrode. On the other hand, it is desirable to use chromic acid or permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, catalyst nuclei are applied to the wiring board whose surface of the adhesive layer has been roughened. It is desirable to use a noble metal ion, a noble metal colloid, or the like for providing the catalyst nucleus, and in general, palladium chloride or a palladium colloid is used. In addition, it is desirable to perform heat treatment to fix the catalyst nuclei. Palladium is preferable as such a catalyst nucleus.

(6) Next, the surface of the adhesive for electroless plating is subjected to electroless plating to form an electroless plated film so as to follow the entire roughened surface. At this time, the thickness of the electroless plated film is set to 0.1 to 5 μm, and more preferably 0.5 to 3 μm. Next, a plating resist is formed on the electroless plated film. As the plating resist composition, it is particularly preferable to use a composition comprising an acrylate of a cresol novolac type epoxy resin or a phenol novolac type epoxy resin and an imidazole curing agent, but a commercially available dry film can also be used.

(7) Next, electrolytic plating is applied to the plating resist non-formed portion to form a conductor circuit and a via hole having the opening filled with the plating. At this time, the thickness of the electrolytic plating film is preferably 5 to 30 μm, and the thickness of the conductor circuit is set to be less than 1/2 of the via hole diameter.
Here, it is desirable to use copper plating as the electrolytic plating.

(8) Further, after removing the plating resist, the electroless plating film under the plating resist is dissolved and removed by a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate or ammonium persulfate to remove the plating resist. Conductor circuit and filled via hole.

(9) Next, a roughening layer is formed on the surface of the conductor circuit. As a method for forming the roughened layer, there are etching treatment, polishing treatment, redox treatment, and plating treatment. Among these treatments, the redox treatment is NaOH (20g / l), NaClO
₂ (50 g / l), Na ₃ PO ₄ (15.0 g / l) as an oxidation bath (blackening bath), NaOH (2.7 g / l) and NaBH ₄ (1.0 g / l) as a reduction bath. The roughened layer made of the copper-nickel-phosphorus alloy layer is formed by deposition by electroless plating. As electroless plating solution for this alloy, copper sulfate 1-40
g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-
20 g / l, hypophosphite 10-100 g / l, boric acid 10-40
It is desirable to use a plating bath having a liquid composition of g / l and a surfactant of 0.01 to 10 g / l.

Further, the surface of the roughened layer is covered with a layer of a metal or a noble metal having an ionization tendency larger than that of copper and not more than titanium. In the case of tin, tin borofluoride-thiourea and tin chloride-thiourea liquids are used. At this time, Cu-
A Sn layer of about 0.1 to 2 μm is formed by the Sn substitution reaction. In the case of a noble metal, a method such as sputtering or vapor deposition can be adopted.

(10) Next, an adhesive layer for electroless plating is formed as an interlayer resin insulating layer on this substrate. (11) Further, the above steps (3) to (8) are repeated to provide an upper conductor circuit. This conductor circuit is a conductor pad or via hole that functions as a solder pad.

(12) Next, the surface of the wiring board thus obtained is coated with a solder resist composition, the coating film is dried, and then a photomask film having an opening is drawn on the coating film. Then, the substrate is exposed to light and developed to form an opening that exposes the solder pad (including the conductor pad and the via hole) of the conductor circuit. here,
The opening diameter of the opening may be larger than the diameter of the solder pad, and the solder pad may be completely exposed. On the contrary, the opening diameter of the opening can be made smaller than the diameter of the solder pad, and the periphery of the solder pad can be covered with the solder resist layer. In this case, the solder pad can be suppressed by the solder resist layer, and peeling of the solder pad can be prevented.

(13) Next, a "nickel-gold" metal layer is formed on the solder pad portion exposed from the opening. The nickel layer is preferably 1-7 μm, and the gold layer is 0.01-0.
06 μm is good. The reason for this is that if the nickel layer is too thick, the resistance value will increase, and if it is too thin, it will easily peel off. On the other hand, if the gold layer is too thick, the cost will increase, and if it is too thin, the adhesion effect with the solder body will decrease.

(14) Next, a solder body is supplied onto the solder pad portion exposed from the opening. As a method of supplying the solder body, a solder transfer method or a printing method can be used. Here, the solder transfer method is to bond a solder foil to a prepreg and form a solder carrier film by forming a solder pattern by etching this solder foil leaving only a portion corresponding to an opening portion, and this solder carrier film Is applied to the solder resist opening portion of the substrate, then laminated so that the solder pattern contacts the pad, and this is heated and transferred.
On the other hand, the printing method is a method in which a metal mask having through-holes at positions corresponding to pads is placed on a substrate, solder paste is printed, and heat treatment is performed.

[0048]

EXAMPLES (Example 1) (1) The compositions obtained in the following 1 to 3 were mixed and stirred to prepare an adhesive for electroless plating. ． 35 parts by weight (solid content 80%) of 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500), 4 parts by weight of photosensitive monomer (Toon Gosei, Aronix M315), defoaming agent (San Nopco Made, S-65) 0.
5 parts by weight and 3.6 parts by weight of NMP were mixed by stirring. ． After mixing 8 parts by weight of polyether sulfone (PES) and 7.245 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle size of 0.5 μm, 20 parts by weight of NMP was further added and mixed by stirring. ． Imidazole curing agent (Shikoku Kasei, 2E4MZ-CN) 2 parts by weight, photoinitiator (Ciba-Geigy, Irgacure I-9)
07) 2 parts by weight, photosensitizer (Nippon Kayaku, DETX-S) 0.2
By weight, 1.5 parts by weight of NMP were mixed by stirring.

(2) A bismaleimide triazine (BT) resin substrate 1 (see FIG. 1 (a)) having a conductor circuit 2 formed on the surface thereof was used, and 8 g / l of copper sulfate, 0.6 g of nickel sulfate, 15 g / l of citric acid, Sodium hypophosphite 29g / l, boric acid 31
g / l, 0.1 g / l of surfactant, pH = 9 electroless plating solution, and the conductor circuit 2 has a thickness of 3 μm.
A roughened layer 3 made of copper-nickel-phosphorus was formed. Then, the substrate was washed with water and immersed in an electroless tin displacement plating bath consisting of a 0.1 mol / l tin borofluoride-1.0 mol / l thiourea solution at 50 ° C. for 1 hour, and the surface of the roughened layer 3 was 0.3. μ
m tin layer was provided (see FIG. 1 (b), but the tin layer is not shown).

(3) The adhesive for electroless plating prepared in (1) above was applied to the substrate treated in (2) above (FIG. 1 (c)).
After drying, a photomask film is placed, exposed, developed, and then heat-cured to form an interlayer with an opening (opening 5 for via hole) having a diameter of 60 μm and a thickness of 20 μm. A resin insulation layer 4 was formed (Fig. 1
(See (d)).

(4) The substrate on which the interlayer resin insulation layer 4 was formed was dipped in chromic acid for 19 minutes to form a roughened surface 6 having a depth of 4 μm on the surface (see FIG. 1 (e)). (5) The substrate on which the roughened surface 6 was formed was immersed in an electroless plating solution to form an electroless copper plating film 7 having a thickness of 0.6 μm on the entire rough surface (see FIG. 1 (f)). (6) The plating resist 8 was formed by a conventional method (Fig. 2 (a)
reference).

(7) Next, under the following conditions, the plating resist
Electroless plating is applied to the non-formed part to obtain a 20 μm thick electrolytic
At the same time when the conductive film is formed by providing the plating film 9, the opening portion is formed.
The inside was filled with plating to form a via hole 10 (Fig. 2
(See (b)). [Electrolytic plating solution] Copper sulphate pentahydrate: 60 g / l Leveling agent (Atotech, HL): 40 ml / l Sulfuric acid: 190 g / l Brightener (Atotech, UV): 0.5 ml / l Chloride ion: 40 ppm [Electrolytic plating conditions] Bubbling: 3.0 liters / minute Current density: 0.5 A / dm² Set current value: 0.18 A Plating time: 130 minutes

(8) After removing the plating resist 8 by peeling,
The electroless plated film 7 under the plating resist is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate or ammonium persulfate to obtain a thickness composed of the electroless plated film 7 and the electrolytic copper plated film 9. About 20μm, L / S = 25μ
A conductor circuit 11 of m / 25 μm was formed. At this time, the surface of the via hole 10 was flat, and the heights of the conductor circuit surface and the via hole surface were the same. According to the knowledge of the inventors, when the thickness of the interlayer resin insulation layer 4 is 20 μm, the diameter of the via hole 10 is 25 μm, 40 μm, 60 μm, 80 μm.
Then, the thickness of the plating film required for each filling is
10.2 μm, 11.7 μm, 14.8 μm and 23.8 μm.

(9) A roughened layer 3 was formed on this substrate in the same manner as in (2), and the steps (3) to (8) were repeated to produce a multilayer printed wiring board (see FIG. 2 ( See c)).

(Example 2) An interlayer resin insulation layer having a thickness of 20 μm
A multilayer printed wiring board was manufactured in the same manner as in Example 1 except that a fluororesin film having a diameter of 60 m was formed by thermocompression bonding, and an opening having a diameter of 60 μm was provided by irradiation with an ultraviolet laser.

(Example 3) (1) W. L. Gore (WL Gore & Associates, In
c. ) GORE-TEX (registered trademark GORE-TEX, a fiber of expanded tetrafluoroethylene resin (PTFE) available as a fiber for expanded PTFE woven fabric) is woven into a cloth, and the structure of the cloth is 2.54 cm in the longitudinal direction. 53 400 denier fibers per meter and transverse
(Having 52 400 denier fibers per 2.54 cm) was used as the fluororesin fiber cloth to make up the interlayer resin insulation layer.

(2) This fluororesin fiber cloth is cut into a sheet of 15.24 cm × 15.24 cm,
Similarly W. L. Gore Tetra Etch (registered trademark TE
TRA-ETCH) and immersed in an alkali metal-naphthalene solution. After this treatment, the cloth was washed with warm water and rinsed with acetone. At this time, the fibers turned dark brown due to tetraetch and the fabric shrank 20% in the machine and cross directions. So, this cloth
The edges were grabbed by hand and stretched to their original dimensions. On the other hand, as a thermosetting resin to be impregnated into the fluororesin fiber cloth, a liquid epoxy resin was prepared according to the guidelines of # 296-396-783 of Dow Chemical Co. product catalog for Dow epoxy resin 521-A80.

(3) The liquid epoxy resin is impregnated in the fluororesin fiber cloth obtained in (2) above, and the resin-impregnated cloth is
It was heated and dried at 0 ° C. to obtain a B-stage sheet. At this time, the thickness of the sheet was 0.3556 cm, and the amount of impregnated resin in the sheet was 5 g.

(4) This B-stage sheet is used in the first embodiment.
It was laminated on the substrate of (2) and pressed at a pressure of 80 kg / cm ² at 175 ° C. to form an interlayer resin insulation layer. Further, the interlayer resin insulation layer is irradiated with an ultraviolet laser having a wavelength of 220 nm to obtain a diameter of 60 nm.
An opening for forming a via hole of μm was provided. Thereafter, a multilayer printed wiring board was manufactured according to the steps (4) to (9) of Example 1.

(Comparative Example 1) Copper sulfate: 0.06 mol / l, formalin: 0.3 mol / l, according to JP-A-2-188992.
NaOH: 0.35 mol / l, EDTA: 0.35 mol / l, additive: a little, temperature: 75 ° C, immersed in an electroless plating solution of pH = 12.4 for 11 hours, a conductor consisting of a 25 μm thick electroless plating film only Except for forming circuits and via holes,
A multilayer printed wiring board was manufactured in the same manner as in Example 1.
In this wiring board, even if the opening of the interlayer resin insulation layer was filled with plating, a depression of about 20 to 25 μm was observed at the center thereof.

(Comparative Example 2) A multilayer printed wiring board was manufactured according to Japanese Patent Laid-Open No. 9-312472. That is, in the first embodiment
Perform steps (1) to (5), then copper sulfate 0.05 mol / liter, formalin 0.3 mol / liter, sodium hydroxide 0.35 mol / liter, ethylenediaminetetraacetic acid (EDTA)
It was immersed in an electroless plating solution consisting of an aqueous solution of 0.35 mol / liter to form a plating film having a thickness of 40 μm. Further, a dry film is attached, exposed and developed, L / S = 25 μm /
When a 25 μm etching resist was formed and etched with a mixed solution of sulfuric acid and hydrogen peroxide, the conductor circuit was peeled off due to undercut.

With respect to the multilayer printed wiring boards of Examples 1, 2, 3 and Comparative Example 1 thus manufactured, the surface flatness of the interlayer resin insulating layer and the connection reliability of via holes were examined. With respect to the above, it was judged whether or not a recess was formed in the interlayer resin insulating layer after one application. As for the above, when a via hole was further formed on the via hole, it was examined with a probe whether or not there is a conduction failure in the upper via hole. The results are shown in Table 1.

As is clear from the results shown in Table 1,
Since the multilayer printed wiring boards of Examples 1, 2 and 3 are excellent in the surface flatness of the interlayer resin insulation layer, even if a via hole is further formed on the via hole, there is no pattern disconnection defect due to the depression. Excellent connection reliability and I
Excellent mountability for C chips. Furthermore, the multilayer printed wiring boards of Examples 1, 2, and 3 according to the present invention were excellent in via hole connection reliability even when mass-produced. Further, according to the multilayer printed wiring boards of Examples 1, 2, and 3, a fine pattern such as L / S = 25/25 μm can be formed.

[0064]

[Table 1]

[0065]

As described above, according to the present invention, it is possible to provide a multilayer printed wiring board having a filled via structure capable of forming a fine pattern and having excellent surface smoothness and connection reliability.

[Brief description of drawings]

FIG. 1 is a diagram showing each manufacturing process of a multilayer printed wiring board according to the invention.

FIG. 2 is a diagram showing each manufacturing process of the multilayer printed wiring board according to the invention.

[Explanation of symbols]

1 substrate 2,11 conductor circuit 3 roughening layer 4 Interlayer resin insulation layer 5 Via hole openings 6 roughened surface 7 Electroless plating film 8 Plating resist 9 Electroplated film 10 Filled via holes

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Motoo Asai             1-1 Ibide, Northern Ibigawa-cho, Ibi-gun, Gifu Prefecture             Within the corporation F-term (reference) 5E343 AA07 AA16 AA17 AA18 AA19                       AA22 AA23 BB23 BB24 BB44                       BB54 BB67 CC17 CC73 DD33                       DD43 EE37 EE52 GG13                 5E346 AA43 CC08 CC09 CC10 CC12                       CC13 CC14 CC16 CC32 CC37                       CC43 DD12 DD23 DD24 GG40                       HH07

Claims (7)

[Claims] 1. In a multilayer printed wiring board in which conductor circuits and interlayer resin insulation layers are alternately laminated, an opening is provided in the interlayer resin insulation layer, and the opening is filled with plating. The surface of the via hole having a flat surface is formed to have the same surface height as other conductor circuits located in the same layer as the via hole, and the thickness of the conductor circuit is 1 / the diameter of the via hole. A multilayer printed wiring board characterized by being less than 2. 2. The multilayer printed wiring board according to claim 1, wherein a wall surface of the opening is roughened. 3. The multilayer printed wiring board according to claim 1, wherein the conductor circuit on the lower layer side to which the via hole is connected has a surface roughened. 4. The multilayer printed wiring board according to claim 1, further comprising a via hole formed on the via hole. 5. The multi-layer print according to claim 1, wherein the interlayer resin insulation layer in which the via hole is formed is made of a composite of a thermoplastic resin and a thermosetting resin. Wiring board. 6. The multilayer printed wiring board according to claim 1, wherein a ratio of (diameter of via hole) / (thickness of interlayer resin insulation layer) is 1 to 4. 7. The multilayer printed wiring board according to claim 1, wherein the conductor circuit has a thickness of less than 25 μm.