JP2003124224A - Bipolar transistor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic resistance and contact resistance in a bipolar transistor for its speeding-up, and securely connect a base region and a base electrode, and further ensure the miniaturization thereof and reduce the manufacturing cost thereof. SOLUTION: A buffer layer 109 having substantially the same impurity concentration as that of an n type subcollector 103 is formed on the n type subcollector 103, and an intrinsic base layer 111a is grown upwardly from the surface of the buffer layer 109, and a lead base layer 111b is grown horizontally from a sidewall of the base electrode 107a. Further, a base region 111 is formed by coupling the intrinsic base layer 111a and the lead base layer 111b.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a bipolar transistor, and more particularly to a bipolar transistor used in a high frequency circuit.

[0002]

2. Description of the Related Art A bipolar transistor used in a high frequency circuit has a p-type silicon substrate 3 as shown in FIG.
An n ⁺ type sub-collector 302 and an n-type sub-collector 303 composed of an epitaxial layer are formed on 01.
Further, a part of the surface of the n-type subcollector 303 includes a field oxide film 304 of a silicon oxide film, n ⁺ -type subcollector 302 n ⁺ -type subcollector 30 which is connected to
2a is formed. A silicon oxide film 305 and a silicon nitride film 306 are formed on the n-type subcollector 303, the field oxide film 304, and the n ⁺ -type subcollector 302a, and the silicon oxide film 305 and the silicon nitride film 306 have an opening 311. ing. Further, a base electrode 307 and a silicon nitride film 308 are formed on the silicon nitride film 306, and the base electrode 307 and the silicon nitride film 308 have an opening 310. The opening 311 is formed wider than the opening 310, and a part of the base electrode 307 projects into the opening 311 and the eaves portion 30.
7a is formed.

A p-type base region 312 is provided in the opening 311.
Are formed, and the base region 312 has an intrinsic base layer 3
12a and a drawing base layer 312b. The intrinsic base layer 312a is made of single crystal Si by the n-type sub-collector 30.
It is formed by epitaxially growing upward from the surface of No. 3. The extraction base layer 312b is made of polycrystalline S
It is formed by growing i downward from the lower surface of the eaves portion 307a. Here, the intrinsic base layer 312a
And the growth rate ratio of the extraction base layer 312b is 4: 1. That is, the n-type subcollector 303 and the base electrode 307
When the intrinsic base layer 312a has grown to 80% or more of the distance between the base region 312 and the intrinsic base layer 312a, the intrinsic base layer 312a and the lead-out base layer 312b grown from above and below are connected to each other, and the base region 312
Is formed.

The surface of the intrinsic base layer 312a has n
An emitter region 315 of the mold is formed, and an emitter electrode 314 is formed in contact with the surface of the emitter region 315. In addition, the base electrode 30 exposed in the opening 310
7 and the side wall of the silicon nitride film 308, a first side wall 309 made of a silicon nitride film is formed, and further a second side wall 313 made of a silicon oxide film is formed so as to cover the first side wall 309. Has been done. Further, the silicon oxide film 305, the silicon nitride film 306, the base electrode 307, and the silicon nitride film 30.
8 is formed with an opening exposing the n ⁺ type subcollector 302a, and the n ⁺ type subcollector 3 is formed in the opening.
A collector electrode 316 connected to 02a is formed.

[0005]

In such a bipolar transistor structure, the base-collector capacitance becomes large because the distance between the base electrode 307 and the n-type subcollector 303 is short. In addition, a space is required to connect the base region 312 to the eaves portion 307a, the area of the base region 312 becomes large, and the base-collector capacitance becomes large.

Further, since the lead-out base layer 312b is connected to the base electrode 307 at the eaves portion 307a with a narrow contact area, the base electrode 307 and the lead-out base layer 3 are formed.
The contact resistance with 12b is large, which hinders high-speed operation. Eaves 307a to reduce contact resistance
When is larger, the base region 312 does not grow in the inner portion of the eaves portion 307a. Therefore, there is a limit to increase the contact area between the extraction base layer 312b and the eaves portion 307a, and it is difficult to reduce the contact resistance of the base electrode 307.

As described above, since the base-collector capacitance and the contact resistance of the base electrode 307 are large, the high speed operation of the bipolar transistor is hindered. Further, the film thickness of the intrinsic base layer 312a is defined by the characteristics of the bipolar transistor, and as described above, the intrinsic base layer 31a.
From the relationship between the growth rates of 2a and the extraction base layer 312b,
The film thickness of the extraction base layer 312b is also defined. On the other hand, in the double insulating film of the silicon oxide film 305 and the silicon nitride film 306, the variation in the forming process of each film is added, and therefore the variation in the process may increase. If the thickness of the double insulating films 305 and 306 is increased due to the process variation, the intrinsic base layer 312a and the lead-out base layer 312b that grow from above and below may not be electrically connected. Further, the eaves portion 307a having a complicated structure is required for forming the base region 312, which hinders downsizing and reduction in manufacturing cost.

It is an object of the present invention to reduce the parasitic capacitance and contact resistance of a bipolar transistor to increase the speed.

Another object of the present invention is to reliably electrically connect a base region and a base electrode in a bipolar transistor. Another object of the present invention is to reduce the size and manufacturing cost of a bipolar transistor.

[0010]

A bipolar transistor according to a first aspect of the present invention includes a first electrode electrically connected to a first region and an insulating film formed on a part of the surface of the first region. A second region of the first conductivity type electrically connected to a part of the surface of the first region, and a second electrode formed on the insulating film with an opening exposing the second region. ing. Further, the bipolar transistor has a second growth layer having a first growth layer grown on the second region and a second growth layer grown on the sidewall of the second electrode in the opening and connected to the first growth layer. A third region of the mold is provided. Further, the bipolar transistor includes a fourth region of the first conductivity type which is electrically connected to the third region and a third electrode which is electrically connected to the fourth region. There is.

In this bipolar transistor, the contact area between the third region and the second region is reduced by connecting the third region (second growth layer) to the sidewall of the second electrode in the first opening. The capacitance between the third region and the second region can be reduced. Further, by increasing the thickness of the insulating film, the capacitance formed by the second electrode and the first region with the insulating film sandwiched can be reduced. Further, by increasing the film thickness of the second electrode, it is possible to increase the contact area between the second electrode and the third region and reduce the contact resistance of the second electrode. Therefore, the speed of the bipolar transistor can be increased.

Further, the third region can be surely electrically connected to the second electrode regardless of the thickness of the insulating film. Further, since it is not necessary to form the eaves portion on the second electrode, it is possible to reduce the size and manufacturing cost.

A bipolar transistor according to a second aspect of the invention is
In the bipolar transistor according to the first aspect of the invention, the insulating film is formed of a double insulating film and the second region is formed of a single crystal semiconductor.

In this case, the double insulating film is formed of a silicon oxide film, a silicon nitride film or the like, a part of the double insulating film is removed by etching to form an opening, and a third region is formed in this opening. Good.

A bipolar transistor according to a third aspect of the invention is
In the bipolar transistor according to the second aspect of the present invention, the second region has a thickness equal to or less than the thickness of the insulating film,
It has a film thickness larger than the film thickness of the growth layer. When the film thickness of the second region is selected in such a range,
The second region is not electrically short-circuited with the second electrode, and the third region can be reliably connected to the second electrode.

A bipolar transistor according to invention 4 is
In the bipolar transistor according to the first aspect of the present invention, the insulating film is formed of either a porous film or a polycrystalline film, the second region is formed by implanting impurities into the insulating film at a high concentration, and the third region is formed. The surface connected to is formed of at least a single crystal semiconductor.

In this bipolar transistor, the insulating film is formed of porous Si or the like, and the second region is formed by implanting impurities into part of the porous Si, so that the step of etching the insulating film can be omitted. . Moreover, since the surface of the second region is a single crystal, the third region can be formed from a single crystal therefrom.

A method of manufacturing a bipolar transistor according to a fifth aspect of the present invention includes a first region forming step, a first electrode forming step,
It includes an insulating film forming step, a second electrode forming step, an opening forming step, a second area forming step, a third area forming step, and a fourth area forming step. In the first region forming step, a first region of the first conductivity type is formed. In the first electrode forming step, the first electrode is formed so as to be electrically connected to the first region. In the insulating film forming step, an insulating film is formed on the surface of the first region. In the second electrode forming step, the second electrode is formed on the insulating film. In the opening forming step, an opening that penetrates the insulating film and the second electrode and exposes the first region is formed. In the second region forming step, a second region of the first conductivity type is formed on the surface of the first region exposed in the opening. The third region forming step is a step of forming a third region of the second conductivity type, and includes a first growth layer forming step and a second growth layer forming step. In the first growth layer forming step, the first growth layer is grown on the second region. In the second growth layer forming step, the second growth layer is grown on the sidewall of the second electrode in the opening so as to be connected to the first growth layer. In the fourth region forming step, the fourth region of the first conductivity type is formed so as to be electrically connected to the third region. In the third region forming step, the third electrode is formed so as to be electrically connected to the fourth region.

According to this manufacturing method, if the second region is formed to have an appropriate film thickness, the first growth layer and the second growth layer in the third region are surely connected when the third region is formed thereon. can do. Further, the bipolar transistor manufactured by this method has the same effects as the bipolar transistor according to the first aspect of the invention.

A method for manufacturing a bipolar transistor according to a sixth aspect of the present invention is the method for manufacturing a bipolar transistor according to the fifth aspect, wherein the second region forming step includes an oxide film forming step, a second region growing step, and an oxide film removing step. Is included. In the oxide film forming step, an oxide film is formed on the second electrode in the opening. In the second region growing step, the second region is grown from the first region by epitaxial growth. In the oxide film removing step, the oxide film is removed. In this case, since the side wall of the second electrode is covered with the oxide film when the second region is grown, it is possible to prevent the material forming the second region from adhering to the second electrode.

A method of manufacturing a bipolar transistor according to a seventh aspect of the present invention comprises a first region forming step, a first electrode forming step,
It includes an insulating film forming step, a second electrode forming step, an opening forming step, a second area forming step, a third area forming step, a fourth area forming step, and a third electrode forming step. First
In the area forming step, the first area of the first conductivity type is formed.
In the first electrode forming step, the first electrode is formed so as to be electrically connected to the first region. In the insulating film forming step, the first
An insulating film is formed on the region as porous Si, polycrystalline Si, polycrystalline S
It is formed of either iGe or polycrystalline SiGe: C. In the second electrode forming step, the second electrode is formed on the insulating film. In the opening forming step, while penetrating the second electrode,
An opening that exposes the insulating film is formed. In the second region forming step, the second region electrically connected to the first region is formed inside the insulating film by implanting impurities into the insulating film. The third region forming step is a step of forming a third region of the second conductivity type, and includes a first growth layer forming step and a second growth layer forming step. In the first growth layer forming step, the first growth layer is grown on the second region. In the second growth layer forming step, the first sidewall is formed on the sidewall of the second electrode in the opening.
A second growth layer is grown so as to be connected to the growth layer. In the fourth region forming step, the fourth region of the first conductivity type is formed so as to be electrically connected to the third region. A third electrode is formed so as to be electrically connected to the fourth region.

In this manufacturing method, the insulating film is made of porous Si.
And the like, and the second region is formed by implanting impurities into part of the porous Si, so that the step of etching the insulating film can be omitted. In addition, the bipolar transistor manufactured by this method is the invention 1
The same operational effects as those of the bipolar transistor according to the present invention are obtained.

A method for manufacturing a bipolar transistor according to an eighth aspect of the present invention is the method for manufacturing a bipolar transistor according to the seventh aspect, wherein in the second region forming step, part or all of the surface of the second region is monocrystallized by hydrogen annealing. It further includes a single crystallization step. By partially or entirely crystallizing the surface of the second region, the third region can be formed from the single crystal thereover.

A method for manufacturing a bipolar transistor according to a ninth aspect of the present invention is the method for manufacturing a bipolar transistor according to the eighth aspect, wherein the second region forming step is performed on a part or all of the surface of the second region prior to the single crystallization step. The method further includes an oxidation step of oxidizing a few atomic layers. By oxidizing a few atomic layers on part or all of the surface of the second region, viscous fluidity is increased and single crystallization can be promoted.

In the bipolar transistor manufacturing method according to the tenth aspect of the present invention, the second region forming step further includes the step of doping the second region with oxygen. Thereby, the dielectric constant of the second region can be lowered.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIGS. 1 to 5 are views showing a manufacturing process of a bipolar transistor according to an embodiment of the present invention, and FIG. 6 is a completed sectional view thereof.

[Structure] As shown in FIG. 6, the bipolar transistor according to the present embodiment has a p-type silicon substrate 10.
An n ⁺ -type subcollector 102 and an n-type subcollector 103 are formed on the substrate 1 by single crystal Si. A groove is formed by etching on a part of the surface of the n-type subcollector 103, and a field oxide film 104 made of a silicon oxide film is formed so as to fill the groove. Moreover, the part of the surface of the n-type subcollector 103, are heavily doped, n ⁺ -type subcollector 102a is formed to be connected to the n ⁺ -type subcollector 102.

On the n-type subcollector 103, the field oxide film 104 and the n ⁺ type subcollector 102a, a double insulating film is formed by the silicon oxide film 105a and the silicon nitride film 106a. In addition, the silicon nitride film 1
A base electrode 107a made of polycrystalline Si is formed on 06a, and a silicon nitride film 108c is formed on the base electrode 107a.

Further, the double insulating films 105a and 106a, the base electrode 107a and the silicon nitride film 108c have openings 1
N-type sub-collector 1 in the opening 110
A buffer layer 109 having a film thickness substantially the same as the film thickness of the double insulating films 105a and 106a is formed on 03.
The buffer layer 109 is formed of n-type single crystal silicon and has an impurity concentration similar to that of the n-type subcollector 103. In addition, in succession to the buffer layer 109,
The base region 111 is formed of p-type SiGe. The base region 111 is an intrinsic base layer 1 epitaxially grown upward from the surface of the buffer layer 109.
11a and the extraction base layer 111b grown in the horizontal direction from the side wall of the base electrode 107a are connected and formed. Further, a sidewall 112 of a silicon oxide film is formed in the opening 110 so as to cover the sidewall of the silicon nitride film 108c and the extraction base layer 111b. The n-type emitter region 11 is formed on the surface of the intrinsic base layer 111a not covered with the sidewall 112.
3 is formed, and the emitter electrode 114 is formed of polycrystalline Si so as to be connected to the emitter region 113. The silicon oxide film 105a, the silicon nitride film 106a, the base electrode 107a, and the silicon nitride film 108c have an opening 116 so as to expose the n ⁺ -type subcollector 102a.
Collector electrode 1 connected to ⁺ type sub-collector 102a
15 is made of polycrystalline Si.

[Manufacturing Flow] The manufacturing process of the bipolar transistor of this embodiment will be described below with reference to FIGS.

As shown in FIG. 1, p of the plane orientation (100) is
Impurity concentration of 10 ²¹ cm on the surface of the silicon substrate 101
An n ⁺ type sub-collector 102 of about ⁻³ and an impurity concentration of 10
^An n-type subcollector 103 made of an epitaxial layer having a thickness of about ¹⁸ cm ⁻³ is formed. In addition, the n-type sub-collector 10
Part of the surface of 3 is heavily doped with an n-type impurity such as As to form an n ⁺ -type subcollector 102 a so as to be connected to the n ⁺ -type subcollector 102. Further, a part of the surface of the n-type subcollector 103 is removed by etching to form a groove, and C is filled so as to fill the groove.
A silicon oxide film is formed by VD, and a field oxide film 104 is formed. Next, the n-type subcollector 103, the field oxide film 104, and the n ⁺ -type subcollector 102a
A silicon oxide film layer 105 and a silicon nitride film layer 10
6 is formed. Further, a base electrode layer 107 made of polycrystalline Si is formed on the silicon nitride film layer 106, and a silicon nitride film layer 108 is formed so as to cover the base electrode layer 107.

After that, as shown in FIG. 2, the silicon oxide film layer 105, the silicon nitride film layer 106, and the base electrode layer 1 are formed.
07 and a part of the silicon nitride film layer 108 are removed by etching, an opening 110 having a width of about 0.2 μm is formed, and the surface of the n-type subcollector 103 is exposed. Silicon oxide films 108a and 108b are formed on the surface of the n-type subcollector 103 exposed in the opening 110 and the sidewall of the base electrode layer 107, respectively. Here, the silicon oxide film 1 is formed on the n-type sub-collector 103 of single crystal silicon.
08a is formed, and the polycrystalline silicon base electrode layer 10 is formed.
A silicon oxide film 108b is formed on the substrate 7. At this time, the film thickness of the silicon oxide film 108a is about one third of the film thickness of the silicon oxide film 108b. Next, etching is performed so that only the thin silicon oxide film 108a is removed, and the surface of the n-type subcollector 103 is exposed again.

Next, as shown in FIG. 3, single crystal silicon is selectively epitaxially grown on the n-type subcollector 103 by the LPCVD method to form a buffer layer 109. Here, the buffer layer 109 is formed to have an impurity concentration of 10 ¹⁸ cm ^{−3, which} is approximately the same as that of the n-type subcollector 103, and to have the same thickness as that of the double insulating film layers 105 and 106. At this time, since the base electrode layer 107 is covered with the silicon nitride film layer 108 and the silicon oxide film 108b, single crystal silicon can be prevented from growing on the base electrode layer 107.

Next, the silicon oxide film 108b is removed by etching, and the base electrode layer 1 is formed in the opening 110.
The side wall of 07 is exposed. Then, as shown in FIG. 4, a base region 111 is formed in the opening 110 with SiGe. The base region 111 is formed by connecting the intrinsic base layer 111a made of single crystal silicon and the extraction base layer 111b made of polycrystalline silicon. The intrinsic base layer 111a is formed by epitaxially growing single crystal SiGe from the surface of the buffer layer 109, and the extraction base layer 111b is formed by growing polycrystalline SiGe horizontally from the side wall of the base electrode layer 107. . At this time, at the edge of the opening 110, the intrinsic base layer 111a and the extraction base layer 111b both grow and are connected.

The SiGe film forming method is the APCVD method or L method.
A PCVD method, a UHV-CVD method or the like can be used. In this embodiment, the UHV-CVD method is used, which can obtain a high-quality SiGe film at a low temperature. For example, the film forming temperature 5
Under conditions of 50 ° C. and a film forming pressure of 10 ⁻³ Torr, SiH ₄ , GeH _4, and B ₂ H ₆ were used as a film forming gas, the boron concentration was about 10 ¹⁹ cm ⁻³ , and the germanium concentration had a peak value of 15
Forming a base region 111 having a slope distribution of%. In this embodiment, the film thickness of the intrinsic base layer 111a is 100 n.
m.

Next, as shown in FIG. 5, a sidewall 112 that covers the sidewall of the silicon nitride film layer 108 exposed in the opening 110 and the extraction base layer 111b is formed of a silicon oxide film. In addition, the double insulating film layers 105 and 10
6, the base electrode layer 107 and a part of the silicon nitride film layer 108 are removed by etching to remove the n ⁺ -type subcollector 1.
The opening 116 that exposes 02a is formed. This allows
A silicon oxide film 105a, a silicon nitride film 106a, a base electrode 107a, and a silicon nitride film 108c are formed.

Then, polycrystalline Si is laminated and patterned so as to be connected to the surfaces of the intrinsic base layer 111a and the n ⁺ type subcollector 102a, and the emitter electrode 114 and the collector electrode 115 are formed. Further, As is ion-implanted into the emitter electrode 114 at 70 keV and 5 × 10 ¹⁵ cm ⁻² , and RTA (Rapid Thermal Ane) is applied.
by an aling process, n-type impurities are diffused from the emitter electrode 114 to the intrinsic base layer 111a to form the emitter region 113. (A) Although the thickness of the buffer layer 109 is formed to be approximately the same as the thickness of the double insulating films 105a and 106a in the above,
You may form in the following ranges. That is, the buffer layer 1
The thickness of 09 is less than or equal to the thickness of the double insulating films 105a and 106a, and is greater than or equal to the thickness of the double insulating films 105a and 106a minus the thickness of the intrinsic base layer 111a. You may. By setting the thickness of the buffer layer 109 to be equal to or less than the thickness of the double insulating films 105a and 106a,
This is because it is possible to prevent the buffer layer 109 and the base electrode 107a from coming into contact with each other and electrically short-circuiting. On the other hand, by setting the film thickness of the buffer layer 109 to be equal to or larger than the film thickness of the double insulating films 105a and 106a minus the film thickness of the intrinsic base layer 111a, the intrinsic base layer 111a and the drawn base layer 111b are reliably formed. Can be connected to. As a result, the base region 111 can be reliably electrically connected to the base electrode 107a. (B) Further, the impurity concentration of the buffer layer 109 is set to the same level as that of the n-type subcollector 103, but the impurity concentration may be lower. Although the buffer layer 109 is formed of single crystal silicon, single crystal SiGe or SiGe: C is used.
You may form by. (C) Further, the SIC layer (Selective) is provided inside the n-type subcollector 103 below the intrinsic base layer 111a.
Ion-Implanted Collector) may be formed.

[Summary] In the bipolar transistor according to the present embodiment, the base region 111 is formed in the base electrode 107.
By connecting to the side wall of a, the area of the base region 111 can be prevented from increasing and the base-collector capacitance can be reduced. Further, the double insulating film layer 105,
The base-collector capacitance can be reduced by increasing the film thickness of 106.

Further, by increasing the thickness of the base electrode 107a, the base region 111 is changed to the base electrode 107a.
The contact resistance of the base electrode 107a can be reduced by forming a large area in contact with the base electrode 107a.

By thus reducing the base-collector capacitance and the contact resistance of the base electrode 107a, it is possible to speed up the bipolar transistor. Furthermore, since SiGe that grows in the upward and horizontal directions is always connected at the edge of the opening 110, the intrinsic base layer 111 is irrespective of the film thickness of the double insulating film layers 105 and 106.
It is possible to reliably connect the a and the drawer base region 111b. Thereby, the base region 111 and the base electrode 1
07a can be surely electrically connected.

Further, it is not necessary to form a complicated eave portion on the base electrode 107a, the base region 111 is formed in a small area for downsizing, and the manufacturing process is simplified, so that the cost can be reduced. it can.

[Second Embodiment] FIGS. 7 to 9 are views showing a manufacturing process of a bipolar transistor according to an embodiment of the present invention, and FIG. 10 is a completed sectional view thereof.

[Structure] As shown in FIG. 10, the bipolar transistor according to the present embodiment has a p-type silicon substrate 2
The n ⁺ -type subcollector 202 and the n-type subcollector 203 are formed on the surface 01 of the single crystal Si. Also, n
A groove is formed by etching on a part of the surface of the mold subcollector 203, and a field oxide film 204 made of a silicon oxide film is formed so as to fill the groove.
Further, a part of the surface of the n-type subcollector 203 is heavily doped to form an n ⁺ -type subcollector 202 a so as to be connected to the n ⁺ -type subcollector 202.

On the n-type subcollector 203, the field oxide film 204 and the n ⁺ type subcollector 202a, a semiconductor film 205a as an insulating film is formed of porous Si. The thickness of the semiconductor film 205a is 500 nm, which is three times or more that of the conventional semiconductor film, and the dielectric constant is 2, which is about half that of the silicon oxide film. The semiconductor film 205a has a resistance value of 5
It is MΩ or more and satisfies the normal standard as an insulating film that the leak current is 1 μA or less when the base-collector voltage is 5V.

On the semiconductor film 205a, the polycrystalline S
A base electrode 206a is formed of i, and a silicon nitride film 207a is formed on the base electrode 206a. The semiconductor film 205a, the base electrode 206a, and the silicon nitride film 207a have an opening 208 and an opening 209. The opening 208 is formed leaving a part of the semiconductor film 205a, and the opening 209 is formed so as to expose the surface of the n ⁺ type subcollector 202a.
Further, in the opening 208, a part of the semiconductor film 205a is heavily doped with impurities, so that the low resistance region 205b is formed.
Are formed.

In the opening 208, the semiconductor film 205a
A base region 210 is formed on the low resistance region 205b. In the base region 210, the intrinsic base layer 210a epitaxially grown upward from the surface of the semiconductor film 205a and the extraction base layer 210b horizontally grown from the side wall of the base electrode 206a are connected to each other in the opening 208. Has been formed. The intrinsic base layer 210a and the n-type subcollector 203 form the low resistance region 2
It is electrically connected via 05b.

Further, a sidewall 211 is formed of a silicon oxide film so as to cover the sidewall of the silicon nitride film 207a exposed in the opening 208 and the extraction base layer 210b.
Are formed. An n-type emitter region 212 is formed on the surface of the intrinsic base layer 210a which is not covered with the side wall 211, and an emitter electrode 213 is formed of polycrystalline Si so as to be connected to the emitter region 212. . In the opening 209, a collector electrode 214 connected to the n ⁺ type sub-collector 202a is formed of polycrystalline Si.

[Manufacturing Flow] Hereinafter, the manufacturing process of the bipolar transistor of the present embodiment will be described with reference to FIGS.

As shown in FIG. 7, p of the plane orientation (100) is
Impurity concentration of 10 ²¹ cm
^-3 n ⁺ type sub-collector 202 and impurity concentration 10
^An n-type subcollector 203 composed of an epitaxial layer having a thickness of about ¹⁸ cm ⁻³ is formed. In addition, the n-type sub-collector 20
A part of the surface of 3 is heavily doped with an n-type impurity such as As to form an n ⁺ -type subcollector 202 a so as to be connected to the n ⁺ -type subcollector 202. Further, a part of the surface of the n-type subcollector 203 is removed by etching to form a groove, and C is filled so as to fill the groove.
A silicon oxide film is formed by VD, and a field oxide film 204 is formed. Also, the n-type subcollector 203, the field oxide film 204, and the n ⁺ -type subcollector 202a
A semiconductor film layer 205 of porous Si is formed thereon.

The film thickness of the semiconductor film layer 205 is 500 times as large as three times or more than the conventional one in order to reduce the base-collector capacitance.
nm. Moreover, the impurity concentration of porous Si is set to 1 × 1.
It is formed to be 0 ¹¹ cm ^-3 or less. In order for porous Si to function as an insulating film, the specific resistance of porous Si is 1 × 10 ⁴ Ω.
Must be at least cm. Porous Si has a resistivity of 2 × 10 ⁵ Ωcm and an impurity concentration of 1 × 1 when the impurity concentration is intrinsic (1.5 × 10 ¹⁰ cm ⁻³ ).
When it is 0 ¹¹ cm ^−3, the specific resistance is 1 × 10 ⁴ Ωcm. Therefore, the semiconductor film layer 205 having a specific resistance of 1 × 10 ⁴ Ωcm or more can be formed by controlling the impurity concentration of porous Si to be 1 × 10 ¹¹ cm ⁻³ or less. At this time, the dielectric constant of the semiconductor film layer 205 is 2, which is about half that of the silicon oxide film. Further, if the semiconductor film layer 205 is doped with oxygen, the dielectric constant can be further reduced.

Next, as shown in FIG. 8, the semiconductor film layer 20
A base electrode layer 206 of polycrystalline silicon is formed on the substrate 5, and a silicon nitride film layer 207 is formed so as to cover the base electrode layer 206. Subsequently, the semiconductor film layer 205 and the base electrode layer 206 are formed so that part of the semiconductor film layer 205 remains.
Then, the opening 208 is formed by etching the silicon nitride film layer 207. Subsequently, 600 to 1100 in an atmosphere with a vacuum degree of about 10 Torr with a small amount of hydrogen attached.
Anneal at ℃. By this annealing, silicon is fluidized on the surface of the semiconductor film layer 205 to fill the holes, and at the same time, the surface is crystallized. Note that the surface of the semiconductor film layer 205 may be single-crystallized by performing hydrogen annealing after oxidizing only a few atomic layers on the surface of the semiconductor film layer 205 in the opening 208. Further, the surface of the semiconductor film layer 205 exposed in the opening 208 is heavily doped with an n-type impurity such as As to form the low resistance region 205b.

Next, as shown in FIG. 9, a base region 210 is formed of SiGe in the opening 208. Single crystal SiGe is grown upward from the surfaces of the single crystallized semiconductor film layer 205 and the low resistance region 205b to form the intrinsic base layer 210a, and the base electrode layer 206 and the semiconductor film layer 205 are horizontally extended from the sidewalls. Polycrystalline SiGe is grown to form the extraction base layer 210b. At the edge of the opening 208, the intrinsic base layer 210a and the drawn base layer 210b are formed.
Grow together and are surely connected. The film forming conditions for the base region 210 of SiGe are the same as those described in the first embodiment. Further, a sidewall 211 is formed of a silicon oxide film so as to cover the silicon nitride film layer 207 and the extraction base layer 210b exposed in the opening 208. In addition, the semiconductor film layer 205 and the base electrode layer 206
Then, the silicon nitride film layer 207 is etched to form an opening 209 exposing the n ⁺ type subcollector 202a.
As a result, the semiconductor film 205a, the base electrode 206a, and the silicon nitride film 207a are formed.

Next, as shown in FIG. 10, polycrystalline Si is laminated and patterned so as to be connected to the surfaces of the intrinsic base layer 210a and the n ⁺ type subcollector 202a, and an emitter electrode 213 and a collector electrode 214 are formed. To do. Further, As is applied to the emitter electrode 213 at 70 keV, 5 × 1.
Ion implantation at 0 ¹⁵ cm ^-2 , RTA (Rapid Th
The emitter region 212 is formed by diffusing an n-type impurity from the emitter electrode 213 to the intrinsic base layer 210a by an optical annealing process. (A) Although the present embodiment has been described based on the silicon substrate, SiC, GaN, InP, GaAs, or the like may be used. (B) Further, in the above embodiment, the semiconductor film layer 205 is formed of porous Si, but it may be formed of porous silicon or a polycrystalline film, particularly a porous film or a polycrystalline film of Si, SiGe, SiGe: C. it can. Here, the polycrystal includes microcrystals.

[Summary] In the bipolar transistor according to the present embodiment, the base region 210 is formed in the base electrode 206.
By connecting to the side wall of a, the area of the base region 210 can be prevented from increasing and the base-collector capacitance can be reduced. Further, the base-collector capacitance can be reduced by increasing the thickness of the semiconductor film 205a as the insulating film.

Further, by increasing the thickness of the base electrode 206a, the base region 210 becomes smaller than the base electrode 206a.
It is possible to reduce the contact resistance of the base electrode 206a by forming a large area in contact with the base electrode 206a.

By thus reducing the base-collector capacitance and the contact resistance of the base electrode 206a, it is possible to speed up the bipolar transistor. Furthermore, since SiGe that grows in the upward and horizontal directions is always connected at the edge of the opening 208, the semiconductor film 20
It is possible to reliably connect the intrinsic base layer 210a and the drawn base layer 210b regardless of the film thickness of 5a. As a result, the base region 210 and the base electrode 206a can be reliably electrically connected.

Further, it is not necessary to form a complicated eaves portion on the base electrode 206a, the base region 210 is formed in a small area for downsizing, and the manufacturing process is simplified to reduce the cost. it can.

[0058]

According to the present invention, the capacitance between the base and the collector and the contact resistance of the base electrode can be reduced,
The speed of the bipolar transistor can be increased.

Further, according to the present invention, the base region and the base electrode can be surely electrically connected. Further, according to the present invention, it becomes easy to form a film on the base region,
It is possible to reduce the size and manufacturing cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) for explaining the manufacturing flow of the bipolar transistor according to the first embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) for explaining the manufacturing flow of the bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view (3) explaining the manufacturing flow of the bipolar transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view (4) for explaining the manufacturing flow of the bipolar transistor according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view (5) for explaining the manufacturing flow of the bipolar transistor according to the first embodiment of the present invention.

FIG. 6 is a completed cross-sectional view of the bipolar transistor according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view (1) for explaining the manufacturing flow of the bipolar transistor according to the second embodiment of the present invention.

FIG. 8 is a sectional view (No. 2) for explaining the manufacturing flow of the bipolar transistor according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view (3) explaining the manufacturing flow of the bipolar transistor according to the second embodiment of the present invention.

FIG. 10 is a completed cross-sectional view of the bipolar transistor according to the second embodiment of the present invention.

FIG. 11 is a completed sectional view of a conventional bipolar transistor.

[Explanation of symbols]

101, 201 p-type silicon substrate 102, 102a, 202, 202a n ⁺ -type subcollector 103, 203 n-type subcollector 104, 204 field oxide film 105 silicon oxide film 106 silicon nitride film 107, 206 base electrode 108, 207 silicon nitride Films 108a, 108b Silicon oxide film 109 Buffer layers 110, 116, 208, 209 Openings 111, 210 Base regions 111a, 210a Intrinsic base layers 111b, 210b Lead-out base layers 112, 211 Side walls 113, 212 Emitter regions 114, 213 Emitter electrodes 115, 214 collector electrode 205 semiconductor film layer

Claims (4)

[Claims] 1. A first region of a first conductivity type, a first electrode electrically connected to the first region, and an insulating film formed on a part of the surface of the first region. A second region of the first conductivity type electrically connected to a part of the surface of the first region, and a second electrode formed on the insulating film with an opening exposing the second region. A first growth layer grown on the second region, and a second growth layer grown on the sidewall of the second electrode in the opening and connected to the first growth layer. A third region, a fourth region of the first conductivity type electrically connected to the third region, and a third electrode electrically connected to the fourth region. Bipolar transistor equipped. 2. The bipolar transistor according to claim 1, wherein the second region is formed of a single crystal semiconductor. 3. The second region has a thickness equal to or less than a thickness of the insulating film and equal to or greater than a thickness obtained by subtracting a thickness of the first growth layer from a thickness of the insulating film. The bipolar transistor according to claim 2. 4. The insulating film is formed of either a porous film or a polycrystalline film, and the second region is formed by implanting impurities into the insulating film at a high concentration, and the third region is formed. The bipolar transistor according to claim 1, wherein the surface connected to the region is formed of at least a single crystal semiconductor.