JP2003108541A - Processor, memory test method and memory test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor, a memory test method, and a memory test system capable of an operation test of a built-in data memory by a passage similar to a case of making access to the built-in data memory at ordinary operation time (command executing time). SOLUTION: In a processor 1, a program executing command code 5a is supplied to a selecting means (MUXC) 8 via an instruction register (IR) 5 from a program memory 3, and a memory test executing pseudo-command code 7a is supplied to the selecting means (MUXC) 8 from a test circuit 7. When executing a test of the data memory 2, the selecting means 8 selects the pseudo- command code 7a, and supplies the code to a decoder 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor having a test circuit for a built-in data memory, a memory test method for a semiconductor device having a built-in data memory, and a memory test system for a semiconductor device having a built-in data memory.

[0002]

2. Description of the Related Art When an operation test of a memory such as a data memory built in a semiconductor device such as a processor is performed, an external terminal that can directly control the memory such as the data memory is provided on the chip of the semiconductor device such as the processor. A test signal was directly input from the outside to directly test a memory such as a data memory.

[0003]

However, in the semiconductor device such as a processor which adopts the conventional method, the path of each test signal when the operation test of the data memory is executed actually drives the semiconductor device such as the processor. Since this is different from the case of accessing the built-in data memory, there is a problem in that it is not possible to detect a defect on the path between the core unit of the processor (central part of the processor including the control unit) and the data memory.

The present invention has been made in view of the above circumstances, and an object thereof is to perform an operation test of the internal memory by the same route as when accessing the internal memory during normal operation (when executing an instruction). To provide a possible processor.

Another object of the present invention is, in a memory test method for a semiconductor device having a built-in memory, to access a data memory to be tested by using the same path as a normal operation path in the semiconductor device. By
An object of the present invention is to provide a highly reliable memory test method for a semiconductor device.

Another object of the present invention is to provide, in a memory test system for a semiconductor device having a built-in memory, a path that is the same as a path during normal operation (instruction execution) of the semiconductor device even during test execution. In order to provide a highly reliable memory test system for a semiconductor device by accessing the data memory to be tested.

[0007]

A processor according to a first aspect of the present invention is a processor including a data memory and a program memory, a decoder for decoding an instruction code of the program memory, and a pseudo instruction for testing the data memory. A test circuit that outputs a code and a selection unit that selects one of the instruction code and the pseudo instruction code are included. The selection unit selects the instruction code when executing an instruction and the pseudo instruction code when performing a test. It is characterized in that it is configured to be provided to the decoder.

A processor according to a second aspect of the present invention is the processor according to the first aspect, wherein the selecting means receives the instruction code and the pseudo instruction code as input, and outputs the instruction code when the instruction is executed.
The multiplexer is characterized in that it is a multiplexer which selects each pseudo instruction code and gives it to the decoder during the test execution.

A processor according to a third invention is characterized in that, in the first invention or the second invention, the processor comprises an address register for storing an access address to the data memory at the time of executing the test.

A memory test method according to a fourth aspect of the present invention is a memory test method in a semiconductor device including a data memory, a program memory, and a test circuit, wherein an instruction code output from the program memory and an output from the test circuit. Selecting means for selecting one of the pseudo instruction codes to be performed, and the selecting means tests the data memory by selecting the pseudo instruction code at the time of test execution.

A memory test system according to the fifth invention is
In a memory test system in a semiconductor device including a data memory, a program memory, and a test circuit, an instruction code output from the program memory and a pseudo instruction code output to test the data memory from the test circuit It is characterized in that it comprises a selecting means for selecting and outputting any one of them, and the selecting means is configured to select the instruction code at the time of instruction execution and the pseudo instruction code at the time of test execution.

According to the first aspect of the present invention, the instruction code is selected when the instruction is executed and the pseudo instruction code is selected and output to the decoder when the test is executed, and the pseudo instruction code for testing the data memory is output to the decoder inside the processor. Since it is supplied, the data memory to be tested can be accessed through the same path as the path during normal operation (instruction execution) in the processor even during test execution,
The data memory access operation test can be performed under the same conditions as the actual processor operation.

In the second aspect of the invention, since the selecting means is constituted by the multiplexer, it is possible to switch between the instruction code and the pseudo instruction code with a simple structure.

In the third aspect of the invention, since the address register for storing the access address to the data memory is provided at the time of test execution, the data memory can be easily accessed at the time of test execution, and continuous writing and reading are performed. Is possible.

According to a fourth aspect of the present invention, there is provided a selecting means for selecting and outputting either the instruction code or the pseudo instruction code, and the selecting means selectively outputs the pseudo instruction code at the time of test execution to test the data memory. Since the test method is used, the data memory to be tested can be accessed through the same route as the route during normal operation (instruction execution) of the semiconductor device even during test execution, and in the same situation as the actual operation of the semiconductor device. It is possible to test the access operation of the data memory.

According to a fifth aspect of the invention, in a memory test system for a semiconductor device, there is provided a selecting means for selectively outputting either an instruction code output from a program memory or a pseudo instruction code output from a test circuit, and at the time of executing an instruction. Since the instruction code is configured to select and output the pseudo instruction code at the time of test execution, even at the time of test execution, the data of the test target is subjected to the same path as the normal operation (instruction execution) path of the semiconductor device. The memory can be accessed, and the access operation test of the data memory can be performed in the same situation as the actual operation of the semiconductor device.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 1 is a main block diagram of a processor according to the present invention. In the figure, reference numeral 1 is a processor or a semiconductor device, specifically, for example, a DSP (digital signal processor) or the like. The processor 1 has a data memory 2, a program memory 3, a processor core unit 4, an instruction register (IR) 5, a decoder 6, a test circuit 7, a selection unit (MUXC) 8 and a memory bus interface 9 as main components.

A data memory write bus 2W and a data memory read bus 2R are arranged between the data memory 2 and the memory bus interface 9. Data memory 2
A data memory address bus 4 a is arranged between the processor core unit 4 and the processor core unit 4. The data memory 2 further includes a data memory A (2A) and a data memory B (2B) (hereinafter may be simply referred to as the data memory A and the data memory B, or the data memory 2A and the data memory 2B).
2 data memories (see FIG. 4).
The program memory 3 stores the instruction code of the program necessary for operating the processor 1, and the program memory 3 outputs a program signal 3a including the instruction code of the program to the instruction register 5.

The instruction register 5 reads the instruction code of the program memory 3 and temporarily holds it. The instruction code 5a output from the instruction register 5 is input to the selecting means 8. The pseudo instruction code 7a output from the test circuit 7 is also input to the selection unit 8. The selecting means 8 selects either the instruction code 5a or the pseudo instruction code 7a and outputs it to the decoder 6, and is composed of a multiplexer (MUXC). In the processor core unit 4, a processor write bus 4W and a processor read bus 4R are arranged between the memory bus interface 9. The test write data 7b is also output from the test circuit 7 to the processor write bus 4W. The test circuit 7 includes a processor 1
The test mode enable signal 7c and the test circuit control command 7d are input from the external terminal of the control circuit 7 to control the test function (test mode). An external memory (not shown) is connected to the memory bus interface 9, and the external memory write bus 9W and the external memory read bus 9 are connected.
R is placed.

FIG. 2 is a main block diagram of the processor core unit according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, the instruction code 5a from the instruction register 5 and the pseudo instruction code 7a from the test circuit 7 are the selection means 8
, The test mode signal TST from the test circuit 7
One is selected according to the MODE and is output to the decoder 6. The test mode signal TSTMODE is logic "1".
Then, it becomes active and enters the test mode operation, that is, the test execution mode, and the pseudo instruction code 7a is selected by the selecting means 8. Test mode operation (test execution)
Time is always logical "1". Test mode signal TST
MODE is a logic "0", and the test mode is non-operation, that is, the normal mode operation (instruction execution), and the instruction code 5a is selected by the selection means 8. Test mode signal T
STMODE is a multiplexer for other parts (for example,
(MUXA, MUXB, etc. in FIG. 5) are also input and similar switching is performed.

The processor core unit 4 includes a decoder 6, an address register (a0) 42 and an address register (a
4) An address generator 41 including 43 is provided. The address register (a0) 42 holds an access address for the data memory A, and the address register (a4) 43
Holds an access address for the data memory B. The address register (a0) 42 receives the address register (a0) reference input ADR-A, and the address register (a4) 43 receives the address register (a4) reference input A.
DR-B is output to each test circuit 7. The address register (a0) reference input ADR-A is an input for referring to which address is being accessed at the time of performing a read test or a write test on the data memory A. The reference input ADR-B is an input for referring to what address is being accessed at the time of performing a read test or a write test on the data memory B.

The decoder 6 decodes the instruction content of the pseudo instruction code 7a. The pseudo-instruction code 7a includes a pseudo-instruction for executing three operations in parallel: "memory access (read, write)", "address operation", and "update of address data". , The address register (a0) for the data memory A (see FIG. 4)
Data memory B at the address indicated by 42 (see FIG. 4)
The memory access (reading and writing) is performed at the address indicated by the address register (a4) 43. In parallel with the memory access, in the address generation unit 41, an address calculation unit (not shown) calculates an address and updates the address. Since the address is updated, "the value next to the address register (a0) 42 is calculated, and the result is stored in the address register (a0) 42", "the next value to be entered into the address register (a4) 43 is calculated. , Store result in address register (a4) 43 ”
The action of doing can also be performed. The test circuit 7
This pseudo instruction is continuously issued to the processor core unit 4 the designated number of times. As a result, the address generator 4
Continuous writing and reading can be executed by using the address register (a0) 42 and the address register (a4) 43 in 1.

From the processor core unit 4, the processor write bus A (BDA-W) and the processor write bus B (BD) corresponding to the processor write bus 4W in FIG.
B-W) is output. In addition, the processor core unit 4 includes
A processor read bus A (BDA-R) and a processor read bus B (BDB-R) corresponding to the processor read bus 4R in FIG. 1 are input. The processor write bus A (BDA-W) is a bus for transferring data from the processor core unit 4 to the data memory A, the data memory B, an external memory (not shown), and the processor write bus B (BDB-B). -W) is a data memory B,
An external memory (not shown) or the like is provided with the processor core unit 4
A processor read bus A (BDA-R) for transferring data from the data memory A, the data memory B, an external memory (not shown), etc. to the processor core unit 4. The processor read bus B (BDB-R) is a bus for transferring data from the data memory B, an external memory (not shown), etc. to the processor core unit 4, and these are mainly used. Signals are exchanged with a predetermined corresponding portion via the memory bus interface 9.

From the processor core unit 4, the data memory A address 4aA and the data memory A read signal 4aA-
R, data memory A write signal 4aA-W is output to data memory A, and data memory B address 4a
B, the data memory B read signal 4aB-R, and the data memory B write signal 4aB-W are output to the data memory B. These correspond to those abbreviated as the data memory address bus 4a in FIG.

FIG. 3 is an explanatory view of main functions of the test circuit according to the present invention. The same parts as those in FIG. 1 and the like are designated by the same reference numerals and the description thereof will be omitted. In the figure, the terminals of the test circuit 7 are shown. In principle, the pin name is used, but it may be used as it is as the signal name. The terminal INST corresponds to the pseudo instruction output output to the selection unit 8 (MUXC) of the processor core unit 4, that is, the pseudo instruction code 7a in FIG. The terminal TESTMODE is connected to the test mode signal T
ESTMODE multiplexer (MUXA to MUX
It is output to C) and the like, and each multiplexer is switched as needed during test execution. Terminal ADR-A, ADR-B
Inputs the access addresses of the address register (a0) 42 and the address register (a4) 43, respectively.
The terminals DMI-A and DMI-B are connected to the data memories A and A, respectively.
Data in the data memory B is transferred to the processor read bus A
(BDA-R), processor read bus B (BDB-
It is input to the test circuit 7 via R) and taken in.

The terminals DOUT-A and DOUT-B output write data from the test circuit 7 to the data memory A and the data memory B, and the multiplexers MUXA and MUX.
Output to UXB (see FIG. 5), and data memory A, data memory B via memory bus interface 9
Write data is written in. The terminal TSTDI is connected to the external memory read bus 9R from the outside of the processor 1.
Data necessary for the test is input to the test circuit 7 through the processor read bus A (BDA-R) (FIG. 1). The data necessary for the test includes, for example, a test start address, a test end address, write test data,
These are read comparison test data and the like. In addition, processor 1
When a terminal dedicated to the terminal TSTDI is provided in the input terminal, input can be performed without using the external memory read bus 9R.

Terminals XRE-A, XWE-A, XRE-
B and XWE-B are a read permission signal of the data memory A, a write permission signal of the data memory A, and a data memory B, respectively.
And a write enable signal for the data memory B are output. Both are logic "0" and are in the read enable state and the write enable state. The permission state is defined by the input to the OR circuits (7a to 7d) shown in FIG.

The terminal CNT inputs a test circuit control command (corresponding to 7d in FIG. 1) from the test circuit control command external terminal TCCC of the processor 1. This allows the test circuit 7 to execute a desired operation. An example of the test circuit control command is shown below. Command code (not shown below) "0000" for "unused", "00"
"01" means "memory configuration initialization", "0010" means "set start address 0 (internal register of test circuit 7)", "0011" means "set start address 1 (internal register of test circuit 7)", "0100" sets "end address 0 (internal register of test circuit 7)", "0101" sets "end address 1 (internal register of test circuit 7)", "0110" loads "offset data 0" , "0111" for "load offset data 1", "1000" for "mode set A", "1001" for "mode set B", "1"
"010" for "mode set AB", "1011" for "mode set counter", "1100" for "write data set (internal register of test circuit 7)", "110".
"1" means "write", "1110" means "read + compare",
“1111” is “unused” or the like.

The processor 1 is connected to the terminal TSTMODEN.
A test mode enable signal (corresponding to 7c in FIG. 1) is input from the external terminal TE for test mode enable of, and the logic "1" shifts from the normal mode operation to the test mode operation to enable the test circuit 7 to operate. Become. Terminal ER
RA and ERR-B output the error occurrence display flags in the data memory A and data memory B to the error display external terminals ED-A and ED-B, respectively. For example, a logic "1" is used to indicate that an error has occurred.

FIG. 4 is an explanatory view of main signals of the data memory according to the present invention. The same parts as those in FIG. 1 and the like are designated by the same reference numerals and the description thereof will be omitted. Note that general terminals such as clock and reset are omitted. In the figure,
The data memory 2 is composed of, for example, two systems, a data memory A (2A) and a data memory B (2B).
From the processor core unit 4, as described above, the data memory A address 4aA and the data memory A read signal 4aA.
-R, data memory A write signal 4aA-W is output to data memory A, and data memory B address 4a
B, the data memory B read signal 4aB-R, and the data memory B write signal 4aB-W are output to the data memory B. As described above, the terminal XRE-A of the test circuit 7,
The XWE-A, XRE-B, and XWE-B output a read permission signal for the data memory A, a write permission signal for the data memory A, a read permission signal for the data memory B, and a write permission signal for the data memory B, respectively. . The OR circuit 7a includes a data memory A read signal 4aA-R and a terminal XR.
A read enable signal of the data memory A from EA, a write enable signal 4aA-W of the data memory A to the OR circuit 7b and a write enable signal of the data memory A from the terminal XWE-A, and a data memory of the OR circuit 7c. B read signal 4a
A read enable signal of the data memory B from B-R and the terminal XRE-B, and a data memory B write signal 4aB-W and a data memory B from the terminal XWE-B to the OR circuit 7d.
Write enable signals are input to control input during test execution.

In the data memory A, the data memory A
The read bus DDIA-R is the memory bus interface 9
And the data memory A write bus DDIA-W is input from the memory bus interface 9. In the data memory B, the data memory B read bus DDIB-
R is output to the memory bus interface 9, and the data memory B write bus DDIB-W is input from the memory bus interface 9. Data memory A read bus DD
The IA-R is a bus for transferring the data read from the data memory A to the processor core unit 4, and the data memory A write bus DDIA-W is the processor core unit 4.
From the data memory A to the data memory A. The data memory B read bus DDIB-R is a bus for transferring the data read from the data memory B to the processor core unit 4, and the data memory B write bus D
The DIB-W is the data memory B from the processor core unit 4.
Is a bus for transferring data to.

FIG. 5 is a main route diagram of the memory bus interface according to the present invention. The same parts as those in FIG. 1 and the like are designated by the same reference numerals and the description thereof will be omitted. From the processor core unit 4, the processor write bus A (BDA-
W) and the processor write bus B (BDB-W) are input to one input ends of the multiplexers MUXA and MUXB, respectively. Terminals DOUT-A and DOU of the test circuit 7 are connected to the other input ends of the multiplexers MUXA and MUXB.
Write data (corresponding to 7b in FIG. 1) to the data memory A and the data memory B is input from T-B. The multiplexers MUXA and MUXB are connected to the test mode signal TE.
Either input is selected according to STMODE. The outputs of the multiplexer MUXA are the data memory A write bus DDIA-W and the external memory write bus OD (9
W), the processor read bus A (BDA-R), etc. The output of the multiplexer MUXB is the data memory B write bus DDIB-W, the external memory write bus OD (9W), the processor read bus B (BDB-R).
Etc. are output.

The external memory write bus OD (9W) is
It is a bus for transferring write data from the processor 1 to an external memory (not shown). The external memory read bus ID (9R) is a bus for transferring the data read from the external memory (not shown) to the inside of the processor 1. The external memory read bus ID (9R) is the processor read bus A (BDA-R) via the switching means.
And processor read bus B (BDB-R). The processor read bus A (BDA-R) is connected to the terminals DMI-A and TSTDI of the test circuit 7 as described above. Processor read bus B (BDB-R)
Is connected to the terminal DMI-B of the test circuit 7 as described above. The data memory A read bus DDIA-R is
The processor read bus A (BDA-R), the data memory B read bus DDIB-R are connected to the processor read bus A (BDA-R) and the processor read bus B (BDB).
-R). It should be noted that a switching means for various signals is provided between these connections as required, and the signal path is appropriately switched according to the switching of the test mode.

FIG. 6 is a basic operation flow of the test circuit according to the present invention. The same parts as those in FIG. 1 and the like are designated by the same reference numerals and the description thereof will be omitted. In the flowchart, the data memory is simply referred to as a memory. A logic "1" (1 bit) is input as the test mode enable signal 7c to activate the test mode (step S
1). Test circuit control command (hereinafter simply "COMM
AND)) = 0001 (4 bits) is input, and at the same time, the value to be set in the wait register is input to TSTDI to initialize the memory configuration (step S
2). COMMAND = 0010 (4 bits) is input, at the same time, the start address is input to TSTDI,
The start address of the memory A test is set (step S3). COMMAND = 0011 (4 bits) is input, and at the same time, the start address is input to TSTDI to set the start address of the memory B test (step S4). COMMAND = 0100 (4 bits)
Is input, and at the same time, the end address is input to TSTDI to set the end address of the memory A test (step S5). COMMAND = 0101 (4 bits) is input, and at the same time, the end address is input to TSTDI to set the end address of the memory B test (step S6).

COMMAND = 0110 (4 bits) is input, and at the same time, an offset value is input to TSTDI.
An offset value for updating the address of the memory A test is set (step S7). COMMAND = 0111 (4 bits) is input and at the same time, the offset value is input to TSTDI to set the offset value for updating the address of the memory B test (step S8). COMMAND = 110
Input 0 (4 bits) and write data to TSTDI at the same time to set test write data (step S9). COMMAND corresponding to the write mode is input to set the write mode (step S10).
For example, the type of write mode is “COMMAND = 10
At 00 (4 bits), the test write data set in step S9 is continuously written. COMMAND = 1
At 001 (4 bits), the bit inversion of the test write data set in step S9 is continuously written. CO
If MMAND = 1010 (4 bits), step S9
Alternately write the test write data set in and its bit inversion. , Etc. COMMAND = 101
With 1 (4 bits), the counter value is written.

COMMAND = 1101 (4 bits) is input, writing is performed in the memory in the set address range, and test writing is started (step S11). When the value of the address register matches the set end address, the writing ends (write enable signal XWE-A
And both XWE-B become logic "1" and end.
COMMAND = 1111 (4 bits) is input, and one dummy cycle is input (step S1).
2). Input COMMAND according to the read mode,
The read mode is set (step S13). COMM
Input AND = 110 (4 bits) to start reading (step S14). An error is judged by checking the expected value at the same time as reading (step S1).
5) If there is an error, the error display external terminal ED-A
Alternatively, ED-B is set to logic "1" and an error is displayed (step S16). The memory in the set address range is read, and when the value of the address register matches the set end address, the reading is ended (both read enable signals XRE-A and XRE-B become logic "1"). If so, the test ends (step S17).

[0037]

As described in detail above, according to the first aspect of the present invention, at the time of test execution, the data memory to be tested is accessed through the same path as the path during normal operation of the processor (when executing instructions). Therefore, the access operation test of the data memory can be performed in the same situation as the actual operation of the processor. Therefore, since it is not necessary to directly input the data memory address and the write data from the outside, the number of terminals can be reduced as compared with the method of directly accessing the data memory from the outside, and it is not necessary to provide an address arithmetic circuit dedicated to the test. The circuit scale in the processor can be reduced.
Furthermore, it is possible to provide a processor having a built-in test circuit that can easily detect a defect on the path between the core unit of the processor and the data memory.

According to the second aspect of the invention, since the selecting means is constituted by the multiplexer, it is possible to provide a processor which can easily switch between the instruction code and the pseudo instruction code.

In the third invention, since the address register for storing the access address to the data memory at the time of test execution is provided, it is easy to access the data memory at the time of test execution, and continuous writing and reading are performed. It is possible to provide a processor that can do this.

In the fourth aspect of the invention, the selecting means for selecting and outputting either the instruction code or the pseudo instruction code is a memory test method for selecting and outputting the pseudo instruction code at the time of test execution to test the data memory. During test execution, the data memory to be tested can be accessed through the same path as the normal operation (instruction execution) of the semiconductor device, and the data memory can be accessed in the same situation as the actual operation of the semiconductor device. It becomes possible to perform an operation test, and it is possible to provide a memory test method capable of easily detecting a defect on the path between the processor core and the data memory.

According to a fifth aspect of the invention, in a memory test system for a semiconductor device, there is provided a selection means for selectively outputting either an instruction code output from a program memory or a pseudo instruction code output from a test circuit, and at the time of executing an instruction. Since the instruction code is configured to select and output the pseudo instruction code at the time of test execution, even at the time of test execution, the data of the test target is subjected to the same path as the normal operation (instruction execution) path of the semiconductor device. It is possible to provide a memory test system in a semiconductor device that can access a memory and can perform an access operation test of a data memory in a situation similar to the actual operation of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a main block diagram of a processor according to the present invention.

FIG. 2 is a main block diagram of a processor core unit according to the present invention.

FIG. 3 is an explanatory diagram of main functions of a test circuit according to the present invention.

FIG. 4 is an explanatory diagram of main signals of a data memory according to the present invention.

FIG. 5 is a main route diagram of a memory bus interface according to the present invention.

FIG. 6 is a basic operation flow of the test circuit according to the present invention.

[Explanation of symbols]

1 processor 2 data memory 3 program memory 3a Program signal 4 Processor core part 5 Instruction register 5a instruction code 6 decoder 7 Test circuit 7a Pseudo instruction code 8 selection means 9 Memory bus interface 42 and 43 address registers

Claims (5)

[Claims] 1. A processor including a data memory and a program memory, a decoder for decoding an instruction code of the program memory, and a test circuit for outputting a pseudo instruction code for testing the data memory.
Selecting means for selecting one of the instruction code and the pseudo instruction code, and the selecting means selects the instruction code at the time of executing an instruction and the pseudo instruction code at the time of performing a test, and supplies the selected pseudo instruction code to the decoder. A processor characterized by having done. 2. The multiplexer is a multiplexer which receives the instruction code and the pseudo instruction code as input, selects the instruction code when the instruction is executed, and selects the pseudo instruction code when the test is executed and gives the decoder to the decoder. The processor of claim 1 characterized. 3. The processor according to claim 1, further comprising an address register that stores an access address to the data memory when the test is executed.
Processor described in. 4. A data memory, a program memory,
In a memory test method for a semiconductor device including a test circuit, a selection means for selecting either an instruction code output from the program memory or a pseudo instruction code output from the test circuit is provided, and the selection means performs a test. A memory test method, wherein the data memory is tested by selecting the pseudo instruction code during execution. 5. A data memory, a program memory,
In a memory test system in a semiconductor device including a test circuit, either an instruction code output from the program memory or a pseudo instruction code output from the test circuit to test a data memory is selected and output. A memory test system comprising: a selecting means, wherein the selecting means is configured to select the instruction code when executing an instruction and the pseudo instruction code when performing a test.