JP2003199329A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supply a step-up voltage with suppressed excessive step-up by constantly optimizing the current supply capacity when the step-up circuit is in a binary control state. <P>SOLUTION: The step-up system circuit is provided with: a step-up circuit 12 that generates a step-up voltage, upon receiving a drive pulse of an oscillator 11 that generates N types of drive pulses having a certain intrinsic frequency; a capacity 14 for stabilizing the step-up voltage; and a voltage detection circuit that detects the size of the step-up voltage and controls the operating state of the oscillator. A circuit 16, having the function of detecting the operating state of the load circuit, is connected between the output of the step-up circuit and the load circuit 10 of the step-up circuit, which has the function of actively adjusting the current supply capacity of the step-up circuit, based on the detected result. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a booster circuit, which is used for a nonvolatile semiconductor memory such as a flash memory.

[0002]

2. Description of the Related Art FIG. 15 shows the structure of a conventional booster circuit incorporated in a semiconductor integrated circuit.

Reference numeral 11 is an oscillator, and 121 to 12N are N to which drive pulses having a predetermined phase difference are supplied from the oscillator 11, respectively.
The plurality of booster circuit cells are included in the booster circuit 12.

Reference numeral 13 denotes a booster circuit output node in which the boosted outputs of the N booster circuit cells 121 to 12N are combined, and 14 is a stabilizing capacitor (pool capacitor; for stabilizing the boosted output of the booster circuit output node 13). Pool Capacitors) and 10 are load circuits connected to the booster circuit output node 13.

Reference numeral 15 is a voltage detection circuit which detects whether or not the boosted output of the booster circuit output node 13 has reached a target voltage, and controls the operation of the oscillator 11 by the detected output. That is, driving pulses having a phase difference are supplied to each of the N boosting circuit cells 121 to 12N, and when the voltage detecting circuit 15 detects that the boosted output has reached the target voltage, the operation of the oscillator 11 is stopped. As a result, the boosting operation is stopped. Then, the voltage detection circuit detects that the boost output has dropped below the target voltage.
When detected by 15, the oscillator 11 is driven again to repeat the control of restarting the boosting operation.

FIG. 16A is a waveform diagram showing an operation example of the boosting system circuit of FIG.

In the booster circuit of FIG. 15, when the oscillator operation 11 is started at a certain time to drive the booster circuit 12, the output voltage Vout starts to rise. The voltage detection circuit 15
The output voltage Vout of the booster circuit 12 is divided into a certain size by using an element having a resistance component, and the divided voltage value and the reference voltage (supplied by a reference voltage generation circuit (not shown)) are compared.

As a result of this voltage comparison, if it is detected that the reference voltage is larger, the operation of the oscillator 11 is continued, and conversely to the above, the voltage value obtained by dividing the output voltage Vout is larger. When detected, the operation of the oscillator 11 is stopped and the boosting operation is also stopped.

If the output voltage Vout of the booster circuit 12 is divided into (N / M) in the voltage detection circuit 15, the output voltage Vout of the booster circuit 12 reaches (reference voltage × M / N). At that time, the voltage detection circuit 15 controls so as to stop the boosting operation. Note that both M and N are arbitrary positive integers, and N <
Let's say M.

As described above, the output voltage Vout is constantly detected while boosting, and the boosting operation is stopped once the output voltage Vout reaches a desired voltage. The desired voltage described here is a voltage value obtained by multiplying the reference voltage by (M 2 / N 2).

After that, when the output voltage drops below the desired voltage due to the leakage current or the current required by the load circuit 10, the booster circuit 12 is operated again to keep the output voltage Vout at the desired voltage, and the desired voltage is restored. When the voltage is detected, the control such as stopping again is repeated.

Thereafter, in the present specification, the booster circuit 12 is in a state of performing the boosting operation only when the boosted voltage becomes equal to or lower than the desired voltage after the operation of boosting the output voltage to the desired voltage is once completed. When, that is, when the output voltage Vout is near the desired voltage
The stop control will be called binary control.

As shown in FIG. 16A, the booster circuit 12
On the other hand, in the binary control state, when the load circuit 10 requires a current substantially equal to the maximum current that can be supplied by the booster circuit, the operation / stop cycle of the booster circuit 12 becomes the fastest, When the circuit 10 does not require much current, the operation / stop cycle of the booster circuit 12 becomes long.

When the boosting operation up to the desired voltage is completed once, and after a certain time, it is detected again that the output voltage Vout of the boosting circuit 12 is the desired voltage or less, the voltage detecting circuit 15 It works to operate the oscillator 11, and at least one oscillation pulse is supplied to the booster circuit.

At this time, in the conventional booster circuit shown in FIG. 15, the output voltage Vout of the booster circuit 12 is near the desired voltage, and the oscillation pulse 1 when the booster circuit 12 is in the binary control state.
The amount of electric charge supplied by the generation is exactly equal to the amount of electric charge supplied by one oscillation pulse in the process of boosting from the initial voltage when the booster circuit is stopped before the boosting operation is started to the desired voltage.

As a characteristic of the boosting system circuit, boosting output is
Voltage detection circuit indicates that Vout has reached the desired (target) voltage.
It takes a finite time ΔT from the detection by 15 until the operation (boosting operation) of the oscillator 11 is completely stopped.

Therefore, if the amount of electric charge (supply current) supplied from the booster circuit 12 per unit time exceeds the amount of electric charge (consumption current) consumed by the load per unit time within the time ΔT, the voltage is excessively boosted. Occurs.

FIG. 16 (B) is a waveform diagram shown for explaining over boosting in the binary control state in FIG. 16 (A).

When the output voltage Vout is in the vicinity of a desired voltage and the booster circuit 12 is in the binary control state, the amount of current supplied by the several oscillation pulses during the operation of the booster circuit is the amount of current required by the load circuit 10. If it exceeds, it will be in the state of over boosting.

Therefore, the ripple (overshoot) of the output voltage becomes large, and the power consumption of the entire booster circuit becomes large by driving the booster circuit 12 with a current supply capacity more than necessary.

In order to suppress this overshoot,
Conventionally, there is no choice but to connect a large-capacity stabilizing capacitor 14, the pattern area required for that is increasing, and the chip area tends to increase.

[0022]

As described above, the booster circuit incorporated in the conventional semiconductor integrated circuit requires a large-capacity stabilizing capacitor to suppress overshoot,
There is a problem that the pattern area increases and the chip area increases.

The present invention has been made to solve the above-mentioned problems, and can suppress excessive boosting of the boosted voltage when the booster circuit is in the binary control state, and connect a large capacity capacitor more than necessary. It is an object of the present invention to provide a semiconductor integrated circuit that is optimized so as to reduce the ripple of the boost output without the need.

Another object of the present invention is to prevent the booster circuit from being driven with an unnecessarily high capacity when the load circuit does not need the maximum current that can be supplied by the booster circuit. An object is to provide a semiconductor integrated circuit that can realize power saving.

[0025]

According to a first semiconductor integrated circuit of the present invention, an oscillator for generating N kinds of drive pulses having a specific frequency, and a drive pulse supplied from each of the oscillators to generate a boosted voltage. A stabilizing capacitor for connecting N boosting circuit cells to be generated and a boosting circuit output node that combines the boosting outputs of the N boosting circuit cells, and stabilizing the boosting output of the boosting circuit output node. And a voltage detection circuit for detecting the magnitude of the boosted output of the booster circuit output node to control the operation / stop of the oscillator, wherein the load is provided between the booster circuit output node and the load circuit. A load state detection circuit having a function of detecting the operating state of the circuit is connected, and the current supply capacity of the booster circuit can be actively adjusted based on the detection result. To.

A second semiconductor integrated circuit according to the present invention has a built-in booster circuit, and the output voltage becomes equal to or lower than the desired voltage after the operation of boosting the output voltage of the booster circuit to a desired voltage is completed once. Only when the boosting operation is performed, the operating state of the load circuit of the boosting circuit is always detected, and the current supply capacity of the boosting circuit is optimized to over boost the output voltage of the boosting circuit. It is characterized by having a suppressing function.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
2 shows a configuration of a booster system circuit incorporated in the semiconductor integrated circuit according to the embodiment.

This boosting system circuit is different from the boosting system circuit of the conventional example described above with reference to FIG.
And the difference that the amplifier circuit 19 is newly provided,
Since the others are the same, the same reference numerals as those in FIG. 15 are attached.

The load state detection circuit 16 is composed of a load current detection resistor 17 and a comparison detection circuit 18.

That is, in the booster circuit shown in FIG.
Is an oscillator that generates a drive pulse having a specific frequency (in this example, a pulse that forms a complementary pair with an oscillation pulse and its inversion pulse). Reference numeral 12 is a booster circuit, and similarly to the conventional example described above with reference to FIG. 15, N (a plurality of, for example, 8 to 16) drive pulses (complementary pulses in this example) are respectively supplied from the oscillator 11 to boost the voltage. ) Has a booster circuit cell.

Reference numeral 13 is a booster circuit output node where boosted outputs of N booster circuit cells are combined, and 14 is a booster circuit output node.
It is a stabilizing capacitor (Pool Capacitor) for stabilizing the boosted output of 13 (suppressing ripple).

Reference numeral 16 denotes a booster circuit output node 13 and a load circuit 10.
Is a load state detection circuit having a function of detecting the operating state of the load circuit 10 between, and the cycle of the oscillator 11 from the detection result of the load state detection circuit 16, and each booster circuit cell constituting the booster circuit 12. It has a function of actively adjusting the current supply capacity of the entire booster circuit by adjusting either or both of the current supply capacities.

The load state detection circuit 16 detects the operating state of the load circuit 10 according to the magnitude of the voltage drop generated in the element having a resistance component connected in series between the booster circuit output node 13 and the load circuit 10. It has a function to do.

In this example, the load state detection circuit 16 is connected in series between the booster circuit output node 13 and the load circuit 10 and is used for a current monitor for observing the amount of current required by the load circuit 10. A resistance detecting element 17 is provided with a comparison detecting circuit 18 having a function of comparing the voltage across the resistance element 17 and detecting the voltage drop VR generated across the resistance element 17.
The load circuit 10 is configured to observe a current (load current) Iload required by the load circuit 10 based on the detected output voltage V1 of 18.

Further, the detection output voltage V1 of the comparison detection circuit 18
An amplifier circuit 19 for amplifying the signal is provided. The reason why amplification is performed by the amplifier circuit 19 will be described. The voltage drop VR generated across the resistance element 17 must be a small potential difference that does not affect the operation of the load circuit 10 even when the maximum current Imax that can be constantly supplied by the booster circuit 12 flows. is there. However, it is difficult to measure the current value from this minute potential difference, and since it is not suitable as a signal for adjusting the current supply capacity of the booster circuit 12, the detection output voltage V1 of the comparison detection circuit 18 is set by the amplification circuit 19. It is desirable to amplify (amplification degree Av) and convert to a signal voltage V2 having a large potential difference.

FIG. 2A is a circuit diagram showing a configuration example of the amplifier circuit 19 in FIG.

In this amplifier circuit 19, the detection output voltage V1 of the comparison detection circuit 18 is input to the non-inverting (+) side input terminal of the operational amplifier OPAMP, and the voltage V2 at the output terminal of the operational amplifier OPAMP is input to the resistance element R1 ,. The voltage divided by R2 is input to the inverting (-) side input terminal of the operational amplifier OPAMP.

FIG. 2B is a characteristic diagram showing the relationship between the current Iload flowing through the resistance element 17 in FIG. 1 and the output voltage V2 of the amplifier circuit 19.

FIG. 2C shows one of the cycle of the oscillator 11 and the current supply capacity of each booster circuit cell constituting the booster circuit 12 according to the output voltage V2 of the amplifier circuit 19 in FIG. FIG. 9 is a characteristic diagram showing a state in which the current supply capability of the entire booster circuit circuit is adjusted stepwise or continuously by adjusting both or both.

Next, referring to FIGS. 3 to 4, FIG.
The operation of the booster circuit will be described.

FIG. 3 shows an example of the operation of the booster circuit of FIG. 1 in the first boosting process.

At this stage, the operation of the booster circuit 12 is stopped in the initial state, and the output voltage Vo of the booster circuit 12 is reduced.
ut is also stable at an initial voltage smaller than the desired voltage. At a certain time, the oscillator 11 starts operating and at the same time the booster circuit
The output voltage Vout of 12 also starts to rise gradually.

The current Iload supplied from the booster circuit output node 13 to the load circuit 10 will now be described. Generally, the boost circuit 12 maintains the desired voltage while maintaining the load circuit 10.
Since the ability to supply the current Iload required by the booster circuit 12 is required, the maximum voltage that the booster circuit 12 can supply is designed to be higher than the desired voltage. Therefore, if the feedback control for the booster circuit 12 is not performed, the booster circuit 12 operates so as to continue to output the voltage Vmax higher than the desired voltage, and if the discharge current from the stabilizing capacitor 14 is zero, the output voltage is increased. Vout is
Increase to Vmax.

The stabilizing capacity 14 and the load capacity of the load circuit 10 are charged, and the maximum output voltage Vm of the booster circuit 12 is increased.
The potential difference between ax and the output voltage Vout gradually becomes smaller (ΔVC <ΔVB <ΔVA), and the charging current decreases as the potential difference decreases.
Iout also decreases.

In the booster circuit of the conventional example, each of the oscillation pulses P1 to P6 generated from the start of boosting to the end of boosting is 1
The amount of charge supplied by each launch is designed to be completely equal, so that the current Iout supplied by the booster circuit 12 exceeds the current Iload consumed by the load circuit 10 when the output voltage Vout is in the vicinity of the desired voltage. If this happens, over boosting will occur.

That is, despite the fact that the difference between the desired voltage and the output voltage Vout gradually becomes smaller (ΔV3 <ΔV2 <ΔV1), the operation is such that a constant charge amount is always supplied to the output. It was a problem.

Therefore, in the circuit shown in this embodiment, the load current Iload is observed by the voltage drop VR generated across the current monitor resistance element 17 at the same time as the boosting is performed, and the booster circuit 12 of the booster circuit 12 is based on the result. The current supply capacity is controlled so as to be optimized, and its specific operation will be described below.

When designing the booster circuit 12, generally,
The maximum current Imax that the booster circuit 12 can constantly supply while maintaining a desired voltage is obtained in advance.

When the load circuit 10 requires a current that is substantially equal to the maximum current Imax, the current monitoring resistance resistance element 17
The voltage VR generated between both ends of the voltage Vmax becomes maximum, and the output voltage V2 amplified by the amplifier circuit 19 becomes the maximum value V2max.

When the load circuit 10 requires a current smaller than the maximum current Imax, the output voltage V2 of the amplifier circuit 19 has the following relationship with the maximum value V2max.

V2 = α · V2max (0 <α <1) (1) Therefore, when boosting from the initial voltage before the start of boosting, the current supply capacity is set to the maximum, and while boosting, The magnitude of the output voltage V2 of the amplifier circuit 19 is read, and the current supply capacity of the booster circuit 12 is adjusted according to the value of α in the above equation (1). Here, the closer α is to 1, the more
The booster circuit 12 is driven so that the current supply capacity of 12 increases.

In other words, in the conventional example, the charge supply amount per oscillation pulse from the start of boosting to the end of boosting was designed to be completely equal, but in the circuit according to this embodiment, the boosting is performed at that time. The booster circuit itself performs the boosting operation while actively adjusting the charge supply amount (current supply capacity) according to the amount of current required by the load circuit 10 of the circuit, so the charge supply amount per oscillation pulse is Not always equal.

There are two methods for adjusting the current supply capacity of the booster circuit 12, as shown in FIGS. 9 to 14 which will be described later. Alternatively, some of the methods shown in FIGS. 9 to 14 may be combined to form a circuit.

FIGS. 4A to 4C show an operation example of the booster circuit of FIG. 1 in the binary control state. Here, FIG. 4A is an operation example when the load current Iload is constant in the step-up process, FIG. 4B is an operation example when the load current Iload is decreased in the step-up process, and FIG. An operation example when the load current Iload increases in the process is shown.

In the operation example in which the load current Iload is constant in the step-up process in the binary control state shown in FIG. 4A, the step-up operation is first terminated and the step-up output voltage Vout
Is discharged by the load current Iload, the load current Iload at this time is observed, and based on the output voltage V2 of the amplifier circuit 19 obtained as a result, the next boost operation Ts is started.
The current supply capacity Ps of the booster circuit 12 is determined. By starting boosting with this current supply capability Ps and actively optimizing the current supply capability while actively boosting, a boosted voltage in which over boosting is suppressed is supplied. The current supply capacity at time Te when the boosting ends is Pe.

The point that the current supply capability is optimized while boosting is the same as the operation when boosting from the initial voltage to the desired voltage. However, the booster circuit 12 is 2
In the value control state, the current supply capacity at time Ts when boosting starts is not always 100%, but load current Iload
Is determined by the size of.

In the operation example in which the load current Iload decreases in the step-up process in the binary control state shown in FIG. 4B, first, the step-up operation is once terminated and the step-up output voltage Vo
When ut enters the discharge state due to the load current Iload, the load current Iload at this time is observed, and based on the output voltage V2 of the amplifier circuit 19 obtained as a result, when the next boost operation starts
The current supply capacity Ps of the Ts booster circuit 12 is determined. Boosting is started with this current supply capacity Ps, and the current supply capacity is actively optimized while boosting. In this case, the load current decreases in the boosting process, so the booster circuit should be balanced with it.
It is necessary to further reduce the charging current Iout supplied from 12.

Therefore, in the boosting process, the load current Iout
When the decrease of the current supply capacity is detected, the current supply capacity is weakened at a decrease rate larger than the decrease rate of the current supply capacity before that, and finally reduced to the current supply capacity Pe.

According to the boosting method of the conventional example, in such a case, since the charging current Iout greatly exceeds the load current I1oad, the tendency of over-boosting becomes stronger, but by the method shown in this example. It is possible to suppress over boosting to a low level.

In the operation example in which the load current Iload increases in the step-up process in the binary control state shown in FIG. 4C, first, the step-up operation is once terminated and the step-up output voltage Vo
When ut enters the discharge state due to the load current Iload, the load current Iload at this time is observed, and based on the output voltage V2 of the amplifier circuit 19 obtained as a result, when the next boost operation starts
The current supply capacity Ps of the Ts booster circuit 12 is determined. Boosting is started with this current supply capacity Ps, and the current supply capacity is actively optimized while boosting. In this case, the load current increases during the step-up process, so the step-up circuit should be balanced with it.
It is necessary to increase the charging current Iout supplied from 12 midway.

Therefore, in the boosting process, the load current Iout
When an increase in is detected, control is performed to increase the current supply capacity that was in the decrease state before that.

Therefore, according to the booster system circuit of the first embodiment, the booster output voltage is maintained by the stabilizing capacitor 14 having a smaller capacity than that of the conventional example while maintaining the capability of the booster system circuit equal to that of the conventional example. It becomes possible to suppress the ripple of Vout smaller than that of the conventional example.

Further, by varying the current supply amount per one oscillation pulse when the booster circuit 12 is in the binary control state according to the current amount required by the load circuit 10,
When the load circuit 10 does not require the maximum current that can be supplied by the booster circuit 12 while suppressing the ripple small, the booster circuit 12
Drive with more current supply capacity than necessary,
Realize power saving in the entire booster circuit.

<Second Embodiment> FIG. 5 shows a second embodiment of the present invention.
2 shows a configuration of a booster system circuit incorporated in the semiconductor integrated circuit according to the embodiment.

The boosting system circuit of FIG. 5 is different from the boosting system circuit according to the first embodiment described above with reference to FIG. 1 in the following points and is otherwise the same, so that the same reference numerals as those in FIG. Is attached.

That is, (1) the load state detection circuit 16a is connected to the booster circuit output node 13 and the boosted output voltage Vo
A falling slope detection circuit 51 for observing the variation amount of ut (level reduction amount due to discharge) and a rising slope detection circuit 51 receiving a signal detected by the voltage detection circuit that the boosted output voltage Vout has become equal to or lower than a desired voltage. A voltage holding circuit 52 that holds the output V1 of the downward slope detection circuit 51 is provided.

Then, based on the amplified output of the buffer amplifier circuit 53 that buffer-amplifies the output held by the voltage holding circuit 52, the boosted output voltage by the load current Iload is generated when the booster circuit 12 is in the binary control state and in the boost stop state. Observe the amount of decrease of Vout per unit time.

(2) Since the booster circuit 12 carries out the boosting operation while being fixed at the ability at the start of boosting in the binary control state, the oscillation pulse of the oscillator 11 is pulsed (PULSE) counter 54.
Therefore, it is necessary to detect whether or not the boosted output voltage Vout has reached a desired voltage even after counting a certain number of times. If it is detected that the boost output voltage Vout has not reached the desired voltage, the boost capability control circuit 55
The booster circuit 12 is configured to perform control so as to increase the current supply capacity.

In this case, the number of pulses counted by the pulse counter 54 is determined as follows. As mentioned above, the output voltage of the booster circuit 12 is a characteristic of the booster circuit.
When Vout drops due to the discharge current Iout, the output voltage
It takes a certain finite time ΔT from when Vout becomes equal to or lower than the desired voltage to when the boosting operation starts. The time ΔT
When the amount of decrease in the potential of the stabilizing capacitor 14 from the desired potential during the period is represented by ΔV, this ΔV becomes maximum when the discharge current Iout is maximum. Therefore, Δ from this desired potential
The number of pulses required for the charging (boosting) operation for recovering the maximum amount of decrease in V is set as the maximum count number of the pulse counter 54.

In order to obtain the number of pulses, as an ideal state, assuming that the load circuit 10 is not connected to the booster circuit output node 13 and an leak current does not occur, an open state in which the leakage current does not occur is assumed. Consider a case where the capacitor C is charged by the booster circuit 12 driven with the minimum current supply capacity.

Assuming that there is no discharge path from the capacitance C as described above, the potential of the capacitance C becomes (desired voltage −ΔV
If N oscillation pulses are required to charge from () to the desired voltage, this N can be the maximum number of pulses required for charging. Naturally, if the current supply capacity is increased, charging should be completed in less than N times.

Therefore, assuming that the number of counts of the pulse counter 54 is N, even if the booster circuit 12 is driven by N pulses, if the output voltage Vout does not reach the desired voltage, the booster circuit 12 at that time is Current supply capacity is discharge current Iout
Can be considered as not having the ability to overcome and charge.

In summary, when the booster circuit 12 is in the binary control state, the oscillation pulse is counted at the same time when the boosting operation is started, and the output voltage Vout is desired even after the booster circuit 12 is driven by N oscillation pulses. If the voltage has not been reached, the boosting capability control circuit 55 performs control to restore the current supply capability of the boosting circuit 12 to the maximum capability.

FIG. 6 shows the falling slope detection circuit 5 in FIG.
1 is a circuit diagram showing a configuration example of a voltage holding circuit 52 and an amplifier circuit 53. FIG.

FIG. 7A shows an example of operation waveforms of the falling slope detection circuit 51 and the voltage holding circuit 52 of FIG.

FIG. 7B shows an input voltage (boosted output voltage Vout) of the falling slope detection circuit 51 and a voltage holding circuit in FIG.
FIG. 7 is a characteristic diagram showing an example of the relationship of the output voltage V1 of 52.

FIG. 7C shows the buffer amplifier circuit shown in FIG.
FIG. 7 is a characteristic diagram showing an example of the relationship between the output voltage V2 of 53 and the current supply capacity of the booster circuit 12.

When designing the booster circuit 12 in FIG. 5, generally, the maximum amount of current that the booster circuit 12 can supply is designed to be substantially equal to the maximum amount of current required by the load circuit 10. Further, the size of the stabilizing capacitor 14 connected to the booster circuit output node 13 is also predetermined. From the above, the amount of decrease per unit time of the output voltage Vout when the stabilizing capacitor 14 is once charged to a desired voltage and discharged at the maximum current amount required by the load circuit 10 is also obtained. It is possible to predict in advance at the time of design.

Here, by designing the output voltage V1 of the falling slope detection circuit 51 connected to the booster circuit output node 13 to be maximum when the boosted output voltage Vout is discharged by the maximum current, The amount of current required by the load circuit 10 can be predicted from the amount of decrease in the output voltage Vout per unit time.

The output voltage V1 of the falling slope detection circuit 51 when the boosted output voltage Vout is discharged by the maximum current is set to V1.
If it is set to max, the output voltage Vl of the falling slope detection circuit 51 when the load circuit 10 does not require the maximum current has the following relationship with V1max.

V1 = αV1max (0 <α <1) Here, control is performed so that the closer α is to 1, the higher the current supply capacity of the booster circuit 12.

Next, the operation of the booster circuit of FIG. 5 will be described.

The operation of the booster circuit of FIG. 5 in the first boosting process (the process of boosting from the initial voltage before the booster circuit operation to the desired voltage) has been described above with reference to FIG. 3 in the first embodiment. This is similar to the operation example.

FIGS. 8A to 8C show an operation example in the binary control state of the booster circuit of FIG. Here, FIG. 8A is an operation example when the load current Iload is constant in the step-up process, FIG. 8B is an operation example when the load current Iload is decreased in the step-up process, and FIG. An operation example when the load current Iload increases in the process is shown.

First, an operation example when the load current Iload is constant in the boosting process in the binary control state shown in FIG. 8A will be described.

The falling slope detection circuit 51 constantly observes the amount of change in the output voltage Vout of the booster circuit 12. When the voltage detection circuit detects that the output voltage Vout has dropped below the desired voltage and the output voltage Vout is discharged by the load current Iload once the boosting operation ends, the falling slope detection is performed. The voltage holding circuit 52 holds the output voltage V1 of the circuit 51. At this time, the magnitude of the voltage held determines the current supply capacity of the booster circuit 12 at the start of the next boosting operation.

In this case, the buffer amplifier circuit 53 is used to amplify the output held by the voltage holding circuit 52. The reason for this is that when the current supply capacity of the booster circuit 12 is controlled, the voltage holding circuit 52
This is because there is a possibility that the driving capability may be insufficient when the output voltage of 1 is directly used.

Then, the output voltage V2 of the buffer amplifier circuit 53
Based on the above, the current supply capacity Ps of the booster circuit at the time Ts of starting the next boosting operation is determined, and thereafter, boosting is performed with the capacity Ps until time Te. It should be noted that the holding operation of the voltage holding circuit 52 ends when the boosting operation ends.

At the same time when boosting starts, the pulse counter
The count of oscillation pulses is started by 54. In this case, since the load current Iload does not change in the boosting process, the boosting operation is completed before the pulse counter 54 counts N times.

When the load circuit 10 does not require the maximum current, the step-up circuit 12 performs a step-up operation according to the load current Iload, so that it is possible to suppress overstep-up of the output voltage as compared with the conventional example. is there.

Next, an operation example in the case where the load current Iload decreases in the step-up process in the binary control state shown in FIG. 8B will be described.

Also in this case, the output voltage Vout of the booster circuit 12 is similar to the operation example when the load current Iload is constant.
The output voltage of the falling slope detection circuit 51 is detected when the voltage detection circuit detects that
The voltage holding circuit 52 holds V1. Then, the current supply capacity of the booster circuit 12 at the start of the next boosting operation is determined by the magnitude of the voltage held at this time. Voltage holding circuit 52
The holding operation of is finished when the boosting operation is finished.

In the conventional example, the load current Il is increased during the step-up process.
When 0ad decreases, the boosting operation is always performed with the maximum capacity, so that the difference between the supply current and the load current is further expanded, and the overboosting is further increased.

On the other hand, in the operation of this embodiment, since the current supply capacity Ps at the start of boosting is weakened in advance, the tendency of over boosting is alleviated as compared with the conventional example. However, when the capability Ps at the start of the boosting operation is set to the maximum capability, it is the same as the conventional example. Further, in this case, since the load current does not exceed the supply current, the pulse counter 54
The boosting operation is completed before counting N times.

Next, an operation example in the case where the load current Iload increases above the supply current in the boosting process in the binary control state shown in FIG. 8C will be described.

Also in this case, the output voltage Vout of the booster circuit 12 is the same as the operation example when the load current Iload is constant.
The output voltage of the falling slope detection circuit 51 is detected when the voltage detection circuit detects that
The voltage holding circuit 52 holds V1. Then, the current supply capacity of the booster circuit 12 at the start of the next boosting operation is determined by the magnitude of the voltage held at this time. Voltage holding circuit 52
The holding operation of is finished when the boosting operation is finished.

In this case, since the load current Iload increases above the supply current during the step-up process, even if the step-up is started with the current supply capacity Ps, charging to the desired voltage is completed while the pulse counter 54 counts N times. do not do. Therefore, the oscillation pulse
After finishing counting N times, when the voltage detection circuit detects that the output voltage Vout has not reached the desired voltage, the boosting capability control circuit 55 in FIG. 5 is set so that the current supply capability is restored to the maximum. Is controlled by.

In the booster circuit of FIG. 5, the oscillator 11
It is also possible to apply the method of counting whether the boosted output voltage Vout has reached the desired voltage even after counting a certain number of times by the pulse counter 54 to the booster circuit of FIG. Is.

Next, the first to fifth embodiments of the method for controlling the current supply capacity of the booster circuit shown in FIG. 1 or 5 will be described with reference to FIG.
It will be described with reference to FIGS.

FIGS. 9A and 9B are circuit diagrams showing a first embodiment of the method for controlling the current supply capacity of the booster circuit 12 shown in FIGS. 1 and 5 and a modification thereof.

In the booster circuit shown in FIG. 9A, the N booster circuit cells 121 to 12N are oscillated pulse φ and its inverted pulse /.
Driven by pulses φ and / φ forming a complementary pair with φ. In this case, when it is desired to supply the maximum current, the booster circuit cells 121 to 12N are driven, and when it is not necessary to supply the maximum current, the pulses φ and / φ are supplied only to the booster circuits 121 to 12K, and the remaining booster circuits are supplied. The supply of pulses φ and / φ to 12L to 12N is stopped to reduce the amount of current supply per oscillation pulse. Here, 1 <K <L <N and L = K + 1.

Further, in the booster circuit shown in FIG. 9B, the N booster circuit cells 121 to 12N are pulses having different phases from .phi.1 to .phi.N and their inverted pulses / .phi.1 to.
Pulses (φ1, / φ1) to (φ which form a complementary pair with / φN
N and / φN) respectively. Then, when it is desired to drive the maximum current, all the booster circuit cells 121 to 12N are driven, and when it is desired to reduce the current supply capacity, complementary signals (φ1,
Only the booster circuit cells driven by any x phase of / φ1) to (φN, / φN) are driven, and other y (= Nx)
The driving of the booster circuit cell driven in each phase is stopped.

With such a method, the current supply capability of the booster circuit can be adjusted stepwise, and when the maximum current is not required, the total number of driven booster cells is reduced, so that the power consumption is also reduced. It is possible to reduce.

In the booster circuit cells 121 to 12N shown in FIGS. 9A and 9B, at least two unit circuits each having one end of the capacitor C connected to the output node of the diode D are connected to the final stage. One diode D is connected to. Then, complementary driving pulses are supplied to the other ends of the odd-numbered capacitor C and the even-numbered capacitor C, respectively, so that the odd-numbered unit circuits and the even-numbered unit circuits alternate. Boost operation is performed.

In Examples 2 to 5 of the method for controlling the current supply capability of the booster circuit 12 shown below, the same pulse forming a complementary pair with N booster circuit cells 121 to 12N as shown in FIG. 9A. A single booster circuit cell when φ and / φ are supplied will be described as a representative example. As shown in FIG. 9B, a complementary pair is provided to the N booster circuit cells 121 to 12N. Pulses with different phases (φ1, / φ1) to (φN, / φN
) Is supplied, the same can be applied.

10A and 10B show a second embodiment of the method for controlling the current supply capacity of the booster circuit 12 in FIGS. 1 and 5.
It is a circuit diagram which shows and its modification. FIG. 10 (C)
FIG. 11 is a characteristic diagram showing current supply characteristics by the circuit of FIG. 10 (B).

As shown in FIG. 10A, when it is desired to maximize the current supply capacity of the booster circuit cell, all the diodes D1 to DN for charging the first-stage capacitance C1 are turned on to lower the current supply capacity. If you want, turn on only the diodes D1 to DK, turn off the rest of the diodes DL to DN, and set the capacitance of the first stage capacitor C1.
Reduce the amount of charge that is charged to. Where 1 <K <L <N
, L = K +1.

With such a method, it is possible to adjust the current supply capacity of the booster circuit cell step by step, and when the maximum current is not required, the charging current to the first-stage capacitance C1 is reduced, so that it is consumed. Electric power can also be reduced.

In the booster circuit shown in FIG. 10B, the NMOS transistor NT is used in place of the diode for charging the capacitance C1 in the first stage of the booster circuit cell, and its gate bias VG is increased or decreased, It is possible to control the current supply capacity. In this case, unlike the booster circuit cell shown in FIG. 10A, the current supply capability can be continuously adjusted as shown in FIG. 10C.

FIG. 11 shows a booster circuit 12 shown in FIGS.
6 is a circuit diagram showing a third embodiment of the current supply capacity control method of FIG.

The booster circuit shown in FIG. 11 has a plurality of capacitors C1i, C2i (i = 1, 2, ..., N) as the capacitors (C1, C2 in the case of two stages) of each stage constituting the booster circuit cell. The number of parallel connections of) is configured to be selectively controllable by a switch element.

In the booster circuit shown in FIG. 11, when it is desired to supply the maximum current, all the capacitors C11 ...
Connect C1N and C21 to C2N in parallel. If you want to reduce the current supply capacity, select some capacity C11 to C1K as the capacity of each stage,
C21 to C2K are connected in parallel, and the remaining capacity C1L to C1N and C2L
Disconnect the ~ C2N connection. Where 1 <K <L <N, L
= K + 1

In this case, when only one capacitance C11 and C21 is connected as the capacitance of each stage, the capacitances of the buffer circuits Buffer11 and Bu corresponding to those capacitances are correspondingly provided.
Drive with ffer21.

A plurality of capacitors C1 are provided as capacitors of each stage.
When 1 to C1K and C21 to C2K are connected in parallel, multiple buffer circuits Buffer11 to
Drive with Buffer1K, Buffer21 ~ Buffer2K.

As the capacity of each stage, all capacities C11
When ~ C1N and C21 ~ C2N are connected in parallel, all of the buffer circuits Buffer11 ~ Buff
Drive with er1N and Buffer21 to Buffer2N.

As described above, when a small capacitance value is connected to the booster circuit cell, the capacitor is driven by the buffer circuit having a small driving ability, and when the booster circuit cell is connected to a large capacitance value, the driving ability is large. By driving the capacitance by the buffer circuit, power consumption by the buffer circuit can be suppressed when the maximum current is not required. Even when the booster circuit cell has a capacity of three or more stages, it can be implemented according to the above.

FIG. 12 shows a booster circuit 12 shown in FIGS. 1 and 5.
FIG. 9 is a circuit diagram showing a modification of the third embodiment of the current supply capacity control method of FIG.

The booster circuit shown in FIG. 12 has a plurality of capacitors C1i, C2i (i = 1, 2, ..., N) as the capacitors (C1, C2 in the case of two stages) of each stage constituting the booster circuit cell. ) Is configured to be selectively controllable by a switch element.

In the booster circuit shown in FIG. 12, when it is desired to supply the maximum current, only one capacitor C11 and C21 is connected to each stage. If you want to reduce the current supply capacity, select some capacity C11 to C1K, C21 to each stage capacity.
C2K is connected in series and the remaining capacity C1L to C1N, C2L to C2N
By disconnecting the connection, the capacitance value that contributes to boosting is reduced and the current supply capability is reduced. Where 1 <K
<L <N, L = K +1. In addition, all capacity C11
By connecting C1N to C1N and C21 to C2N in series, the capacity value contributing to boosting may be minimized and the current supply capacity may be minimized.

In this case, according to the third embodiment described with reference to FIG. 11, the size of the buffer circuit for driving the capacitance is switched according to the value of the capacitance connected to the booster circuit cell. This makes it possible to suppress the power consumption by the buffer circuit when the maximum current is not required. Even when the booster circuit cell has a capacity of three or more stages, it can be implemented according to the above.

FIG. 13 shows a booster circuit 12 shown in FIGS. 1 and 5.
6 is a circuit diagram showing a fourth embodiment of the current supply capacity control method of FIG.

The booster circuit shown in FIG. 13 is provided in front of the drive pulse input terminals (P1 and P2 in the case of two stages) of the booster circuit cell.
Corresponding to each clock buffer circuit Clock Buffer1
, Clock Buffer2 are inserted, and the operation power supplies of these clock buffer circuits Clock Buffer1 and ClockBuffer2 are supplied from the step-down circuit 130.

In the step-up circuit shown in FIG. 13, when it is desired to supply the maximum current, the step-down circuit 130 supplies the clock buffer circuits Clock Buffer1 and Clock Buffer2 with a voltage of maximum amplitude, that is, in a state in which nothing is stepped down. Supply voltage. At this time, if the amplitudes of the complementary signals φ and / φ inputs are h2, the clock buffer circuit ClockBuf
Amplitude h1 = h2 of pulses φ and / φ output from fer1 and Clock Buffer2.

On the other hand, when it is desired to reduce the current supply capacity, the power source stepped down by the step-down circuit 130 is supplied to the clock buffer circuits Clock Buffer1 and Clock Buffer2.
At this time, the clock buffer circuits Clock Buffer1, Clock
Amplitude h1 of complementary signals φ and / φ output from Buffer2 is <h2
Is.

If the step-down circuit 130 is configured to generate the step-down power supply in stepwise size, it becomes possible to control the current supply capacity stepwise, and the step-down circuit 130 continuously increases the step-down power supply. If it is configured to generate the current, it becomes possible to continuously control the current supply capacity.

FIGS. 14A and 14B are circuit diagrams showing a fifth embodiment in which the current supply capacity of the boosting system circuit shown in FIGS. 1 and 5 is controlled by adjusting the frequency of the oscillator.

FIG. 14A shows a pulse φ, / for driving the booster circuit cell when it is desired to supply the maximum current from the booster circuit.
The figure shows that the φ frequency is set high.

FIG. 14B shows a pulse φ, / for driving the booster circuit cell when it is desired to reduce the current supply capability of the booster circuit.
The figure shows that the φ frequency is set low.

With such a method, it is possible to increase or decrease the current supply amount of the booster circuit cell per unit time.
In this case, if the frequencies of the pulses φ and / φ are changed stepwise, the current supply amount per unit time can be changed stepwise.

When the current supply capability of the booster circuit is lowered, the frequencies of the pulses φ and / φ are set low,
It is also possible to reduce the power consumption of the oscillator 11 that generates it.

[0132]

As described above, according to the semiconductor integrated circuit of the present invention, boosting is performed only when the boosted voltage becomes equal to or lower than the desired voltage after the operation of boosting the output voltage of the booster circuit to the desired voltage is completed once. By constantly optimizing the current supply capability of the booster circuit in the operation state, it is possible to supply the boosted voltage in which over boosting is suppressed.

Moreover, when the load circuit does not require the maximum current that can be supplied by the booster circuit, it is possible to prevent the booster circuit from being driven with an unnecessarily high capacity, and it is possible to realize power saving in the entire booster system circuit. it can.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a booster circuit incorporated in a semiconductor integrated circuit according to a first embodiment of the present invention.

2 is a circuit diagram showing a configuration example of an amplifier circuit in FIG. 1 and a characteristic diagram showing a relationship among a load current Iload, an amplifier circuit output voltage V2, and a booster circuit current supply capacity.

FIG. 3 is a waveform diagram showing an operation example of the booster circuit of FIG. 1 in a first boosting process.

FIG. 4 is a diagram illustrating the booster circuit of FIG.
FIG. 6 is a waveform diagram showing an operation example when the load current Iload is constant in the boosting process, an operation example when the load current Iload decreases in the boosting process, and an operation example when the load current Iload increases in the boosting process.

FIG. 5 is a block circuit diagram showing a configuration of a booster circuit incorporated in a semiconductor integrated circuit according to a second embodiment of the present invention.

6 is a circuit diagram showing a configuration example of a falling slope detection circuit, a voltage holding circuit, and an amplification circuit in FIG.

7 is a characteristic diagram showing the relationship among the input voltage (output voltage Vout of the booster circuit) of the falling slope detection circuit of FIG. 6, the output voltage V1, the output voltage V2 of the amplifier circuit, and the current supply capability of the booster circuit.

8 is a diagram showing the booster circuit of FIG. 5 in a binary control state;
FIG. 6 is a waveform diagram showing an operation example when the load current Iload is constant in the boosting process, an operation example when the load current Iload decreases in the boosting process, and an operation example when the load current Iload increases in the boosting process.

9 is a circuit diagram showing a first embodiment of a method for controlling the current supply capacity of the booster circuit shown in FIGS. 1 and 5 and a modification thereof.

10 is a circuit diagram showing a second embodiment of the method for controlling the current supply capability of the booster circuit shown in FIGS. 1 and 5 and a modification thereof.

FIG. 11 is a circuit diagram showing a third embodiment of a method for controlling the current supply capability of the booster circuit shown in FIGS. 1 and 5.

FIG. 12 is a circuit diagram showing a modification of the third embodiment of the method for controlling the current supply capability of the booster circuit shown in FIGS. 1 and 5.

FIG. 13 is a circuit diagram showing a fourth embodiment of a method for controlling the current supply capability of the booster circuit shown in FIGS. 1 and 5.

FIG. 14 is a circuit diagram showing a fifth embodiment of a method for controlling the current supply capacity of the booster circuit shown in FIGS. 1 and 5.

FIG. 15 is a block diagram showing a configuration of a conventional booster system circuit incorporated in a semiconductor integrated circuit.

16 is a waveform diagram showing an operation example of the boosting system circuit of FIG. 15 and a waveform diagram shown for explaining overboosting in the binary control state of the boosting system circuit.

[Explanation of symbols]

10 ... load circuit, 11 ... oscillator, 12 ... Boost circuit, 121 ~ 12N ... booster circuit cell, 13 ... Boost circuit output node, 14 ... stabilizing capacity, 16 ... Load condition detection circuit, 17 ... Resistance element for current monitor, 18 ... Comparison detection circuit, 19 ... Amplifier circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toru Okawa             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5B025 AA01 AD10 AE06                 5H730 AA14 AA15 AS04 BB02 DD12                       DD13 EE59 FD01 FD31 FF01                       FG01                 5J055 AX08 AX63 BX17 CX27 DX22                       DX61 EY01 EY10 EY12 EY21                       EZ07 EZ09 EZ10 EZ28 EZ54                       FX18 FX28 GX01 GX02 GX04                       GX05 GX06

Claims (8)

[Claims] 1. An oscillator that generates N kinds of drive pulses having a specific frequency, N booster circuit cells that are supplied with drive pulses from the oscillators to generate boosted voltages, and N boosters. A boosting circuit output node, which combines the boosted outputs of the circuit cells, is connected, and a stabilizing capacitance for stabilizing the boosted output of the boosted circuit output node and the magnitude of the boosted output of the boosted circuit output node are detected. A voltage detecting circuit for controlling the operation / stop of the oscillator by a load state detecting circuit having a function of detecting the operating state of the load circuit between the output node of the step-up circuit and the load circuit. A semiconductor integrated circuit, which is connected and has a function of actively adjusting the current supply capability of the booster circuit based on the detection result. 2. The load state detection circuit detects a voltage drop occurring in an element having a resistance component connected in series between the booster circuit output node and a load circuit, and the load circuit is detected based on the detection result. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a function of determining the amount of current required by the load circuit and detecting the operating state of the load circuit based on the magnitude of the voltage drop. 3. An amplifier circuit having a function of amplifying the result of detecting the magnitude of the voltage drop, and having a function of detecting the operating state of the load circuit by the output of the amplifier circuit. The semiconductor integrated circuit according to claim 2. 4. The load state detection circuit has a function of detecting an oscillation state of an output voltage of the booster circuit and predicting a current required by the load circuit based on the detection result. 1. The semiconductor integrated circuit according to 1. 5. An amplification circuit having a function of amplifying a result of detecting an oscillation state of an output voltage of the booster circuit, and having a function of detecting an operation state of the load circuit by an output of the amplification circuit. The semiconductor integrated circuit according to claim 4, wherein 6. The load state detection circuit, as a result of detecting the operating state of the load circuit, determines that the amount of current required by the load circuit is obviously smaller than the amount of current which the booster circuit can supply at maximum. In case of the above, the current supply capacity of the booster circuit is actively reduced, and
2. The semiconductor integrated circuit according to claim 1, which has a function of reducing the power consumption of the entire booster system circuit. 7. The oscillator generates N kinds of oscillation pulses having a specific frequency and their inversion pulses, and each of the booster circuit cells has a unit circuit in which one end of a capacitor is connected to an output node of a diode. Are connected in at least two stages, and complementary drive pulses generated by the oscillator are supplied to the other ends of the odd-stage capacitors and the even-stage capacitors of the booster circuit cells, respectively. The semiconductor integrated circuit according to any one of claims 1 to 6, wherein: 8. A step-up circuit is built-in, and the step-up circuit is set to perform a step-up operation only when the output voltage becomes equal to or lower than a desired voltage after the operation of boosting the output voltage to the desired voltage is completed once. At a certain time, an operating state of the load circuit of the booster circuit is constantly detected, and the current supply capacity of the booster circuit is optimized to suppress an excessive boosting of the output voltage of the booster circuit. Integrated semiconductor circuit.