JP2003196980A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize operation, to increase operation speed, and to reduce power consumption, with low power source voltage. <P>SOLUTION: Threshold voltage of a transistor used for a memory cell Qs is made higher than threshold voltage of a transistor used for a word driver WK, and threshold voltage of a transistor used for the word driver WD is made higher than threshold voltage of a transistor used for a voltage converting circuit VCHG for word line. The voltage converting circuit for driving word line is provided with MISFETQE having a gate connected to a drain of a charge pump circuit. Further, cross couple is formed in the charge pump circuit. Therefore, a leak of electronic charges of a memory cell is prevented and a refresh- characteristic is stabilized. When the number of word drivers are many and threshold voltage is low, a leak current is problem as total sum, such a leak current is prevented effectively. Also, as a circuit scale of the voltage converting circuit is not so large, a leak current is relatively small as total sum, as MOS of threshold voltage can be utilized, driving capability is improved and stabilized even with low power source voltage. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high speed and highly integrated semiconductor device which is composed of minute elements and which operates at a low voltage suitable for a battery-operable semiconductor integrated circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (LSI = Large Scale)
Inegration) integration is improved by the MO
This has been promoted by miniaturization of S transistors. When a so-called deep sub-micron LSI having an element size of 0.5 micron or less is formed, the withstand voltage of the element decreases and the LSI
The increase in the power consumed by the car becomes a problem. For such problems, it is considered to be an effective means to reduce the operating power supply voltage with the miniaturization of elements.
Since the mainstream power supply voltage of the current LSI is 5 V, the LSI is used as a means for configuring the LSI with fine elements.
The technology to mount a voltage conversion circuit that reduces the external power supply voltage on the chip is described in IEE Journal of Solid State Circuits, Vol. 21, Vol.
Issue, pages 605-611 (1986) (IEEE Jounal
of Solid-State Circuits, vol.21, No5, pp.605-611,
October 1986). The values of the external power supply voltage and the internal power supply voltage in this case are 5V and 3.5V, respectively. In this way, dynamic RAM (DRAM = Dynamic Random
The problem of power consumption is becoming apparent in Access Memory). In accordance with this tendency, there is a movement to lower the external voltage of the LSI itself. For example, in a 64-megabit DRAM using a 0.3-micron processing technique, the external power supply voltage will be reduced to about 3.3V. As the degree of integration increases, the external power supply voltage may further decrease.

In addition, with the spread of portable electronic devices in recent years,
There is an increasing demand for low-voltage, low-power-consumption LSIs that can operate on batteries and hold information on the batteries. For such applications, LS that operates at a minimum of 1 to 1.5V
I is required. Especially for dynamic memory,
The degree of integration has already reached the megabit level, and there is a movement to use the semiconductor memory in the field of large-capacity storage devices, which could only use magnetic disk devices in the past. For that purpose, it is necessary to back up with a battery so that the data is not lost even when the power is turned off. The duration of this backup usually needs to be guaranteed for weeks to years. Therefore, it is necessary to reduce the current consumption of the memory as much as possible. To reduce the power consumption, it is effective to reduce the operating voltage. However, if this voltage is set to around 1.5 V, only one dry battery is required as the backup power source, so the cost is low and the occupied space is small.

A CMOS (Complementary MOS) LSI composed only of an inverter and various digital logic circuits,
For example, in a processor, the power supply voltage is 1.5V.
Even if the voltage is lowered to a certain level, it is possible to operate with a power supply voltage as low as about 1.5 V without causing a significant deterioration in performance if the constants and threshold voltages of the MOS transistors are properly selected. However, in addition to the external power supply voltage (VCC or VSS), an intermediate voltage between them or a voltage exceeding their range is generated on the LSI, and in the LSI that uses it, the decrease in the power supply voltage is decisive. It was causing performance degradation. A typical example of such an LSI is a DRAM. Therefore, when an information device that operates at a low voltage is configured by a plurality of types of LSI such as a processor and a memory, a voltage other than the power supply voltage is generated on the LSI and used for the operation, as represented by DARM. Low voltage operation of LSI is essential.

When the DRAM is operated at a low voltage, problems occur in the following three types which are mainly used conventionally.

(1) A circuit for reading a minute signal read from a memory.

(2) A circuit for generating a high voltage for driving a word line necessary for transmitting a signal without loss by making a MOS transistor constituting a memory cell conductive sufficiently high.

(3) A circuit for generating an intermediate voltage (VCC / 2) which serves as a reference voltage when detecting a read signal from the memory cell storage plate electrode and further the read signal from the memory cell.

These conventional examples will be described in order below.

The point (1) is as follows. L
Along with the higher integration and larger scale of SI, the parasitic capacitance of the signal wiring increases, which causes a problem that the operating speed is reduced. In the case of a dynamic memory, the speed at which a minute signal read from each memory cell onto the data line is amplified by a sense amplifier, and the input / output control line (common I / O) for reading out information from the selected data line. The operation speed of the line) occupies a large proportion of the operation speed of the whole memory, and the technology for speeding up these operations is indispensable for improving the performance of the memory. As a conventional input / output control circuit, for example, I.E.E.E., Journal of Solid State Circuits, S.C. 22 (1987), pages 663 to 667 (IEEE, Journal of Solid- State Circuits, Vol.
SC-22, No5, October, 1987, pp663-
667) and two MISs.
(Metal Insulator Semiconductor) type FET (Field
In general, an effect transistor is used to apply a selection signal to those gate electrodes to control the connection between the data line pair and the common I / O line pair.

FIG. 20 shows a conventional example of (2).
This shows a circuit related to a DRAM memory cell array (MA) and a word driver (WD). Also,
FIG. 21 shows the waveform of each part. This circuit is, for example, IEEE JOURNAL OF SOLID-STAT.
E CIRCUITS, VOL. sc-21, NO.
3, JUNE 1986, pp. 381-387.

A conventional example of (3) is as follows. D that precharges the data line to VCC / 2 voltage
The RAM system has become the mainstream of 1-megabit and later DRAMs together with CMOS circuits because of its features such as high speed, low power consumption, and noise resistance. An example of the conventional intermediate voltage generating circuit for generating the VCC / 2 voltage is the IEE Journal of Solid State Circuits, Volume 21, No. 5, Nos. 643 to 648.
Page (1986) (IEEE Jounal of Solid-State Circuit
s, vol.21, No.5, pp.643-648, Octorber 1986).

[0013]

The problems to be solved by the present invention as compared with the above-mentioned conventional examples are as follows.

First, the conventional example (1) is as follows. An example of the conventional method is shown in FIGS. 7 (a) and 7 (c).
Shown in. This method is effective for reducing the area of the entire memory because it can be configured with the minimum number of transistors, but it has the following drawbacks. (A) If the MIS-FET (T50, T51) for I / O control is turned on before the signal voltage of the data line (D0, D0) is sufficiently amplified, the operation of the sense amplifier SA0 is hindered. It causes a malfunction.

(B) For the above reason, the selection signal Y01 is applied after the sense amplifier operates, and the MIS-FE is turned on.
It is necessary to set a time delay (timing margin) before T is turned on, which causes a decrease in operating speed (see FIG. 7).
(C)).

(C) In order to prevent such a malfunction, the channel conductance (conductivity between drain and source) of the MIS-FET and the MIS that constitutes the sense amplifier.
There is a design constraint on the channel conductance ratio of the FET. Generally, it is necessary to make the former smaller than the latter, and the common I / O lines (IO0, IO0)
It is difficult to obtain a large driving capacity. for that reason,
In addition to (b), the operation speed further decreases.

(D) With the improvement in the degree of integration of the memory, the internal power supply voltage tends to decrease in order to cope with the reduction of power consumption and the reduction of breakdown voltage of the element. Therefore, the above MI
The driving capability of the S-FET is further reduced, and the operating speed is further reduced.

(E) Mainly because of the reason (c) above, it is difficult to write or read in parallel between one common I / O line and a plurality of data lines connected to it, and it is difficult to perform parallel writing or reading. Restricted in terms of test function such as degree.

For these reasons, the conventional input / output circuit system cannot provide a circuit system suitable for a highly integrated memory which operates at high speed even at a low voltage.

Next, the conventional example of (2) is as follows. As shown in FIG. 20, the word driver is composed of transistors QD and QT. Here, when the X decoder output N1 becomes High level (VL), the gate N2 of QD is charged through QT and QD is turned on.
At this time, the voltage of N2 becomes VL-VT. Next, the word line drive signal φX (amplitude is VL) generated by the peripheral circuit FX.
When (+ VT or more) becomes High level, a current flows from the drain of QD to the source to set the word line W to High level. At this time, the potential difference between the gate of QT and N1 is 0,
Since N2 is Vt, QT is in a cutoff state. Therefore, when φX rises, the voltage of N2 rises with φX due to the coupling due to the capacitance between the gate and source of QD. Here, when φX reaches the maximum value and the voltage between the gate and source of QD is VT or more, the voltage of the word line becomes equal to φX. On the other hand, if φX becomes lower than VT while it rises, the capacitance between the gate and source of QD becomes 0, so N2 rises at that point, and as shown in FIG. 21, VL-VT + α (VL-2VT) /
(1-α). The voltage of the word line is (V _DL -2V
_T ) / (1-α). Here, α is the ratio of the gate capacitance of the QD and the total capacitance of the node N2.

Here, consider a case where VL is lowered to 1.1V due to exhaustion of the battery. α = 0.9, VT = 0.5
If it is set to (V), the voltage of N2 will be 1.5V from the above formula.
Therefore, the voltage of the word line rises only to 1.0V. Normally, the threshold voltage of the switch transistor QS of the memory cell is higher than that of the peripheral circuit and is 0.5 V or more, so that the amount of charge stored in the memory cell is the maximum value (CS
(CS × 0.5) which is less than half of (1.1), soft error resistance and a significant decrease in S / N of the sense amplifier occur. That is, the stored data is easily destroyed.

As described above, when the DRAM is operated by the conventional technique as a battery, if the electromotive force of the battery drops to nearly twice the threshold voltage VT of the MOS transistor, the memory is defective due to the malfunction of the word driver. There is a problem that the write voltage to the cell is lowered and data destruction easily occurs, and there is a problem that needs to be solved.

Regarding (3), the following two problems occur in the conventional intermediate voltage generating circuit due to the lower voltage and higher integration. (A) As the power supply voltage decreases, the voltage setting accuracy decreases, and the signal-to-noise (S / N) ratio deteriorates.

(B) Since the element operates in the source follower mode, the response speed is determined by the driving capability of the transistor and the value of the load capacitance, which increases the load capacitance due to high integration and further increases the load capacitance. The response speed becomes slow because the driving capability of the device is lowered due to the low voltage.

FIG. 30 shows a conventional example of an intermediate voltage generating circuit for DRAM. The above problems will be described below with reference to FIG. In FIG. 30, TN5 and TN6 are N
Channel MIS FETs, TP5 and TP6 are P channel MIS FETs, R1 and R2 are resistors, and CL is a load capacitance. The circuit of FIG. 30 is a kind of complementary push-pull circuit, and TN6 and TP6 are the power supply voltage VC.
A voltage divider circuit that divides C (VSS is ground potential) into an intermediate voltage of HVC is configured, and TN5 and TP5 for applying a bias voltage to these gates configure a bias circuit. In the VCC / 2 precharge type DRAM, the load capacitance is almost equal to the total data line capacitance, 5 to 10 nF (nano farad) in the 4-megabit DRAM and 20 to 40 nF in the 16-megabit DRAM.
In a 4-megabit DRAM, the value is about 80 to 160 nF. In this circuit, the output is stabilized to a constant voltage by constantly passing a minute current through each FET. If the current is very small, terminals 20 and 22
The voltage difference of V, that is, V (20) -V (22) is almost FET
The threshold voltage VTN of TN5, and the voltage difference between the terminals 22 and 21, that is, V (22) -V (21), is almost F.
It becomes equal to the absolute value VTP of the threshold voltage of ETTP5. Further, the gate width-to-gate length ratio W / L of the FETs TN6 and TP6 is W of TN5 and TP5, respectively.
/ L is selected to be several times to several tens of times. Therefore, the bias current of TN6 is several times to several tens times the bias current of TN5.

First, the first problem will be described.
Assuming that there is no difference in device characteristics (eg, threshold voltage, channel conductance per unit gate width, etc.) between the FET pair TN5 and TN6 and TP5 and TP6, the output HVC is connected to the terminal 22. A voltage equal to the voltage of is obtained. The output voltage is V (HVC) = R2 / (R1 + R2) × VCC-R2 /
(R1 + R2) × VTN + R1 / (R1 + R2) × VT
Expressed as P. Here, it is assumed that VSS is at the ground potential. Under standard conditions, VTN and VTP values are almost equal, and R1 =
When designed to be R2, V (HVC) = VCC / 2−VTN / 2 + VTP / 2 That is, when the difference between the values of VTN and VTP can be ignored compared to the value of VCC, V (HVC) ≈VCC / It becomes 2. In general, it is considered that the variation in the threshold voltage of the element does not become small even with high integration, and is constant, so that V (HVC) decreases as VCC decreases.
The setting accuracy of is reduced. For example, assuming that VTN and VTP each fluctuate ± 0.1V with respect to the standard value, when the power supply voltage is 5V (HVC is 2.5V),
The fluctuation of the intermediate voltage is about ± 4%, whereas when the power supply voltage is 1.5V (HVC is 0.75V), the fluctuation of the intermediate voltage reaches about ± 13%, and the stable operation of the memory is achieved. I'm having trouble.

Next, the second problem will be described. When the load is charged / discharged, the output MISFET operates in the saturation region, and therefore its drain current ID is expressed as ID = β / 2 × (VGS-VT) ² . Where VGS is the gate-source voltage,
VT is the gate threshold voltage of the MISFET, and β is a constant determined by the structure and size of the element. Now, in the conventional circuit, the time t required to raise the voltage of the load (load capacitance = CL) from 0 V to 90% of the intermediate voltage VCC / 2.
r is represented as tr = 18CL / β × 1 / (VCC / 2). The number of memory cells connected to one data line is 256, and the capacitance value per one data line is 0.5p.
Suppose F. Since these values are almost constant as the memory is highly integrated, the value of the load capacity becomes four times larger for each generation. For example, in a 4 Mbit DRAM, CL≈
CL = 33nF, 64M for 8.2nF, 16Mbit
In bits, CL≈131 nF. On the other hand, when the power supply voltage decreases from generation to generation, 5V → 3.3V → 1.5V, if β of the MISFET is constant at 10 mA / V ² ,
The rise time tr increases from 5.9 μs → 36 μs → 314 μs by about 10 times for each generation. In order to keep the response speed constant, β of the MISFET needs to be increased 10 times for each generation. However, the rise time is actually increased due to the side effect of increasing the layout area and increasing the steady current. It is impossible to keep tr constant.

It is an object of the present invention to solve the conventional problems described above and to provide a semiconductor device that operates stably at high speed even at a low voltage. More specifically, it aims at the following three.

(1) It operates at high speed even at a low voltage, has excellent operational stability, and has a parallel test function.
To provide a method of an input / output control circuit for a highly integrated memory.

(2) To provide a circuit capable of generating a sufficiently high word line voltage so that data destruction does not occur even when the electromotive force of the battery is lowered.

(3) To provide a voltage supply circuit (voltage follower) that operates with high accuracy and high speed even in a highly integrated, low power supply voltage LSI.

[0032]

In order to achieve the above-mentioned object (1), an input / output control circuit for reading information from a data line or writing information to a data line is provided on the left and right sides of a memory array. And the common I / O lines and the data lines have different transmission impedances when the information is read and when the information is written. Further, as a sense circuit for detecting a signal on the read line (RO line), an M complementary to the MISFET for selection is used.
A current-voltage conversion means by ISFET is provided. This means is intended to operate at high speed even at low voltage.

In order to achieve the purpose of (2), the following measures are taken as described in the claims. That is, (a) an output of a data line power supply that applies to the data line a voltage that is 1.5 to 2 times the threshold voltage of the switch transistor of the memory cell array as the lowest operating voltage applied to the memory cell array and the data line. In a semiconductor integrated circuit having a word driver, a voltage conversion circuit for converting a data line power supply voltage into a voltage higher than the data line voltage by a threshold voltage of a switch transistor of a memory cell array or more,
A static word driver that operates using the output of the voltage conversion circuit as a power source is provided to drive the word line.

(B) The voltage conversion circuit of the above-mentioned first means has a structure of a charge pump circuit and a rectifying circuit.

(C) The charge pump circuit in the means of the above-mentioned item 2 includes first, second, third and fourth MOS transistors and first and second capacitors, and the second, third, The drain of the fourth MOS transistor serves as a power source, the gate of the second MOS transistor serves as the source of the fourth MOS transistor, the source of the third MOS transistor serves as the source of the second MOS transistor, and the third and fourth The gate of the MOS transistor is connected to the power supply, one terminal of the first capacitor is the source of the fourth MOS transistor, and one terminal of the second capacitor is the second MO transistor.
In the charge pump circuit, which is connected to the source of the S transistor and the other ends of the first and second capacitors are supplied with pulses of opposite phases, the drain of the first MOS transistor is further supplied with power. The source to the source of the fourth MOS transistor and the gate to the second
It was decided to connect to the source of the MOS transistor.

This means further speeds the start-up of the charge pump circuit even at a low power supply voltage and further increases the output voltage thereof.

(D) In the rectifier circuit in the means of the second item, the rectifying element is composed of a MOS transistor, the drain of the MOS transistor is an input and the source is an output, and the input is the charge described in the third item. Pump circuit,
The source is connected to a circuit for transmitting the electric charge from the output, a capacitor for storing the electric charge and a circuit for transmitting the electric charge to the power supply, and when the voltage of the input is at the high level, one end of the capacitor is set to the high level. The gate voltage of the MOS transistor is set equal to or higher than the sum of the input voltage and the threshold voltage of the MOS transistor, and when the voltage of the input is low level, one end of the capacitor is set to low level and at the same time the gate voltage of the MOS transistor is set to low level. It was decided to use the power supply voltage.

This means reduces the voltage drop of the rectifying transistor and obtains a high output voltage.

(E) In the means of the above-mentioned items 1 and 2, the threshold values of the MOS transistors used in the memory cell array, the word driver and the voltage conversion circuit are three kinds,
The memory cell array has the highest value, the word driver has the highest value, and the voltage conversion circuit has the lowest value.

The present means achieves further stabilization, higher speed, and lower power consumption as an integrated circuit even at a low power supply voltage.

Further, in order to achieve the above-mentioned object (3), in the semiconductor device of the present invention, the input of the reference voltage equal to the intermediate voltage and the at least two first and first outputs for connecting the output in parallel to the same load are connected. The second complementary push-pull circuit and the push-pull current amplification circuit that amplifies and outputs the reference current are provided.
The push-pull circuit includes, in its bias circuit, an input of the reference voltage and a bias voltage source added to the input,
A bias voltage is applied to the gate of the voltage dividing transistor of the push-pull circuit, and the voltage dividing circuit of the push-pull circuit forms the reference current circuit of the current amplification circuit.
Moreover, the output terminal of the current amplification circuit is connected to the bias circuit of the second complementary push-pull circuit.

That is, a reference voltage generation unit equal to the intermediate voltage is provided separately from the bias circuit of the complementary push-pull circuit, and at least two complementary push-pull circuits drive the load in parallel to output the output. The difference between the voltage and the input voltage is detected as a current flowing through one push-pull circuit, and the other push-pull circuit is driven by an amplified current that is substantially proportional to the current.

Here, it is preferable that the bias voltage of the first and second complementary push-pull circuits is made substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied. This keeps the current flowing through these transistors low in the steady state.

Alternatively, if the current amplifying circuit is a current mirror type push-pull amplifying circuit, a high driving ability can be easily obtained with a simple circuit configuration with little variation.

Alternatively, it is preferable that the first and second complementary push-pull circuits are composed of field effect transistors because they can be operated with a low power supply voltage.

In the semiconductor device of the present invention for achieving the above-mentioned object (3) more effectively, an input of a reference voltage equal to the intermediate voltage and at least two first outputs for connecting the output in parallel to the same load are connected. And the second complementary
The first complementary push-pull circuit includes a push-pull circuit, a tri-state drive circuit, and a push-pull current amplification circuit that amplifies and outputs a reference current. A bias voltage source added to the current amplification circuit, the voltage division circuit of the push-pull circuit forms a reference current circuit of the current amplification circuit, and the output terminal of the current amplification circuit is connected to the second complementary push-pull circuit. Connecting to a bias circuit, the tri-state drive circuit,
A first determination voltage lower than the input voltage and a second determination voltage higher than the input voltage are provided, and when the output voltage is lower than the first determination voltage, the output is charged, and the output voltage is It is characterized by comprising means for discharging the output when the voltage is higher than the second judgment voltage.

That is, in the present invention, the tristate drive circuit is connected in parallel with the load together with the complementary push-pull circuit to supplement the drive capability of the push-pull circuit.

Here, the bias voltage of the first and second complementary push-pull circuits is set to a voltage substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied, or As described above, it is preferable that the current amplifying circuit is a current mirror type push-pull amplifying circuit, or that the first and second complementary push-pull circuits are composed of field effect transistors.

Here, it is preferable to properly set the input and output voltages to ½ of the power supply voltage in order to properly apply to a circuit such as a DRAM.

Furthermore, an integrated circuit (LSI) which includes at least a plurality of blocks of the same kind and which brings one or a plurality of blocks selected by the block selection signal into an operating state and a voltage is supplied to the blocks as a load. In the case of a semiconductor device having a driving means, in order to achieve a high-speed response, as the driving means for driving the block, first and second driving circuits, and a block provided in each block and in an operating state. And a switching means for connecting the non-operating block to the second drive circuit.

Such means is suitable for an integrated circuit such as a large capacity dynamic memory.

In such a case, the block includes at least a memory cell array, and as the load, a precharge voltage supply of a data line for transmitting a signal from the counter electrode of the memory cell storage capacitor and the memory cell to the signal detection circuit. It is preferable to include at least a line.

Here, it is preferable from the viewpoint of application to DRAM that the drive circuit generates a voltage which is half the power supply voltage.

Further, if the semiconductor device of the present invention is used as the drive circuit, the accuracy is improved even for a large capacity LSI,
It is possible to achieve speedup.

With regard to (1), since the input / output control circuit can be laid out at a pitch twice the data line pitch with the above configuration, the optimum input / output can be achieved without significantly increasing the chip area as compared with the prior art. A circuit configuration can be taken. As a result, the operation margin of the input / output circuit is remarkably improved, and stable and high speed operation can be achieved even with a low voltage. Further, even if writing and reading are performed in parallel, the operation is stable, so that a parallel test with a high degree of parallelism is possible.

Regarding (2), the static type word driver has a P-channel transistor connected to the power supply side and an N-channel transistor connected to the ground side.
Therefore, if the gate is set to the ground level (0 V) when driving the word line, the P-channel transistor is always turned on if the power supply voltage is equal to or higher than the threshold voltage VT.
Its output voltage rises to the power supply voltage. As described above, since the gate voltage of the drive transistor operates at a low level, the static word driver operates stably even with a low power supply voltage.

Therefore, by using the output of the voltage conversion circuit as the power source of the word driver, it is possible to apply a voltage higher than the data line voltage by the threshold voltage of the switch transistor of the memory cell array or more as the word line voltage. As a result, it becomes possible to stabilize the memory operation even if the power supply voltage drops to about 1V.

Furthermore, the charge pump circuit of the present invention feeds back its output voltage to the precharge transistor, and by using this output voltage in the voltage conversion circuit, a fast rise and a high output voltage are obtained even for a low power supply voltage. It will be possible.

The rectifier circuit of the fourth term of the above means synchronizes the gate voltage of the rectifying transistor with the output voltage of the charge pump circuit, and when the output thereof, that is, the drain voltage of the transistor is at the high level, the gate voltage is changed. The threshold voltage is made higher by the threshold voltage or more, and both are set to the same level at the Low level. This makes it possible to reduce the voltage drop of the rectifying transistor and prevent the backflow of charges.

When the threshold voltage of the transistor is lowered, the driving capability of the transistor generally increases. Therefore, it is effective to use such a transistor in a voltage conversion circuit whose scale is not so large as in the fifth term of the above means. However, as will be described later, in the case of using a large number of transistors like a word driver, conversely, the leakage current flowing in the off state of the transistors cannot be ignored, and therefore the standard threshold current is used. Further, when the threshold voltage of the transistors of the memory cell array is lowered, the refresh interval is shortened as described later, resulting in an increase in power consumption. Therefore, it is preferable to use a transistor higher than the standard one.

That is, the fifth term of the above means acts to further stabilize the integrated circuit even at a low power supply voltage, to increase the speed, and to reduce the power consumption.

With regard to (3), by dividing the generation unit of the reference voltage equal to the intermediate voltage from the bias circuit of the complementary push-pull circuit, the voltage can be set independently of the bias circuit, and the intermediate voltage The output can be made highly accurate.

Further, the voltage difference between the input and the output is converted into a current through the transistor of the first complementary push-pull circuit, and the second complementary push-pull circuit is driven by the amplified current proportional to the current. As a result, while there is a voltage difference between the input and output, the drive capacity of the push-pull circuit is increased, and the load capacity is charged and discharged at high speed. In addition, the charging and discharging driving capacities at that time can be made uniform, so that it is possible to provide a voltage supply circuit (voltage follower) that operates stably at high speed even at a low voltage.

Further, as described above, if the bias voltage of the complementary push-pull circuit is made substantially equal to the threshold voltage of the voltage application transistor and the current of the push-pull circuit is suppressed to a low value, the semiconductor device can be regulated. It becomes possible to obtain a high driving capability when the output voltage fluctuates while constantly reducing the power.

If a current mirror type amplifying circuit is used for the current amplifying circuit, not only the current can be amplified with a simple circuit configuration, but also the same kind of element is used for the transistors of the mirror circuits which require the same characteristics. As a result, it becomes possible to easily obtain high driving capability with little variation.

Since the gate threshold voltage of the field effect transistor can be lowered by controlling the impurity concentration, the power supply voltage can be reduced by configuring the first and second complementary push-pull circuits with field effect transistors. Even if it becomes lower, the required operation can be easily obtained.

Further, according to the above-mentioned means of connecting the tri-state drive circuit together with the complementary push-pull circuit in parallel to the load, when the voltage error between the input and output becomes larger than the above-mentioned judgment voltage, the load is increased. By charging or discharging the capacitor, the voltage error operates so as to converge within the determination voltage, thereby compensating for the push-pull circuit operation and further increasing the response speed during the transient.

Further, according to the means of the present invention, which includes a plurality of blocks of the same kind in an integrated circuit, and when a part of them is operated, only the block in the operating state is selected as a load, the large capacity DRAM is provided. In such a case as well, since a part of the load is substantially carried, a high-speed response can be achieved without flowing a large transient current. In addition, if the device of the present invention is used for this drive circuit, it becomes possible to more effectively obtain high-accuracy and high-speed response as described above.

[0069]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be specifically described below with reference to Examples. In the following description, an example in which the present invention is applied to a dynamic memory (DRAM) will be described. However, other than this, for example, a static memory (SRA)
M) and read only memory (ROM) are also applicable. In addition to the memory using the MIS type FET element, a memory using a bipolar element, a so-called BiCMOS type memory in which a bipolar element and MIS-FET are combined, and a semiconductor material other than silicon are used. The same can be applied to the memory.

1 to 6 show an embodiment of the memory circuit of the present invention. 1 to 6, MA is one MIS-F
A memory cell array in which a plurality of memory cells each consisting of ET and one storage capacitor are arranged two-dimensionally, CKT0, CKT1
Is an input / output control circuit for detecting a memory cell signal and exchanging information with the outside of the memory through a read line or a write line, between D0 and D0, D1 and D1 A data line pair for transmitting signals, WD is a word line drive circuit for designating a row address in the memory cell array and applying a drive signal to one word line, W0 to Wm are word lines, YD Is Y for designating the column address of the memory cell array.
A (column) decoder and Y01 are column selection signal lines, respectively. In the input / output control circuit, SA0, SA
Reference numeral 1 is a detection circuit (sense amplifier) for detecting a minute signal voltage on the data line, CSN0 and CSP0, CSN1.
And CSP1 are drive signal lines for the detection circuits SA0 and SA1, CD0 or CD1 are drive signal generation circuits for the detection circuit, and PR0 and PR1 are for operating the sense amplifier while short-circuiting the data line pair in the non-operating state. RG0 or RG1 is a precharge circuit for setting a good voltage of T1, a read gate for reading a signal (voltage difference) appearing on the data line pair to the outside of the memory array, and T1.
~ T4 is an N channel MIS- which constitutes a read gate
FET, WG0 or WG1 is a write gate that drives a data line according to external information, T5 to T8 are N-channel MIS-FETs that form one write gate,
RO0, RO0￣, RO1, RO1￣ are reading lines, W
I0, WI0-, WI1, WI1- are write lines, RC
S0, RCS0-, RCS1, RCS1-represent read control lines, and WR0, WR0-, WR1, WR1-represent write control lines. In addition, SWR0, SWR
1 is a common reading line from the reading line CRO, CRO
SWW0 and SWW1 are switch circuits for connecting to the write line and the common write lines CWI and CWI, and SEL0 and SEL1 are signals for selecting either the left or right switch. AMP is CRO
A sense amplifier for detecting and amplifying a signal appearing on CRO, DOB is an output buffer, and DIB is an input buffer. In this embodiment, the input / output control circuits CKT0, CKT1
Are alternately arranged on the left and right of the memory cell array for each data line pair, and the I / O line in the input / output control circuit is separated into a read line (RO line) and a write line (WI line). .
Hereinafter, these specific configurations and effects will be described.

FIG. 2 shows a plan layout diagram of the read gate and write gate circuits. Generally, as the degree of integration of the memory increases, it becomes difficult to lay out the input / output control circuit Ci at the data line pitch.
However, by arranging the input / output control circuits alternately on the right and left sides of the memory cell array as in this embodiment, the layout pitch of the input / output control circuits is twice the pitch of the data line pairs, that is, 2
Since it can be dy, layout can be performed without significantly increasing the chip area. In high-integrated memory, for example, IEE Journal of Solid State Circuits, 23 (1988).
Year) pp. 1113 to 1119 (IEEE, Journal of So
lid-State Circuits, vol.23, No.5, October 1
988, pp1113-1119), there is a problem that the signal-to-noise ratio is significantly reduced due to capacitive coupling between adjacent data lines. It is known that the capacitive coupling noise in the memory cell array part can be reduced by a method such as crossing the data lines in the middle of the memory cell array. Since it was non-uniform, it was not possible to sufficiently reduce noise. In this embodiment, by providing a shield wiring between the data line pair of the input / output control circuit, it is possible to significantly reduce the line-to-line capacitive coupling noise as compared with the conventional case. This will be described below. In the layout of the input / output control circuit unit as shown in FIG. 2, another signal line formed simultaneously with the data line is arranged between the data line pair. Here, for example, the reading gate RGi
Reading lines RO and R that are wired perpendicular to the data lines in the section
The O and read control lines RCS and RCS are connected to the wiring material formed at the same time as the data line through the through hole and arranged in parallel with the data line. By doing so, the parasitic capacitance between the data line and the adjacent data line can be reduced, the noise accompanying the read operation can be minimized, and stable operation can be expected.

Next, the specific configurations of the read switch SWR0, the write switch SWW0, and the sense amplifier circuit AMO will be described.

FIG. 3A shows a read switch SWRi (i
= 0, 1). In this circuit, one of the plurality of read lines ROi and ROi is connected to the common read line CRO,
The signal is taken out to the read line by controlling the voltage of the read control lines RCSi and RCSi of the selected memory block while being selectively connected to CRO. In the figure, T10 to T17 are N channel MISs.
FET and INV100 are inverters, and NAND1 is a 2-input inverting AND circuit that outputs a low level only when both inputs are at a high level. When the memory block is selected and the selection signal SELi is at a high level and the memory is in the read state and the write signal WE is at a high level, the MISFETs T10 to T13 are conductive and T14 to T17 are nonconductive. Therefore, the read lines ROi and ROi are respectively the common read lines CRO and
Read control line RCS connected to CRO
i and RCSi are grounded. As a result, for example, when the column selection signal Y01 becomes high level in FIG. 1, T3 and T4 become conductive, and the read lines RO0 and RO0 are read to the read control line RCS in accordance with the voltage difference between the data line pair D0 and D0.
A signal is obtained as the difference between the currents flowing through 0 and RCS0. Here, the read control lines RCS0 and RCS0 are not necessarily separated in consideration of only the read operation, but separation is indispensable when performing a parallel test as described later.

When the memory block is deselected and the selection signal SELi is at the low level or the memory is in the write state and the write signal WE is at the low level, the MISFET
T10 to T13 are non-conductive, and T14 to T17 are conductive. Therefore, the read lines ROi and ROi and the read control lines RCSi and RCSi are connected to the same voltage (here, the intermediate voltage HVL). As a result, for example, even if the column selection signal Y01 becomes high level in FIG. 1 and T3 and T4 become conductive, no current flows from the read lines ROi and ROi to the read control lines RCSi and RCSi. As described with reference to FIG. 10, it is convenient to select a column address of a plurality of memory blocks (including a selected block and a non-selected block) with one column selection signal line.

FIG. 3B shows the write switch SWWi (i
= 0, 1). In this circuit, one of the plurality of write lines WIi and WIi is connected to the common write line CWI,
Writing is performed by selectively connecting to CWI and setting the write control line WRi of the selected memory block to a high level. In the figure, T20,
T23 to T26 are N-channel MISFETs, T21, T
22 is a P channel MISFET, INV101 to INV
Reference numeral 103 indicates an inverter, and NAND2 indicates a 2-input inverting AND circuit. When the memory block is selected and the selection signal SELi is at the high level and the memory is in the write state and the write signal WE is at the high level, MI
The SFETs T20 to T23 are conductive and T24 to T26 are non-conductive. Therefore, the write lines WIi and WIi are connected to the common write lines CWI and CWI, respectively, and a high level is output to the write control line WRi. Thus, for example, in FIG. 1, the column selection signal Y01
Goes high, T5 and T6 become conductive, the data line pair D0 and D0 is connected to the write lines WI0 and WI0, and the write information on the write line is written to the data line.

When the memory block is deselected and the selection signal SELi becomes low level, or the memory is in the read state and the write signal WE becomes low level, the MISFET is turned off.
T20 to T23 are non-conductive, and T24 to T26 are conductive. Therefore, the write lines WIi and WIi are connected to the same voltage (here, the intermediate voltage HVL), and
The write control line WRi goes low. As a result, for example, even if the column selection signal Y01 becomes high level in FIG. 1 and T5 and T6 become conductive, the data line and the write line do not become conductive. Therefore, as described in FIG.
This is convenient when the column address of a plurality of memory blocks (including the selected block and the non-selected block) is selected by one column selection signal line.

Next, FIG. 4 shows common read lines CRO and CRO.
The configuration of the sense amplifier circuit for amplifying the read signal is shown. In the figure, amp1 is a first sense amplifier circuit that inputs common read lines CRO and CRO, and outputs d1 and d1, and amp2 is a second sense amplifier circuit that inputs d1 and d1 and outputs d2 and d2. Sense amplifier circuit,
amp3 is a third sense amplifier circuit that inputs d2, d2 ￣ and outputs d3, d3 ￣, and T42 and T43 are MISFETs for initializing the third sense amplifier circuit before operation.
Is. The first sense amplifier circuit amp1 has the same configuration as 2
It consists of two current-voltage conversion circuits. The current-voltage conversion circuit is a differential amplifier circuit DA1, P-channel MISFET T3
0, N channel MISFET T31. The second sense amplifier circuit amp2 is composed of two differential amplifier circuits DA3 and DA4 having the same configuration. The third sense amplifier circuit amp3 includes two inversion OR circuits MOR1,
NOR2, two inverters INV105, INV10
It is composed of 6.

Next, the operation of this embodiment will be described with reference to the operation waveforms of FIGS. Here, an example of reading information read on the data lines D0 and D0 and writing external information to D0 and D0 is described, but the same operation is performed in all the memory arrays. Obviously, it can be selectively performed on the memory cells.
Further, although the case where the operating voltage is 1.5 V has been described here, the present invention is not limited to this, and the present invention can be similarly applied and the same effect can be obtained even when operating with another voltage.

First, the read operation will be described with reference to FIG. The control signal PC of the precharge circuit section PR0 falls at time t0, and the precharge operation for the data line is completed. Subsequently, the selected word line W0 rises at t1,
A signal is read from the memory cell to the data lines D0 and D0. Next, at t3, the sense amplifier drive signal CSP is changed from the intermediate potential to the high level and CSN is changed from the intermediate potential to the low level to drive the sense amplifier SA0. This allows
The signal read to the data line is Hig by the sense amplifier.
It is amplified to h and Low. Here, in this embodiment, the data line is read out from the transistors T1 and T in the read gate RG0.
It is connected to the gate of 2 and is connected to read lines RO0 and RO0 through transistors T3 and T4. Read control lines RCS0, R of the selected input / output circuit CKT0
CS0 is driven low at t1. This configuration separates the data line from the read line, so the data line
In the middle of the amplification before being set to the high and low levels, here, at t3, even if the column selection signal line Y01 is input, the information of the data line is not destroyed. Therefore, the information on the data line can be transmitted to the read line without destroying the information, so that the read operation can be speeded up. The reason why the speed can be increased and the effect thereof will be described in detail later. Here, the signal voltages of the read line and the common read line, that is, RO0, RO0 and C
The voltage difference between RO and CRO is about 20 mV, the output signal amplitude of the first sense amplifier circuit (voltage difference between d1 and d1) is about 200 mV, and the output signal amplitude of the second sense amplifier circuit (d2 and d2). The voltage difference is about 1 to 1.5V. That is, the voltage amplification factor of the first sense amplifier circuit is approximately 10 and the voltage amplification factor of the second sense amplifier circuit is approximately 5 to 5.
It is about 7. The voltage amplification factor of the third sense amplifier circuit is 1
~ 2. However, the third sense amplifier circuit has a function of storing output information, a so-called latch function. That is, by amplifying the input signal and then turning both inputs low, the output corresponding to the previous input is held until the next input is input. As a result, it is not necessary to keep all of the first to third amplifier circuits in operation at all times, and after output, the first and / or second amplifier circuits are deactivated to reduce power consumption. can do.

This drawing also shows an example of so-called static column operation in which after reading one information, the column address is switched to read other information. That is, Y23 is raised next to the column selection signal Y01 to read information. According to the present embodiment, the voltage amplitude of the read line and the common read line is 20 mV, which is 1 / the conventional value, by inputting a current to the sense amplifier circuit as described later.
It has been reduced to 10. As a result, the time required for charging and discharging the parasitic capacitance of the read line and the common read line is about 1/10.
The delay from switching the address to outputting the information can be made extremely small.

Next, an example in which the read operation is followed by the write operation will be described with reference to FIG. In the figure, the first read operation is the same as in FIG. When WE becomes high at t4, the column selection signal line Y01 remains High, and the control signal line RCS0 of RG0 becomes HVL (0.
75V), the control signal line WR0 of the write gate WG0 becomes "High". Along with this, the input / output line WI for writing
When write data is given to 0 and WI0, transistors T5, T7, and T in the write gate WG0 are given.
Data is written to the data lines D0 and D0 through T6 and T8.

As shown in the above example, as a means for changing the transfer impedance between the I / O line and the data line in the write operation and the read operation, by separating the read line and the write line, the read Since the operation margin and the write operation margin can be set individually, it is possible to speed up and stabilize the operation even in low voltage operation.

Next, the effect of the sense amplifier circuit used in this embodiment will be described with reference to FIGS. FIG. 7A schematically shows the configuration of a conventional sense amplifier circuit, and FIG. 7B schematically shows the configuration of the sense amplifier circuit according to the present invention. See also FIG.
FIG. 3C schematically shows operation waveforms of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention. In the conventional circuit, from the memory cell MC to the data lines (D0, D0
The minute signal read out to (1) is amplified by the sense amplifier SA0 and then controlled by the column selection signal Y01.
Turn on T T50 and T51 and turn on the read line (IO
0, IO0). The conventional circuit has two problems that hinder the speedup. One is that the MISFET must be turned on after it has been sufficiently amplified by the sense amplifier. Otherwise, the data line (CD about 0.
This is because there is a capacitance difference of several tens of times between the read line (3 pF) and the read line (CR about 8 pF), and a large amount of charge flows in from the read line, destroying the information that has been amplified. The other is that it is necessary to amplify a read line having a large parasitic capacitance to a voltage as large as 200 mV by a sense amplifier having a small driving capability. This is because of the signal detection sensitivity of the second sense amplifier circuit in the next stage.

Therefore, in the present invention, the NMOS transistors T1 and T2 whose gate receives the signal of the data line are provided,
Separated the sense amplifier and the read line. As a result, the MISFETs T3 and T4 controlled by the column selection signal can be turned on without waiting for the data line to be sufficiently amplified. Therefore, the voltage information of the data line is converted into current information and read at high speed. You can get out. Further, in order to be suitable for low voltage operation, a current sense circuit achieved by a P-channel MISFET and an amplifier circuit is provided so that a voltage output proportional to a current input can be obtained. By using current input, the voltage amplitude of the signal line is about one digit (20
(0 mV → 20 mV), and the time required for charging / discharging the parasitic capacitance CR is significantly shortened and the speed is increased.

FIG. 8 is a comparison of the operating speeds of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention based on the computer simulation results. Here, the sense time is the signal CSN, C for starting the sense amplifier.
The delay time from when the SP is turned on until the signal voltage of 200 mV is obtained on the I / O line (in the conventional case) or until the output of 200 mV is obtained at the output of the first sense amplifier circuit (of the present invention). The case is defined by the delay time.
With the circuit of the present invention, it is 20 ns at 1.5 V compared to the conventional
Since the speed is increased, it has been shown that the present invention operates at low voltage and high speed.

As described above, in this embodiment, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array, and the read and write input / output lines are separated from each other.
It is possible to speed up and stabilize the operation even in the low voltage operation. Further, the first sense amplifier circuit for detecting the signal of the read line is composed of a current-voltage conversion circuit, and the MISFET for driving the read line and the MISFET for converting the voltage of the data line into the current of the read line are complementary. With this configuration, it is possible to provide a sense amplifier circuit that operates at high speed even with a low power supply voltage of about 1 to 2V.

FIG. 9 shows an embodiment for further stabilizing the operation. As described above, the parasitic capacitance between the data lines could be reduced in the input / output control circuit section. Here, the operation is further stabilized by balancing the parasitic capacitance between the data lines in the memory cell array section. That is, the data lines are crossed line by line at the center of the memory cell array. The parasitic capacitances between D1 and D1 and data line D0 are Cc01 _L and Cc01 _R , respectively.
However, since Cc01L and Cc01R match, D
The parasitic capacitances between 1, D1 and data line D0 can be made equal. Similarly, since the parasitic capacitances between D1 and D1 and the data line D2 can be made equal, the parasitic capacitance between adjacent data lines can be balanced by the paired data lines. Therefore, the read operation can be further stabilized even in the memory cell array.

FIG. 10 shows an embodiment in the case where a plurality of memory cell arrays exist, and the read operation will be described here. The input / output control circuit CKTij is shared by the left and right memory cell arrays, switch transistors T60 to T63 are connected between CKTij and each memory cell array, and their gates are SHRij which is a selection signal of the memory cell array. Is entered. SWRi is read line R
This is a switch connected to a common read line CRO shared by O and a plurality of RO lines, and the selection signal SHRij of the memory cell array is also input to this switch. SHRij is set to High in advance, and for example, when the memory cell array MA2 is selected, SHR1 _R and SHR3 _L are selected.
Only low. If the column selection signal Y01 is selected, the data lines D1, D1 and D0, D0 are selected.
The signal read to ￣ is the input / output control circuit CKT12, C
RO12, RO12, RO23, R through KT23
It is read out to O23. These are switches S
Common I / P line CRO0, through WR1 and SWR2
It is read to CRO0, CRO1, and CRO1. As described above, even when there are a plurality of memory cell arrays, it is possible to arrange the input / output control circuits alternately on the left and right of the memory cell array and share them with the left and right memory cell arrays without increasing the chip area significantly. It is possible to improve the characteristics described above.

FIG. 11 shows an example of parallel testing using the present invention. The parallel test is performed by simultaneously selecting a plurality of column selection signals (multiple selection). That is, in the parallel test, the column selection signal is multiplex selected by the test signal TEST. As a result, in the read operation, the read signals of the data lines are read simultaneously on the read lines according to the multiplicity. If all the information of the data lines read at the same time is the same, one of the read lines RO and RO is a "High" voltage level according to the read information and the other is "Lo".
The voltage level becomes w ”. If even one error information is read, both RO and RO become“ Low ”voltage level. On the other hand, in the write operation, the input / output line for writing was selected. The data is written to the data line connected to the write gate.Here, in the present invention, even in the case of the parallel test, the parallel test can be performed without providing a new test I / O line, and the data can be written in the same manner as the normal test. Line to am
Information is transmitted to P. Further, since the read signal line and the write signal line are separated, as described above, the operation margin can be set individually for the read operation and the write operation, and there is no restriction on increasing the multiplicity. It is eliminated and a high degree of parallel read / write is possible. In the same figure, the drive signal RCS of the read gate RG is paired to separate the RCS connected to the read lines RO and RO in the read operation. This is an effective means for discriminating one misread even when the multiplicity is increased. When the multiplicity is increased, it is necessary to increase the current flowing from RO to RCS. On the other hand, the current flowing from RCS to GND saturates at a certain level due to the wiring resistance of the read line. In other words, R
The potential of CS rises. Therefore, if the RCS is not separated, the signal current of the I / O line on the side where misreading occurs will decrease with an increase in the multiplicity, making detection difficult. By separating RCS, the potential of RCS on the misread side does not rise and only the current flowing from RO to RCS need be detected, so that more accurate detection can be performed. As mentioned above,
Since the present invention enables a high degree of parallel testing, a significant reduction in test time can be realized.

FIG. 12 shows an embodiment of a concrete circuit for determining the multiplicity. Normally, Y0 to Yn-1 are applied to the column decoder YD.
Is entered. Yn-1 divides the column direction into two, and Yn-2
Is further divided into two, and so on. Y0 repeats "0" (Low) and "1" (High) for each column selection signal. Here, the test signal TEST is set to High and Yn
The OR gate output signals of −1−, Yn−1 and TEST are AYn−1, AYn−1 ′, and these are Yn−1, Y
By inputting to the column decoder instead of n-1, Yn-1
AYn-1, AYn-1 'regardless of High or Low
Since both can be set to High and two column selection signals can be selected, the multiplicity can be set to 2.

FIG. 13 shows an embodiment in which the multiplicity is 4.
The NAND gate outputs of Yn-1 and Yn-2 are input to the NAND gate together with TEST, and their outputs are AYn
The multiplicity can be set to 4 by setting -20 to 3 and inputting them to the column decoder. As described above, based on the embodiments shown in FIGS. 12 and 13, multiple column decoders can be selected during the parallel test, and the test signal TEST is set to Low during the normal test.
Thus, one column selection signal can be selected. FIG. 14 shows an embodiment of the sense amplifier circuit for realizing the parallel test. A method of outputting the test result during the parallel test will be described with reference to FIG. During a normal read operation, the two differential amplifier circuits DA that constitute amp2T
4, the output after current-voltage conversion is directly input to the inverting and non-inverting inputs of DA5, and those outputs are input to amp3. Two differential amplifier circuits DA during parallel test
4, V _RT is input as a reference voltage to the non-inverting input of DA5. In the parallel test, if at least one of the data lines selected in multiplex contains misinformation, RO, RO￣
An electric current flows through both. Therefore, the current-voltage conversion outputs d1 and d1− of the first sense amplifier circuit amp1 both become low level. On the other hand, the reference voltage V _RT is set to a voltage between the high level and the low level of the current-voltage conversion output.
In this way, if even one false information is included, 2
A high level is output to the outputs of the two differential amplifier circuits DA4 and DA5. That is, when both d2 and d2 are at a high level, it can be determined that the information read in parallel contains erroneous information. At the time of the parallel test, these outputs are taken into the judgment circuit TEJ by setting TEST to Low. TEJ is ERR according to the output voltage of d2, d2
Outputs High or Low to. That is, if all the results of the parallel test are correct, ERR outputs Low, and if even one is incorrect, it outputs High. In this way, the determination of the parallel test result with the increased multiplicity can be performed using the input / output circuit system and the sense amplifier circuit according to the present invention.

FIG. 15 shows the reference voltage V _RT used in the parallel test.
It is an example of a generation circuit. Also in the figure, the current-voltage conversion circuit described above is used, and V _RT is generated by setting the parallel test signal TEST to High during the parallel test. In this circuit, a reference current corresponding to about half the signal current is applied to the input of the current-voltage conversion circuit. As a result, when a signal current flows through both RO lines, the converted voltage becomes smaller than V _RT . If the result of the parallel test is correct, one of the converted voltages is higher than V _RT . Therefore, the test result can be discriminated by comparing the converted voltage with VRT.

FIG. 16 shows a specific example of the write switch SWW. WE is a write signal. The present embodiment is based on FIG. 10, where there are a plurality of memory cell arrays, and it is assumed that the memory cell array on the right side of the SWW operates (SELR is High, SELL is Low). TEST is low during parallel test. W during read operation
E is Low and the circuit WST keeps WI and WI at the same potential. When the write operation is started, WE is High
become. The signals input to GR are all High during the read operation, so WER is Low and one WEL
Becomes High. Therefore, the write control signal WR is Hi
gh, N-channel MISFET T77,
T78 and P-channel MISFET T75, T76
Data is written from CWI, CWI to WI, WI through.

FIG. 17 shows an embodiment in which the voltage level of the power supply line on the high voltage side of the sense amplifier for detecting and amplifying the signal read from the memory cell to the data line can be arbitrarily set. The write voltage level when writing "1" to the memory cell is the voltage level of the power supply line on the high voltage side of the sense amplifier. Therefore, it suffices that the voltage level of the power supply line on the high voltage side can be arbitrarily set. Here, two types of high-voltage power supply wirings are provided, and one power supply wiring is used as V _DL for normal writing. The other power supply wiring V _DM can be arbitrarily set, for example, from outside the chip. This allows
When the signals MT0 and MT1 are set to Low, the drive signal CSP of the sense amplifier is V _DL , while the signals MT0 and MT1 are set to High.
Then, the drive signal CSP of the sense amplifier can be V _DM . According to this embodiment, only the voltage level of information "1" can be set arbitrarily. Further, the voltage level of the information "1" can be set by changing every other pair. Therefore,
As in the case of testing the coupling noise between the data lines, it is possible to write a marginal voltage at which information is inverted every other pair, which is effective when a margin test is desired. Further, there is also an effect that the test time such as the information retention characteristic of the memory cell can be shortened.

18 and 19 show one embodiment of the word drive circuit according to the present invention. The feature of this embodiment is that QD1 and QD are replaced by a conventional dynamic word driver.
That is, a static type word driver composed of D2, QP and QT was used. Further, as its power supply, a voltage conversion circuit VC that always generates a voltage higher than the data line voltage VL by the amount VT of the switch transistor QS of the memory cell or more.
That is, HG is provided. The operation of this embodiment will be described below.

First, when the X decoder XD is selected by the address signal Ai, its output N1 becomes low level. Then, the electric charge at the node of N2 is extracted through the transistor QT, and N2 also becomes Low level. Then, the transistor QD1 is turned on to raise the word line W to the level of VCH. VCH level is VL + VT
Since it is (QS) or more, the maximum voltage VL is written in the memory cell CS.

Next, in the precharge cycle, first φ
_P becomes Low level, which turns on QP and sets node N2 to VCH. Then, QD1 turns off and Q
Since D2 is turned on, the word line W becomes Low level and the electric charge is held in the memory cell.

As described above, in this embodiment, the gate voltage of the drive transistor operates at the low level, so that the word driver operates stably even if the power supply voltage becomes low.

FIG. 22 shows a concrete example of the word line voltage conversion circuit VCHG of FIG. FIG. 23 shows the internal waveform and input timing at the time of starting the circuit. The feature of this embodiment is that in order to obtain a fast rise and a high output voltage even with a low power supply voltage, the charge pump circuit feeds back to the output voltage precharge transistor (QB in FIG. 22). The operation will be described below.

First, the input pulses φ and φ are respectively Hi.
Consider the case of gh and Low. At this time, the voltage of the node B becomes VL-VT because it is charged from VL through QC. On the other hand, the node A has a value determined by the charges stored in the capacitors CA and CD and the amplitude of φ. In this embodiment,
This voltage is assumed to be VL. Next, when the voltages of φ and φ are exchanged, the node B is boosted by CB and VL-V.
It becomes T + αVL. Here, α is the ratio of the total capacity of CB and node B. At this time, the voltage of the node A becomes a voltage VL−2VT + αVL which is lower than the voltage of B by the VT of QA.

Next, when the voltages φ and φ are exchanged again, the node A is boosted again. If this is VL
If it is higher than δ, the voltage of the node B becomes VL− due to QC.
Since it is precharged to VT, QB is turned on and the voltage of the node B is further raised by δ. Therefore, in the next cycle, the voltage of the node B is further raised and the voltage of the node A is further raised. The voltage of the node A rises by repeating the above process, and finally, the node A reciprocates between VL and 2VDL.

If a rectifying circuit indicated by 2 or a diode-connected MOS transistor QD is connected to this output and a smoothing capacitor CD is further added to the output, a boosted DC voltage VCH is obtained. This output voltage becomes 2VL-VT in the unloaded state.

Here, the circuit connecting QA and CA is divided into two, and the output point of each circuit, that is, QA and CA is connected.
If one of the connection points of and is connected to the rectifier circuit 2 and the other is connected to the gate of the QB, the gate of the QB is separated from the load circuit. The voltage of A can be raised.

A feature of this circuit is that the output voltage is fed back to the precharge circuit as described above, so that the precharge voltage can be increased and a high output voltage can be obtained even with a low power supply voltage. For example, VL = 0.8 (V), V
If T = 0.5 (V), no feedback, that is, QB
Without, the voltage at node B rises only up to 1.1V (2VL-VT when α = 1), resulting in node A at 1.4V (3VL-2VT) and VCH at 0.9V.
(3VL-3VT). If there is QB, 1.6V (2VL) and 1.6V (2V)
L) and 1.1 V (2VL-VT), which are both higher than the former.

FIG. 28 shows the results of computer simulation comparing the boosting rates with and without the feedback transistor QB (invention) and the conventional method. Here, the solid line indicates that the threshold voltage of the transistor is standard, and the broken line indicates that it is low. From this figure,
In the conventional method, the power supply voltage drops sharply at 1 to 1.5 V, whereas in the present invention, it is constant up to 0.8 V, and it can be seen that stable operation is possible even at a low power supply voltage. Here, it is assumed that the rectifier circuit has no voltage effect due to the threshold voltage of the transistor.

The embodiment shown in FIGS. 24 and 25 is a circuit for obtaining a higher output voltage. The feature of this embodiment is that its gate voltage is synchronized with the output voltage of the charge pump circuit in order to reduce the voltage drop in the rectifying transistor, and when the output is at the high level (2VL), it is higher than that by VT and low. V at the level (VL)
That is L.

In FIG. 24, CP and QD are the above-mentioned charge pump circuit and rectifying circuit. Also, Q1 to Q19,
C1 to C4 are added elements, Q1 is a rectifying transistor, Q3 to Q10, C1 to C3 are circuits for controlling the gate voltage of Q1, Q11 to Q13, Q15 to Q18, and C4 are charging circuits for the gate boosting capacitor C3. , Q19 is VC
This is a precharge transistor for speeding up the rise of H. Also, PA and PA are P of the charge pump circuit.
B and PB- are control signals of the gate voltage control circuit. The operation will be described below.

1 is the charge pump described above, PA,
By alternately setting PA to High and Low, the voltage of the node A is boosted and reciprocates between VL and βVL (β≈2). At this time, PA and PA are set so that High periods do not overlap with each other as shown in FIG. This is because φ ￣ corresponding to PA ￣ in Fig. 22 is 0.
The voltage of the node B is still VL + VT without falling to V
If φ corresponding to PA rises and the voltage of the node A rises in the above condition, QA is in the ON state, and the electric charge stored in CA is leaked to the power supply side through QA.

Next, in the rectifier circuit, PA and PB are Lo
When w, PA and PB are high, the gate of Q4 is C
Since the voltage is boosted to VL + VT or higher by 1, the voltage of the gate G of Q1 is equal to VL. At this time, since node A is VL, there is no backflow from VCH to node A.
The gate of Q11 is PA13 after precharging C4 to VCH (2VL) -VT by Q13 and Q18.
Since the voltage is boosted by (VL), it becomes 3VL-VT. Therefore, if VL ≧ 2VT, the voltage is boosted to VCH (2VL) + VT or higher, and the node C becomes VCH. At this time, since the gate-source voltage of Q10 is VCH-VL and exceeds VT, it is turned on and the gate voltage of Q9 becomes equal to the node C. Therefore, Q9 is turned off and no current flows from the node C to the node G.

Next, PA and PB are High, PA and P, respectively.
When B is low, node A has 2VL and node C has V
It becomes L + VCH. On the other hand, the gate of Q7 is V due to C3.
Since the voltage is boosted to L + VT or higher, its source becomes VL. That is, the gate of Q9 becomes VL, the voltage between the gate and the source becomes VCH, Q9 turns on, and the gate of Q1 becomes VL + γVCH (γ≈1). Therefore, FIG.
As in the second embodiment, 2VL is output as it is without dropping by VT.

In this embodiment, PB is set to the Low level before PA, but when the gate voltage of Q1 is still VL + VT or higher, PA becomes Low.
This is to prevent the voltage of the node A from becoming VL and the electric charges from flowing back from the output to the node A. Also, Q4, Q7
The minimum potential of the gate control circuit is set to VL as in the case of the source in order to reduce the potential difference between the electrodes of the transistor. As a result, the potential difference between the electrodes becomes 2 VL or less, and the same fine transistor as in the other portions can be used.

The above is the feature of the embodiment shown in FIG. 24. In the same figure, the same effect can be obtained by deleting Q7 and Q10 and connecting the gate of Q9 to the gate of Q4.
For example, when PB is VL and PB is 0, node C is V
Since the gates of CH + VL, Q4, and Q9 are VL, Q
4 turns off, Q9 turns on, and the node G becomes VCH + VL. On the other hand, when PB is 0 and PB is VL, node C
Is VCH (2VL), and the gates of Q4 and Q9 are 2VL, so Q4 is on, Q9 is off, and the node G is VL.

26 and 27 show a circuit for generating the timing shown in FIG. Inverter I in FIG.
5 to I8, a resistor R2, a capacitor C2, a NAND gate NA2, and a NOR gate NO1 are circuits for preventing duplication of PA and PA. Circuit, I9-I1
3, NA3 is a circuit that creates a delay when PA and PB fall. Further, I14 to I25 are inverters for buffers. This may be any number of steps as long as the odd number of steps is the same, and may be adjusted according to the magnitude of the load. FIG. 27 is an example of a circuit for generating the input pulse OSC of the circuit. This circuit is generally called a ring oscillator. The feature of this circuit is that the time constants of R and C are made sufficiently larger than the delay time of the inverter in order to suppress the fluctuation of the oscillation frequency due to the power supply voltage. Therefore, the oscillation frequency is stable even if the ratio of the VT of the transistor to the power supply voltage is 1 to 3 or less and the delay time of the inverter greatly depends on the power supply voltage.

In addition to the above countermeasures, lowering the VT of the transistors of the embodiments of FIGS. 22 and 24 stabilizes the operation at a lower voltage. This is because the driving capability of the transistor is increased by lowering the VT. Low VT
Although the subthreshold current also increases due to the increase in the number of elements, the number of elements in the voltage conversion circuit is at most several tens, so that it can be almost ignored when viewed from the entire chip. On the other hand, the driving capability of the word driver and the memory cell is also increased by lowering the VT, but the former uses 10 ³ to 10 ⁴ in the M-bit class DRAM, so that the leakage current flowing in the off state of the transistor cannot be ignored. Further, in the latter case, there is a problem that the charge holding time becomes short and the refresh interval must be shortened. This leads to the largest increase in power consumption. Therefore, it is best to set VT low in the voltage conversion circuit, standard in the word driver and higher than the standard in the memory cell.

As described above, according to this embodiment, the gate voltage of the rectifying transistor can be made higher than the drain voltage by the threshold voltage VT or more, and the backflow of charges can be prevented, so that the output voltage of the rectifying transistor is doubled. It can be increased to 2 VL which is the theoretical value of the circuit. Further, by using the oscillation circuit and the timing generation circuit using the RC delay, the delay time between the oscillation frequency and the timing becomes stable against the fluctuation of the power supply voltage, so that the voltage conversion efficiency can always be kept in the optimum state. Further, by providing three kinds of transistor VTs, the voltage conversion circuit is low, the word driver is standard, and the memory cells are higher than standard, stabilization at low voltage, high speed, and low power consumption can be achieved. Therefore, it is possible to realize a semiconductor integrated circuit that operates stably even with an electromotive force of one battery as the power supply voltage.

Next, an embodiment in which the present invention is applied to an intermediate voltage generating circuit will be described. Although VCC is used as a symbol representing the higher power supply voltage in the following description of the embodiments, it does not have to be different from VL used so far.
You can replace it with VL as it is. Also, although HVC is used as a symbol representing the intermediate voltage,
It does not have to be different from the HVL used so far, and it can be replaced with the HVL as it is. FIG. 29 is a configuration example of the voltage follower circuit according to the present invention. This circuit outputs a voltage that is approximately equal to the voltage applied to its input,
It is designed to drive a large load capacity. In FIG. 1A, 1 is a first complementary push-pull circuit, which is composed of an N-channel MOS transistor TN2 and a P-channel MOS transistor TP2, and bias voltage sources VN1 and VP1. Reference numeral 2 denotes a current mirror type push-pull amplifier circuit, which is a pair of N-channel MOS transistors TN1 and T forming a current mirror circuit.
N3, P channel MOS transistor pair TP1 and TP
3 and. 3 is the second complementary
It is a push-pull circuit and is composed of an N-channel MOS transistor TN4, a P-channel MOS transistor TP4, and bias power supplies VN2 and VP2.

The constant setting of various transistors and voltage sources of this circuit and the operation in the steady state will be described. Voltage source VN
1 and VP1 have values of transistors TN2 and TP, respectively.
It is chosen to be approximately equal to the gate threshold voltage of 2. This prevents both transistors TN2 and TP2 from being cut off at the same time under any operating condition. Therefore, it is possible to prevent the output impedance from becoming high and the potential not being determined, or the output voltage from fluctuating depending on load conditions. By making the value of the voltage source approximately equal to the gate threshold voltage of the transistor, the current that flows through the two transistors in the steady state is suppressed to a low value, and the standby circuit power of the integrated circuit is reduced while it is high. It is designed to obtain load driving capability. The operation under such a bias condition is generally called class AB operation. Now, assuming that the current values flowing through TN2 and TP2 are IC1 and ID1, respectively, these currents are TP3 by the current mirror circuit composed of the P channel MOS transistor pair TP1 and TP3 and the N channel MOS transistor pair TN1 and TN3, respectively. Is converted into a current ID2 flowing through the current IC2 and a current ID2 flowing through TN3. The current ratio of IC1 and IC2 is the β ratio of the transistors TP1 and TP3, and the current ratio of ID1 and ID2 (mirror ratio) is the β ratio of the transistors TN1 and TN3.
The ratios are approximately equal to each other. That is, M _p = IC2 / IC1 = β _TP3 / β _{TP1 MN} = ID2 / ID1 = β _TN3 / β _TN1 . By setting this ratio to a value of 1 or more, the current can be amplified and the drive capability of the load (terminals 6, 7) in the next stage can be increased. In the present invention, this ratio is selected to be a value of about 1-10. The values of the voltage sources VN2 and VP2 are made substantially equal to the gate threshold voltages of the transistors TN4 and TP4, as in the first push-pull circuit. As a result, the second push-pull circuit also performs class AB operation.

Now, what happens when the first push-pull circuit deviates from the steady state, that is, the state where IC1 = ID1 is satisfied will be described. The current value when the output voltage is forcibly changed by the voltage δV from the steady state is expressed as follows.

IC1-ID1 =-(√ (2β _N I) + √
(2β _P I)) × δV + (βN−βP) / 2 × δV ² where β _N and β _P are transistors TN2 and TP, respectively.
The β of 2 and I represent the current (that is, I = IC1 = ID1) flowing in the first push-pull circuit in the steady state.

For the sake of simplicity, the characteristics of TN2 and TP2 are almost the same, and β _N and β _P are equal (β = β _N =
Assuming β _P ), the above equation becomes IC1-ID1≈−2√ (2βI) × δV. If the mirror ratios of the two current mirror circuits are equal (M = M _N = M _P ), IC2-ID2≈−2 × M × √ (2βI) × δV.

For example, M = 5, β = 1 mA / V ² , I =
Assuming 0.2 μA, when the output voltage drops by 0.1 V (δV = −0.1 V), IC2-ID2 = 20 μA
Becomes

That is, even when the output voltage changes slightly by 0.1 V, the steady current of IC2 and ID2 is 1 μA (0.2
A sufficiently large drive current of 20 μA is obtained for μA × 5). Therefore, the terminal 6 can be driven to the minimum VSS and the terminal 7 can be driven to the maximum VCC to the limit of the power supply voltage range even with a slight change in the output voltage. The driving direction is that when the output voltage drops, the terminal 7
When CC and the output voltage rise, the terminal 6 is driven to VSS. As a result, when there is an error in the output voltage, the second push-pull circuit is driven by the signal in which the error is amplified, and operation is performed to eliminate the error in the output voltage. Therefore, as compared with the case of simply driving with the source follower circuit as in the conventional example, it is possible to provide a remarkably high driving ability. Even if the bias current in the steady state is suppressed to a sufficiently low value, a high drive current can be obtained by amplifying the error. In addition, this circuit operates symmetrically with respect to the direction of error,
The same drive capability can be obtained for output charging and discharging.

Next, the accuracy of this circuit as a voltage follower will be described. In this circuit, an error in the output voltage is detected by the first push-pull circuit, and a signal obtained by amplifying the error is used to drive the second push-pull circuit. Therefore, the output voltage accuracy (input / output voltage difference) is determined by the voltage accuracy (input / output voltage difference) of the first push-pull circuit. In the first push-pull circuit, the steady state or IC
When the condition for 1 = ID1 is obtained, the input voltage V (I
The relationship between N) and the output voltage V (OUT) is obtained, and is given by the following equation.

V (OUT) -V (IN) = β × (VN1
-VTN)-(VP1-VTP) / (β _R +1) where β _R = √ (β _TN2 / β _TP2 ), and VTN and VTP are the gate threshold voltage of the N-channel and P-channel MOS transistors, respectively. Is the absolute value of. As is clear from this equation, by making VN1 and VP1 have characteristics that change following changes in VTN and VTP, respectively, and selecting β of the transistor appropriately, due to variations in the manufacturing process, etc. Even if the element characteristics of the channel transistor change independently, the voltage difference between the output and the input can be made zero. As described in the next embodiment, the voltage source as described above can be easily constructed by connecting the gate and drain of each channel conductivity type MOS transistor and passing a predetermined current through it. In general, even if there are variations in characteristics between elements of different conductivity types, transistors of the same conductivity type go through the same manufacturing process, so the characteristic difference between elements can be suppressed to a sufficiently small value. In particular, with respect to variations in the processed shape, by designing the gate width and the gate length with values sufficiently larger than the processing accuracy, it is possible to further reduce the characteristic difference between the element pairs. For example, taking the gate threshold voltage as an example,
The difference between a pair of elements of the same conductivity type is easily 20 to 30 mV
Although it is possible to reduce the difference to less than or equal to the level, the difference in the difference between the elements of different conductivity types is about 200 mV at the maximum, which is a large value of about an order of magnitude. As described above, the voltage accuracy (input / output voltage difference) of the first push-pull circuit is determined by the threshold voltage difference of the transistor pair.
The value can be suppressed to about 30 mV, which is lower than that of the conventional method by an order of magnitude.

Now, the transient operation will be described with reference to FIG. Now, consider a case where the input voltage V (IN) drops from time t0 to t1 and rises from time t4 to t5. Since the output does not immediately follow immediately after the input voltage drops, the transistor TN2 is in the cutoff state from time t1 to t2, and the value of the current IC1 becomes almost zero. On the other hand, ID1 increases, and the voltage V (6) at the terminal 6 is dropped to almost VSS (0V). As a result, the driving capability of the transistor TP4 is increased, and the output OUT is discharged at high speed. When the difference between the output voltage and the input voltage decreases after the time t2, the transistor TN2 starts to conduct, and finally the voltage difference between the input and the output disappears at the time t.
At 2, IC1 = ID1, and a steady state is achieved. When the input voltage rises, the voltage of the terminal 7 rises to VCC symmetrically, and the output is charged at high speed.

As described above, according to the present invention, even if there are variations in the manufacturing process, the error between the input and output voltages is small, and during a transition, a large capacity load can be charged and discharged at high speed. A voltage follower capable of providing can be provided. Besides being applied as a voltage follower, this circuit can also be used as a high performance current detection circuit by inputting a signal current to the output terminal OUT and taking out an output from the terminals 6 or 7.

An embodiment in which the above-described circuit is applied to the intermediate voltage (VCC / 2) generation circuit of the dynamic memory will be described below with reference to FIGS. 31 and 32. FIG. 31 is a configuration example of an intermediate voltage generating circuit according to the present invention. In the figure,
Reference numeral 30 is a reference voltage generating circuit, 31 is a first complementary push-pull circuit, 32 is a current mirror type amplifier circuit, and 33 is a second complementary push-pull circuit. The reference voltage generating circuit generates an intermediate voltage at the terminal 34 by dividing the power supply voltage in half by two resistors R3 and R4 having the same resistance value. By using the same kind of element for the resistors R3 and R4, it is possible to obtain a fairly accurate value for the intermediate voltage. In addition,
The element for obtaining the intermediate voltage is not limited to the resistor, and for example, MO
It is obvious that a similar circuit can be constructed by using S transistors and the like. The first push-pull circuit is basically the same as the push-pull circuit 1 shown in FIG. Here, instead of the voltage source VN1, resistors R5 and N
The channel MOS transistor TN10 is connected to the voltage source VP1.
Instead of, a resistor R6 and a P-channel MOS transistor TP10 are used respectively. By doing so, as described in the previous embodiment, the voltage of the terminal 35 is always automatically set to a value higher than that of the input terminal 34 by the gate threshold voltage of the N-channel MOS transistor. You can Note that the resistance value is selected so that the current flowing through R5 and R6 is a small value, which is a fraction of the current flowing through R3 and R4 to about one tenth. This is because even if the characteristics of the N-channel transistor and the P-channel transistor vary independently and the current value flowing (or flowing out) from the push-pull circuit to the reference voltage generating circuit fluctuates, the voltage at the terminal 34 is affected. This is to prevent fluctuation. The current mirror type amplifier circuit 32 has exactly the same configuration as the current mirror type amplifier circuit 2 shown in FIG. The second push-pull circuit is basically the same as the push-pull circuit 3 shown in FIG. Here, instead of the voltage source VN2, an N channel M
The OS transistor TN14 uses a P-channel MOS transistor TP14 instead of the voltage source VP2. By doing so, as in the case of the first push-pull circuit, the value of the bias current flowing through the push-pull circuit does not fluctuate with respect to the change in the threshold voltage of the transistor. With the circuit configuration as described above, a highly accurate intermediate voltage can be obtained for the output HVC, and the load capacitance CL can be charged and discharged at high speed.

32A and 32B show the results obtained by computer analysis of the performance comparison between the present circuit system shown in FIG. 31 and the conventional circuit system shown in FIG. Figure 32
In (a), the horizontal axis represents the difference between the absolute values of the gate threshold voltages of the N-channel transistor and the P-channel transistor, and the vertical axis represents the value of the intermediate voltage. From this result, in the conventional circuit, when the threshold voltage difference fluctuates by ± 0.2 V, the output voltage fluctuates by approximately ± 100 mV (approximately ± 13% with respect to 0.75 V). In the circuit of, the output voltage fluctuation is about ± 8mV (about ± 1 against 0.75V).
%), Which can be reduced by one digit or more compared to the conventional case.
FIG. 32B is a plot of the rise time of the output voltage after the power is turned on with respect to the power supply voltage. The rise time is defined as the time when the output voltage reaches 90% of the steady value. In addition, the value of the load capacity is 64 Mbit DRA.
The total capacitance of the M bit line precharge power supply and the plate electrode is assumed. As can be seen from this analysis result, according to the circuit of the present invention, it is possible to start up the load in a time shorter than that of the conventional circuit by about one digit.

FIG. 33 (a) is a circuit diagram showing another embodiment of the present invention. In the figure, 40 is a complementary push-pull type voltage follower circuit, and 41 is a tri-state buffer. The voltage follower circuit is
It is basically the same as the push-pull circuit 1 of FIG. Here, the tri-state buffer operates so as to supplement the driving capability of the push-pull circuit. The tri-state buffer includes a P-channel transistor TP21 and an N-channel transistor TN21 for driving a load, two differential amplifier circuits (comparators) AMP1 and AMP2 for driving these transistors, and two voltages for setting an offset amount. Source VOSL and VOSH. The operation of this circuit depends on which of the following three voltage conditions is met:

(1) V (OUT)> V (IN) + VOSH (2) V (IN) + VOSH> V (OUT)> V (IN)-
Under the voltage condition of VOSL (3) V (IN) -VOSL> V (OUT) (1), the voltage of the output OUT becomes higher than the voltage of the terminal 43 and the voltage of the terminal 45 becomes a high voltage level (VCC). . Further, the voltage of the terminal 44 also becomes a high voltage level (VCC). Therefore, the N-channel transistor TN21 becomes conductive, and the P-channel transistor T
P21 is cut off and the load is discharged. Under the voltage condition of (2), the output OUT is higher than the voltage of the terminal 43.
Becomes low and the voltage at the terminal 45 becomes low (V
SS). Also, the voltage at terminal 44 remains at a high voltage level (VCC). Therefore, the two transistors T
Both N21 and TP21 are cut off, and the output is in a high impedance state. Under the voltage condition (3), the voltage of the output OUT becomes lower than the voltage of the terminal 42, and the voltage of the terminal 44 becomes a low voltage level (VSS). Further, the voltage of the terminal 45 maintains a low voltage level (VSS). Therefore, the N-channel transistor TN21 is cut off and the P-channel transistor TP21 becomes conductive to charge the load. In this way, there are three states in which the output voltage is discharged when it exceeds a certain fixed range centered on the input voltage, discharged, charged when it exceeds a certain fixed range, and neither charged nor discharged if it is within the fixed range ( A drive circuit having a tri-state) can be realized. The transient operation of this circuit is shown in FIG. Now, input voltage V (I
Consider the case where N) drops at time t0 and rises at time t2. At the time of falling, the voltage of the terminal 45 becomes VCC, the transistor TN21 becomes conductive, and the load is discharged from time t0 to time t1 when the output voltage becomes equal to “(steady-state voltage) + VOSH”. Further, at the rising time, the voltage of the terminal 44 becomes VSS until the time t3 when the output voltage becomes equal to “(voltage in steady state) −VOSL” from the time t2, and the transistor TP2
1 is conducted and the load is charged.

As described above, by combining the push-pull circuit with the tri-state buffer, when the voltage error between the input and the output becomes large to a certain extent or more, the transistor with high driving capability is made conductive, so that the response at the time of transient is generated. The speed can be increased. The two voltage sources VOSL and VOSH for setting the offset amount can be set to have as small values as possible to speed up the convergence to the set voltage, but in order to avoid malfunction, the differential amplifier circuit (comparator) AMP1 is used. And a value sufficiently larger than the input offset voltage of AMP2. When the circuit is composed of MOS transistors, this value is preferably 50 mV or more. The circuit configuration of the tri-state buffer is not limited to the example shown here, and any other system may be used as long as it realizes the same function.

An embodiment in which a voltage follower using a tri-state buffer is applied to an intermediate voltage (VCC / 2) generation circuit of a dynamic memory will be described with reference to FIGS. 34 and 35. FIG. 34 is a configuration example of an intermediate voltage generating circuit according to the present invention. In FIG. 34, 50 is a reference voltage generating circuit, 51 is the voltage follower circuit described in FIG.
Is a tri-state buffer. This adds a tri-state buffer to the intermediate voltage generating circuit shown in FIG. 31 to enhance the restoring capability when the voltage error between the input and the output becomes large. The structure and operation of the tri-state buffer will be described below. The feature of this embodiment is that the first push-pull circuit is used as it is,
The point is that the error voltage is detected by utilizing the difference in the mirror ratio of the current mirror circuit and the tri-state buffer is activated.
In FIG. 34, TP36 and TP37 are P channel MOs.
S-transistors, TN36 and TN37 are N-channel MO
S transistors INV1 and INV2 are inverters, TP
Reference numeral 38 denotes a P-channel MOS transistor designed to drive a load with the output of the inverter INV1, and TN38 denotes an N-channel MOS transistor designed to drive a load with the output of the inverter INV2. T
P32 and TP36 and TP32 and TN37 respectively constitute a current mirror circuit. Now, let the current flowing through the transistor TN31 be IC1, the transistor TP31.
Is a current flowing through the transistor TN36, a current flowing through the transistor TN36 is ID2, and a current flowing through the transistor TP36 is I.
Put C2, respectively. Output voltage error δV and IC1,
As described above, the relationship of ID1 can be approximated as IC1-ID1≈−2√ (2βI) × δV. When the mirror ratio of the current mirror circuit is M _P1 = IC2 / IC1 = β _TP36 / β _TP32 M _N1 = ID2 / ID1 = β _TN36 / β _TP32 , the following formula is obtained. IC2 / M _P1 −ID2 / M _N1 ≈−2√ (2βI) × δV When the offset voltage Vos is applied to the output, IC
If 2 = ID2 and the current value at that time is I ₂ , then the offset voltage Vos is Vos≈I ₂ / (2 × α) × (M _P1 −M _N1 ) / (M _N1 ×
M _P1 ). Here, α = √ (2βI ₁ ) Further, β is β of the transistor forming the first push-pull circuit, and I ₁ is a current flowing through the first push-pull circuit in the steady state. For example, I ₁ = 0.2 μA, I ₂
When = 1 μA, β = 1 mA / V ² , M _N1 = 1 and M _P1 = 0.2, the offset voltage Vos becomes −100 mV.
That is, when the output voltage decreases from the steady value by 100 mV or more, the input voltage of the inverter INV1 transits from the low level to the high level, and the output voltage transits from the high level to the low level to make the driving P-channel MOS transistor TP38 conductive. Charge the load. Similarly, the transistor T
By properly selecting the constants of P37 and TN37, when there is a predetermined plus side offset, N channel M
The OS transistor TN38 can be made conductive to discharge the load.

As described above, by adopting the circuit configuration shown in this embodiment, it is possible to realize the same function as that shown in FIG. Further, in this circuit system, since the offset amount is determined by the mirror ratio of the current mirror circuit, the offset amount can be set with high accuracy if consideration is given to reducing the characteristic difference between the transistor pairs. Furthermore, since it is not necessary to separately provide a high-precision differential amplifier circuit, it is possible to realize high performance with low power consumption and a simple configuration.

FIG. 35 shows a result obtained by computer analysis of performance comparison between the present circuit system and the conventional circuit system shown in FIG. FIG. 35 is a plot of the rise time of the output voltage after the power is turned on with respect to the power supply voltage. The rise time is
It is defined as the time when the output voltage reaches 90% of the steady value. Further, the value of the load capacitance is assumed to be the total capacitance of the bit line precharge power supply and the plate electrode of the 64-Mbit DRAM. As can be seen from this analysis result, according to the circuit of the present invention, the rise time can be further shortened by about a half digit as compared with the embodiment shown in FIG.
The load can be started up in about one and a half times shorter than the conventional circuit. As explained above, by combining the push-pull circuit with the tri-state buffer,
It becomes possible to provide a voltage follower circuit that can follow an input at a higher speed. Since the setting accuracy of the voltage is determined by the push-pull circuit, the voltage error between the availability can be made extremely small, as in the case of the previous embodiment.

In the above embodiments, the circuit configuration for driving a large capacity load in an integrated circuit (LSI) at high speed has been described. However, if you try to drive even faster,
Transient current during charging and discharging becomes a big problem. For example, the load capacitance of the intermediate voltage generation circuit of a DRAM of about 64 Mbits is about 115 nF, but the current value when it is driven with an amplitude of 1 V for 5 μs reaches 23 mA. This is comparable to the current consumption value of the DARM, and driving at a higher speed causes an influence on the main circuit characteristics, for example, noise generation of the power supply line and deterioration of reliability of the drive signal wiring. Not desirable because it is dangerous.
In general, ultra-highly integrated LSI, especially LS in memory
In many cases, the entire I is composed of a plurality of blocks of the same type, and only a part of these blocks is activated during operation. In such an LSI,
It is effective to apply the embodiments described below.

36 and 37 show an embodiment in which the present invention is applied to an intermediate voltage supply system of a dynamic memory (DRAM). In FIG. 36, MB0 and MB1
MBi is i + 1 memory blocks, 60 to 62 are word line selection circuits, 68 to 70 are intermediate voltage lead lines from each memory block, 76 and 77 are two sets of intermediate voltage generation circuits, and 74 and 75 are two. Signal lines for supplying the intermediate voltages HVC1 and HVC2 from the set of intermediate voltage generating circuits to the memory blocks, and 71 to 73 are provided for each block so as to supply one of the two signal lines to the memory block. It is a switch. Further, the memory block MB0 is a memory cell array MA0 in which memory cells are two-dimensionally arranged, an input / output control for amplifying a signal read from the memory cell and outputting the amplified signal to the outside or writing an external signal to the memory cell. The circuit block MC0 and the input / output circuit 67 are included. DL0, DL0-, DLj- are data lines for transmitting a signal to the memory cell, 63 is a plate electrode forming a counter electrode of the storage capacitor, and 64 is a precharge voltage arranged to set the data line to an intermediate voltage when not selected. Supply lines, PC is a precharge signal line, SA0 to SAj are sense amplifiers for detecting and amplifying signals read from the memory cells, and 65 and 66 are common input / output for performing signal transmission between the input / output circuit 67 and each data line. The line pairs IO0 to IOj are IO gates that control the connection between the data line pair selected by the address designation signal and the common input / output line pair.

Now, let us consider a case where only one block MB0 is selected from the i + 1 memory blocks and is brought into an operating state. At this time, one word line in MA0 is selected by the word line selection circuit 60 and transits to the high level. At the same time, the switch 71 is controlled and the intermediate voltage lead-out line 68 is connected to the signal line 75 for supplying the intermediate voltage. On the other hand, the memory blocks MB1 to MB1 in the non-selected state
Lead lines 69 and 70 from MBi are connected to a signal line 74 for supplying an intermediate voltage. In this way, the load of i memory blocks is connected to the intermediate voltage generating circuit 76, whereas only the load of one memory block is connected to the intermediate voltage generating circuit 77. For example, i = 1
Assuming 5, the load capacity driven by the intermediate voltage generation circuit 77 is 1/15 of the load capacity driven by the intermediate voltage generation circuit 76. Therefore, even if the same circuit is used for 76 and 77, the intermediate voltage of the selected block MB0 operates 15 times faster than the intermediate voltage of the non-selected block. From the viewpoint of circuit performance, the response speed of the non-selected memory block is irrelevant to the memory performance, so that the performance of the entire memory can be improved with almost no increase in transient current. FIG. 37 shows the time change of the intermediate voltage when the power supply voltage changes during the memory operation. That is, the voltage V is between time t0 and time t2.
It is assumed that CC has decreased. Further, between the time t0 and t1 and after the time t3, the memory block MB0 is
It is assumed that the memory block MB1 is selected from 1 to t3. Between the times t0 and t1, the block MB1 is not selected, so that the intermediate voltage V (69) responds slowly, while the block MB0 is selected, the intermediate voltage V (68) is Follows at high speed. Time t
When the block MB1 is switched to the selected state and the block MB0 is switched to the non-selected state in 1, V (69) changes promptly toward the voltage to be set. As described above, according to the present embodiment, it becomes possible to drive a large-capacity load such as the intermediate voltage of the dynamic memory at substantially high speed with almost no increase in the transient current. In addition, although the example in which the present invention is applied to the intermediate voltage of the dynamic memory has been described in this example, the applicable range is not limited to this, and it is configured by blocks of the same kind, and a part of them is activated during operation. The present invention can be applied to integrated circuits in general.

Although the present invention has been described in detail with reference to the embodiments, the scope of application of the present invention is not limited to these. For example, although the case where the LSI is composed of the CMOS transistors has been mainly described here, the LSI using the bipolar transistor and the L using the junction FET are described.
SI, a BiCMOS type LSI in which a CMOS transistor and a bipolar transistor are combined, and further, a material other than silicon, for example, an LSI in which elements are formed on a substrate such as arsenic of gallium can be applied as it is.

In the present embodiment, the current mirror circuit is used as the current amplifier circuit, but other current amplifier circuits can be used.

[0140]

As described above, according to the present invention, the input / output control circuits for connecting the data lines and the I / O lines are alternately arranged on the left and right sides of the memory cell array, and the data lines and the I / O lines are arranged. By adopting a circuit configuration in which the transfer impedance between and is changed between the reading operation and the writing operation, it is possible to operate stably at high speed even at low voltage.

The present invention is also suitable for parallel testing, and can significantly reduce the test time.

Further, according to the present invention, the drive transistor of the word line operates at the low level of its gate voltage, and therefore operates stably as a word driver even if the power supply voltage drops. In addition, the voltage conversion circuit that constantly operates to act as the power supply for the word driver by boosting the data line voltage VL to a voltage VCH higher than the data line voltage VL by the threshold voltage VT of the switch transistor of the memory cell is rectified. Since the gate voltage of the use transistor can be made higher than the drain voltage by a threshold voltage or more and the backflow of charges can be prevented, the output voltage can be increased to 2VL which is the theoretical value of the voltage doubler generation circuit. Further, by using the oscillation circuit and the timing generation circuit using the RC delay, the delay time between the oscillation frequency and the timing becomes stable against the fluctuation of the power supply voltage, so that the voltage conversion efficiency can always be kept in the optimum state. Further, by selecting three types of threshold voltage of the transistor, it is possible to stabilize at a low voltage, speed up, and reduce power consumption. And by these, the power supply voltage
It is possible to realize a semiconductor integrated circuit that operates stably even with an electromotive force for each piece.

Furthermore, according to the present invention, in an ultra-highly integrated LSI, a large load capacitance can be operated at a high speed without a circuit configuration for driving a large load capacitance at high speed with high voltage accuracy or without causing a large transient current to flow. A driving circuit system can be provided. For example, in the conventional circuit, when the threshold voltage difference between the transistors is 0.2 V, the output voltage fluctuates by about 13% with respect to 0.75 V. According to the present invention, it is suppressed to about 1%. Thus, the voltage accuracy is improved by one digit or more, and the high-speed response is obtained so that the rise time of the output voltage after the power is turned on is improved by about one digit or more as compared with the conventional circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a first embodiment of the present invention.

FIG. 4 is a diagram showing a first embodiment of the present invention.

FIG. 5 is a diagram showing a first embodiment of the present invention.

FIG. 6 is a diagram showing a first embodiment of the present invention.

FIG. 7 is a diagram showing the effect of the present invention.

FIG. 8 is a diagram showing the effect of the present invention.

FIG. 9 is a diagram showing an embodiment in which the effect obtained by using FIGS. 1 to 6 is further enhanced.

FIG. 10 is a diagram showing an embodiment when a plurality of memory cell arrays are present.

FIG. 11 is a diagram showing an example of a parallel test.

FIG. 12 is a diagram showing an example of a parallel test.

FIG. 13 is a diagram showing an example of a parallel test.

FIG. 14 is a diagram showing an example of a parallel test.

FIG. 15 is a diagram showing an example of a parallel test.

FIG. 16 is a diagram showing an example of a parallel test.

FIG. 17 is a diagram showing an example for writing an arbitrary write voltage to a memory cell.

FIG. 18 is an example of the present invention.

FIG. 19 is a timing chart.

FIG. 20 is a conventional example and its timing chart.

FIG. 21 is a conventional example and its timing chart.

FIG. 22 is an example of the present invention.

FIG. 23 is a timing chart.

FIG. 24 is an example of the present invention.

FIG. 25 is a timing chart.

FIG. 26 is an example of the present invention.

FIG. 27 is an example of the present invention.

FIG. 28 is a diagram showing the effect of the embodiment of FIG. 22.

FIG. 29 (a) is an example for explaining the basic concept of the present invention. (B) is a figure explaining operation at the time of the transition.

FIG. 30 is a conventional example of an intermediate voltage generating circuit for DRAM.

FIG. 31 is a specific example in which the present invention is applied to an intermediate voltage generation circuit of a DRAM.

FIG. 32 is a view for explaining the effect of the present invention.

FIG. 33 (a) is an embodiment for explaining another basic concept of the present invention. (B) is a figure explaining the operation.

FIG. 34 is a specific example applied to an intermediate voltage generation circuit of a DRAM.

FIG. 35 is a view for explaining the effect.

FIG. 36 is a diagram for explaining a specific example in which another basic concept of the present invention is applied to an intermediate voltage driving system of DRAM.

FIG. 37 is a diagram for explaining intermediate voltage changes in the embodiment of FIG. 37A when the power supply voltage fluctuates during the memory operation.

[Explanation of symbols]

MA ... Memory cell array, CKT ... Input / output control circuit, R
G0, RG1 ... Read gate, WG0, WG1 ... Write gate, SA0, SA1 ... Sense amplifier, SWR
0, SWR1 ... Read switch, SWW0, SWW1
… Write switch, RO, RO￣… Read line, W
I, WI -... write I / O line, dy ... data line pitch, WD ... word driver, XD ... X decoder, VLG
... Memory array voltage conversion circuit, VCHG ... Word line voltage conversion circuit, W ... Word line, φP ... Precharge signal, FX ... Word line drive pulse generation circuit, φX ... Word line drive pulse, CP ... Charge pump Circuit, RECT ...
Rectifier circuit, VL ... Data line voltage or internal (for array) power supply voltage, VCH ... Word line voltage conversion circuit output voltage, φ, φ-PA, PA-PA, PB, PB -... Word-line voltage conversion circuit Boost pulse, OSC ... Ring oscillator output pulse, C, C1, C2, C3, C4, CA, C
B, CD ... Capacitor, R, R1, R2 ... Resistor, QD
1, QP, Q9, Q10 ... P-channel MOS transistor, QT, QD2, QS, QD, QA, QB, QC, Q
P, Q1, Q8, Q11, Q19 ... N-channel MOS transistors, I1, I25, I30, I33 ... Inverter, NA1, NA2 ... NAND circuit, NO1 ... NOR circuit, VEXT ... External power supply voltage 1, 31, 40 ... One complementary push-pull circuit, 2, 32 ... Current mirror type push-pull amplifier circuit, 3, 33 ... Second complementary push-pull circuit, 30, 50 ... Reference voltage generating circuit, 41, 52 ... Tri-state buffer , AMP1, AMP2 ... Differential amplifier circuits, MB0 to M
Bi ... Memory block, 60-62 ... Word line selection circuit, 71-73 ... Switch, 76, 77 ... Intermediate voltage generation circuit (driving circuit), MA0 ... Memory cell array, MC0
... Signal amplification and input / output control circuit group, SA0 to SAj ...
Sense amplifier circuits (sense amplifiers), IO0 to IOj ... I / O gates, 67 ... I / O circuits.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kiyoo Ito             1-280, Higashikoigokubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hitoshi Tanaka             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Yasushi Watanabe             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Eiji Kume             1-280, Higashikoigokubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masanori Isoda             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Eiji Yamazaki             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F-term (reference) 5F083 AD00 GA05 LA05                 5M024 AA02 BB08 BB29 CC25 FF03                       GG05 HH09 HH11 PP01 PP02                       PP03 PP07 PP10

Claims (14)

[Claims] 1. A memory cell provided at an intersection of a word line and a data line, a word driver connected to the word line for supplying a drive voltage to the selected word line, and the drive voltage generated. And a source / drain path coupled between the first node having a first node and a second node and the second node and the operating voltage. The first MIS with
An FET, a second MISFET having a source / drain path coupled between the second node and the operating voltage and a gate connected to the drain, and a second capacitor having a third node and a fourth node, A third MISFE having a source / drain path coupled between the fourth node and the operating voltage and a gate connected to the drain
T, the gate of the first MISFET is connected to the fourth node, the threshold voltage of the transistor used in the word driver is lower than the threshold voltage of the transistor used in the memory cell, A semiconductor device, wherein a threshold voltage of a transistor used in the voltage conversion circuit is lower than a threshold voltage of a transistor used in the word driver. 2. The first node of the first capacitor is alternately driven to a high level and a low level in a predetermined cycle, and the third node of the second capacitor is the first node. The semiconductor device is driven to a low level during a period in which the signal is at a high level and is driven to a high level during a period for which the first node is at a low level. 3. The charge pump circuit according to claim 1, wherein the charge pump circuit has a source / drain path coupled between the fourth node and the operating voltage, and a gate thereof is coupled to the second node. 4 MISFET
A semiconductor device further comprising: 4. The semiconductor device according to claim 1, wherein the voltage of the second node is output to the output node via a first rectifier circuit. 5. The voltage conversion circuit according to claim 1, wherein the voltage conversion circuit outputs a voltage higher than the first voltage from a second output node, and the charge pump circuit includes the second charge pump circuit. And a second rectifier circuit including a fifth MISFET having a source / drain path coupled between the second node and the output node, the gate of the fifth MISFET being the second charge pump circuit of the second charge pump circuit. A semiconductor device controlled by an output of an output node. 6. The low-level voltage and the high-level voltage are alternately output to the second node in a predetermined cycle, and the second node of the second charge pump circuit is set to the high level. A semiconductor device which outputs a high level voltage from the second output node for a period shorter than a period. 7. The method according to claim 5, wherein each of the first to fifth MISFETs is an N-type MIS.
The second charge pump circuit, which is a FET and transmits a high level voltage of the second node to the output node, has a voltage higher than a high level voltage appearing at the second node at the gate of the fifth MISFET. A semiconductor device comprising: 8. A memory cell provided at an intersection of a word line and a data line, a word driver connected to the word line for supplying a driving voltage to the selected word line, and an operating voltage A semiconductor device comprising: a voltage conversion circuit that outputs a first voltage having a voltage higher than the operating voltage from an output node, wherein the voltage conversion circuit includes a first capacitor having a first node and a second node; A first MISFET having a source / drain path coupled between a second node and the operating voltage; and a source / drain path coupled between the second node and the operating voltage and a drain thereof. 2nd M with a gate
A first charge pump circuit including an ISFET; a rectifier circuit including a third MISFET having a source / drain path connected between the second node and the output node; and a gate of the first MISFET having a voltage higher than the operating voltage. A second charge pump circuit for applying a voltage, and a third charge pump circuit for applying a voltage higher than the first voltage to the gate of the third MISFET, and a transistor used for the word driver. The threshold voltage is lower than the threshold voltage of the transistor used in the memory cell, and the threshold voltage of the transistor used in the voltage conversion circuit is lower than the threshold voltage of the transistor used in the word driver. A semiconductor device characterized by the above. 9. The method according to claim 8, wherein the first node of the first capacitor is alternately driven to a high level and a low level in a predetermined cycle, and the third node of the second capacitor is the one node. The semiconductor device is driven to a low level during a period in which the signal is at a high level and is driven to a high level during a period for which the first node is at a low level. 10. A plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines, and a word driver connected to the word lines for supplying a driving voltage to the selected word lines. A voltage conversion circuit that receives a first potential to generate a second potential, and when one of the plurality of word lines is selected, the corresponding word driver sets the second potential to a switch unit. Applied to the selected word line via the voltage conversion circuit, the voltage conversion circuit having a first node and a second node.
A capacitor, a first MOS transistor having a source / drain path coupled between the first potential and the second node, a second capacitor having a third node and a fourth node, the first potential and the A second MOS transistor having a source / drain path coupled between the four nodes, and a fifth MOS transistor
A third capacitor having a node and a sixth node; and a third MOS transistor having a source / drain path coupled between the first potential and the sixth node, wherein the gate of the first MOS transistor is the Connected to a fourth node, the gate of the second MOS transistor is connected to the second node, the gate of the third MOS transistor is connected to the fourth node, the threshold of the transistor used in the word driver The voltage is lower than the threshold voltage of the transistor used in the memory cell, and the threshold voltage of the transistor used in the voltage conversion circuit is lower than the threshold voltage of the transistor used in the word driver. Semiconductor device. 11. The switching device according to claim 9, further comprising a P-type MISFET, wherein the first node is driven to the high level and the low level at a predetermined cycle, and the third node is the first node. Is driven at a low level when driven at a high level, is driven at a high level when the first node is driven at a low level, and the fifth node is driven when the first node is driven at a high level. Is driven at a high level, and is driven to a low level when the first node is driven at a low level. 12. The drive voltage according to claim 1, wherein the drive voltage is higher than an amplitude voltage of the data line by a threshold voltage of a transistor used in the memory cell or more. Semiconductor device. 13. The word driver according to claim 11, wherein the word driver is a static word driver, and an operating voltage of the word driver is always higher than a data line voltage by a threshold value of a transistor in the memory cell or more. A semiconductor device characterized by the above. 14. The semiconductor device according to claim 1, wherein the memory cell is a dynamic memory cell.