JP2003179181A - Resin wiring board - Google Patents
Resin wiring boardInfo
- Publication number
- JP2003179181A JP2003179181A JP2001376656A JP2001376656A JP2003179181A JP 2003179181 A JP2003179181 A JP 2003179181A JP 2001376656 A JP2001376656 A JP 2001376656A JP 2001376656 A JP2001376656 A JP 2001376656A JP 2003179181 A JP2003179181 A JP 2003179181A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- wiring board
- substrate
- main surface
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structure Of Printed Boards (AREA)
- Waveguides (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、信号を伝送する信
号導体線が形成された樹脂製の配線基板に関し、特に、
高周波信号を伝送する信号導体線が形成された樹脂製の
配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin wiring board on which a signal conductor line for transmitting a signal is formed, and in particular,
The present invention relates to a resin wiring board on which a signal conductor line for transmitting a high frequency signal is formed.
【０００２】[0002]
【従来の技術】従来より、高周波信号を扱うＩＣチップ
などを搭載し、この高周波信号を伝送する信号導体線が
形成された樹脂製の配線基板が知られている。例えば、
従来形態１として図６に断面図を示す樹脂製配線基板８
０１が挙げられる。この樹脂製配線基板８０１は、基板
主面８１２と基板裏面８１３を有する略板形状の基板本
体８１１を備える。基板主面８１２側には、入出力端子
としてのピン８９１が複数立設されている。また、基板
本体８１１には、基板主面８１２と基板裏面８１３との
間を貫通する階段状のキャビティ（透孔）８１５が形成
されている。そして、このキャビティ８１５内には、基
板裏面８１３に固着されたヒートシンク８８１の部品搭
載突起部８８３が挿入されている。さらに、この部品搭
載突起部８８３上には、ＩＣチップ８７１が固着されて
いる。ＩＣチップ８７１の各端子は、基板本体８１１に
形成されたＩＣ接続端子とワイヤーボンディングにより
接続されている。また、キャビティ８１５内は、樹脂８
７５により封止されている。2. Description of the Related Art Heretofore, there has been known a resin wiring board on which an IC chip for handling high frequency signals is mounted and a signal conductor line for transmitting the high frequency signals is formed. For example,
As a conventional form 1, a resin wiring board 8 whose cross-sectional view is shown in FIG.
01 is mentioned. The resin wiring board 801 includes a substantially plate-shaped board body 811 having a board main surface 812 and a board back surface 813. A plurality of pins 891 as input / output terminals are provided upright on the substrate main surface 812 side. Further, the substrate body 811 is provided with a stepped cavity (through hole) 815 penetrating between the substrate main surface 812 and the substrate back surface 813. The component mounting protrusion 883 of the heat sink 881 fixed to the back surface 813 of the substrate is inserted into the cavity 815. Further, an IC chip 871 is fixed on the component mounting protrusion 883. Each terminal of the IC chip 871 is connected to the IC connection terminal formed on the substrate body 811 by wire bonding. Further, the inside of the cavity 815 is made of resin 8
It is sealed by 75.
【０００３】このうち基板本体８１１は、４層の樹脂絶
縁層８２１，８２２，８２３，８２４が積層されてい
る。また、各樹脂絶縁層８２１，８２２，８２３，８２
４の層間には、所定パターンの導体層８２６，８２７，
８２８がそれぞれ形成されている。さらに、基板裏面８
１２には、ヒートシンク８８１をハンダで固着するため
の導体層８２９が枠状に形成されている。また、基板本
体８１１には、基板主面８１２と基板裏面８１３との間
を貫通する略筒状のスルーホール導体８１７が複数形成
され、各々のスルーホール導体８１７は、導体層８２
６，８２７，８２８のいずれかと接続している。さら
に、これらのスルーホール導体８１７内には、基板主面
８１２側からピン８９１が挿入され、ハンダで固着され
ている。Of these, the substrate body 811 has four resin insulation layers 821, 822, 823 and 824 laminated. In addition, each resin insulating layer 821, 822, 823, 82
Between the four layers, conductor layers 826, 827,
828 are formed respectively. Furthermore, the back surface 8 of the substrate
A conductor layer 829 for fixing the heat sink 881 with solder is formed on the frame 12 in a frame shape. In addition, a plurality of substantially cylindrical through-hole conductors 817 penetrating between the substrate main surface 812 and the substrate back surface 813 are formed in the substrate body 811, and each of the through-hole conductors 817 includes the conductor layer 82.
6, 827 or 828. Further, pins 891 are inserted into the through-hole conductors 817 from the substrate main surface 812 side and fixed by soldering.
【０００４】このような樹脂製配線基板８０１では、Ｉ
Ｃチップ８７１で取り扱う高周波信号は、層間の導体層
８２６，８２７，８２８に含まれる配線とスルーホール
導体８１７とからなる信号導体線を伝送され、さらにピ
ン８９１を介して外部に伝送される。In such a resin wiring board 801, I
The high-frequency signal handled by the C chip 871 is transmitted through the signal conductor line including the wiring included in the conductor layers 826, 827, and 828 between the layers and the through-hole conductor 817, and is further transmitted to the outside via the pin 891.
【０００５】また、別の従来形態２として図７に断面図
を示す樹脂製配線基板９０１が挙げられる。この樹脂製
配線基板９０１は、多数のＩＣ接続端子９１５が形成さ
れた基板主面９１２と、多数のハンダバンプ９１７が形
成された基板裏面９１３とを有する略板形状の基板本体
９１１を備える。そして、基板主面９１２の中央には、
フリップチップ型のＩＣチップ９７１が搭載されてい
る。Another conventional form 2 is a resin wiring board 901 whose sectional view is shown in FIG. This resin wiring board 901 includes a substantially plate-shaped board body 911 having a board main surface 912 on which a large number of IC connection terminals 915 are formed and a board back surface 913 on which a large number of solder bumps 917 are formed. Then, in the center of the substrate main surface 912,
A flip chip type IC chip 971 is mounted.
【０００６】このうち基板本体９１１は、その中心に６
層の樹脂絶縁層９２１，９２２，９２３，９２４，９２
５，９２６が積層されたコア基板９２０を備える。コア
基板９２０の基板主面９１２側には、３層の樹脂絶縁層
９３１，９３２，９３３が積層され、さらにその上に
は、ソルダーレジスト層９３４が積層されている。同様
に、コア基板９２０の基板裏面９１３側にも、３層の樹
脂絶縁層９３６，９３７，９３８が積層され、さらにそ
の上には、ソルダーレジスト層９３９が積層されてい
る。このうちコア基板９２０には、これを貫通する略筒
状のスルーホール導体９２８が多数形成されている。一
方、コア基板９２０に積層された樹脂絶縁層９３１，９
３２，９３３，９３６，９３７，９３８には、ビア導体
９４１，９４２，９４３，９４６，９４７，９４８がそ
れぞれ多数形成されている。また、コア基板９２０と樹
脂絶縁層９３１，９３６の層間、樹脂絶縁層９３２，９
３３，９３７，９３８同士の層間、樹脂絶縁層９３３，
９３８とソルダーレジスト層９３４，９３９の層間に
は、所定パターンの導体層９５１，９５２，９５３，９
５６，９５７，９５８がそれぞれ形成されている。Of these, the substrate main body 911 has 6
Layer resin insulation layers 921, 922, 923, 924, 92
A core substrate 920 in which 5, 926 are stacked is provided. Three resin insulating layers 931, 932, 933 are laminated on the substrate main surface 912 side of the core substrate 920, and a solder resist layer 934 is further laminated thereon. Similarly, three resin insulation layers 936, 937, 938 are laminated also on the substrate back surface 913 side of the core substrate 920, and a solder resist layer 939 is further laminated thereon. Of these, the core substrate 920 has a large number of substantially cylindrical through-hole conductors 928 penetrating the core substrate 920. On the other hand, resin insulation layers 931 and 9 stacked on the core substrate 920
A large number of via conductors 941, 942, 943, 946, 947, and 948 are formed on 32, 933, 936, 937, and 938, respectively. In addition, between the core substrate 920 and the resin insulation layers 931 and 936, between the resin insulation layers 932 and 9
33, 937, 938 between the layers, resin insulation layer 933,
The conductor layers 951, 952, 953, 9 having a predetermined pattern are provided between the 938 and the solder resist layers 934, 939.
56, 957, and 958 are formed, respectively.
【０００７】このような樹脂製配線基板９０１では、Ｉ
Ｃチップ９７１で取り扱う高周波信号は、層間の導体層
９５１，９５２，９５３，９５６，９５７，９５８に含
まれる配線とビア導体９４１，９４２，９４３，９４
６，９４７，９４８とスルーホール導体９２８とからな
る信号導体線を伝送され、さらにハンダバンプ９１７を
介して外部に伝送される。In such a resin wiring board 901, I
The high frequency signals handled by the C chip 971 are the wirings and via conductors 941, 942, 943, 94 included in the conductor layers 951, 952, 953, 956, 957, 958 between the layers.
6, 947, 948 and through-hole conductors 928 are transmitted through the signal conductor lines, and further transmitted via solder bumps 917 to the outside.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、これら
の樹脂製配線基板８０１，９０１では、信号導体線の一
部にスルーホール導体８１７，９２８やビア導体９４
１，９４６等が介在するため、これらの部分で高周波信
号の伝送ロスが大きくなり、伝送特性が劣る。However, in these resin wiring boards 801, 901, the through-hole conductors 817, 928 and the via conductors 94 are formed in a part of the signal conductor lines.
1, 946 and the like intervene, the transmission loss of the high frequency signal increases in these portions, and the transmission characteristics deteriorate.
【０００９】本発明は、かかる現状に鑑みてなされたも
のであって、高周波信号を伝送する信号導体線が形成さ
れた樹脂製配線基板について、高周波信号の伝送特性を
向上させることができる樹脂製配線基板を提供すること
を目的とする。The present invention has been made in view of the above circumstances, and a resin wiring board having a signal conductor line for transmitting a high frequency signal is made of a resin which can improve the transmission characteristic of the high frequency signal. An object is to provide a wiring board.
【００１０】[0010]
【課題を解決するための手段、作用及び効果】その解決
手段は、基板主面と基板裏面とを有する樹脂製の基板本
体を備える樹脂製配線基板であって、上記基板本体は、
樹脂絶縁層と、上記樹脂絶縁層の表面上に形成された２
００Ｍｂ／Ｓｅｃ以上の高周波信号を伝送する信号導体
線であって、上記基板主面に露出して搭載する電子部品
の端子と接続される部品接続部を一端に有し、上記基板
主面に露出して外部と接続される外部接続部を他端に有
する信号導体線と、を備える樹脂製配線基板である。Means for Solving the Problem, Action and Effect The solution means is a resin wiring board comprising a resin substrate body having a substrate main surface and a substrate back surface, the substrate body comprising:
A resin insulation layer and 2 formed on the surface of the resin insulation layer
A signal conductor wire for transmitting a high-frequency signal of 00 Mb / Sec or more, which has a component connecting portion exposed at the main surface of the substrate and connected to a terminal of an electronic component to be mounted at one end, and exposed at the main surface of the substrate. And a signal conductor wire having an external connection portion at the other end, which is connected to the outside, and a resin wiring board.
【００１１】本発明によれば、樹脂製配線基板には、搭
載する電子部品と外部とを結ぶ高周波用の信号導体線が
形成されている。この信号導体線は、ビア導体やスルー
ホール導体などを介することなく、同一平面上（樹脂絶
縁層の表面上）に形成されているので、信号導体線を通
る信号の損失を小さく抑えることができる。従って、高
周波信号の伝送特性を向上させることができる。しか
も、この配線基板は、樹脂絶縁層を備える樹脂製配線基
板であるので、セラミック製配線基板と比べ安価にする
ことができる。According to the present invention, the resin wiring board is provided with the high-frequency signal conductor wire connecting the mounted electronic component and the outside. Since the signal conductor line is formed on the same plane (on the surface of the resin insulating layer) without passing through the via conductor or the through-hole conductor, it is possible to reduce the loss of the signal passing through the signal conductor line. . Therefore, the transmission characteristics of the high frequency signal can be improved. Moreover, since this wiring board is a resin wiring board having a resin insulating layer, it can be made cheaper than a ceramic wiring board.
【００１２】さらに、上記の樹脂製配線基板であって、
前記樹脂絶縁層は、誘電率が７以下である樹脂製配線基
板とすると良い。Further, in the above resin wiring board,
The resin insulating layer is preferably a resin wiring board having a dielectric constant of 7 or less.
【００１３】本発明によれば、表面に信号導体線が形成
された樹脂絶縁層の誘電率が７以下と小さい。このた
め、信号導体線を通る信号の誘電損失をより低減させる
ことができる。従って、高周波信号の伝送特性をより向
上させることができる。According to the present invention, the dielectric constant of the resin insulation layer on the surface of which the signal conductor wire is formed is as small as 7 or less. Therefore, the dielectric loss of the signal passing through the signal conductor line can be further reduced. Therefore, the transmission characteristics of the high frequency signal can be further improved.
【００１４】さらに、上記のいずれかに記載の樹脂製配
線基板であって、前記信号導体線は、メッキにより形成
されている樹脂製配線基板とすると良い。Further, in the resin wiring board according to any one of the above, it is preferable that the signal conductor line is a resin wiring board formed by plating.
【００１５】本発明によれば、信号導体線は、メッキに
より形成されている。このため、導体ペーストで形成し
た信号導体線よりも抵抗が低く、その結果、信号導体線
を通る信号の損失をさらに低減させることができる。従
って、高周波信号の伝送特性をさらに向上させることが
できる。According to the present invention, the signal conductor wire is formed by plating. Therefore, the resistance is lower than that of the signal conductor wire formed of the conductor paste, and as a result, the loss of the signal passing through the signal conductor wire can be further reduced. Therefore, the transmission characteristic of the high frequency signal can be further improved.
【００１６】さらに、上記のいずれかに記載の樹脂製配
線基板であって、前記樹脂絶縁層の表面上に形成され、
前記信号導体線と間隔をあけて信号導体線の一方の側に
拡がった第１グランド層と、上記樹脂絶縁層の表面上に
形成され、上記信号導体線と間隔をあけて信号導体線の
他方の側に拡がった第２グランド層と、を備える樹脂製
配線基板とすると良い。Further, in the resin wiring board according to any one of the above, it is formed on the surface of the resin insulating layer,
A first ground layer extending to one side of the signal conductor line with a space from the signal conductor line, and the other of the signal conductor lines formed on the surface of the resin insulating layer and spaced from the signal conductor line. It is advisable to use a resin-made wiring board that includes a second ground layer that extends toward the side.
【００１７】本発明によれば、信号導体線の両側には、
接地電位とされるグランド層（第１，第２グランド層）
が形成されている。このため、信号導体線のシールド性
が高くなる。従って、信号導体線を通る高周波信号の伝
送特性をさらに向上させることができる。According to the present invention, on both sides of the signal conductor line,
Ground layer (first and second ground layers) with ground potential
Are formed. Therefore, the shielding property of the signal conductor line is improved. Therefore, the transmission characteristics of the high frequency signal passing through the signal conductor line can be further improved.
【００１８】さらに、上記のいずれかに記載の樹脂製配
線基板であって、前記基板本体には、前記基板主面と基
板裏面との間を貫通する透孔が形成され、Ｃｕを含有す
る金属からなり、上記基板本体の基板裏面に固着された
ヒートシンクであって、上記基板本体の透孔内に上記基
板裏面側から挿入されて上記基板主面側に露出し、前記
電子部品を搭載する部品搭載突起部を有するヒートシン
クを備える樹脂製配線基板とすると良い。Further, in the resin-made wiring board according to any one of the above, a through hole is formed in the substrate body to penetrate between the substrate main surface and the substrate back surface, and a metal containing Cu. A heat sink fixed to the back surface of the substrate of the board body, the heat sink being inserted into the through hole of the board body from the back surface side of the board and exposed to the main surface side of the board, and mounting the electronic component A resin wiring board including a heat sink having a mounting protrusion is preferable.
【００１９】本発明によれば、電子部品を搭載する部品
搭載突起部を有するヒートシンクが基板本体の基板裏面
に固着されている。このため、電子部品で発生する熱を
効率よく基板裏面側から放熱することができる。また、
ヒートシンクはＣｕを含有する金属からなるため、基板
本体との熱膨張率の差を小さくすることができ、配線基
板の熱に対する信頼性を高くすることができる。According to the present invention, the heat sink having the component mounting protrusion for mounting the electronic component is fixed to the back surface of the substrate of the substrate body. Therefore, the heat generated in the electronic component can be efficiently radiated from the back surface side of the substrate. Also,
Since the heat sink is made of a metal containing Cu, it is possible to reduce the difference in the coefficient of thermal expansion from the substrate body, and to increase the reliability of the wiring board against heat.
【００２０】さらに、前記のいずれかに記載の樹脂製配
線基板であって、前記樹脂絶縁層上に形成され、前記信
号導体線の部品接続部に形成されたフリップチップ接続
用信号端子を含む多数のフリップチップ接続用端子を備
え、前記電子部品の搭載の際に、上記電子部品の端子が
上記フリップチップ接続用端子にそれぞれ接続される樹
脂製配線基板とすると良い。Further, the resin wiring board according to any one of the above, including a plurality of flip-chip connection signal terminals formed on the resin insulation layer and formed in a component connection portion of the signal conductor line. It is preferable that the resin wiring board is provided with the flip-chip connection terminals, and the terminals of the electronic components are respectively connected to the flip-chip connection terminals when the electronic component is mounted.
【００２１】本発明の樹脂製配線基板は、信号導体線の
部品接続部に形成されたフリップチップ接続用信号端子
を含む多数のフリップチップ接続用端子を備える。そし
て、これらのフリップチップ接続用端子には、電子部品
を搭載する際に、電子部品の端子がそれぞれ接続され
る。このため、フリップチップ型のＩＣチップを基板本
体に搭載することができる。なお、フリップチップ接続
用端子としては、パッドの他、ハンダバンプやＡｕバン
プなどを用いてもよい。The resin wiring board of the present invention includes a large number of flip-chip connecting terminals including the flip-chip connecting signal terminals formed in the component connecting portions of the signal conductor lines. The terminals of the electronic component are connected to these flip-chip connection terminals when the electronic component is mounted. Therefore, the flip chip type IC chip can be mounted on the substrate body. As the flip-chip connection terminal, a solder bump or an Au bump may be used instead of the pad.
【００２２】さらに、上記のいずれかに記載の樹脂製配
線基板であって、前記基板本体の基板主面に固着された
金属製のスティフナであって、前記信号導体線のうち部
品接続部と外部接続部を除いた部分の少なくとも一部を
覆うスティフナを備える樹脂製配線基板とすると良い。Further, in the resin wiring board according to any one of the above, a metal stiffener fixed to a main surface of the board of the board main body, the stiffener being made of metal, and being connected to a component connecting portion and an external portion of the signal conductor wire. A resin wiring board having a stiffener that covers at least a part of the portion excluding the connection portion may be used.
【００２３】本発明の樹脂製配線基板は、信号導体線の
うち部品接続部と外部接続部を除いた部分の少なくとも
一部を絶縁しつつ覆うスティフナを備える。また、この
スティフナは金属製である。従って、金属製スティフナ
によって信号導体線の少なくとも一部が覆われるので、
信号導体線のシールド性が高くなる。よって、信号導体
線を通る高周波信号の伝送特性をさらに向上させること
ができる。The resin wiring board of the present invention is provided with a stiffener which insulates and covers at least a part of the signal conductor line excluding the component connecting portion and the external connecting portion. Also, this stiffener is made of metal. Therefore, since at least a part of the signal conductor wire is covered with the metal stiffener,
The shielding property of the signal conductor wire is improved. Therefore, the transmission characteristics of the high frequency signal passing through the signal conductor line can be further improved.
【００２４】さらに、上記のいずれかに記載の樹脂製配
線基板であって、前記電子部品が露出して搭載され、前
記電子部品との接続部が、樹脂により封止されている樹
脂製配線基板とすると良い。The resin wiring board according to any one of the above, wherein the electronic component is exposed and mounted, and a connecting portion with the electronic component is sealed with resin. Is good.
【００２５】本発明によれば、電子部品が露出して搭載
され、その接続部が樹脂により封止されている。このた
め、電子部品の接続信頼性を向上させることができる。
一方、セラミック基板で一般に行われるような枠状のフ
レーム部をつくりシールリングを用いて電子部品をその
内部に封止するのに比べ、樹脂を用いれば、安価に電子
部品を封止することができる。According to the present invention, the electronic component is exposed and mounted, and the connecting portion is sealed with resin. Therefore, the connection reliability of the electronic component can be improved.
On the other hand, compared with the case where a frame-shaped frame portion is generally formed with a ceramic substrate and an electronic component is sealed inside by using a seal ring, resin can be used to seal an electronic component at a low cost. it can.
【００２６】さらに、上記の樹脂製配線基板であって、
前記樹脂は、誘電率が７以下である樹脂製配線基板とす
ると良い。Further, in the above resin wiring board,
The resin is preferably a resin wiring board having a dielectric constant of 7 or less.
【００２７】本発明によれば、封止する樹脂の誘電率が
７以下と小さい。このため、信号の誘電損失を低減する
ことができる。従って、高周波信号の伝送特性を向上さ
せることができる。According to the present invention, the dielectric constant of the resin to be sealed is as small as 7 or less. Therefore, the dielectric loss of the signal can be reduced. Therefore, the transmission characteristics of the high frequency signal can be improved.
【００２８】[0028]
【発明の実施の形態】（実施形態１）以下、本発明の実
施の形態を、図面を参照しつつ説明する。本実施形態１
の樹脂製配線基板１０１について、図１に基板主面１１
２側から見た平面図を、図２に図１におけるＡ−Ａ断面
図を示す。この樹脂製配線基板１０１は、基板主面１１
２と基板裏面１１３とを有する略板形状の基板本体１１
１を備える。基板主面１１２側には、入出力端子として
のピン１９１が複数立設されている。また、基板本体１
１１は、キャビティ（透孔）１１５を有し、このキャビ
ティ１１５内には、基板裏面１１３に固着されたヒート
シンク１８１の部品搭載突起部１８３が挿入されてい
る。さらに、この部品搭載突起部１８３上には、ＩＣチ
ップ（電子部品）１７１が固着されている。BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) Hereinafter, embodiments of the present invention will be described with reference to the drawings. Embodiment 1
Regarding the resin wiring board 101 of FIG.
2 is a plan view seen from the 2 side, and FIG. 2 is a sectional view taken along line AA in FIG. This resin wiring board 101 has a substrate main surface 11
2 and a substrate back surface 113 having a substantially plate-like substrate body 11
1 is provided. A plurality of pins 191 as input / output terminals are provided upright on the substrate main surface 112 side. In addition, the substrate body 1
11 has a cavity (through hole) 115, and the component mounting protrusion 183 of the heat sink 181 fixed to the back surface 113 of the substrate is inserted into the cavity 115. Further, an IC chip (electronic component) 171 is fixed on the component mounting protrusion 183.
【００２９】詳細に説明すると、基板本体１１１には、
その平面視略中央に、基板主面１１２と基板裏面１１３
との間を貫通する平面視略矩形状のキャビティ１１５が
形成されている。この基板本体１１１は、図２に示すよ
うに、ガラス−エポキシ樹脂からなる２層のコア樹脂絶
縁層１２１，１２２が積層されたコア基板１２０を備え
る。そして、その基板主面１１２側には、エポキシ樹脂
等からなり、誘電率が約４．４の主面側樹脂絶縁層１３
１が１層積層されている。More specifically, the substrate body 111 includes
The substrate main surface 112 and the substrate back surface 113 are provided substantially at the center in plan view.
A cavity 115 having a substantially rectangular shape in a plan view is formed so as to penetrate therethrough. As shown in FIG. 2, the substrate body 111 includes a core substrate 120 in which two core resin insulating layers 121 and 122 made of glass-epoxy resin are laminated. Then, on the substrate main surface 112 side, a resin insulation layer 13 made of epoxy resin or the like and having a dielectric constant of about 4.4 is formed on the main surface side.
1 is laminated in one layer.
【００３０】この主面側樹脂絶縁層１３１の表面上、即
ち基板主面１１２には、図１に示すように、５１２Ｍｂ
／Ｓｅｃ程度の高周波信号を伝送するための２本の信号
導体線１４１，１４２が、それぞれキャビティ１１５の
外周縁から基板本体１１１の外周縁まで直線的に延びて
いる。これらの信号導体線１４１，１４２は、Ｃｕメッ
キにより形成されたものである。また、これらの信号導
体線１４１，１４２は、それらの一端であるキャビティ
１１５の外周縁近傍に、ＩＣチップ１７１の端子とワイ
ヤーを介して接続される部品接続部１４１Ｓ，１４２Ｓ
を有し、また、それらの他端である基板本体１１１の外
周縁近傍に、図示しない他の基板の端子に接続される外
部接続部１４１Ｔ，１４２Ｔを有する。本実施形態１で
は、信号導体線１４１，１４２全体が基板主面１１２に
それぞれ露出しているので、部品接続部１４１Ｓ，１４
２Ｓや外部接続部１４１Ｔ，１４２Ｔも基板主面１１２
に露出している。On the surface of the main surface side resin insulating layer 131, that is, on the main surface 112 of the substrate, as shown in FIG.
Two signal conductor lines 141 and 142 for transmitting a high-frequency signal of about / Sec linearly extend from the outer peripheral edge of the cavity 115 to the outer peripheral edge of the substrate body 111. These signal conductor lines 141 and 142 are formed by Cu plating. In addition, these signal conductor lines 141, 142 are connected to the terminals of the IC chip 171 via wires in the vicinity of the outer peripheral edge of the cavity 115, which is one end of the signal conductor lines 141S, 142S.
Further, in the vicinity of the outer peripheral edge of the substrate main body 111, which is the other end thereof, external connection portions 141T and 142T connected to terminals of another substrate (not shown) are provided. In the first embodiment, since the entire signal conductor lines 141, 142 are exposed on the main surface 112 of the board, the component connecting portions 141S, 14S.
2S and external connection parts 141T and 142T are also the main surface 112 of the substrate.
Is exposed to.
【００３１】さらに、基板主面１１２には、信号導体線
１４１，１４２とそれぞれ間隔をあけて、接地電位とさ
れるグランド層が略矩形状に形成されている。具体的に
は、図中右側の信号導体線１４１の図中上方には、主面
側第１グランド層１４６が形成され、図中下方には、主
面側第２グランド層１４７が形成されている。一方、図
中左側の信号導体線１４２の図中上方にも、主面側第１
グランド層１４８が形成され、図中下方にも、主面側第
２グランド層１４９が形成されている。また、基板主面
１１２には、ＩＣチップ１７１の端子とそれぞれワイヤ
で接続される略矩形状のＩＣ接続端子１４５がキャビテ
ィ１１５の外周縁近傍に４個形成されている。Further, on the main surface 112 of the substrate, a ground layer having a ground potential is formed in a substantially rectangular shape at intervals from the signal conductor lines 141 and 142. Specifically, a main surface side first ground layer 146 is formed on the upper side of the signal conductor line 141 on the right side of the drawing, and a main surface side second ground layer 147 is formed on the lower side of the drawing. There is. On the other hand, the signal line 142 on the left side of the figure also has the first main surface side on the upper side of the figure.
The ground layer 148 is formed, and the main surface side second ground layer 149 is also formed in the lower part of the drawing. Further, on the main surface 112 of the substrate, four substantially rectangular IC connection terminals 145 that are respectively connected to the terminals of the IC chip 171 by wires are formed near the outer peripheral edge of the cavity 115.
【００３２】主面側樹脂絶縁層１３１とコア基板１２０
との間には、図２に示すように、接地電位とされる裏面
側グランド層１５１が略全面に形成されている。この裏
面側グランド層１５１は、主面側樹脂絶縁層１３１を貫
通して形成された複数のビア導体１３３を介して、主面
側第１グランド層１４６，１４８及び主面側第２グラン
ド層１４７，１４９と接続している（図１参照）。ま
た、裏面側グランド層１５１は、ビア導体１３３を介し
て、一部のＩＣ接続端子１４５とも接続している（図１
参照）。Main surface side resin insulation layer 131 and core substrate 120
As shown in FIG. 2, a back-side ground layer 151 having a ground potential is formed on the substantially entire surface between and. The back surface side ground layer 151 includes the main surface side first ground layers 146, 148 and the main surface side second ground layer 147 via a plurality of via conductors 133 formed so as to penetrate the main surface side resin insulating layer 131. , 149 (see FIG. 1). The back side ground layer 151 is also connected to a part of the IC connection terminals 145 via the via conductor 133 (FIG. 1).
reference).
【００３３】また、基板裏面１１３には、図２に示すよ
うに、ヒートシンク１８１をハンダ１８５で接続するた
めの導体層１５３が略全面に形成されている。この導体
層１５３は、コア基板１２０を貫通して形成されたスル
ーホール導体１２５の一部を介して、裏面側グランド層
１５１と接続している。従って、この導体層１５３も接
地電位とされる。On the back surface 113 of the substrate, as shown in FIG. 2, a conductor layer 153 for connecting the heat sink 181 with the solder 185 is formed on substantially the entire surface. The conductor layer 153 is connected to the back side ground layer 151 via a part of the through-hole conductor 125 formed so as to penetrate the core substrate 120. Therefore, the conductor layer 153 is also set to the ground potential.
【００３４】また、コア基板１２０を構成するコア樹脂
絶縁層１２１，１２２の層間には、図２に示すように、
所定パターンの導体層１２３が形成されている。この導
体層１２３は、コア基板１２０に形成された多数のスル
ーホール導体１２５と接続している。これらのスルーホ
ール導体１２５の一部は、主面側樹脂絶縁層１３１に形
成されたビア導体１３３と直接接続して、さらに一部の
ＩＣ接続端子１４５と接続している。また、一部のスル
ーホール導体１２５は、基板主面１１２まで延び、これ
にピン１９１が挿入され固着されている。ピン１９１
は、他の基板の端子と接続される。ピン１９１には、電
源電位あるいは接地電位とされるもの、信号を伝送する
ものがある。Further, as shown in FIG. 2, between the layers of the core resin insulating layers 121 and 122 constituting the core substrate 120, as shown in FIG.
The conductor layer 123 having a predetermined pattern is formed. The conductor layer 123 is connected to many through-hole conductors 125 formed on the core substrate 120. Some of these through-hole conductors 125 are directly connected to the via conductors 133 formed on the main surface side resin insulating layer 131, and are further connected to some of the IC connection terminals 145. Further, some of the through-hole conductors 125 extend to the main surface 112 of the substrate, and pins 191 are inserted and fixed thereto. Pin 191
Are connected to terminals of another substrate. Some of the pins 191 have a power supply potential or a ground potential, and some transmit signals.
【００３５】次に、ヒートシンク１８１について説明す
ると、ヒートシンクは、ＣｕＷからなる。ヒートシンク
１８１は、基板裏面１１３の導体層１５３にハンダ１８
５を介して固着されている。ヒートシンク１８１のうち
略中央の部品搭載突起部１８３は、基板本体１１１のキ
ャビティ１１５内に遊嵌状に挿入されている。そして、
この部品搭載突起部１８３の頂面には、ＩＣチップ１７
１が固着されている。このＩＣチップ１７１は、基板主
面１１２側に複数の端子を有し、これらの端子は、ワイ
ヤーボンディングにより、基板本体１１１の部品接続部
１４１Ｔ，１４２Ｔ及びＩＣ接続端子１４５とそれぞれ
接続されている。また、ＩＣチップ１７１との接続部
は、Ａｇエポキシ樹脂からなり、誘電率が約４の樹脂１
７５により封止されている。具体的には、キャビティ１
１５内が樹脂１７５で充填され、さらに、キャビティ１
１５上と基板主面１１２のうちキャビティ１１５の周囲
上が樹脂１７５で覆われている。Next, the heat sink 181 will be described. The heat sink is made of CuW. The heat sink 181 is soldered on the conductor layer 153 on the back surface 113 of the substrate.
It is fixed through 5. The component mounting protrusion 183 at the substantially center of the heat sink 181 is loosely fitted into the cavity 115 of the substrate body 111. And
The IC chip 17 is provided on the top surface of the component mounting protrusion 183.
1 is fixed. The IC chip 171 has a plurality of terminals on the main surface 112 side of the substrate, and these terminals are connected to the component connecting portions 141T and 142T and the IC connecting terminal 145 of the substrate body 111 by wire bonding. The connecting portion with the IC chip 171 is made of Ag epoxy resin and has a dielectric constant of about 4.
It is sealed by 75. Specifically, cavity 1
15 is filled with resin 175, and the cavity 1
15 and the periphery of the cavity 115 of the substrate main surface 112 are covered with a resin 175.
【００３６】以上で説明したように、この樹脂製配線基
板１０１には、搭載するＩＣチップ１７１と他の基板と
を結ぶ、２００Ｍｂ／Ｓｅｃ以上の高周波用の信号導体
線１４１，１４２が形成されている。これらの信号導体
線１４１，１４２は、ビア導体やスルーホール導体など
を介することなく、同一平面上（主面側樹脂絶縁層１３
１の表面上）に形成されているので、信号導体線１４
１，１４２を通る信号の損失を小さく抑えることができ
る。従って、高周波信号の伝送特性を向上させることが
できる。しかも、この配線基板１０１は、樹脂製配線基
板であるので、セラミック製配線基板と比べ安価にする
ことができる。As described above, the resin wiring board 101 is provided with the high-frequency signal conductor lines 141 and 142 of 200 Mb / Sec or more for connecting the mounted IC chip 171 and another board. There is. These signal conductor lines 141 and 142 are on the same plane (main surface side resin insulation layer 13) without interposing via conductors or through-hole conductors.
1), the signal conductor line 14
It is possible to suppress the loss of the signal passing through 1,142. Therefore, the transmission characteristics of the high frequency signal can be improved. Moreover, since this wiring board 101 is a resin wiring board, it can be made cheaper than a ceramic wiring board.
【００３７】さらに、本実施形態１では、表面に信号導
体線１４１，１４２が形成された主面側樹脂絶縁層１３
１の誘電率（約４．４）が７以下と小さい。このため、
信号導体線１４１，１４２を通る信号の誘電損失をより
低減させることができる。従って、高周波信号の伝送特
性をより向上させることができる。また、信号導体線１
４１，１４２は、メッキにより形成されているので、導
体ペーストで形成した信号導体線よりも抵抗が低く、そ
の結果、信号導体線１４１，１４２を通る信号の損失を
さらに低減させることができる。従って、高周波信号の
伝祖特性をさらに向上させることができる。また、各々
の信号導体線１４１，１４２の両側には、主面側第１，
第２グランド層１４６，１４７，１４８，１４９が形成
されている。このため、信号導体線１４１，１４２のシ
ールド性が高くなる。従って、信号導体線１４１，１４
２を通る高周波信号の伝送特性をさらに向上させること
ができる。Further, in the first embodiment, the main surface side resin insulating layer 13 having the signal conductor lines 141 and 142 formed on the surface thereof is used.
The dielectric constant of 1 (about 4.4) is as small as 7 or less. For this reason,
The dielectric loss of the signal passing through the signal conductor lines 141, 142 can be further reduced. Therefore, the transmission characteristics of the high frequency signal can be further improved. Also, the signal conductor line 1
Since 41 and 142 are formed by plating, the resistance is lower than that of the signal conductor line formed of the conductor paste, and as a result, the loss of the signal passing through the signal conductor lines 141 and 142 can be further reduced. Therefore, the transmission characteristic of the high frequency signal can be further improved. Also, on both sides of each of the signal conductor lines 141, 142, the main surface side first
Second ground layers 146, 147, 148, 149 are formed. Therefore, the shield properties of the signal conductor lines 141 and 142 are improved. Therefore, the signal conductor lines 141, 14
It is possible to further improve the transmission characteristics of the high-frequency signal passing through 2.
【００３８】また、本実施形態１では、ＩＣチップ１７
１を搭載する部品搭載突起部１８３を有するヒートシン
ク１８１が基板本体１１１の基板裏面１１３に固着され
ている。このため、ＩＣチップ１７１で発生する熱を効
率よく基板裏面１１３側から放熱することができる。ま
た、ヒートシンク１８１はＣｕを含有する金属（Ｃｕ
Ｗ）からなるため、基板本体１１１との熱膨張率の差を
小さくすることができ、配線基板１０１の熱に対する信
頼性を高くすることができる。また、本実施形態１で
は、ＩＣチップ１７１が搭載され、その接続部が樹脂１
７５により封止されているので、ＩＣチップ１７１の接
続信頼性を向上させることができる。一方、セラミック
基板で一般に行われるような枠状のフレーム部をつくり
シールリングを用いて電子部品を封止するのに比べ、樹
脂１７５を用いれば、安価にＩＣチップ１７１を封止す
ることができる。さらに、封止する樹脂１７５の誘電率
（約４）が７以下と小さい。このため、信号の誘電損失
をより低減することができる。従って、高周波信号の伝
送特性をより向上させることができる。Further, in the first embodiment, the IC chip 17
A heat sink 181 having a component mounting protrusion 183 for mounting 1 is fixed to the substrate back surface 113 of the substrate body 111. Therefore, the heat generated in the IC chip 171 can be efficiently radiated from the substrate back surface 113 side. The heat sink 181 is made of a metal containing Cu (Cu
Since it is made of W), the difference in the coefficient of thermal expansion from the substrate body 111 can be reduced, and the reliability of the wiring substrate 101 against heat can be increased. In addition, in the first embodiment, the IC chip 171 is mounted, and its connecting portion is made of the resin 1.
Since it is sealed by 75, the connection reliability of the IC chip 171 can be improved. On the other hand, the resin chip 175 can be used to inexpensively seal the IC chip 171 as compared with the case where a frame-shaped frame portion is generally formed with a ceramic substrate and an electronic component is sealed with a seal ring. . Furthermore, the dielectric constant (about 4) of the sealing resin 175 is as small as 7 or less. Therefore, the dielectric loss of the signal can be further reduced. Therefore, the transmission characteristics of the high frequency signal can be further improved.
【００３９】次いで、この樹脂製配線基板１０１の製造
方法について説明する。この樹脂製配線基板１０１は、
公知の手法により製造することができる。最初に基板本
体１１１を製造する。まず、２層のコア樹脂絶縁層１２
１，１２２からなり、層間に導体層１２３を有するコア
基板１２０を形成する。その後、コア基板１２０にこれ
を貫通するスルーホール導体１２５を形成する。さら
に、コア基板１２０の両面に、裏面側グランド層１５１
と導体層１５３を形成する。Next, a method of manufacturing the resin wiring board 101 will be described. This resin wiring board 101 is
It can be manufactured by a known method. First, the substrate body 111 is manufactured. First, the two-layer core resin insulation layer 12
1, 122, and the core substrate 120 having the conductor layer 123 between the layers is formed. Then, a through-hole conductor 125 penetrating the core substrate 120 is formed on the core substrate 120. Further, the back side ground layer 151 is formed on both surfaces of the core substrate 120.
And a conductor layer 153 is formed.
【００４０】次に、このコア基板１２０に、ビア孔を有
する主面側樹脂絶縁層１３１を形成する。その後、ビア
孔にビア導体１３３を形成すると共に、主面側樹脂絶縁
層１３１の表面に信号導体線１４１，１４２やＩＣ接続
端子１４５、主面側第１，第２グランド層１４６，１４
７，１４８，１４９を有する導体層をＣｕメッキにより
形成する。また、コア基板１２０と主面側樹脂絶縁層１
３１を貫通するスルーホール導体１２５を形成する。そ
の後、この基板本体１１１に、基板主面１１２と基板裏
面１１３との間を貫通するキャビティ１１５を形成すれ
ば、基板本体１１１ができる。Next, on the core substrate 120, a main surface side resin insulating layer 131 having a via hole is formed. After that, the via conductor 133 is formed in the via hole, and at the same time, the signal conductor lines 141 and 142, the IC connection terminals 145, the main surface side first and second ground layers 146 and 14 are formed on the surface of the main surface side resin insulating layer 131.
A conductor layer having 7,148,149 is formed by Cu plating. In addition, the core substrate 120 and the main surface side resin insulating layer 1
A through-hole conductor 125 penetrating 31 is formed. Then, by forming a cavity 115 penetrating between the substrate main surface 112 and the substrate back surface 113 in the substrate body 111, the substrate body 111 can be formed.
【００４１】次に、基板主面１１２側から一部のスルー
ホール導体１２５内にピン１９１を挿入し接続する。次
に、基板本体１１１の基板裏面１１３の導体層１５３
に、ハンダ１８５によりヒートシンク１８１を固着す
る。次に、ヒートシンク１８１の部品搭載突起部１８３
上にＩＣチップ１７１を固着する。その後、ＩＣチップ
１７１の端子と基板本体１１１の部品接続部１４１Ｔ，
１４２Ｔ及びＩＣ接続端子１４５とをワイヤーによりそ
れぞれ接続する。さらに、ＩＣチップ１７１との接続部
に未硬化の樹脂１７５を充填、塗布し、さらにこれを硬
化させて封止樹脂１７５を形成すれば、樹脂製配線基板
１０１が完成する。Next, the pins 191 are inserted and connected from the substrate main surface 112 side into some of the through-hole conductors 125. Next, the conductor layer 153 on the substrate back surface 113 of the substrate body 111
Then, the heat sink 181 is fixed by the solder 185. Next, the component mounting protrusion 183 of the heat sink 181
The IC chip 171 is fixed on the top. After that, the terminals of the IC chip 171 and the component connecting portions 141T of the substrate body 111,
The wires 142T and the IC connection terminal 145 are connected to each other. Further, the uncured resin 175 is filled and applied to the connection portion with the IC chip 171, and the resin is cured to form the sealing resin 175, whereby the resin wiring board 101 is completed.
【００４２】（実施形態２）次いで、第２の実施の形態
について、図を参照しつつ説明する。なお、上記実施形
態１と同様な部分の説明は、省略または簡略化する。本
実施形態２の樹脂製配線基板２０１について、図３に主
面側第３樹脂絶縁層１３３の表面を見た平面図を、図４
に基板主面２１２側から見た平面図を、図５に図４にお
けるＡ−Ａ断面図を示す。なお、図４において、ＩＣチ
ップ２７１等は省略してある。この樹脂製配線基板２０
１は、基板主面２１２と基板裏面２１３とを有する略板
形状の基板本体２１１を備える。そして、基板主面２１
２の略中央には、フリップチップ型のＩＣチップ２７１
が搭載されている。また、基板主面２１２には、平面視
略口字形状のスティフナ２８１が固着されている。(Second Embodiment) Next, a second embodiment will be described with reference to the drawings. The description of the same parts as those in the first embodiment will be omitted or simplified. FIG. 4 is a plan view of the resin wiring board 201 according to the second embodiment, in which the surface of the third resin insulating layer 133 on the main surface side is viewed.
5 is a plan view seen from the substrate main surface 212 side, and FIG. 5 is a sectional view taken along line AA in FIG. Note that the IC chip 271 and the like are omitted in FIG. This resin wiring board 20
1 includes a substantially plate-shaped substrate body 211 having a substrate main surface 212 and a substrate back surface 213. Then, the substrate main surface 21
A flip-chip type IC chip 271 is provided in the approximate center of 2.
Is installed. Further, a stiffener 281 having a substantially square shape in a plan view is fixed to the substrate main surface 212.
【００４３】詳細に説明すると、基板本体２１１は、図
５に示すように、その中心にガラス−エポキシ樹脂から
なる６層のコア樹脂絶縁層２２１，２２２，２２３，２
２４，２２５，２２６が積層されたコア基板２２０を備
える。そして、コア基板２２０の基板主面２１２側に
は、エポキシ樹脂等からなり、誘電率が約４．４である
３層の主面側樹脂絶縁層（主面側第１樹脂絶縁層２３
１，主面側第２樹脂絶縁層２３２，主面側第３樹脂絶縁
層２３３）が積層され、さらにその上には、ハンダバン
プ（フリップチップ接続用端子）２５４を形成するため
の多数の開口を有する主面側ソルダーレジスト層２３４
が積層されている。同様に、コア基板２２０の基板裏面
２１３側にも、エポキシ樹脂等からなる３層の裏面側樹
脂絶縁層（裏面側第１樹脂絶縁層２３６，裏面側第２樹
脂絶縁層２３７，裏面側第３樹脂絶縁層２３８）が積層
され、さらにその上には、ハンダバンプ２５９を形成す
るための多数の開口を有する裏面側ソルダーレジスト層
２３９が積層されている。More specifically, as shown in FIG. 5, the substrate body 211 has six core resin insulation layers 221, 222, 223, 2 made of glass-epoxy resin in the center thereof.
A core substrate 220 in which 24, 225 and 226 are stacked is provided. Then, on the substrate main surface 212 side of the core substrate 220, three main surface side resin insulation layers (main surface side first resin insulation layer 23) made of epoxy resin or the like and having a dielectric constant of about 4.4.
1, a main surface side second resin insulation layer 232, and a main surface side third resin insulation layer 233) are laminated, and a large number of openings for forming solder bumps (flip chip connection terminals) 254 are further formed thereon. Main surface side solder resist layer 234
Are stacked. Similarly, on the substrate back surface 213 side of the core substrate 220, three layers of back surface side resin insulation layers (back surface side first resin insulation layer 236, back surface side second resin insulation layer 237, back surface side third layer) made of epoxy resin or the like are also provided. A resin insulation layer 238) is laminated, and a back side solder resist layer 239 having a large number of openings for forming the solder bumps 259 is further laminated thereon.
【００４４】コア基板２２０と主面側第１樹脂絶縁層２
３１との間には、配線やパッドを有する所定パターンの
主面側第１導体層２４１が形成され、また、コア基板２
２０と裏面側第１樹脂絶縁層２３６との間にも、配線や
パッドを有する所定パターンの裏面側第１導体層２４６
が形成されている。これら主面側第１導体層２４１と裏
面側第１導体層２４６とは、コア基板２２０を貫通して
所定の位置に形成された多数のスルーホール導体２２７
を介して接続している。The core substrate 220 and the main surface side first resin insulation layer 2
A main surface side first conductor layer 241 having a predetermined pattern having wirings and pads is formed between the core substrate 2 and the core substrate 2.
20 and the backside first resin insulation layer 236 also have wirings and pads between the backside first conductor layer 246 and the predetermined pattern.
Are formed. The main surface side first conductor layer 241 and the back surface side first conductor layer 246 penetrate the core substrate 220 and are formed with a large number of through-hole conductors 227.
Connected through.
【００４５】また、主面側第１樹脂絶縁層２３１と主面
側第２樹脂絶縁層２３２の層間にも、配線やパッドを有
する所定パターンの主面側第２導体層２４２が形成され
ている。この主面側第２導体層２４２は、主面側第１樹
脂絶縁層２３１の所定の位置に形成された多数のビア導
体２５１を介して、主面側第１導体層２４１と接続して
いる。さらに、主面側第２樹脂絶縁層２３２と主面側第
３樹脂絶縁層２３３の層間にも、配線やパッドを有する
所定パターンの主面側第３導体層２４３が形成されて
る。この主面側第３導体層２４３は、主面側第２樹脂絶
縁層２３２の所定の位置に形成された多数のビア導体２
５２を介して、主面側第２導体層２４２と接続してい
る。またさらに、主面側第３樹脂絶縁層２３３と主面側
ソルダーレジスト層２３４の層間にも、所定パターンの
主面側第４導体層２４４が形成されている。この主面側
第４導体層２４４は、主面側第３樹脂絶縁層２３３の所
定の位置に形成された多数のビア導体２５３を介して、
主面側第３導体層２４３と接続している。また、この主
面側第４導体層２４４の一部のパッド等は、主面側ソル
ダーレジスト層２３４の開口の所に位置し、その上に
は、ハンダ（ハンダバンプ）２５４が溶着している。Further, between the main surface side first resin insulating layer 231 and the main surface side second resin insulating layer 232, a main surface side second conductor layer 242 having a predetermined pattern having wirings and pads is formed. . The main surface side second conductor layer 242 is connected to the main surface side first conductor layer 241 through a large number of via conductors 251 formed at predetermined positions of the main surface side first resin insulation layer 231. . Further, between the main surface side second resin insulating layer 232 and the main surface side third resin insulating layer 233, a main surface side third conductor layer 243 having a predetermined pattern having wirings and pads is formed. The main surface side third conductor layer 243 has a large number of via conductors 2 formed at predetermined positions of the main surface side second resin insulation layer 232.
It is connected to the main surface side second conductor layer 242 via 52. Further, a main surface side fourth conductor layer 244 having a predetermined pattern is also formed between the main surface side third resin insulating layer 233 and the main surface side solder resist layer 234. The main surface side fourth conductor layer 244 is provided with a large number of via conductors 253 formed at predetermined positions of the main surface side third resin insulation layer 233,
It is connected to the third conductor layer 243 on the main surface side. Further, some pads and the like of the main surface side fourth conductor layer 244 are located at the openings of the main surface side solder resist layer 234, and solder (solder bumps) 254 is welded thereon.
【００４６】これらの導体層のうち、主面側第４導体層
２４４についてさらに説明すると、主面側第４導体層２
４４は、主面側第３樹脂絶縁層２３３と主面側ソルダー
レジスト層２３４の層間、即ち、主面側第３樹脂絶縁層
２３３の表面上に形成されている。この主面側第４導体
層２４４としては、図３に示すように、５１２Ｍｂ／Ｓ
ｅｃ程度の高周波信号を伝送するための２本の信号導体
線２６１，２６２が形成されている。これらの信号導体
線２６１，２６２は、Ｃｕメッキにより形成されたもの
である。これらの信号導体線２６１，２６２は、それぞ
れＩＣチップ２７１が搭載される領域の外周近傍から基
板本体２１１の外周縁まで直線的に延びている。また、
これらの信号導体線２６１，２６２は、それらの一端で
あるＩＣチップ搭載領域の外周近傍に、ＩＣチップ２７
１の端子とハンダ２５４を介して接続される部品接続部
２６１Ｓ，２６２Ｓを有し、また、それらの他端である
基板本体２１１の外周縁近傍に、図示しない他の基板の
端子に接続される外部接続部２６１Ｔ，２６２Ｔを有す
る。そして、図４に示すように、これら部品接続部２６
１Ｓ，２６２Ｓと外部接続部２６１Ｔ，２６２Ｔは、基
板主面２１２側にそれぞれ露出している。なお、部品接
続部２６１Ｓ，２６２Ｓ上には、信号ハンダバンプ（フ
リップチップ接続用信号端子）２５４が溶着している
（図５参照）。Of these conductor layers, the main surface side fourth conductor layer 244 will be further described. The main surface side fourth conductor layer 2
44 is formed between the main surface side third resin insulating layer 233 and the main surface side solder resist layer 234, that is, on the surface of the main surface side third resin insulating layer 233. As shown in FIG. 3, the main surface side fourth conductor layer 244 is 512 Mb / S.
Two signal conductor lines 261 and 262 for transmitting a high frequency signal of about ec are formed. These signal conductor lines 261 and 262 are formed by Cu plating. These signal conductor lines 261 and 262 linearly extend from the vicinity of the outer periphery of the region where the IC chip 271 is mounted to the outer peripheral edge of the substrate body 211. Also,
These signal conductor lines 261 and 262 are provided on the IC chip 27 near the outer periphery of the IC chip mounting area which is one end thereof.
1 has terminal parts 261S and 262S connected to each other via solder 254, and is connected to terminals of another board (not shown) near the outer peripheral edge of the board body 211, which is the other end thereof. It has external connection parts 261T and 262T. Then, as shown in FIG.
The 1S, 262S and the external connection parts 261T, 262T are exposed on the substrate main surface 212 side, respectively. Signal solder bumps (flip-chip connection signal terminals) 254 are welded on the component connection parts 261S and 262S (see FIG. 5).
【００４７】さらに、主面側第４導体層２４４として、
信号導体線２６１，２６２とそれぞれ間隔をあけて、接
地電位とされるグランド層が略矩形状に形成されてい
る。具体的には、図３中右側の信号導体線２６１の図中
上方には、第１グランド層２６６が形成され、図中下方
には、第２グランド層２６７が形成されている。一方、
図中左側の信号導体線２６２の図中上方にも、第１グラ
ンド層２６８が形成され、図中下方にも、第２グランド
層２６９が形成されている。なお、第１，第２グランド
層２６６，２６７，２６８，２６９の所定の部位には、
ハンダバンプ２５４が溶着している。また、主面側第４
導体層２４４として、ＩＣチップ２７１の端子とそれぞ
れハンダ２５４で接続されるＩＣ接続端子２６５が、主
面側第３樹脂絶縁層２３３の表面中央に格子状に多数形
成されている。これらのＩＣ接続端子２６５上には、そ
れぞれハンダバンプ２５４が溶着している（図５参
照）。なお、この主面側第４導体層２４４は、ハンダバ
ンプ２５４が溶着される部分と、信号導体線１６１，１
６２の外部接続部２６１Ｔ，２６２Ｔ近傍を除き、主面
側ソルダーレジスト層２３４に覆われている。Further, as the main surface side fourth conductor layer 244,
A ground layer, which is at a ground potential, is formed in a substantially rectangular shape at a distance from each of the signal conductor lines 261 and 262. Specifically, the first ground layer 266 is formed above the signal conductor line 261 on the right side in FIG. 3, and the second ground layer 267 is formed below the signal conductor line 261 in the figure. on the other hand,
The first ground layer 268 is formed also above the signal conductor line 262 on the left side in the figure, and the second ground layer 269 is also formed below the signal conductor line 262 in the figure. It should be noted that, in predetermined portions of the first and second ground layers 266, 267, 268, 269,
The solder bumps 254 are welded. In addition, the main surface side fourth
As the conductor layer 244, a large number of IC connection terminals 265, which are respectively connected to the terminals of the IC chip 271 by the solder 254, are formed in a lattice pattern in the center of the surface of the third resin insulation layer 233 on the main surface side. Solder bumps 254 are welded on these IC connection terminals 265 (see FIG. 5). The main surface side fourth conductor layer 244 and the signal conductor wires 161 and 1 are welded to the portion where the solder bumps 254 are welded.
The area 62 is covered with the main surface side solder resist layer 234 except for the vicinity of the external connection portions 261T and 262T.
【００４８】次に、基板裏面１１３側について説明する
と、図５に示すように、裏面側第１樹脂絶縁層２３６と
裏面側第２樹脂絶縁層２３７の層間にも、配線やパッド
を有する所定パターンの裏面側第２導体層２４７が形成
されている。この裏面側第２導体層２４７は、裏面側第
１樹脂絶縁層２３６の所定の位置に形成された多数のビ
ア導体２５６を介して、裏面側第１導体層２４６と接続
している。さらに、裏面側第２樹脂絶縁層２３７と裏面
側第３樹脂絶縁層２３８の層間にも、配線やパッドを有
する所定パターンの裏面側第３導体層２４８が形成され
てる。この裏面側第３導体層２４８は、裏面側第２樹脂
絶縁層２３７の所定の位置に形成された多数のビア導体
２５７を介して、裏面側第２導体層２４７と接続してい
る。またさらに、裏面側第３樹脂絶縁層２３８と裏面側
ソルダーレジスト層２３９の層間にも、配線やパッドを
有する所定パターンの裏面側第４導体層２４９が形成さ
れている。この裏面側第４導体層２４９は、裏面側第３
樹脂絶縁層２３８の所定の位置に形成された多数のビア
導体２５８を介して、裏面側第３導体層２４８と接続し
ている。また、この裏面側第４導体層２４９の一部のパ
ッドは、裏面側ソルダーレジスト層２３９の開口の所に
位置し、その上には、ハンダバンプ２５９が溶着してい
る。Next, the substrate back surface 113 side will be described. As shown in FIG. 5, a predetermined pattern having wirings and pads between the back surface side first resin insulation layer 236 and the back surface side second resin insulation layer 237. A second conductor layer 247 on the back surface thereof is formed. The back surface side second conductor layer 247 is connected to the back surface side first conductor layer 246 via a large number of via conductors 256 formed at predetermined positions of the back surface side first resin insulating layer 236. Further, a backside third conductor layer 248 having a predetermined pattern having wirings and pads is also formed between the backside second resin insulating layer 237 and the backside third resin insulating layer 238. The back surface side third conductor layer 248 is connected to the back surface side second conductor layer 247 via a large number of via conductors 257 formed at predetermined positions of the back surface side second resin insulating layer 237. Further, a backside fourth conductor layer 249 having a predetermined pattern having wirings and pads is also formed between the backside third resin insulating layer 238 and the backside solder resist layer 239. The back side fourth conductor layer 249 is formed on the back side third conductor layer 249.
It is connected to the back side third conductor layer 248 via a large number of via conductors 258 formed at predetermined positions of the resin insulating layer 238. Further, a part of the pads of the back side fourth conductor layer 249 are located at the openings of the back side solder resist layer 239, and the solder bumps 259 are welded thereon.
【００４９】次に、ＩＣチップ２７１について説明する
と、このＩＣチップ２７１はフリップチップ型であり、
ハンダ２５４を介して部品接続部２６１Ｓ，２６２Ｓ及
びＩＣ接続端子２６５と接続している。そして、ＩＣチ
ップ２７１との接続部は、Ａｇエポキシ樹脂からなり、
誘電率が約４の樹脂２７５により封止されている。具体
的には、ＩＣチップ２７１と基板主面２１２との隙間が
樹脂２７５で充填され、さらに、基板主面２１２のうち
ＩＣチップ２７１の周縁が樹脂２７５で覆われ、封止さ
れている。また、基板主面２１２には、基板本体２１１
を補強するためにスティフナ２８１が固着されている。
このスティフナ２８１は、表面にＮｉ−Ａｕの保護メッ
キを施したＣｕからなり、平面視口字形状の略板形状で
ある。信号導体線２６１，２６２の部品接続部２６１
Ｓ，２６２Ｓと外部接続部２６１Ｔ，２６２Ｔ、並び
に、ＩＣチップ２７１の搭載領域を除いて、基板主面２
１２を覆っている。Next, the IC chip 271 will be described. The IC chip 271 is a flip chip type,
It is connected to the component connecting portions 261S and 262S and the IC connecting terminal 265 via the solder 254. And the connecting portion with the IC chip 271 is made of Ag epoxy resin,
It is sealed with a resin 275 having a dielectric constant of about 4. Specifically, the gap between the IC chip 271 and the main surface 212 of the substrate is filled with the resin 275, and the peripheral edge of the IC chip 271 on the main surface 212 of the substrate is covered with the resin 275 and sealed. In addition, on the substrate main surface 212, the substrate body 211
A stiffener 281 is fixed to reinforce.
The stiffener 281 is made of Cu with Ni-Au protective plating on the surface, and has a substantially plate shape with a square shape in plan view. Component connection part 261 of signal conductor lines 261 and 262
S, 262S, the external connection portions 261T, 262T, and the substrate main surface 2 except for the mounting area of the IC chip 271.
It covers 12.
【００５０】以上で説明したように、この樹脂製配線基
板２０１には、搭載するＩＣチップ２７１と他の基板と
を結ぶ、２００Ｍｂ／Ｓｅｃ以上の高周波信号用の信号
導体線２６１，２６２が形成されている。これらの信号
導体線２６１，２６２は、ビア導体やスルーホール導体
などを介することなく、同一平面上（主面側第３樹脂絶
縁層２３３の表面上）に形成されているので、信号導体
線２６１，２６２を通る信号の損失を小さく抑えること
ができる。従って、高周波信号の伝送特性を向上させる
ことができる。しかも、この配線基板２０１は、樹脂製
配線基板であるので、セラミック製配線基板と比べ安価
にすることができる。As described above, the resin wiring board 201 is provided with the signal conductor lines 261 and 262 for high frequency signals of 200 Mb / Sec or more, which connect the mounted IC chip 271 and another board. ing. Since the signal conductor lines 261 and 262 are formed on the same plane (on the surface of the third resin insulation layer 233 on the main surface side) without interposing via conductors or through-hole conductors, the signal conductor lines 261 are formed. , 262, the loss of the signal passing therethrough can be suppressed small. Therefore, the transmission characteristics of the high frequency signal can be improved. Moreover, since this wiring board 201 is a resin wiring board, it can be made cheaper than a ceramic wiring board.
【００５１】さらに、本実施形態２でも、表面に信号導
体線２６１，２６２が形成された主面側第３樹脂絶縁層
２３３の誘電率（約４．４）が７以下と小さい。このた
め、信号導体線２６１，２６２を通る信号の誘電損失を
より低減させることができる。従って、高周波信号の伝
送特性をより向上させることができる。また、これらの
信号導体線２６１，２６２も、メッキにより形成されて
いるので、導体ペーストで形成した信号導体線よりも抵
抗が低く、その結果、信号導体線２６１，２６２を通る
信号の損失をさらに低減させることができる。従って、
高周波信号の伝送特性をさらに向上させることができ
る。また、各々の信号導体線２６１，２６２の両側に
は、第１，第２グランド層２６６，２６７，２６８，２
６９も形成されているので、信号導体線２６１，２６２
のシールド性が高くなる。従って、高周波信号の伝送特
性をさらに向上させることができる。Further, also in the second embodiment, the dielectric constant (about 4.4) of the main surface side third resin insulating layer 233 having the signal conductor lines 261 and 262 formed on the surface is as small as 7 or less. Therefore, the dielectric loss of the signal passing through the signal conductor lines 261 and 262 can be further reduced. Therefore, the transmission characteristics of the high frequency signal can be further improved. Further, since these signal conductor lines 261 and 262 are also formed by plating, the resistance thereof is lower than that of the signal conductor lines formed of the conductor paste, and as a result, the loss of signals passing through the signal conductor lines 261 and 262 is further increased. Can be reduced. Therefore,
The transmission characteristics of the high frequency signal can be further improved. Further, on both sides of each of the signal conductor lines 261, 262, the first and second ground layers 266, 267, 268, 2 are provided.
Since 69 is also formed, the signal conductor lines 261 and 262
The shielding property of is improved. Therefore, the transmission characteristic of the high frequency signal can be further improved.
【００５２】また、本実施形態２では、信号導体線２６
１，２６２の部品接続部２６１Ｓ，２６２Ｓに溶着する
信号ハンダバンプ２５４を含む多数のハンダバンプ２５
４を備え、ＩＣチップ２７１の搭載の際に、ＩＣチップ
２７１の端子がハンダバンプ２５４にそれぞれ接続され
る。このため、フリップチップ型のＩＣチップ２７１を
基板本体２１１に搭載することができる。また、本実施
形態２では、信号導体線２６１，２６２のうち部品接続
部２６１Ｓ，２６２Ｓと外部接続部２６１Ｔ，２６２Ｔ
を除いた部分を覆うスティフナ２８１を備える。また、
このスティフナ２８１は金属製である。従って、スティ
フナ２８１によって信号導体線２６１，２６２の一部が
覆われるので、信号導体線２６１，２６２のシールド性
が高くなる。よって、信号導体線２６１，２６２を通る
高周波信号の伝送特性をさらに向上させることができ
る。Further, in the second embodiment, the signal conductor line 26
A large number of solder bumps 25 including signal solder bumps 254 that are welded to the component connection parts 261S and 262S of 1,262.
4, the terminals of the IC chip 271 are respectively connected to the solder bumps 254 when the IC chip 271 is mounted. Therefore, the flip chip type IC chip 271 can be mounted on the substrate body 211. Further, in the second embodiment, the component connecting portions 261S and 262S and the external connecting portions 261T and 262T of the signal conductor lines 261 and 262.
The stiffener 281 is provided to cover the part excluding. Also,
The stiffener 281 is made of metal. Therefore, the stiffener 281 partially covers the signal conductor lines 261 and 262, so that the signal conductor lines 261 and 262 have a high shielding property. Therefore, the transmission characteristics of the high frequency signal passing through the signal conductor lines 261 and 262 can be further improved.
【００５３】また、本実施形態２でも、ＩＣチップ２７
１が搭載され、その接続部が樹脂２７５により封止され
ているので、ＩＣチップ２７１の接続信頼性を向上させ
ることができ、また、セラミック基板に比して安価にＩ
Ｃチップ２７１を封止することができる。さらに、封止
する樹脂２７５の誘電率（約４）が７以下と小さいの
で、信号の誘電損失をより低減することができる。従っ
て、高周波信号の伝送特性をより向上させることができ
る。Also in the second embodiment, the IC chip 27
1 is mounted and the connecting portion is sealed by the resin 275, the connection reliability of the IC chip 271 can be improved, and the cost is lower than that of the ceramic substrate.
The C chip 271 can be sealed. Furthermore, since the dielectric constant (about 4) of the sealing resin 275 is as small as 7 or less, the dielectric loss of the signal can be further reduced. Therefore, the transmission characteristics of the high frequency signal can be further improved.
【００５４】次いで、この樹脂製配線基板２０１の製造
方法について説明する。この樹脂製配線基板２０１も公
知の手法により製造することができる。最初に基板本体
２１１を製造する。まず、６層のコア樹脂絶縁層２２
１，２２２，２２３，２２４，２２５，２２６を積層し
たコア基板２２０を用意する。そして、このコア基板２
２０にスルーホール導体２２７を形成する。さらに、コ
ア基板２２０の両面に、主面側第１導体層２４１と裏面
側第１導体２４６を形成する。Next, a method of manufacturing the resin wiring board 201 will be described. This resin wiring board 201 can also be manufactured by a known method. First, the substrate body 211 is manufactured. First, 6 layers of core resin insulation layer 22
A core substrate 220 in which 1, 222, 223, 224, 225 and 226 are laminated is prepared. And this core substrate 2
The through-hole conductor 227 is formed in 20. Further, the main surface side first conductor layer 241 and the back surface side first conductor 246 are formed on both surfaces of the core substrate 220.
【００５５】次に、コア基板２２０に、ビア孔を有する
主面側第１樹脂絶縁層２３１とビア孔を有する裏面側第
１樹脂絶縁層２３６を形成する。その後、主面側第１樹
脂絶縁層２３１のビア孔にビア導体２５１を形成すると
共に、裏面側第１樹脂絶縁層２３６のビア孔にビア導体
２５６を形成する。また、主面側第１樹脂絶縁層２３１
上に主面側第２導体層２４２を形成すると共に、裏面側
第１樹脂絶縁層２３６上に裏面側第２導体層２４７を形
成する。Next, on the core substrate 220, a main surface side first resin insulation layer 231 having a via hole and a back surface side first resin insulation layer 236 having a via hole are formed. After that, the via conductor 251 is formed in the via hole of the main surface side first resin insulating layer 231, and the via conductor 256 is formed in the via hole of the back surface side first resin insulating layer 236. In addition, the main surface side first resin insulation layer 231
The main surface side second conductor layer 242 is formed thereon, and the back surface side second conductor layer 247 is formed on the back surface side first resin insulating layer 236.
【００５６】次に、主面側第１樹脂絶縁層２３１上に、
ビア孔を有する主面側第２樹脂絶縁層２３２を形成する
と共に、裏面側第１樹脂絶縁層２３６上に、ビア孔を有
する裏面側第２樹脂絶縁層２３７を形成する。その後、
主面側第２樹脂絶縁層２３２のビア孔にビア導体２５２
を形成すると共に、裏面側第２樹脂絶縁層２３７のビア
孔にビア導体２５７を形成する。また、主面側第２樹脂
絶縁層２３２上に主面側第３導体層２４３を形成すると
共に、裏面側第２樹脂絶縁層２３７上に裏面側第３導体
層２４８を形成する。Next, on the main surface side first resin insulation layer 231,
The main surface side second resin insulating layer 232 having a via hole is formed, and the back surface side second resin insulating layer 237 having a via hole is formed on the back surface side first resin insulating layer 236. afterwards,
The via conductor 252 is provided in the via hole of the main surface side second resin insulation layer 232.
And the via conductor 257 is formed in the via hole of the second resin insulation layer 237 on the back surface side. Further, the main surface side third conductor layer 243 is formed on the main surface side second resin insulation layer 232, and the back surface side third conductor layer 248 is formed on the back surface side second resin insulation layer 237.
【００５７】次に、主面側第２樹脂絶縁層２３２上に、
ビア孔を有する主面側第３樹脂絶縁層２３３を形成する
と共に、裏面側第２樹脂絶縁層２３７上に、ビア孔を有
する裏面側第３樹脂絶縁層２３８を形成する。その後、
主面側第３樹脂絶縁層２３３のビア孔にビア導体２５３
を形成すると共に、裏面側第３樹脂絶縁層２３８のビア
孔にビア導体２５８を形成する。また、主面側第３樹脂
絶縁層２３３上に主面側第４導体層２４４を形成すると
共に、裏面側第３樹脂絶縁層２３８上に裏面側第４導体
層２４９を形成する。Next, on the second resin insulation layer 232 on the main surface side,
The main surface side third resin insulating layer 233 having a via hole is formed, and the back surface side third resin insulating layer 238 having a via hole is formed on the back surface side second resin insulating layer 237. afterwards,
The via conductor 253 is provided in the via hole of the third resin insulation layer 233 on the main surface side.
And the via conductor 258 is formed in the via hole of the third resin insulation layer 238 on the back surface side. Further, the main surface side fourth conductor layer 244 is formed on the main surface side third resin insulating layer 233, and the back surface side fourth conductor layer 249 is formed on the back surface side third resin insulating layer 238.
【００５８】次に、主面側第３樹脂絶縁層２３３上に、
開口を有する主面側ソルダーレジスト層２３４を形成す
ると共に、裏面側第３樹脂絶縁層２３８上に、開口を有
する裏面側ソルダーレジスト層２３９を形成する。その
後、主面側ソルダーレジスト層２３４の開口にハンダバ
ンプ２５４を形成し、また、裏面側ソルダーレジスト層
２３９の開口にハンダバンプ２５９を形成すれば、基板
本体２１１ができる。Next, on the third resin insulation layer 233 on the main surface side,
The main surface side solder resist layer 234 having an opening is formed, and the back surface side solder resist layer 239 having an opening is formed on the back surface side third resin insulating layer 238. After that, the solder bumps 254 are formed in the openings of the main surface side solder resist layer 234, and the solder bumps 259 are formed in the openings of the back surface side solder resist layer 239, whereby the substrate body 211 is formed.
【００５９】次に、基板本体２１１の基板主面２１２に
スティフナ２８１を固着する。その後、基板本体２１１
のハンダバンプ２５４にＩＣチップ２７１の端子を接続
し、ＩＣチップ２７１を基板本体２１１に実装する。そ
の後、ＩＣチップ２７１と基板本体２１１との接続部に
樹脂２７５を充填、塗布し、さらにこれを硬化させて封
止すれば、樹脂製配線基板２０１が完成する。Next, the stiffener 281 is fixed to the substrate main surface 212 of the substrate body 211. After that, the substrate body 211
The terminals of the IC chip 271 are connected to the solder bumps 254, and the IC chip 271 is mounted on the substrate body 211. After that, the resin wiring board 201 is completed by filling and applying the resin 275 in the connection portion between the IC chip 271 and the board body 211, and then curing and sealing the resin 275.
【００６０】以上において、本発明を実施形態に即して
説明したが、本発明は上記各実施形態１，２に限定され
るものではなく、その要旨を逸脱しない範囲で、適宜変
更して適用できることはいうまでもない。例えば、上記
実施形態１では、主面側樹脂絶縁層１３１上の導体層
（信号導体線１４１，１４２等）が露出している樹脂製
配線基板１０１を示したが、主面側樹脂絶縁層１３１上
にソルダーレジスト層を設け、導体層を保護するように
してもよい。但し、この場合でも、信号導体線１４１，
１４２の部品接続部１４１Ｓ，１４２Ｓと外部接続部１
４１Ｔ，１４２Ｔは、ＩＣチップ１７１や他の基板の端
子と接続させるため、ソルダーレジスト層から露出する
ようにする。Although the present invention has been described above in connection with the embodiments, the present invention is not limited to the first and second embodiments described above, and is appropriately modified and applied without departing from the scope of the invention. It goes without saying that you can do it. For example, although the resin wiring board 101 in which the conductor layers (the signal conductor lines 141, 142, etc.) on the main surface side resin insulating layer 131 are exposed has been shown in the first embodiment, the main surface side resin insulating layer 131 is shown. You may make it provide a solder resist layer on it and may protect a conductor layer. However, even in this case, the signal conductor lines 141,
Component connection parts 141S and 142S of 142 and external connection part 1
41T and 142T are exposed from the solder resist layer so as to be connected to the terminals of the IC chip 171 and other substrates.
【図１】実施形態１に係る樹脂製配線基板の基板主面側
から見た平面図である。FIG. 1 is a plan view of a resin wiring board according to a first embodiment as viewed from a board main surface side.
【図２】実施形態１に係る樹脂製配線基板の図１におけ
るＡ−Ａ断面図である。FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1 of the resin wiring board according to the first embodiment.
【図３】実施形態２に係る樹脂製配線基板のうち、樹脂
絶縁層の表面を見た平面図である。FIG. 3 is a plan view of the surface of a resin insulating layer of the resin wiring board according to the second embodiment.
【図４】実施形態２に係る樹脂製配線基板のうち、ＩＣ
チップがない状態の基板主面側から見た平面図である。FIG. 4 shows an IC of the resin-made wiring board according to the second embodiment.
FIG. 6 is a plan view seen from the main surface side of the substrate without a chip.
【図５】実施形態２に係る樹脂製配線基板の図４におけ
るＡ−Ａ断面図である。5 is a cross-sectional view taken along line AA in FIG. 4 of the resin wiring board according to the second embodiment.
【図６】従来形態１に係る樹脂製配線基板の断面図であ
る。FIG. 6 is a cross-sectional view of a resin-made wiring board according to Conventional Mode 1.
【図７】従来形態２に係る樹脂製配線基板の断面図であ
る。FIG. 7 is a cross-sectional view of a resin-made wiring board according to conventional form 2.
１０１，２０１ 配線基板
１１１，２１１ 基板本体
１１２，２１２ 基板主面
１１３，２１３ 基板裏面
１１５ キャビティ（透孔）
１３１ 主面側樹脂絶縁層
１４１，１４２，２６１，２６２ 信号導体線
１４１Ｓ，１４２Ｓ，２６１Ｓ，２６２Ｓ 部品接続
部
１４１Ｔ，１４２Ｔ，２６１Ｔ，２６２Ｔ 外部接続
部
１４６，１４８ 主面側第１グランド層
１４７，１４９ 主面側第２グランド層
１７１，２７１ ＩＣチップ（電子部品）
１７５，２７５ 樹脂
１８１ ヒートシンク
１８３ 部品搭載突起部
２３３ 主面側第３樹脂絶縁層
２６６，２６８ 第１グランド層
２６７，２６９ 第２グランド層
２８１ スティフナ101, 201 wiring boards 111, 211 board bodies 112, 212 board main surfaces 113, 213 board back surface 115 cavities (through holes) 131 main surface side resin insulating layers 141, 142, 261, 262 signal conductor wires 141S, 142S, 261S, 262S Component connection portions 141T, 142T, 261T, 262T External connection portions 146, 148 Main surface side first ground layers 147, 149 Main surface side second ground layers 171, 271 IC chip (electronic component) 175, 275 Resin 181 Heat sink 183 Component mounting protrusion 233 Main surface side third resin insulating layer 266, 268 First ground layer 267, 269 Second ground layer 281 Stiffener
Claims (9)
板本体を備える樹脂製配線基板であって、 上記基板本体は、 樹脂絶縁層と、 上記樹脂絶縁層の表面上に形成された２００Ｍｂ／Ｓｅ
ｃ以上の高周波信号を伝送する信号導体線であって、上
記基板主面に露出して搭載する電子部品の端子と接続さ
れる部品接続部を一端に有し、上記基板主面に露出して
外部と接続される外部接続部を他端に有する信号導体線
と、 を備える樹脂製配線基板。1. A resin-made wiring board comprising a resin-made substrate body having a substrate main surface and a substrate back surface, wherein the substrate body is formed on a resin insulation layer and a surface of the resin insulation layer. 200 Mb / Se
A signal conductor line for transmitting a high-frequency signal of c or more, which has a component connecting portion exposed at the main surface of the substrate and connected to a terminal of an electronic component to be mounted at one end, and exposed at the main surface of the substrate. A resin wiring board comprising: a signal conductor wire having an external connection portion connected to the outside at the other end.
て、 前記樹脂絶縁層は、誘電率が７以下である樹脂製配線基
板。2. The resin wiring board according to claim 1, wherein the resin insulating layer has a dielectric constant of 7 or less.
線基板であって、 前記信号導体線は、メッキにより形成されている樹脂製
配線基板。3. The resin wiring board according to claim 1 or 2, wherein the signal conductor line is formed by plating.
脂製配線基板であって、 前記樹脂絶縁層の表面上に形成され、前記信号導体線と
間隔をあけて信号導体線の一方の側に拡がった第１グラ
ンド層と、 上記樹脂絶縁層の表面上に形成され、上記信号導体線と
間隔をあけて信号導体線の他方の側に拡がった第２グラ
ンド層と、を備える樹脂製配線基板。4. The resin wiring board according to claim 1, wherein the resin wiring board is formed on a surface of the resin insulating layer and is spaced apart from the signal conductor line. A first ground layer extending to one side, and a second ground layer formed on the surface of the resin insulating layer and extending to the other side of the signal conductor line with a gap from the signal conductor line. Resin wiring board.
脂製配線基板であって、 前記基板本体には、前記基板主面と基板裏面との間を貫
通する透孔が形成され、 Ｃｕを含有する金属からなり、上記基板本体の基板裏面
に固着されたヒートシンクであって、上記基板本体の透
孔内に上記基板裏面側から挿入されて上記基板主面側に
露出し、前記電子部品を搭載する部品搭載突起部を有す
るヒートシンクを備える樹脂製配線基板。5. The resin wiring board according to claim 1, wherein the board body has a through hole penetrating between the board main surface and the board back surface. A heat sink made of a metal containing Cu and fixed to the back surface of the substrate of the board body, the heat sink being inserted into the through hole of the board body from the back surface side of the board and exposed to the main surface side of the board, A resin wiring board including a heat sink having a component mounting protrusion for mounting an electronic component.
脂製配線基板であって、 前記樹脂絶縁層上に形成され、前記信号導体線の部品接
続部に形成されたフリップチップ接続用信号端子を含む
多数のフリップチップ接続用端子を備え、 前記電子部品の搭載の際に、上記電子部品の端子が上記
フリップチップ接続用端子にそれぞれ接続される樹脂製
配線基板。6. The resin wiring board according to claim 1, wherein the flip-chip connection is formed on the resin insulation layer and is formed on a component connecting portion of the signal conductor line. A wiring board made of resin, comprising a large number of flip-chip connection terminals including signal terminals for connection, wherein the terminals of the electronic component are respectively connected to the flip-chip connection terminals when the electronic component is mounted.
脂製配線基板であって、 前記基板本体の基板主面に固着された金属製のスティフ
ナであって、前記信号導体線のうち部品接続部と外部接
続部を除いた部分の少なくとも一部を覆うスティフナを
備える樹脂製配線基板。7. The resin wiring board according to claim 1, which is a metal stiffener fixed to a main surface of the substrate of the board main body, the stiffener being made of metal. A resin wiring board having a stiffener that covers at least a part of the part of the resin connecting part and the external connecting part.
脂製配線基板であって、 前記電子部品が露出して搭載され、 前記電子部品との接続部が、樹脂により封止されている
樹脂製配線基板。8. The resin wiring board according to claim 1, wherein the electronic component is exposed and mounted, and a connecting portion with the electronic component is sealed with a resin. Resin wiring board.
て、 前記樹脂は、誘電率が７以下である樹脂製配線基板。9. The resin-made wiring board according to claim 8, wherein the resin has a dielectric constant of 7 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001376656A JP2003179181A (en) | 2001-12-11 | 2001-12-11 | Resin wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001376656A JP2003179181A (en) | 2001-12-11 | 2001-12-11 | Resin wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003179181A true JP2003179181A (en) | 2003-06-27 |
Family
ID=19184804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001376656A Pending JP2003179181A (en) | 2001-12-11 | 2001-12-11 | Resin wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003179181A (en) |
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2001
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| US7635918B2 (en) | 2006-05-16 | 2009-12-22 | Kabushiki Kaisha Toshiba | High frequency device module and manufacturing method thereof |
| JP4690938B2 (en) * | 2006-05-16 | 2011-06-01 | 株式会社東芝 | High frequency element module |
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