JP2003178590A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable sharing a row decoder decoding an address of a bock being an object of write-in and erasure of data by a plurality of memory cell arrays, in a NAND type EEPROM. <P>SOLUTION: For example, a block address signal ARi indicating a selection block is decoded by a row pre-decoder 23. Then the decoded output (pre-decode signal AROWAi, Bi, Ci, Di, Ei) is decoded by a row decoder 24, and made a block selection signal BLKDECi. This block selection signal BLKDECi is sent to block latch circuit 12a, 12b respectively. Thus, selection of a block corresponding to the block address signal ARi is performed for each memory cell array 11a, 11b. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly, to simultaneously writing data to a plurality of pages existing in a plurality of memory cell arrays, or to a plurality of pages existing in a plurality of memory cell arrays. NAND-type EEPROM (Electrical) that simultaneously selects several blocks to be erased
ly Erasable Programmable
Read Only Memory).

[0002]

2. Description of the Related Art Conventionally, a NAND type EEPROM is generally provided with an operation mode as a function of simultaneously selecting one or a plurality of blocks and erasing data in blocks. 266
7617). Further, in recent years, it has been required to simultaneously write data to a plurality of memory cell arrays in order to increase the writing speed as well as to further increase the capacity.

FIG. 8 shows a conventional NAND type EEPROM having an operation mode in which data is collectively erased in block units.
It shows an example of the configuration of M. In addition, here, pla
A case will be described in which two memory cell arrays indicated by ne0 and ne are included.

In FIG. 8, a memory cell array (pla)
ne0,1) 101a, 101b each have a plurality of memory cells arranged in a matrix. In each of the memory cell arrays 101a and 101b, data write operation and data read operation are performed in page units. One page consists of a predetermined number of memory cells connected to the same word line. In addition, each memory cell array 101
For a and 101b, a batch erase operation of data is performed in block units. One block is composed of a predetermined number of pages (memory cell group). That is, a page is composed of a predetermined number of memory cells connected to one word line, a block is composed of a predetermined number of pages, and each memory cell array 101a, 1 is composed of a predetermined number of blocks.
01b is configured.

The memory cell arrays 101a and 101b
Are provided with row decoder units 102a and 102b, respectively. Each row decoder section 102a, 102b
Is a decoder circuit (decoder) 103a, 103
b, block latch circuit (block latch) 1
04a, 104b and the row sub-decoder circuit (r
ow-sub-decoder) 105a, 105b.

The decoder circuits 103a and 103b decode the address of a block to be processed (hereinafter, selected block) in each operation mode.

Block latch circuits 104a and 104b
Holds a selection flag which is block selection information during each operation mode. The block selection information is information indicating whether or not the corresponding block is the selected block.

Row sub-decoder circuits 105a and 105b
Supplies an operation voltage (word line voltage) according to each operation mode to each word line in the selected block.

In the figure, 106 is an address register, and 107 is a row pre-decode.
r) and 108 are CG. SG drive circuit (CG.SG dr
iv), 109a and 109b are memory cell arrays 1
A sense amplifier (sense amp.) Provided for each of 01a and 101b, and IOi (i = 0−).
Reference numeral 7) is an external input pin provided in the address register 106.

In the conventional NAND type EEPROM described above, the row decoder unit 1 including the decoder circuits 103a and 103b, the block latch circuits 104a and 104b, and the row sub-decoder circuits 105a and 105b.
02a and 102b are the memory cell arrays 101a and 10
It was prepared for each 1b.

However, when reading or writing data, the memory cell array 101 is used.
One block may be selected for each of a and 101b. That is, the data read operation and the data write operation are performed for each memory cell array 101.
It is performed for one page in one block existing in each of a and 101b. Therefore, during the data read operation and the data write operation, the block latch circuit 104 that holds the selection flag.
a and 104b are not always necessary.

On the other hand, each memory cell array 101
When a plurality of blocks are simultaneously selected for a and 101b to collectively erase data in block units, an arbitrary number of blocks are selected for each of the memory cell arrays 101a and 101b. Therefore, the block latch circuits 104a and 104 holding the selection flag
It was necessary to provide b.

Thus, one NAND type EEPRO
In M, an operation mode in which data is simultaneously written to one page in any one of a plurality of blocks existing in each memory cell array 101a, 101b, and some of the plurality of blocks existing in each memory cell array 101a, 101b When trying to realize the operation mode in which the
The row decoder units 102a and 102b are required for each of the memory cell arrays 101a and 101b. As a result, the area of the row decoder sections 102a and 102b occupying the chip becomes large, which increases the chip area and eventually the chip cost.

[0014]

As described above, in the prior art, a row decoder section including a decoder circuit, a block latch circuit and a row sub-decoder circuit was required for each memory cell array, which increases the chip area. As a result, there was a problem of increasing the chip cost.

Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device capable of preventing an increase in chip area and thus suppressing an increase in chip cost.

[0016]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises:
A plurality of memory cells arranged in a matrix and capable of performing a data write operation in page units and a batch erase operation of data in block units, and a write operation of the data in the plurality of memory cell arrays And a control unit for controlling the batch erasing operation of the data, and a target of the data writing operation and the data batch erasing operation, which are provided in common to the plurality of memory cell arrays and based on address data input from the outside. And a block selection circuit that selects a block to be

Further, in the nonvolatile semiconductor memory device of the present invention, a plurality of memory cells are arranged in a matrix, and a data write operation in page units and a batch erase operation of data in block units are possible. A plurality of memory cell arrays, and for the plurality of memory cell arrays,
A control unit for controlling the data write operation and the data batch erase operation, and the data write operation and the data write operation, which are provided in common to the plurality of memory cell arrays and are based on address data input from the outside. A block selection circuit that selects a block to be a target of a batch erase operation, and a write operation of the data and a write operation of the data are provided corresponding to each of the plurality of memory cell arrays, based on address data input from the outside. An array selection circuit for selecting a memory cell array to be a target of a batch erase operation is provided.

According to the nonvolatile semiconductor memory device of the present invention, a plurality of decoder circuits for decoding the address of the block to be read, written or erased based on the address data input from the outside are provided. It can be shared between memory cell arrays. As a result, it becomes possible to reduce the area of the row decoder portion occupied in the chip.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a nonvolatile semiconductor memory device according to one embodiment of the present invention. Note that, here, a case will be described in which the present invention is applied to a NAND-type EEPROM having two memory cell arrays represented by planes 0 and 1.

NAND type EEPROM of this embodiment
Is based on the address data input from the outside,
It is characterized in that a decoder for decoding an address of a block which is a target for writing and erasing data is shared among a plurality of memory cell arrays. Further, when selecting a plurality of blocks existing in each memory cell array, the block selection information is arranged for each memory cell array not only in the data erasing operation but also in the data writing operation and the reading operation. It is characterized in that it is held by a block latch circuit.

In FIG. 1, a memory cell array (pla)
ne0, 1) 11a, 11b each have a plurality of memory cells arranged in a matrix. In each of the memory cell arrays 11a and 11b, a data write operation and a data read operation are performed in page units. One page consists of a predetermined number of memory cells connected to the same word line. In addition, each memory cell array 11a, 11b
In this case, a batch erase operation of data is performed in block units. One block is composed of a predetermined number of pages (memory cell group). That is, a page is composed of a predetermined number of memory cells connected to one word line, a block is composed of a predetermined number of pages, and memory cell arrays 11a and 11b are composed of a predetermined number of blocks, respectively. .

Each of the memory cell arrays 11a and 11b has a block latch circuit (block la).
tch) 12a, 12b, and row sub-decoder circuits (row-sub-decoder) 13a, 13b.
Is provided. Block latch circuits 12a and 12b
Holds a selection flag RDECi (i = 0, 1) which is block selection information during each operation mode. The block selection information is information indicating whether or not the corresponding block is a selected block (a block that is a target of a data read operation, a write operation, or an erase operation). The row sub-decoder circuits 13a and 13b supply an operation voltage (word line voltage) corresponding to each operation mode to each word line in the selected block.

In addition, the memory cell arrays 11a and 11
b is a sense amplifier (sense am)
p. ) 14a, 14b are provided. Each of the sense amplifiers 14a and 14b senses the data read to the bit line by amplifying the potential of the bit line. A decode signal ACi (i = 0, 1) corresponding to a column address signal is supplied to each of the sense amplifiers 14a and 14b from a later-described address register via a predecoder (not shown).

Address data and commands are supplied from outside the chip. That is, the address data supplied from the outside is taken into the address register 21 through the external input pin IOi (i = 0-7) in synchronization with the external clock signal WEN. In addition, the command supplied from the outside is synchronized with the external clock signal WEN, and the command register (com) is supplied from the external input pin IOi (i = 0-7).
(mand register) 22.

Of the above address data, a block address signal ARi (i = 0-) indicating a selected block which is a target of data read operation, write operation, and erase operation.
9) is a row pre-deco
It is decoded by the ode) 23 according to the number of blocks. Then, this decode output (for example, predecode signals AROWAi, Bi, Ci, Di, Ei) is
It is supplied to each selection signal line for block selection. For example, when one memory cell array is composed of 1024 blocks, 20 selection signal lines are required.

Decode output AROWAi, Bi, C
i, Di, and Ei are further row decoders (row d).
(ecoder) 24. Then, by being decoded by the row decoder 24, the block selection signal BLKDECi (i = number of blocks) is obtained. In this case, the row decoder 24 uses the memory cell array 1
It is shared by 1a and 11b. Therefore, the block selection signal BLKDECi is sent to the block latch circuits 12a and 12b, respectively. Thus, by supplying the block selection signal BLKDECi to the block latch circuits 12a and 12b, the block corresponding to the block address signal ARi is selected for each of the memory cell arrays 11a and 11b.

On the other hand, of the above address data, the plane address signal APBi (i = 0) indicating the memory cell array including the block for the data read operation, write operation, and erase operation is a plane decoder. 25a and 25b, the plane selection signal PBRi (i = 0,
It becomes 1). The plane selection signal PBRi is sent to the block latch circuits 12a and 12b, respectively.
Thus, by supplying the plane selection signal PBRi to the block latch circuits 12a and 12b, the memory cell array 11 corresponding to the plane address signal APBi is supplied.
Selection of a and 11b is performed.

Here, the plane selection signal PBRi
Is output from the plane decoders 25a and 25b in response to the completion of the input operation of the address data of the plane and the row (block). That is, an address cycle counter (address) that counts address input cycles in synchronization with the external clock signal WEN.
The cycle counter 26 waits for the plane and row address data to be supplied from the outside, and then sends the address latch signal A to the address register 21.
Output DDL. Regarding the row address, the signal RADDL from the address cycle counter 26 is output to the plane decoders 25a and 25b after waiting for the block selection signal BLKDECi to be input to the block latch circuits 12a and 12b. Thus, the plane decoders 25a and 25b output the plane selection signal PBR in synchronization with the signal RADDL.
i is output.

In this way, the block selection signal BLKDEC
The block latch circuits 12a and 12b of the blocks corresponding to the row address indicated by i and the plane address indicated by the plane selection signal PBRi latch the selection flag (RDECi) indicating that the block is the selected block. As a result, in each operation mode of the data read operation, the write operation, and the erase operation, it is possible to select the block corresponding to the address data externally applied.

As described above, the block corresponding to the block address signal ARi and the plane address signal APBi inputted from the outside is selected, and the block is selected during each operation mode of the data write operation, read operation and erase operation. The state (selection flag RDECi) is held by the block latch circuits 12a and 12b.

The above operation for address input is repeated for a plurality of different address data. By doing so, in the arbitrary memory cell arrays 11a and 11b,
In the block latch circuits 12a and 12b of the blocks corresponding to arbitrary row addresses, the selection flag RD can be freely set.
It becomes possible to hold ECi. For example, during a data write operation and a data read operation,
One for each memory cell array 11a, 11b
You can select one block. Further, during the data erasing operation, an arbitrary memory cell array 11
An arbitrary number of blocks can be simultaneously selected for a and 11b.

The command input to the command register 22 is a control circuit (program, erase, r).
ead control) 31. Then, in the control circuit 31, the row decoder 24
Control signal for controlling the charge pump circuit (charge pumps) 32, the block latch circuit 12a, 1
2b, a control signal RSTn for controlling 2b, and a verify control circuit (verify control).
l) The control signal EVFY for controlling 33 is provided. That is, the control circuit 31 controls each unit / circuit according to the analysis result of the command.

The charge pump circuit 32 includes a P-type well region (Cel) of the memory cell arrays 11a and 11b.
Erase voltage Vera is supplied to (1 P-well).
In addition, CG. SG drive circuit (CG.SG drive
r) 34 with respect to the operating voltage Vpgm in each operation mode,
Supply Vpass and Vread.

CG. The SG drive circuit 34 uses the page address signal ACGi (i =
0-3), signals CGi (i = 0-15), SG
Generate D and SGS. Then, these signals CGi,
The SGD and SGS are output to the row sub-decoder circuits 13a and 13b, respectively.

The verify control circuit 33 is
After the data erase operation, an erase verify operation (verify read) is performed to confirm whether the data in the memory cell in the block to be erased is completely erased. During the erase verify operation, the control circuit 31
The control signal EVFY from is at "H" level.

In practice, before each verify cycle in the erase verify operation, the memory cell array 11 corresponding to the block address signal ARi.
For the blocks to be erased a and 11b, the contents of the block latch circuits 12a and 12b are read to detect the non-selected blocks. Signal EB
SEN and signal BUSi (i = 0, 1) are signals prepared for this detection operation.

FIG. 2 shows a circuit configuration example of the row decoder 24 described above. Here, a case where the number of blocks in each of the memory cell arrays 11a and 11b is 5 will be described.

As shown in FIG. 2, a P-channel MOS transistor 24a and N-channel MOS transistors 24b-24g are connected in series between the power supply and the ground. The enable signal RDEC from the control circuit 31 is applied to the gates of the P-channel MOS transistor 24a and the N-channel MOS transistor 24g.
E is supplied respectively. Predecode signals AROWAi, B from the row predecoder 23 are applied to the respective gates of the N channel MOS transistors 24b to 24f.
i, Ci, Di and Ei are supplied respectively.

The input terminal of the inverter circuit 24h is connected to the connection point between the P-channel MOS transistor 24a and the N-channel MOS transistor 24b. Then, the block selection signal BLKDECi is taken out from the output terminal of the inverter circuit 24h.

Further, the power supply and the inverter circuit 24h
P-channel MOS transistor 2
4i and 24j are connected in series. P channel MO
The gate of the S transistor 24i is grounded, and the gate of the P channel MOS transistor 24j is connected to the output terminal of the inverter circuit 24h.

FIG. 3 shows the block latch circuit 12 described above.
3 shows an example of a circuit configuration of a and 12b.

As shown in FIG. 3, the N-channel MOS transistor 12-1 is supplied with the plane selection signal PBRi from the plane decoders 25a and 25b at its gate.
And the block selection signal BL from the row decoder 24.
An N-channel MOS transistor 12-2 whose gate is supplied with KDECi is connected in series. The source of the N-channel MOS transistor 12-2 is grounded. The drain of the N-channel MOS transistor 12-1 is connected to the input terminal of the inverter circuit 12-3 and the output terminal of the inverter circuit 12-4, which are connected in parallel with each other.

The output terminal of the inverter circuit 12-3 and the input terminal of the inverter circuit 12-4 are connected to the gate of the N-channel MOS transistor 12-5, respectively. The source of the N-channel MOS transistor 12-5 is grounded, and the source of the N-channel MOS transistor 12-6 is connected to the drain.

The signal EBSEN from the verify control circuit 33 is supplied to the gate of the N-channel MOS transistor 12-6. Also, this N channel M
The drain of the OS transistor 12-6 has an N channel M
The source of the OS transistor 12-7 is connected.

The block selection signal BLKDECi from the row decoder 24 is supplied to the gate of the N-channel MOS transistor 12-7. A signal BUSi is supplied from the verify control circuit 33 to the drain of the N-channel MOS transistor 12-7.

The output terminal of the inverter circuit 12-3 and the input terminal of the inverter circuit 12-4 are connected to the drain of the N-channel MOS transistor 12-8, respectively. This N channel MOS transistor 1
The source of 2-8 is grounded, and the control circuit 31 is connected to the gate.
From the control signal RSTn.

Further, the output terminal of the inverter circuit 12-3 and the input terminal of the inverter circuit 12-4 are connected to the input terminals of the NAND circuit 12-9 and the NAND circuit 12-10, respectively. The block input signal BLKDECi from the row decoder 24 and the control signal EVFY from the control circuit 31 are supplied to the other input terminals of the NAND circuit 12-9, respectively. The control signal EVFY is supplied from the control circuit 31 to the other input terminal of the NAND circuit 12-10 via the inverter circuit 12-11.

NAND circuit 12-9 and NAND circuit 1
The output terminals of 2-10 are respectively connected to the NAND circuit 12-12.
Connected to each input terminal of. Then, the selection flag RDECi is taken out from the output terminal of the NAND circuit 12-12. Further, the inverted signal RDECin of the selection flag RDECi is taken out from the output terminal of the NAND circuit 12-12 via the inverter circuit 12-13.

FIG. 4 shows the row sub-decoder circuit 1 described above.
3 shows an example of a circuit configuration of 3a and 13b.

As shown in FIG. 4, the output terminal of the NAND circuit 13-1 to which the clock signal RDOSC is supplied to one of the input terminals is connected to the capacitor 13-2. This NA
The selection flag R is applied to the other input terminal of the ND circuit 13-1.
DECi is supplied. The output terminal of the NAND circuit 13-1 is connected to the capacitor 1 via the inverter circuit 13-3.
It is connected to 3-4. The capacitors 13-2, 13-4
Are composed of depletion type N-channel MOS transistors.

The capacitor 13-2 is an N channel MO.
Source of S-transistor 13-5 and N-channel M
It is connected to the connection point between the gate and drain of the OS transistor 13-6.

The capacitor 13-4 is connected to the gate of the N channel MOS transistor 13-5 and the N channel M transistor.
It is connected to the source of the OS transistor 13-6, the gate and drain of the N-channel MOS transistor 13-7, and the source of the depletion type N-channel MOS transistor 13-8, respectively.

The N-channel MOS transistor 13-5
Is connected to the drain of the N-channel MOS transistor 13-9. The N channel M
The word line voltage VRDEC is supplied to the drains of the OS transistors 13-5 and 13-9, respectively.

The N channel MOS transistor 13-9
Has its gate and source connected. The connection point between the gate and the source of this N-channel MOS transistor 13-9 is
-7 source, depletion type N-channel MOS transistor 13-10 source, and N-channel MO
S transistors 13-11, 13-12, 13-13a, 13-1
, 13-13n are connected to the respective gates.

The depletion type N channel MO
The gates of the S transistors 13-8 and 13-10 are connected to the power source, and the drains thereof are connected to the source of the depletion type N-channel MOS transistor 13-14. The selection flag RDE is applied to the drain of the depletion type N-channel MOS transistor 13-14.
Ci is supplied.

The N-channel MOS transistor 13-1
In the case of 1, the signal SGD is supplied to the drain. The source is connected to the select gate SG1 and the drain of the N-channel MOS transistor 13-15. This N
The source of the channel MOS transistor 13-15 is grounded and the gate thereof has an inverted signal RDECin of the selection flag.
Is supplied.

The N-channel MOS transistor 13-1
2, the signal SGS is supplied to the drain. Further, the source is connected to the select gate SG2 and the drain of the N-channel MOS transistor 13-16. This N
The source of the channel MOS transistor 13-16 is grounded and the gate thereof has an inverted signal RDECin of the selection flag.
Is supplied.

The N-channel MOS transistor 13-1
Signals CG0 to CGn are supplied to the drains of 3a, 13-13b, ..., 13-13n. The word lines WL0 to WLn are connected to the respective sources.

FIG. 5 shows the plane decoder 25 described above.
2 shows an example of the circuit configuration of a and 25b.

As shown in FIG. 5, the address cycle counter 26 is provided at one of the input ends of the NAND circuit 25-1.
Is supplied with the signal RADDL. The address register 21 is connected to the other input terminal of the NAND circuit 25-1.
From the plane address signal APBi and its inverted signal A
PBin and are supplied.

The output terminal of the NAND circuit 25-1 is connected to the input terminal of the inverter circuit 25-2. And
The plane selection signal PBRi is taken out as an output from the output terminal of the inverter circuit 25-2.

Next, the NAND type EEPR having the above structure
The operation of the OM will be briefly described with reference to FIGS.

FIG. 6 shows the operation timing relating to the data read operation.

First, in synchronization with the external clock signal WEN, the command commandA for inputting an address is fetched into the command register 22. This allows
The chip enters the address acceptance state.

In the subsequent cycle of the external clock signal WEN, the decode signal (column address signal) ACi as the address data, the plane address signal APBi, the page address signal ACGi, and the block address signal ARi are transmitted via the external input pin IOi. Are input to the address register 21. Then, the address latch signal ADD output from the address cycle counter 26
The address data is transferred to the address register 21 by L.
Latched on.

Of the above address data, the column address signal ACi is input to the sense amplifiers 14a and 14b via a predecoder (not shown). Then, decoding in the column direction is performed.

The plane address signal APBi is selection information for the memory cell arrays (planes) 11a and 11b, and is input to the plane decoders 25a and 25b.

The page address signal ACGi indicates a page address in the selected block, and the CG. It is input to the SG drive circuit 34.

CG. The SG drive circuit 34 applies the word line voltage V to the row sub-decoders 13a and 13b shown in FIG. 4 during a data read operation, a write operation, and an erase operation.
Supply RDEC.

The block address signal ARi is generated by the row predecoder 23 shown in FIG.
After being decoded into ROWAi, Bi, Ci, Di, Ei, it is input to the row decoder 24. As a result, the address of the block is decoded based on the address data input from the outside.

After the end of 3 cycles of the address input (add), the row decoder 24 output from the control circuit 31.
The row decoder 24 shown in FIG. 2 is enabled by an enable signal RDECE for controlling the.
As a result, the block selection signal BLK of the block corresponding to the block address signal ARi input from the outside
DECi is generated.

When the block selection signal BLKDECi is generated, the signal RADDL output from the address cycle counter 26 is input to the plane decoders 25a and 25b shown in FIG. As a result, the addresses of the memory cell arrays (planes) 11a and 11b are decoded.

As described above, the selection flag RDECi is set in the block latch circuits 12a and 12b of the block corresponding to the block address signal ARi input from the outside.

In FIG. 6, for the two memory cell arrays 11a and 11b indicated by planes 0 and 1,
By inputting one block address signal ARi, two block latch circuits 12a, 12
b, selection flags RDEC (0) and RDEC, respectively.
The case where (1) is set is shown.

As shown in FIG. 3, the control signal RSTn output from the control circuit 31 is input to the block latch circuits 12a and 12b. The control signal RSTn is
It is at "H" level except during the data read operation, write operation, and erase operation. As a result, the block latch circuits 12a and 12b are kept in the reset state.

Following the address input, the read operation command commandB is input to the command register 22. Then, inside the chip, the control circuit 31 activates each operation mode of data reading, writing, and erasing.

In the selected block, that is, the block in which the selection flag RDECi is at "H" level, the row sub-decoders 13a and 13b shown in FIG. 4 are activated based on the selection flag RDECi. This allows
The potential (word line voltage VRDEC) boosted by a booster circuit (not shown) in the chip is supplied to the row sub-decoders 13a and 13b shown in FIG.

The row sub-decoder 13 shown in FIG.
By applying the clock signal RDOSC to a and 13b, the node NA is boosted to VRDEC + VthA (threshold value of the transistor 13-9). This gives C
G. Signals CG0 to CGn, SG from the SG drive circuit 34
D and SGS are respectively transferred to select gates SG1 and SG2 and word lines WL0 to WLn of the selected block. Then, the potentials are controlled so as to be necessary for each operation of reading, writing and erasing data.

In FIG. 6, the selection flag RDEC
An example is shown in which a data read operation is performed on a block having (0) and RDEC (1).

In this case, the read voltage Vread is applied to the select gate SG1 of the selected block, the voltage Vread is applied to the non-selected word line, and the voltage Vss is applied to the selected word line.
However, the voltage Vread is applied to the select gate SG2. In this way, the data is read.

FIG. 7 shows the operation timing relating to the data erasing operation. The erase operation here consists of a net data erase operation and an erase verify operation that is subsequently performed. The erase verify operation is to check whether the data in the memory cell in the selected block to be erased (erase selected block) has been completely erased. These operations are performed under the control of the control circuit 31.

Prior to the erase operation, first, in synchronization with the external clock signal WEN, the command c for address input is input.
commandA is input into the command register 22. As a result, the address of the erase selected block is input.

FIG. 7 shows an example in which two blocks in the same memory cell array are selected at the same time to perform the erase operation. In this case, the block latch circuits 1 of two blocks in the same memory cell array 11a
2a have selection flags RDEC (0) and RDE, respectively.
C (1) is set.

Subsequently, the command command C for the erase operation is input to the command register 22. Then,
The chip is set to the operating mode for erasing.

That is, when the control circuit 31 activates the operation mode for erasing, CG. The SG drive circuit 34 includes the row sub-decoder 13a shown in FIG.
13b, signals CG0-CGn, SGD, SGS
Is output. As a result, the select gates SG1 and SG2 of the erase selected block and the word lines WL0 to WLn are
The voltages Vcc, Vcc, and Vss are supplied, respectively.

Further, the control circuit 31 activates the charge pump circuit 32, and the charge pump circuit 32 causes the P-type well region (Cell P) of the memory cell arrays 11a and 11b.
-Well) is supplied with the erase voltage Vera.

In this case, in the row subdecoders 13a and 13b of the erase selected block, the node NA is at the voltage V
cc, and the select gate SG1 of the erase selected block
Voltage Vera + VthB (threshold value of the transistor 13-11) is applied to the word lines WL0 to W of the erase selected block.
The voltage Vss is applied to all Ln, and the voltage Vera + Vth is applied to the select gate SG2. In this way, the data of the memory cells in the erase selected block are collectively erased.

After the erase operation, an erase verify operation is performed to confirm whether the data in the memory cell in the erase selected block has been completely erased. This erase verify operation is performed by sequentially incrementing the block address signal ARi from address 0.

When the erase verify operation is started, FIG.
As shown in, the enable signal RDECE becomes "H" level, and the block address signal ARi is incremented each time the verify operation is performed once from the head address. Then, according to the change of the block address signal ARi, the predecode signals AROWAi, B
i, Ci, Di, Ei are changed. In this way, verification is performed while sequentially selecting a plurality of blocks in each of the memory cell arrays 11a and 11b.

The block latch circuit 12a shown in FIG.
In 12b, the control signal EVFY is supplied from the control circuit 31. The control signal EVFY becomes "H" level during the erase verify operation. As a result, only the blocks corresponding to the block latch circuits 12a and 12b that are selected by the block address signal ARi that is sequentially incremented (the block selection signal BLKDECi becomes “H” level) and the selection flag RDECi is latched are selected. , The selected state is set during the erase verify operation.

Then, the block latch circuits 12a, 12
b to the row sub-decoders 13a and 13b, the selection flag R
DECi (= “H” level) is transferred, and verify reading is performed.

In the memory cell arrays 11a and 11b having no erase selected block, verify reading is performed in a state where all blocks are unselected.

Although not shown in FIG. 7, before each verify cycle, the signal EBSEN and the signal BUSi are used for the erase selected block of each memory cell array 11a, 11b corresponding to the block address signal ARi. An operation of reading the contents of the block latch circuits 12a and 12b is performed. In this way, the non-selected memory cell arrays 11a and 11b are detected. As a result of this detection operation, which of the non-selected memory cell arrays 11a and 11b having no erase selected block is fed back to the control circuit 31. Then, with respect to the non-selected memory cell arrays 11a and 11b having no erase selected block, control is performed so as to ignore the verification result output from the sense amplifier circuits 14a and 14b.

Further, the block address signal ARi is incremented, and control is performed so that the verify reading is performed only when the selection flag RDECi is detected.

As described above, data reading, writing, and
A row decoder for decoding an address of a block to be erased can be shared by a plurality of memory cell arrays. As a result, it becomes possible to reduce the area of the row decoder portion occupied in the chip.
Therefore, it is possible to prevent the chip area from increasing, and thus to suppress the chip cost from increasing.

Moreover, even in the case of such a configuration,
With respect to a plurality of cell arrays, data is simultaneously written / read to / from pages in a plurality of blocks selected one by one, or data is erased simultaneously from a plurality of cell arrays to an arbitrary number of blocks. It is possible to

In addition, the invention of the present application is not limited to the above (each) embodiment, and can be variously modified at the stage of implementation without departing from the scope of the invention. Further, the above (each) embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example,
(Each) Even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problem (at least one) described in the section of the problem to be solved by the invention can be solved, and The effect mentioned in the column (at least one of)
When the above is obtained, the configuration in which the constituent requirements are deleted can be extracted as the invention.

[0099]

As described above in detail, according to the present invention, it is possible to provide the nonvolatile semiconductor memory device which can prevent the increase of the chip area and can suppress the increase of the chip cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a nonvolatile semiconductor memory device (NAND EEPROM) according to an embodiment of the present invention.

2 is a circuit diagram showing a configuration example of a row decoder in the NAND type EEPROM of FIG.

3 is a circuit diagram showing a configuration example of a block latch circuit in the NAND type EEPROM of FIG.

4 is a circuit diagram showing a configuration example of a row sub-decoder circuit in the NAND type EEPROM of FIG.

5 is a circuit diagram showing a configuration example of a plane decoder in the NAND type EEPROM of FIG.

FIG. 6 is a timing chart similarly shown for explaining a data read operation in the NAND type EEPROM of FIG. 1;

7 is a timing chart shown to explain the data erasing operation in the NAND type EEPROM of FIG.

FIG. 8 is a view for explaining the conventional technology and its problems,
FIG. 3 is a block diagram of a NAND type EEPROM.

[Explanation of symbols]

11a, 11b ... Memory cell array (plane) 12a, 12b ... Block latch circuits 12-1, 12-2, 12-5, 12-6, 12-7, 12-8 ... N
Channel MOS transistors 12-3, 12-4, 12-11, 12-13 ... Inverter circuits 12-9, 12-10, 12-12 ... NAND circuits 13a, 13b ... Row sub-decoder circuit 13-1 ... NAND circuit 13 -2, 13-4 ... Capacitor (depletion type N
Channel MOS transistor) 13-3 ... Inverter circuit 13-5, 13-6, 13-7, 13-9, 13-11, 13-12
, 13-13a, 13-13b, ..., 13-13n, 13-15
, 13-16 ... N-channel MOS transistors 13-8, 13-10, 13-14 ... Depletion type N
Channel MOS transistors 14a, 14b ... Sense amplifier 21 ... Address register 22 ... Command register 23 ... Row predecoder 24 ... Row decoders 24a, 24i, 24j ... P channel MOS transistors 24b-24g ... N channel MOS transistor 24h ... Inverter circuit 25a, 25b ... Plane decoder 25-1 ... NAND circuit 25-2 ... Inverter circuit 26 ... Address cycle counter 31 ... Control circuit 32 ... Charge pump circuit 33 ... Verify control circuit 34 ... CG. SG drive circuit IOi (i = 0-7) ... External input pins SG1, SG2 ... Select gates WL0-WLn ... Word line ACi (i = 0, 1) ... Decode signal (column address signal) ACGi (i = 0-3) ) ... Page address signal ADDL ... Address latch signal APBi (i = 0) ... Plane address signal ARi (i = 0-9) ... Block address signal AROWAi, Bi, Ci, Di, Ei ... Decode output (predecode signal) BLKDECi (I = number of blocks) ... Block selection signal BUSi (i = 0, 1) ... Signal CGi (i = 0-15) ... Signal EBSEN ... Signal EVFY ... Control signal PBRi (i = 0, 1) ... Plane selection signal RADDL .. signal RDECE ... enable signal RDECi (i = 0, 1) ... selection flag RDOSC ... clock signal RSTn Control signal SGD, SGS ... signal Vera ... erase voltage Vpass ... operating voltage Vpgm ... operating voltage Vread ... operating voltage VRDEC ... word line voltage WEN ... external clock signal

Claims (11)

[Claims] 1. A plurality of memory cell arrays, each of which has a plurality of memory cells arranged in a matrix and is capable of a data write operation in page units and a batch erase operation of data in block units; A control unit that controls the data write operation and the data batch erase operation, and the data write operation and the data write operation that are provided in common to the plurality of memory cell arrays and are based on address data input from the outside. A non-volatile semiconductor memory device comprising: a block selection circuit that selects a block that is a target of a batch erase operation. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the control unit simultaneously executes the data write operation on a plurality of pages in the plurality of memory cell arrays. 3. The control unit simultaneously executes the batch erase operation of the data for a plurality of blocks in the plurality of memory cell arrays.
The non-volatile semiconductor memory device described in 1. 4. A memory cell array that is provided corresponding to each of the plurality of memory cell arrays and is a target of the data write operation and the data batch erase operation based on the address data input from the outside. The nonvolatile semiconductor memory device according to claim 1, further comprising an array selection circuit for selecting. 5. The nonvolatile memory according to claim 1, wherein each of the plurality of memory cell arrays is provided with a holding circuit for holding block selection information by the block selection circuit, corresponding to each block. Semiconductor memory device. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cell arrays are capable of reading data in page units. 7. A plurality of memory cell arrays, each of which has a plurality of memory cells arranged in a matrix and is capable of performing a data write operation in page units and a batch erase operation of data in block units, and A control unit that controls the data write operation and the data batch erase operation, and the data write operation and the data write operation that are provided in common to the plurality of memory cell arrays and are based on address data input from the outside. A block selection circuit that selects a block that is a target of a batch erase operation, and a write operation of the data and a write operation of the data based on address data that is provided corresponding to each of the plurality of memory cell arrays. Select the memory cell array that is the target of the batch erase operation. A non-volatile semiconductor memory device comprising a ray selection circuit. 8. The nonvolatile semiconductor memory device according to claim 7, wherein the control unit simultaneously executes the data write operation on a plurality of pages in the plurality of memory cell arrays. 9. The control unit simultaneously executes the batch erase operation of the data for a plurality of blocks in the plurality of memory cell arrays.
The non-volatile semiconductor memory device described in 1. 10. The nonvolatile memory according to claim 7, wherein each of the plurality of memory cell arrays is provided with a holding circuit for holding block selection information by the block selection circuit, corresponding to each block. Semiconductor memory device. 11. The nonvolatile semiconductor memory device according to claim 7, wherein the plurality of memory cell arrays are capable of reading data in page units.