JP2003177829A - Regulator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a regulator circuit constituting a stable internal power source circuit, which is capable of ensuring a phase margin without making it necessary to provide any phase compensating means as an external circuit other than a phase compensating circuit inside an IC, and preventing the increase of the number of the pins of the IC circuit. <P>SOLUTION: This series regulator circuit using an arithmetic amplifier circuit to be operated with a high voltage Vcc where a power source voltage is 10 V or more is provided with a reference voltage circuit Vref, a differential amplification stage 1, and output stages A and B. A transistor 32 for outputting the regulator voltage Vout of the output stage B is constituted of an N channel field effect transistor. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a regulator circuit having a regulator power supply circuit incorporated in an integrated circuit (IC), and more particularly to a regulator circuit suitable for high voltage operation with a power supply voltage of 10 V or higher.

[0002]

2. Description of the Related Art Conventionally, a regulator circuit having an operational amplifier structure uses a P-channel field effect transistor as an amplifier at an output portion of a regulator voltage. For example, in such a configuration, the voltage gain from the gate to the drain of the P-channel field effect transistor as an amplifier of the output section becomes as large as several hundred times, which causes the output voltage to be negatively feedback controlled to a predetermined value. The feedback loop gain increases, and the phase delay when the loop gain becomes 0 dB tends to increase. Here, if the phase margin is defined as the difference from the phase delay of 180 °, this phase margin becomes small and becomes very unstable with respect to the output feedback signal, so that the oscillation phenomenon is likely to occur. Normally,
It is necessary to secure this phase margin of 45 ° or more. Therefore, insert a resistor or capacitor for phase compensation in the negative feedback circuit,
The method of ensuring this phase margin by adjusting the gain and the phase is often used.

However, even if such a method is adopted, it is difficult to generate a stable regulator voltage output, and normally, for example, a stabilizing capacitor of about 0.1 μF is used as an external circuit to force oscillation. I had to hold back. For this reason, if this regulator circuit is used for the internal power supply in the IC circuit, an output pin must be provided for the internal power supply regardless of the purpose in order to stabilize the internal power supply. It hinders the reduction of pin count.

In FIG. 4, a regulator circuit according to the prior art has a differential amplification stage 1, an output stage A (2), and an output stage C.
(3) consists of The sources of the differential amplifier stage 1 are connected in common, and the pair of transistors 12 and 13 are driven by a predetermined constant current of the constant current circuit 11 to perform differential amplification.
And the drains of the transistors 12 and 13 are individually connected, the sources are connected to 0 V of the power supply, and the gates are commonly connected.
4) connected to the drain of the current mirror circuit (14,15)
The drain potential of the pair of transistors 14 and 15 and the other transistor 15 of the pair of transistors 14 and 15 is used as the differential amplifier output Va, and the output stage has its source connected to 0V of the power supply and its gate It consists of a transistor circuit (22, 21) with the differential amplified output Va as the input and another constant current circuit 21 as the load circuit at the drain, and a phase compensation circuit consisting of a resistor R5 and a capacitor C. An output stage A (2) that performs negative feedback from the drain to the circuit of the differential amplifier output Va for phase compensation, and a P-channel transistor 41 that connects the source to the power supply voltage Vcc and connects the drain potential of the transistor 22 to the gate. And a second voltage divider circuit consisting of resistors R1 and R2 connected between this drain and the power source 0V, and an output stage C (4) consisting of, and the second voltage divider circuit (R1, R2) Return the divided voltage signal Vf to the differential amplifier output Va of the differential amplifier stage 1 And configured to drain potential of the P-channel transistor 41 as a regulator output.

With this configuration, the regulator circuit
The reference voltage Vref (eg, 1V) input to the gate of the transistor 12 and the second voltage divider (R1, R2) that is negatively fed back to the gate of the transistor 13 divides the voltage to (1/3) Feedback control is performed so that the difference signal of Vf becomes zero, and for example, an output voltage of 3V is obtained. In FIG. 5, the illustrated example shows the gain / phase characteristics of the conventional regulator circuit, in which the horizontal axis indicates frequencies of 100 mHz to 10 MHz.
, The open-loop gain (dBV) and phase lag (deg) on the vertical axis. In the illustrated example, a delay characteristic based on a first-order delay element mainly composed of a differential amplifier stage 1, an output stage A (2), and a phase compensation circuit composed of a resistor R5 and a capacitor C is shown in the vicinity of 2 Hz. In the vicinity of 30 kHz, the high-order delay characteristics of the differential amplifier stage 1 and the output stage A (2) and the output stage C
It can be seen that the effect of the delay characteristics based on (4) appears and the phase margin decreases. As a result, this feedback control system causes an oscillation phenomenon, or even if the oscillation phenomenon does not occur, when the output voltage fluctuates due to the influence of load fluctuation or noise, this fluctuation does not easily decrease. It becomes a factor. As a result, it can be seen that when the regulator circuit is activated, pulsation is superimposed on the constant voltage output of 3V as shown in FIG.

[0006]

As described above, in the regulator circuit in which the output stage according to the prior art is composed of the P-channel transistor, the loop gain is increased by the gain of this transistor and the phase margin is reduced. When the output voltage fluctuates due to load fluctuations, noise, etc., the system causes an oscillation phenomenon, or even if the oscillation phenomenon does not occur, this variation becomes a factor that causes a state in which this variation does not readily decrease.

The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems and to require other phase compensation means as an external circuit in addition to the phase compensation circuit inside the IC. It is to provide a regulator circuit that secures a phase margin without increasing the number of pins of the IC circuit and forms a stable internal power supply circuit.

[0008]

According to the present invention, a series regulator circuit using an operational amplifier circuit that operates at a high power supply voltage of 10 V or higher has a reference voltage circuit and a differential amplification stage. , An output stage, and an N-type transistor for outputting the regulator voltage of the output stage.
It shall be composed of a channel field effect transistor (hereinafter, abbreviated as Nch-MOS-FET).

With such a configuration, by forming the output transistor of the output stage B by the Nch-MOS-FET, the output transistor can be used as a source follower type, and the gain in the output stage B can be set to 1. it can. As a result, a phase margin can be secured without the need for other phase compensation means as an external circuit, an increase in the number of pins of the IC circuit can be prevented, and a stable internal power supply circuit can be configured.

In the differential amplification stage, a pair of transistors having sources commonly connected and driven by a predetermined constant current to perform differential amplification, and drains of the transistors are individually connected to respective drains. Power source is 0V
, A gate connected in common, a gate connected together to the drain of one of the transistors to form a current mirror circuit, and a drain potential of the other transistor of the one set of transistors as a differential amplifier output. can do.

In the output stage, the source is connected to 0 V of the power supply, the gate receives the differential amplified output, and the drain has a transistor circuit using the other constant current circuit as a load circuit, and a phase compensation circuit including a resistor and a capacitor. And an output stage A that negatively feeds back to the differential amplifier output from the drain of the transistor to compensate the phase, a first voltage dividing circuit that divides the power supply voltage to a predetermined value, and the divided voltage. A source follower of the first Nch-MOS-FET, a drain of the first Nch-MOS-FET is connected in series, a gate of the first Nch-MOS-FET is connected to the drain of the transistor of the output stage A, and a second voltage dividing circuit is connected to the source. An output stage B composed of a second Nch-MOS-FET can be provided.

With such a configuration, the divided voltage signal of the second voltage dividing circuit can be negatively fed back to the input of the differential amplifier stage and the source potential of the second Nch-MOS-FET can be used as the regulator output. Also, the output stage transistor that outputs the regulator output voltage can be configured with an NPN bipolar transistor instead of the Nch-MOS-FET. With this configuration, the regulator circuit can be configured without requiring any other phase compensating means other than the phase compensating circuit including the resistor and the capacitor.

[0013]

1 is a block diagram of a regulator circuit according to an embodiment of the present invention, FIG. 2 is a gain / phase characteristic diagram of the regulator circuit, FIG. 3 is a starting characteristic diagram of the regulator circuit, and FIG. The same members corresponding to those in FIG. 6 are designated by the same reference numerals. Referring to FIG. 1, the series regulator circuit according to the present invention uses an operational amplifier circuit that operates at a high power supply voltage of 10 V or higher, and uses a reference voltage circuit (V
ref), the differential amplification stage 1, and the output stages A (2) and B (3), and the transistor 32 that outputs the regulator voltage Vout of the output stage B (3) is an N-channel field effect transistor. Can be configured.

With this configuration, by configuring the output transistor 32 of the output stage B (3) with an Nch-MOS-FET, the output transistor 32 can be used as a source follower type. The gain of can be 1. As a result, it is possible to secure a phase margin, for example, 45 ° without requiring any other phase compensation means as an external circuit, prevent an increase in the number of pins of the IC circuit, and configure a stable internal power supply circuit.

[0015]

EXAMPLE A supplementary explanation of the regulator circuit will be given. In FIG. 1, the regulator circuit is the differential amplifier stage 1 as described above.
And output stages A (2) and B (3). The sources of the differential amplifier stage 1 are connected in common, and the constant current circuit
A pair of transistors 12 and 13 driven by a predetermined constant current for differential amplification, and drains of the transistors 12 and 13 are individually connected to the drains thereof, and a source thereof is connected to 0V of a power source, A pair of transistors 14 and 15 having gates connected in common and connected to the drain of one of the transistors 14 to form a current mirror circuit.
The drain potential of the other transistor 15 of the pair of transistors 14 and 15 is used as the differential amplifier output Va, and at the output stage, the source is connected to 0 V of the power source, the gate receives the differential amplified output Va, and the drain receives another constant current. It consists of a transistor circuit (21,22) that uses the circuit 21 as a load circuit, and a phase compensation circuit that consists of a resistor R5 and a capacitor C. The drain of this transistor 22 is negatively fed back to the differential amplifier output Va for phase compensation. Output stage A
(2) and the power supply voltage Vcc to a predetermined value (for example, 10V
The first voltage divider circuit R3, R4 that divides the voltage to 5V when the power supply voltage is
, And the first Nch-MOS- that sources-follows this divided voltage.
The FET (31) and the source of this first Nch-MOS-FET (31) are connected in series with the drain, the gate is connected to the output Vc of the output stage A, and the source is connected with the second voltage divider R1 and R2. Second Nch-MOS-
It can be configured by including an output stage B (3) including a FET (32).

With such a configuration, the divided voltage signal Vf of the second voltage dividing circuits R1 and R2 is negatively fed back to the differential amplification stage 1 to generate the second Nch-MOS-FE.
The source potential of T (32) can be output as the regulator output Vout. In this circuit configuration, the first Nch-MOS-FE
T (31) is the power supply voltage Vc applied to the second Nch-MOS-FET (32)
c is reduced to 5V, for example, and the function of limiting the output operation amplitude range of the second Nch-MOS-FET (32) to 5V or less is performed.

The second Nch-MOS-FET (32) itself is
Since the source follower circuit is configured, the loop gain of the negative feedback circuit when stabilizing the regulator output voltage Vout to, for example, 3V does not have the voltage gain at the output stage C (4) as described in the prior art, and the output The voltage gain of the stage B (3) is 1, and the phase delay of the output stage B (3) shifts to a higher frequency band. As a result, the gain / phase characteristic diagram of the regulator circuit can be changed from the conventional gain / phase characteristic diagram shown in FIG. 4 to the characteristic shown in FIG. That is, the phase delay (phase margin) when the open loop gain is 0 dB is approximately -90 °, and the phase margin of 45 ° or more required for stabilizing the feedback signal can be sufficiently secured.

As an example of the regulator circuit shown in FIG. 1, FIG. 3 shows a starting characteristic of 3V output, and a stable output voltage without oscillation phenomenon can be obtained without an external capacitor. In the present invention, since the output voltage range of the second Nch-MOS-FET (32) can be suppressed by the first voltage dividing circuits R3, R4 and the first Nch-MOS-FET (31), for example, when the power supply voltage is Transistors (11-15,22,31,32) in 10V system
To utilize the high gain and high frequency characteristics of the same technology as other transistors (not shown) that are often used in integrated circuits (IC circuits) that house this regulator circuit as an internal power supply (that is, 5V power supply system transistors). Can
The IC circuit process can be simplified.

If the second Nch-MOS-FET (32) is a high withstand voltage Nch-MOS-FET of 10 V or more, the first voltage dividing circuit described above is used.
R3, R4 and the first Nch-MOS-FET (31) can be omitted. Further, in the present invention, an NPN bipolar transistor can be used instead of the second Nch-MOS-FET (32) of the output stage B (2) which outputs the regulator output voltage. that's all,
As mentioned above, the transistor 32 of the output stage B (2) is connected to the Nch-MOS-
By using FETs or NPN bipolar transistors, it is possible to construct a regulator circuit that operates stably without the need for any other phase compensating means other than the phase compensating circuit consisting of the resistor R5 and the capacitor C of the output stage A.

[0020]

As described above, according to the present invention, since the output stage of the regulator is composed of the Nch-MOS-FET or the NPN bipolar transistor, it is easy to secure a phase margin of 45 ° or more. Therefore, when this circuit is used as an internal power supply, a stable internal power supply can be generated without requiring a capacitor for stabilizing the internal power supply. Therefore, it is not necessary to provide an output pin for the internal power supply regardless of the application, and the number of pins of the integrated circuit can be reduced, and an effect of reducing external parts can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a regulator circuit according to an embodiment of the present invention.

[Fig.2] Gain / phase characteristic diagram of regulator circuit

FIG. 3 is a starting characteristic diagram of the regulator circuit.

FIG. 4 is a block diagram of a conventional regulator circuit.

FIG. 5 is a gain / phase characteristic diagram of a conventional regulator circuit.

FIG. 6 is a starting characteristic diagram of a conventional regulator circuit.

[Explanation of symbols]

1 differential amplification stage 11,21 constant current circuit 12 to 15,22,31,32,41 transistors 2 to 4 output stages R1 to R5 resistance C capacity Va, Vc, Vf voltage signal Vref reference voltage Vout output voltage Vcc power supply voltage

Claims (5)

[Claims] 1. A series regulator circuit using an operational amplifier circuit that operates at a high power supply voltage of 10 V or more, comprising a reference voltage circuit, a differential amplification stage, and an output stage, and a regulator of the output stage. A transistor that outputs a voltage is an N-channel field effect transistor (hereinafter Nch-MOS-FE
(Abbreviated as T)). 2. The transistor according to claim 1, wherein the output stage has a source connected to 0 V of a power supply, a gate to which the differential amplification output is input, and a drain to which another constant current circuit is a load circuit. A circuit and a phase compensation circuit composed of a resistor and a capacitor, and an output stage A for performing negative feedback from the drain of the transistor to the output of the differential amplifier for phase compensation, and dividing the power supply voltage into a predetermined value. The first voltage divider circuit and the first Nch-MOS- that sources-follows this divided voltage
A FET and a second Nc in which the drain is connected in series to the source of the first Nch-MOS-FET, the gate is connected to the drain of the transistor of the output stage A, and the second voltage dividing circuit is connected to the source.
and an output stage B which is composed of an h-MOS-FET, and which negatively feeds back the divided voltage signal of the second voltage dividing circuit to the input of the differential amplifier stage and uses the source potential of the second Nch-MOS-FET as a regulator output. A regulator circuit comprising: 3. The regulator circuit according to claim 1, wherein the differential amplification stage includes a pair of transistors whose sources are commonly connected and which are driven by a predetermined constant current to perform differential amplification. A drain is individually connected to each drain of this transistor, a source is connected to 0V of a power supply, a gate is commonly connected, and a pair of transistors that are connected to the drain of one of the transistors to form a current mirror circuit, A regulator circuit, wherein the drain potential of the other transistor of the pair of transistors is used as the output of the differential amplifier. 4. The regulator circuit according to any one of claims 1 to 3, wherein the output stage transistor for outputting the regulator output voltage is an NPN bipolar transistor instead of the Nch-MOS-FET. Regulator circuit to do. 5. The regulator circuit according to any one of claims 1 to 4, wherein no other phase compensating means is required other than the phase compensating circuit composed of the resistor and the capacitor. Regulator circuit.