JP2003169100A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems due to an unnecessary DC component generated in a stage of signal processing. <P>SOLUTION: When a desired signal component is extracted from an input signal having an unnecessary DC component included in a desired signal component, the input of the input signal is branched to two paths and inputted to mixers 2 and 3, a local signal is inputted to local signal terminals 4 and 5 while having a phase difference, and outputs of the mixers 2 and 3 after passing through amplifies 6 and 7 are branched to two systems. Capacitors 12 and 13, amplifiers 14 and 15, low-pass filters 16 and 17, amplifiers 18 and 19, and AD converters 20 and 21 are connected to one path and low-pass filters 8 and 9, amplifiers 52 and 53, and AD converters 10 and 11 are connected to the other path; and the outputs of the AD converters 10 and 11, and 20 and 21 are connected to a digital signal processing part 22. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for extracting a desired signal component from an input signal containing a DC component unnecessary for the desired signal component.

[0002]

2. Description of the Related Art There is a direct conversion type receiver as a device for extracting a desired signal component from an input signal including a desired signal component including an unnecessary DC component. As shown in FIG. 16, for example, this direct conversion type receiving apparatus uses mixers 2 and 3 for local signal terminals 4 and 5 with respect to an RF signal input from input terminal 1.
Is mixed with the local signal applied to the. At this time, by selecting the carrier frequency of the RF signal and the frequency of the local signal to be equal, the desired signal component contained in the RF signal is down-converted to the base band. The local signals added to the mixers 2 and 3 are
By giving a phase difference of 90 degrees to each other, both the amplitude information and the phase information of the desired signal component can be taken in.

This down-conversion operation is shown in FIG.
As shown in. That is, R to which the code 23 is input
The F signal is a signal having a bandwidth fBW centered on the frequency f1. Reference numeral 24 is a desired signal component that has been down-converted. Since the local frequency is selected as f1, the desired down-converted signal component exists in the frequency range from 0 to fBW / 2.

Further, in FIG. 16, the down-converted signal is input to low-pass filters (LPF) 16 and 17 through amplifiers 14 and 15, and unnecessary high frequency components are removed. Note that, in general, the input RF signal is, in addition to the desired RF signal 23, as shown in FIG.
It is usually accompanied by unnecessary RF signals 25, 26, etc. that are close in frequency. These unwanted RF signals 25,
26 and the like are down-converted into unnecessary baseband signals 27 by mixers 2 and 3. Further, the unnecessary baseband signal 27 is removed by passing the low-pass filters 16 and 17.

The outputs of the low-pass filters 16 and 17 are passed through amplifiers 18 and 19 and AD converters (ADC) 20 and 21.
It is converted into a digital signal by the input and input to the digital signal processing unit (DSP) 22. In some cases, the digital signal processing unit 22 may collectively perform the extraction, demodulation, and error correction of a desired signal component, or the output of the result of performing only a part of the process may be performed, and the subsequent process may be performed on another signal. It may be performed by a processing device.

In the example shown in FIG. 16, amplifiers 14, 15, 18, 19 are provided between the blocks, but mixers 2, 3, low-pass filters 16, 17, AD.
Depending on the sensitivity of the converters 20, 21 and the input / output voltage / power levels, some or all of these amplifiers 14, 15, 18, 19 may be omitted.

By the way, such a direct conversion type receiver has a problem that a DC offset occurs. Hereinafter, regarding this problem, FIG.
And FIG. 19 will be described. First, ideally, only the RF signal is input to the input terminal 1 of FIG. However, in an actual receiving device, the local signal sneak into the input terminal 1, or in the configuration in which an amplifier or the like is placed in front of the input terminal 1, the local signal sneak into the input of the amplifier. Therefore, the input signal in the actual receiving apparatus is the sum of the desired RF signal 23 and the mixed local signal 28, as shown in FIG. When this input signal is down-converted by the mixers 2 and 3 of the receiving device shown in FIG. 16, the mixed local signal 28
Is mixed with the local signal, and a DC component 29 appears at the mixer output. This DC component 29 is called a DC offset.

Usually, the strength of the local signal handled in the receiving device is set to be higher than the strength of the RF signal. Therefore, the intensity of the DC component 29 appearing in the outputs of the mixers 2 and 3 may be much higher than the intensity of the down-converted desired signal component 24. Further, the polarity of the DC component 29 can be positive or negative depending on the phase relationship between the mixed local signal 28 and the local signal in the preceding stage of the input terminal 1. The DC component 29 saturates the amplifiers 14, 15, 18, 19 and the low-pass filters 16, 17 and the AD converters 20, 21 following the mixers 2, 3 and hinders the normal operation of the receiving device.

As a first method for solving the problem caused by such a DC offset, the gains of the paths following the mixers 2 and 3 in FIG.
15, 18, 19, low-pass filters 16, 17, AD
The saturation of the converters 20 and 21 can be eliminated. However, in such a method, the voltage amplitude of the desired desired signal component also becomes small. This leads to the drawback of being susceptible to noise.

Further, the AD converters 20 and 21 are required to convert a desired signal component having a small amplitude corresponding to an expected input voltage from the minimum value to the maximum value of the DC offset voltage into digital data. . That is, the AD converter 2
It is necessary to increase the number of bits of 0 and 21. For this reason, the power consumption increases and the tolerance of the semiconductor process for manufacturing the AD converters 20 and 21 becomes small, so that the yield is deteriorated, or the manufacturing process with high uniformity is required, resulting in an increase in cost. However, a high-performance manufacturing process is required to increase the cost, or a power supply voltage higher than that of other blocks constituting the receiving device is required, which makes the receiving device complicated.

A second method for solving the problem caused by DC offset will be described with reference to FIG. In the configuration of FIG. 20, for example, capacitors 12 and 13 are provided after the outputs of the mixers 2 and 3 as elements for blocking direct current. With such a configuration, DC is provided in the path following the mixers 2 and 3.
No offset voltage is input, resulting in mixers 2, 3
The gain of the path that follows can be made sufficiently high. As a result, it is solved that the above-mentioned problem is easily affected by noise or that the number of bits of the AD converters 20 and 21 needs to be increased. However, the configuration of FIG. 20 has a drawback that the components near the direct current among the desired signal components are also lost by providing the capacitors 12 and 13. Therefore, there are disadvantages such as an increase in the error rate of the received signal and a restriction on the RF signal modulation method that can be handled.

As a third method for solving the problem of DC offset, it is known to detect the DC offset and feed it back in an analog manner. In this method, for example, a DC component is detected from the outputs of the mixers 2 and 3 in FIG.
Prevent the offset component from propagating. However, in such a configuration, a kind of feedback loop needs to be configured, which may cause a problem in stability. Further, if the response speed of the feedback loop for eliminating the DC offset component is increased, even the low frequency component of the desired signal component may be eliminated. Further, there are cases where high accuracy is required for the components that form the feedback loop.

Further, in the radio apparatus having the above-mentioned receiving apparatus, DC offset may occur when a local signal wraps around the antenna. In this case, the amount of DC offset generated by a change in the surrounding environment of the antenna, such as a vehicle passing near the antenna, may change with time. Further, the DC offset amount may change with time due to temperature changes of the wireless device. In such a case, the feedback loop that cancels out the DC offset component may not be able to follow up completely and may not function sufficiently.

[0014]

As described above, the conventional technique has a problem that an unnecessary DC component called DC offset is generated in the process of signal processing. In addition, when trying to eliminate the influence of unnecessary DC components, the performance of the device is deteriorated, the cost and power consumption of the device increase,
In some cases, there is a problem that it may not function sufficiently.

The present invention has been made in view of such a situation, and can provide a signal processing apparatus capable of solving the problem caused by an unnecessary DC component generated in the process of signal processing. To do so.

[0016]

A signal processing apparatus according to claim 1 is a signal processing apparatus for extracting a desired signal component from an input signal containing a desired signal component and an unnecessary DC component, The input is branched into two paths, and the first path is provided with an element that blocks direct current and an AD converter.
An AD converter is provided in the second path, and A of the first path
The output of the D converter and the output of the AD converter of the second path are given to the digital signal processing unit, and each output is subjected to digital signal processing by the digital signal processing unit. Further, a low-pass filter may be provided between the branch points of the first path and the second path and the AD converter of the second path. A low-pass filter is provided between the branch points of the first and second paths and the AD converter of the first path, and the low-pass filter is provided between the branch point and the AD converter of the second path. Is provided and the cutoff frequency of the low-pass filter of the first path can be set higher than the cut-off frequency of the low-pass filter of the second path. Further, a low-pass filter is provided before the branch point of the first path and the second path, a low-pass filter is provided between the branch point and the AD converter of the second path, and a low-pass filter before the branch point is provided. The cutoff frequency of the filter may be set higher than the cutoff frequency of the low pass filter of the second path. A high-pass filter is provided between the branch points of the first and second paths and the AD converter of the first path, and a low-pass filter is provided between the branch points and the AD converter of the second path. Can be provided. Further, a bandpass filter is provided between the branch points of the first path and the second path and the AD converter of the first path, and a low-pass filter is provided between the branch point and the AD converter of the second path. A filter may be provided such that the low pass cutoff frequency of the bandpass filter of the first path is higher than the cutoff frequency of the lowpass filter of the second path.
Further, a high-pass filter having a function of an element that blocks direct current may be provided instead of the element that blocks direct current in the first path. Further, it is possible to provide a bandpass filter having the function of an element that blocks direct current instead of the element that blocks direct current in the first path. Further, an amplifier may be provided at at least one place on the first and / or the second path. Further, the gain of the analog part of the first path can be made higher than the gain of the analog part of the second path. Further, the resolution of the AD converter of the first path can be made smaller than the resolution of the AD converter of the second path. Further, the sampling frequency of the AD converter of the first path can be set to be higher than the sampling frequency of the AD converter of the second path. The output of the AD converter of the first path is high-pass filtered in the digital domain, the data of the AD converter of the second path is low-pass processed in the digital domain, and the high-pass cutoff frequency of the first path and the The low-pass cutoff frequency of the second path is made equal, and the difference between the gain of the analog part of the first path and the gain of the analog part of the second path is compensated in the digital domain. After the gain of the analog part of the path and the difference in delay time of the analog part of the second path are compensated, the digital signal of the first path and the digital signal of the second path are added. You can Further, the DC component contained in the output of the AD converter in the second path can be detected by digital processing. Further, the detected DC component contained in the output of the AD converter of the second path can be subtracted from the output of the AD converter of the second path. Further, it is possible to refer to the output intensity of the AD converter and adjust the gains of the analog portions of the first path and the second path. Further, the DC component included in the output of the AD converter of the second path is converted into an analog amount and fed back to the analog portion of the second path, and the DC component of the DC component included in the signal of the second path is analogized. Some or all can be compensated. A signal processing device according to claim 18 is provided with a mixer that down-converts an input RF signal or IF signal into a baseband on the input side of the signal processing device according to any one of claims 1 to 17. The digital signal processing for extracting a desired signal component from the output of the AD converter of the signal processing device is performed. Claim 19
The signal processing device according to claim 1, wherein the signal is branched into a plurality of paths immediately after the input side of the signal processing device according to any one of claims 1 to 17, and the signal is branched into each of the branched paths. A signal processing device is provided, and a desired signal is extracted from the entire output of the AD converter obtained from each signal processing device. Further, the frequencies of the local signals input to the mixers respectively provided in the plurality of signal paths branched immediately after the input side are made equal to each other, and there is a difference in the phase of the local signals. Can be Further, the phase shifter may be provided in the preceding stage of the mixer provided in a part or all of the plurality of signal paths branched immediately after the input side. The signal processing device according to claim 22 is a signal processing device which receives an RF signal or an IF signal as an input, and the signal is branched into two paths immediately after the input side, and the signal is branched into each of the branched paths. The signal processing device described in 18 is provided, and a desired signal is extracted from the entire output of the AD converter obtained from each signal processing device. Further, the frequencies of the local signals input to the two mixers respectively provided in the two signal paths branched immediately after the input side are made equal to each other, and the phases thereof are made different from each other. You can Further, the phase difference between the local signals input to the two mixers respectively provided in the two signal paths branched immediately after the input side can be set to 90 degrees. Moreover, it is branched immediately after the input side 2
A phase shifter may be provided before the input to one or both of the two signal paths. Further, a phase shifter is provided in one or both of the two signal paths branched immediately after the input side, and the phase difference between the RF signal or the IF signal input to the mixer of each path is 90 degrees. You can Further, the frequency of the local signal can be made equal to the carrier frequency of the desired RF signal or the desired IF signal input to the mixer. Further, the frequency of the local signal is equal to or higher than the lower limit frequency of the band of the RF signal or IF signal input to the mixer, and is equal to or lower than the upper limit frequency of the band of the desired RF signal component or the desired IF signal component input to the mixer. Can be done. Further, a harmonic mixer can be used as the mixer. Also,
A value obtained by doubling the frequency of the local signal can be made equal to the carrier frequency of the RF signal or IF signal input to the mixer. Further, a value obtained by doubling the frequency of the local signal is equal to or higher than the lower limit frequency of the band of the desired RF signal component or the desired IF signal component input to the mixer, and the desired RF signal component input to the mixer or It can be set to be equal to or lower than the upper limit frequency of the band of the desired IF signal component. In the signal processing device according to the present invention, when the desired signal component is extracted from the input signal including the unnecessary DC component in the desired signal component,
The input signal is split into two paths, and the first
An element for cutting off direct current and an AD converter are provided in the path of 1, and an AD converter is provided in the second path, and the output of the AD converter of the first path and the output of the AD converter of the second path And are given to the digital signal processing unit so that the digital signal processing unit performs digital signal processing on each output.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In addition, in the figures described below, FIG.
The parts common to those in FIG. 20 are designated by the same reference numerals.

FIG. 1 is a block diagram for explaining the principle of the signal processing device of the present invention, and FIGS. 2 to 5 are diagrams for explaining the operation of the signal processing device of FIG.

In the signal processing device of FIG. 1, the RF signal (or IF signal) input to the input terminal 1 is branched into two paths and input to the mixers 2 and 3. Local signal terminal 4,
A local signal having a phase difference of 90 degrees is input to 5. The outputs of mixers 2 and 3 pass through amplifiers 6 and 7,
Each is divided into two systems. In one path, capacitors 12, 13, amplifiers 14, 15, low-pass filters 16, 17, amplifiers 18, 19, AD converter 20,
21 is connected. On the other path connected to the outputs of the mixers 2 and 3, the low-pass filters 8 and 9 and the AD converter 1 are provided.
0 and 11 are connected. Then, the AD converter 10,
The outputs of 11, 20, and 21 are the digital signal processing unit 22.
It is connected to the.

Next, the operation of the signal processing apparatus having such a configuration will be described. First, R input to the input terminal 1
The F signal is branched into two paths and input to the mixers 2 and 3. A local signal having a phase difference of 90 degrees is input to the local signal terminals 4 and 5, and the frequency of the local signal is equal to the carrier frequency of the desired RF signal. As a result, the desired signals down-converted to the base band are obtained as the outputs of the mixers 2 and 3. The outputs of the mixers 2 and 3 at this time are as shown in FIG. In FIG. 2, reference numeral 24 is a desired signal component,
Reference numeral 27 is an unnecessary signal component adjacent to the desired signal component,
Reference numeral 29 is a DC offset. Further, in FIG. 1, the outputs of the mixers 2 and 3 pass through amplifiers 6 and 7,
Each is divided into two systems.

Since capacitors 12 and 13, amplifiers 14 and 15, low-pass filters 16 and 17, amplifiers 18 and 19 and AD converters 20 and 21 are connected to one of the paths, first, the capacitors 12 and 13 are used to A DC component including the DC offset 29 of 2 is blocked as shown in FIG. Next, the unnecessary signal components 27 of FIG. 2 are blocked by the low-pass filters 16 and 17. Finally, the AD converters 20 and 21 convert the desired signal component 30 into digital data.

The signals input to the AD converters 20 and 21 are shown in FIG. The frequency f2 is the capacitor 12,
13 is the high pass cutoff frequency. Among the desired signal components, the components near the direct current with a frequency of f2 or less are missing. The gains of the paths from the outputs of the mixers 2 and 3 to the AD converters 20 and 21 are such that the intensity of the signal finally input to the AD converters 20 and 21 does not saturate the AD converters 20 and 21. It is taken large enough.

Since the AD converters 20 and 21 handle the signals of FIG. 4, the sampling rate must be at least fBW or higher. Also, the resolution of AD conversion is the AD converters 20 and 2
Since the input signal to 1 is amplified so as to be sufficiently large, the resolution is set to the same level as that required for a normal heterodyne receiver or the like. By the way, the resolution in the example of FIG. 1 is 8 bits.

In the other path connected to the outputs of the mixers 2 and 3, first, high-frequency components of the signal are cut off by the low-pass filters 8 and 9. Assuming that the cutoff frequency is f3, the cutoff frequency f3 is sufficiently lower than the cutoff frequency of the low-pass filters 16 and 17 connected to one of the paths of the mixers 2 and 3 and the capacitor connected to one of the paths of the mixers 2 and 3. It is set to be higher than the high-pass cutoff frequency f2 by 12 and 13.

Finally, the AD converters 10 and 11 convert the data into digital data. Here, the AD converters 10 and 11
FIG. 5 shows the RF signal input to the. AD converter 10,
The DC offset voltage 29 and the low-frequency component 31 of the desired signal component are input to 11. Mixers 2 and 3
The gain of the path from the output of to the AD converters 10 and 11 is
The DC offset voltage is set in a range that does not saturate the AD converters 10 and 11.

The resolution of the AD converters 10 and 11 is
Since it is necessary to handle the signal component 31 buried in the DC offset voltage 29, the resolution is set higher than the resolution of the AD converters 20 and 21. In the example of FIG. 1, the AD converter 1
The resolution of 0 and 11 is 16 bits. On the other hand, AD
The sampling rates of the converters 10 and 11 are set lower than the sampling rates of the AD converters 20 and 21 because the upper limit of the frequency of the input signal is as low as the cutoff frequency f3.

Then, the AD converters 10, 11, 20, 2
The digital data output from 1 is input to the digital signal processing unit 22. Here, among the desired signal components, components with a frequency of f2 or higher are digital data output from the AD converters 20 and 21, and components with a frequency of f3 or lower are A.
Since the frequency f3 is included in the digital data output from the D converters 10 and 11 and the frequency f3 is selected to be equal to or higher than the frequency f2, the digital signal processing unit 22 performs an appropriate digital data processing to obtain a desired signal. All of the ingredients are obtained.

In the signal processing device having such a configuration, the gain of the path from the outputs of the mixers 2 and 3 to the AD converters 20 and 21 is the strength of the signal finally input to the AD converters 20 and 21. The AD converters 20 and 21 are sufficiently large in a range that does not saturate, and the gain of the path from the outputs of the mixers 2 and 3 to the AD converters 10 and 11 is the DC offset voltage. Is taken within a range that does not saturate, so that the problem of saturation of components after mixers 2 and 3 is solved.

Further, the AD converters 20 and 21 need only have the same resolution and sampling frequency as those used in the ordinary heterodyne system, and the AD converters 10 and 11 require high resolution, but are required. The required sampling frequency is low. Therefore, the increase in power consumption, which is a problem in the first method for solving the problem caused by the conventional DC offset, and the tolerance of the semiconductor process for manufacturing the AD converter are reduced, and the yield is deteriorated. Or, the cost will increase due to the need for a highly uniform manufacturing process, or the cost will increase due to the need for a high performance manufacturing process, or a higher power supply voltage will be required than the other blocks that make up the device However, the disadvantages such as complication are eliminated.

Further, since the required sampling frequency is low in the AD converters 10 and 11, the AD converters 10 and 11 are used as a successive approximation type AD converter or a sigma-delta type AD converter. Moreover, it can be used as an AD converter that consumes less power and can increase the number of bits relatively easily and can operate at low voltage.

Further, by dividing the outputs of the mixers 2 and 3 into two paths, respectively, among the desired signal components which are problematic in the second method for solving the problem caused by the conventional DC offset, The problem that the component near DC of is also lost is solved.

Further, the outputs of the mixers 2 and 3 are divided into two paths, respectively, and the outputs of the AD converters 20 and 21 and the AD converters 10 and 11 are given to the digital signal processing section 22, thereby making A point of stability, which is a problem in the third method for solving the problem caused by the DC offset, is that if the response speed of the feedback loop for canceling the DC offset component is increased, the low frequency component of the desired signal component is also eliminated. It is also solved that it is erased, and that it cannot be dealt with when the generated DC offset amount changes with time.

(First Embodiment) FIG. 6 is a block diagram showing a first embodiment of the signal processing apparatus according to the present invention. In the drawings described below, the same parts as those in FIG. 1 are designated by the same reference numerals.

In the signal processing device of FIG. 6, the RF signal (or IF signal) input to the input terminal 1 is branched into two paths and input to the mixers 2 and 3. Local signal terminal 4,
A local signal having a phase difference of 90 degrees is input to 5. The outputs of mixers 2 and 3 pass through amplifiers 6 and 7,
Each is divided into two systems. In one path, capacitors 12, 13, amplifiers 14, 15, low-pass filters 16, 17, amplifiers 18, 19, AD converter 20,
21 is connected. In the other path connected to the outputs of the mixers 2 and 3, the low pass filters 8 and 9, the amplifier 52,
53 and the AD converters 10 and 11 are connected. The outputs of the AD converters 10, 11, 20, 21 are connected to the digital signal processing unit 22.

Next, the operation of the signal processing device having such a configuration will be described. First, R input to the input terminal 1
The F signal (or IF signal) is branched into two paths and input to the mixers 2 and 3. To the mixers 2 and 3, local signals having a phase difference of 90 degrees from the local signal terminals 4 and 5 are input. The frequency of the local signal is made equal to the carrier frequency of the desired RF signal. As a result, the desired signals down-converted to the base band are obtained as the outputs of the mixers 2 and 3. The outputs of the mixers 2 and 3 are branched into two systems after passing through amplifiers 6 and 7.

On one path, capacitors 12, 13,
Since the amplifiers 14 and 15, the low-pass filters 16 and 17, the amplifiers 18 and 19, and the AD converters 20 and 21 are connected, first, the capacitors 12 and 13 remove components near the direct current including the DC offset. Next, the low-pass filters 16 and 17 remove unnecessary high-frequency components. The gain of the path from the outputs of the mixers 2 and 3 to the AD converters 20 and 21 is set to be sufficiently large within a range in which each component forming this path is not saturated. The AD converters 20 and 21 have the same resolution and sampling frequency as those required for a normal heterodyne receiver or the like.

The cut-off frequencies of the low-pass filters 8 and 9 on the other path connected to the outputs of the mixers 2 and 3 are sufficiently lower than the cut-off frequencies of the low-pass filters 16 and 17 and higher than the high-pass cut-off frequencies of the capacitors 12 and 13. Has been. AD converters 10, 1 from outputs of mixers 2, 3
The gain of the path leading to 1 is set in a range in which the components forming this path are not saturated by the DC offset voltage.

The sampling frequencies of the AD converters 10 and 11 are set to be low in accordance with the cutoff frequencies of the low pass filters 8 and 9. That is, the AD converter 20,
It is lower than the sampling frequency of 21. On the other hand, the number of bits, which is the resolution of the AD converters 10 and 11, is D
It is set high enough to convert the desired signal component buried in the C offset voltage into digital data.

As a result, the AD converters 10, 11 and 12 are
The digital data output from 0 and 21 are input to the digital signal processing unit 22, and a desired signal component is obtained by digital data processing.

As described above, in this embodiment, the gain of the path from the outputs of the mixers 2 and 3 to the AD converters 20 and 21 is the strength of the signal finally input to the AD converters 20 and 21. The gain of the path from the outputs of the mixers 2 and 3 to the AD converters 10 and 11 is set to be sufficiently large within a range that does not saturate the AD converters 20 and 21, and the DC offset voltage is the AD converter 10, Since 11 is set in a range that does not saturate, the above-described effects can be obtained.

Further, the AD converters 20 and 21 need only have the same resolution and sampling frequency as those used in the normal heterodyne system, and the AD converters 10 and 11 need high resolution, but are required. Since the sampling frequency required is low, the above-described effects can be obtained.

Further, the outputs of the mixers 2 and 3 are divided into two paths, respectively, and the outputs of the AD converters 20 and 21 and the AD converters 10 and 11 are given to the digital signal processing section 22, so that the above-mentioned operation is performed. The effect is obtained.

The low-pass filters 16 and 17 may be high-pass filters. Also, the mixer 2,
A phase shifter may be provided at least before the third stage. The mixers 2 and 3 may be harmonic mixers. Further, the value obtained by doubling the frequency of the local signal is the RF signal (or IF
Signal) carrier frequency. Further, the value obtained by doubling the frequency of the local signal is equal to or higher than the lower limit frequency of the band of the desired RF signal component (or the desired IF signal component) input to the mixers 2 and 3, and is input to the mixers 2 and 3. It may be set to be equal to or lower than the upper limit frequency of the band of the desired RF signal component (or the desired IF signal component).

(Second Embodiment) FIG. 7 is a block diagram showing a second embodiment of the signal processing apparatus of the present invention. The overall configuration of the signal processing device of FIG. 7 is almost the same as that of FIG. 6, but in FIG. 7, the low-pass filters 32 and 33 for the DC component are arranged immediately after the amplifiers 6 and 7. Is different from.

In such a configuration, the low pass filter 3
Removal of unnecessary high frequency components by 2, 33 is performed by the AD converter 1
Since the processing is performed before branching the path to 0 and 11 and the path to the AD converters 20 and 21, the same operational effect as that of the first embodiment shown in FIG. 6 can be obtained.

(Third Embodiment) FIG. 8 is a block diagram showing a third embodiment of the signal processing apparatus according to the present invention. The overall configuration of the signal processing device of FIG. 8 is almost the same as that of FIG. 6, but in FIG. 6, the components near the direct current including the DC offset are removed by the capacitors 12 and 13, and the unnecessary high frequency component is removed by the low pass filter 16, 17, the bandpass filters 34 and 35 remove the components near the direct current and the unnecessary high-frequency components at the same time.

With such a configuration, the cut-off frequency on the low frequency side of the band-pass filters 34 and 35 is made lower than the cut-off frequency of the low-pass filters 8 and 9, thereby making it possible to realize the first embodiment shown in FIG. Similar effects can be obtained.

(Fourth Embodiment) FIG. 9 is a block diagram showing a fourth embodiment of the signal processing apparatus of the present invention. In FIG. 9, the configuration of FIG. 6 is halved. That is, the number of all the components other than the digital processing unit 22 is reduced to half, such that only one mixer 2 is connected to the input terminal 1.

In such a configuration, all the information of the desired signal can be taken out by down-converting with one mixer 2 for a modulation method in which information is placed only on the amplitude such as AM modulated wave. Further, it is apparent that the same effect as that of the first embodiment shown in FIG. 6 can be obtained for the problem caused by the DC offset.

(Fifth Embodiment) FIG. 10 is a block diagram showing a fifth embodiment of the signal processing apparatus according to the present invention. In FIG. 10, the mixer 2 is removed from the structure of FIG. 9. In the present embodiment, it is assumed that components before the mixer 2 in FIG. 9 are externally attached to the signal processing device. That is, the sum of the DC offset voltage and the desired signal component down-converted to the base band is input to the input terminal 1.

Further, in this embodiment, since the configuration after the mixer 2 in FIG. 9 is the same as that in FIG. 9, DC
With respect to the problem caused by the offset, it is obvious that the same operational effect as that of the first embodiment shown in FIG. 6 can be obtained. The present embodiment is suitable for applications in which an unnecessary DC component and a desired baseband signal component are simultaneously input.

(Sixth Embodiment) FIG. 11 is a block diagram showing a sixth embodiment of the present invention. here,
The concrete structure of the digital signal processing part 22 of FIG. 1 is shown. The signal processing unit 22 has input terminals 36 and 37. The output of the AD converter 20 is connected to the input terminal 36, and the output of the AD converter 10 is connected to the input terminal 37. Alternatively, the output of the AD converter 21 is connected to the input terminal 36, and the output of the AD converter 11 is connected to the input terminal 37.

A high-pass filter 38 in the digital domain is connected to the input terminal 36. The cutoff frequency of the high-pass filter 38 is the AD converter 20 (or 21).
It is set to a frequency lower than the low-pass cutoff frequency by the analog DC cutoff element in the preceding stage, and the AD converter 10 (or 1
It is set to be equal to or lower than the cutoff frequency of the analog low-pass filter in the preceding stage from 1). A low-pass filter 39 in the digital domain is connected to the input terminal 37. The cutoff frequency of the low-pass filter 39 is equal to that of the high-pass filter 38.
Is equal to the cutoff frequency of. High pass filter 3
8 and the output of the low-pass filter 39 are input to the signal processing blocks 40 and 41, respectively. In the signal processing blocks 40 and 41, the analog signal path provided with the AD converter 20 (or 21) and the AD converter 10 (or 1) are used.
The difference in gain and the difference in phase rotation of the analog signal path provided with 1) are compensated. Signal processing block 4
The outputs of 0 and 41 are added by the adder 42 and output terminal 4
It is output from 3.

In such a configuration, the desired signal component lacking the DC component contained in the output of the AD converter 20 (or 21) and the AD converter 10 (or 1) are removed.
By adding the desired signal component near DC included in the output of 1) to one, the desired signal component can be restored without omission. The data output from the output terminal 43 also includes a DC offset component. In order to finally extract only the desired signal component, it is necessary to remove this DC offset component. However, a digital signal processing device having such a function has already been put into practical use in the prior art and has already been used in products. Therefore, the DC realized by the present embodiment
If the sum of the offset component and the desired signal component is obtained, the signal processing thereafter can be handled by the conventional technique. It should be noted that the digital signal processing unit 22 in the present embodiment and the digital signal processing unit 22 having the function of removing the DC offset component according to the conventional technique may be combined to form a digital signal unit.

(Seventh Embodiment) FIG. 12 is a block diagram showing a seventh embodiment of the signal processing apparatus according to the present invention. In FIG. 12, a low-pass filter 39, which is a digital filter following the input terminal 37 of FIG. 11, serves as a band-pass filter 44 in the digital area. The lowpass cutoff frequency of the bandpass filter 44 is chosen to be the same as that of the highpass filter 38 in the digital domain.
The high pass cutoff frequency and the cutoff slope of the bandpass filter 44 are selected so that the DC offset component can be cut off sufficiently and the loss of the desired signal component is minimized.

The outputs of the high pass filter 38 and the band pass filter 44 are AD processed by the signal processing blocks 40 and 41.
After the difference in gain and the difference in phase rotation between the analog signal path provided with the converter 20 (or 21) and the analog signal path provided with the AD converter 10 (or 11) are compensated, the adder 42 is used. They are added and output from the output terminal 43.

In such a configuration, the desired signal component lacking the DC component contained in the output of the AD converter 20 (or 21) and the AD converter 10 (or 1) are removed.
The desired signal component near DC included in the output of 1) is added together. At this time, the bandpass filter 4
Due to the high-pass effect of No. 4, the component near the direct current of the desired signal component is lost. However, a filter in the digital domain can easily realize an extremely low cutoff frequency and an extremely steep cutoff slope, which are difficult to realize in terms of power consumption and accuracy with an analog filter. Therefore, the influence of the lack of signal components near DC can be reduced to a negligible level. In addition, the output terminal 43 in the present embodiment
The data output from does not include a DC offset component. This is because only the desired signal component is extracted.

(Eighth Embodiment) FIG. 13 is a block diagram showing an eighth embodiment of the signal processing apparatus of the present invention. In FIG. 13, the configuration is almost the same as that of FIG. 11, but a signal processing unit including components 45, 46 and 47 is inserted between the input terminal 37 and the low-pass filter 39 in the digital domain. It is different. Component 4
In 5, the DC signal component contained in the digital data from the input terminal 37 is extracted. Specifically, the Hanning window function is applied to all the input data included in a certain time period from the latest input data to the past, and the average value is calculated.

Many methods are already known as methods for extracting the DC signal component, and methods other than taking the moving average value using the Hanning window function described in the present embodiment may be used. In the adder 46, the DC component obtained by the component 45 is subtracted from the data from the input terminal 37. Therefore, the output of the adder 46 has the input terminal 37
A signal from which the DC signal component is removed appears from the data. In general, since the DC offset component is often larger than the desired signal component, the dynamic range of the data that can be output by the adder 46 is larger than the dynamic range of the signal component. That is, the output of the adder 46 includes a redundant component.

The component 47 removes the redundant component and compresses the amount of data. As a result, the data length handled by the low-pass filter 39, the constituent element 41, and the adder 42 in the subsequent digital region is shortened, so that the circuit scale can be reduced. The subsequent processing is the same as that of the sixth embodiment in FIG.

In such a configuration, the desired signal component lacking the DC component contained in the output of the AD converter 20 (or 21) and the AD converter 10 (or 1) are removed.
Data obtained by combining the desired signal component near DC included in the output of 1) is output from the output terminal 43. Further, in the present embodiment, since the data output from the output terminal 43 does not include the DC offset component, it is possible to extract only the desired signal component.

(Ninth Embodiment) FIG. 14 is a block diagram showing a signal processor according to a ninth embodiment of the present invention. 14 is almost the same as the configuration of FIG.
The difference is that the high-pass filter 38 in the digital domain 1 and the low-pass filter 39 in the digital domain are omitted.

In such a configuration, the low-pass cutoff frequency by the analog DC cutoff element in the preceding stage of the AD converter 20 (or 21) and the AD converter 10 (or 11).
It is possible to make the cutoff frequency of the analog low-pass filter in the preceding stage substantially coincide with each other and select each cutoff slope to an appropriate value. As a result, the structure is simpler than that of the sixth embodiment shown in FIG. 11, and the same effects as those of the sixth embodiment shown in FIG. 11 are obtained.

(Tenth Embodiment) FIG. 15 is a block diagram showing a tenth embodiment of the signal processing device of the present invention. 15 is almost the same as the configuration of FIG. 6 except that the amplifiers 48, 49, 50 and 51 have variable gains and the signal processing unit 22 can control the gains. In the signal processing unit 22, the AD converters 10, 1
The outputs of 1, 20, and 21 are monitored, and AD converters 10 and 1
The amplifier 4 is connected so that the analog signal paths connected in front of 1, 20, 21 are not saturated and the analog signal strength input to the AD converters 10, 11, 20, 21 is sufficiently large.
Gains of 8,49,50,51 are controlled. It is clear that this configuration can also obtain the same operational effect as the embodiment of FIG.

[0065]

As described above, according to the signal processing apparatus of the present invention, when the desired signal component is extracted from the input signal including the unnecessary DC component in the desired signal component, the input of the input signal is divided into two paths. Along with branching, an element for blocking direct current and an AD converter are provided in the first path, and A is provided in the second path.
A D converter is provided, and the output of the AD converter of the first path and the output of the AD converter of the second path are given to the digital signal processing unit, and the digital signal processing unit performs digital signal processing on each output. Since this is performed, it is possible to solve the problem caused by an unnecessary DC component generated in the process of signal processing.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the principle of a signal processing device of the present invention.

FIG. 2 is a diagram for explaining the operation of the signal processing device of FIG.

FIG. 3 is a diagram for explaining the operation of the signal processing device in FIG.

FIG. 4 is a diagram for explaining the operation of the signal processing device in FIG.

5 is a diagram for explaining the operation of the signal processing device in FIG. 1. FIG.

FIG. 6 is a block diagram for explaining the first embodiment of the signal processing device of the present invention.

FIG. 7 is a block diagram for explaining a second embodiment of the signal processing device of the present invention.

FIG. 8 is a block diagram for explaining a third embodiment of the signal processing device of the present invention.

FIG. 9 is a block diagram for explaining a fourth embodiment of the signal processing device of the present invention.

FIG. 10 is a block diagram for explaining a fifth embodiment of the signal processing device of the present invention.

FIG. 11 is a block diagram for explaining a sixth embodiment of the signal processing device of the present invention.

FIG. 12 is a block diagram for explaining a seventh embodiment of the signal processing device of the invention.

FIG. 13 is a block diagram for explaining an eighth embodiment of the signal processing device of the present invention.

FIG. 14 is a block diagram for explaining a ninth embodiment of the signal processing device of the present invention.

FIG. 15 is a block diagram for explaining a tenth embodiment of the signal processing device of the present invention.

FIG. 16 is a block diagram for explaining an example of a conventional signal processing device.

FIG. 17 is a diagram for explaining the operation of the signal processing device in FIG.

FIG. 18 is a diagram for explaining the operation of the signal processing device in FIG. 16.

FIG. 19 is a diagram for explaining the operation of the signal processing device in FIG.

20 is a block diagram for explaining the operation of the signal processing device in FIG.

[Explanation of symbols]

1 input terminals 2, 3 mixers 4, 5 local signal terminals 6, 7, 14, 15, 18, 19, 48, 49, 50,
51 amplifiers 8, 9, 16, 17, 39 low-pass filters 10, 11, 20, 21 AD converters 12, 13 capacitors 22 digital signal processing units 34, 35, 44 band-pass filters

Claims (31)

[Claims] 1. A signal processing device for extracting a desired signal component from an input signal including a desired signal component and an unnecessary DC component, wherein an input of the input signal is branched into two paths, and a first path is provided. Is provided with an element for cutting off direct current and an AD converter,
An AD converter is provided in the second path, and the output of the AD converter of the first path and the output of the AD converter of the second path are given to the digital signal processing unit, and the respective outputs are provided. The signal processing device is characterized in that the digital signal processing unit performs digital signal processing on the signal processing apparatus. 2. A low-pass filter is provided between a branch point of the first path and the second path and an AD converter of the second path. Signal processing equipment. 3. A low-pass filter is provided between a branch point of the first path and the second path and an AD converter of the first path, and an AD of the branch point and the AD path of the second path.
A low-pass filter is provided between the converter and the cut-off frequency of the low-pass filter of the first path is higher than the cut-off frequency of the low-pass filter of the second path. The signal processing device according to. 4. A low-pass filter is provided in front of a branch point of the first path and the second path, and a low-pass filter is provided between the branch point and an AD converter of the second path. The cut-off frequency of the low-pass filter in the preceding stage of the branch point is higher than the cut-off frequency of the low-pass filter of the second path.
The signal processing device according to. 5. A high-pass filter is provided between the branch points of the first and second paths and the AD converter of the first path, and AD of the branch points and the second path is provided.
The signal processing device according to claim 1, wherein a low-pass filter is provided between the converter and the converter. 6. A bandpass filter is provided between a branch point of the first path and the second path and an AD converter of the first path, and a bandpass filter is provided between the branch point and the second path. A
A low-pass filter is provided between the low-pass filter and the D converter, and a low-pass cut-off frequency of the band-pass filter of the first path is higher than a cut-off frequency of the low-pass filter of the second path. Item 1. The signal processing device according to item 1. 7. The signal processing apparatus according to claim 5, wherein a high-pass filter having a function of the element for cutting off the direct current is provided in place of the element for cutting off the direct current in the first path. . 8. A bandpass filter having a function of the element for blocking the direct current is provided in place of the element for blocking the direct current in the first path.
The signal processing device according to. 9. The signal processing device according to claim 1, wherein an amplifier is provided in at least one location of the first and / or second paths. 10. The signal processing according to claim 1, wherein the analog part of the first path has a gain higher than that of the analog part of the second path. apparatus. 11. The resolution of the AD converter on the first path is set to be smaller than the resolution of the AD converter on the second path. Signal processing equipment. 12. The sampling frequency of the AD converter of the first path is set to be higher than the sampling frequency of the AD converter of the second path. The signal processing device according to. 13. The output of the AD converter of the first path is high-pass filtered in the digital domain,
Data of the AD converter of the first path is low-pass processed in the digital domain, the high-pass cut-off frequency of the first path and the low-pass cut-off frequency of the second path are equalized, and the first path in the digital domain. Of the gain of the analog section of the second path and the gain of the analog section of the second path are compensated, and the gain of the analog section of the first path and the delay time of the analog section of the second path are compensated in the digital domain. 13. The signal processing apparatus according to claim 1, wherein the digital signal of the first path and the digital signal of the second path are added after the difference between the digital signal of the first path and the digital signal of the second path is added. . 14. The signal processing device according to claim 1, wherein the DC component contained in the output of the AD converter in the second path is detected by digital processing. 15. The detected AD of the second path
The signal processing device according to claim 14, wherein the DC component included in the output of the converter is subtracted from the output of the AD converter in the second path. 16. The intensity of the output of the AD converter is referred to, and the gains of the analog parts of the first path and the second path are adjusted.
The signal processing device according to. 17. The DC component contained in the output of the AD converter of the second path is converted into an analog amount and fed back to the analog section of the second path, and the signal of the second path is analogized. 14. A part or all of the DC component contained in is compensated.
6. The signal processing device according to any one of 6. 18. An RF signal or IF input to the input side of the signal processing device according to claim 1.
A signal processing device comprising a mixer for down-converting a signal to a base band and performing digital signal processing for extracting a desired signal component from an output of an AD converter of the signal processing device. 19. The signal processing according to claim 18, wherein the signal is branched into a plurality of paths immediately after the input side of the signal processing device according to claim 1. A signal processing device, wherein a device is provided, and a desired signal is taken out from the entire output of an AD converter obtained from each signal processing device. 20. The frequencies of the local signals input to the mixers respectively provided in the plurality of signal paths branched immediately after the input side are made equal to each other, and a phase difference between the local signals is provided. The signal processing device according to claim 19, wherein the signal processing device is provided. 21. The phase shifter is provided in front of a mixer provided in a part or all of a plurality of signal paths branched immediately after the input side, according to claim 19 or 20. Signal processing equipment. 22. A signal processing device which receives an RF signal or an IF signal as an input, wherein the signal is branched into two paths immediately after the input side, and each of the branched paths is provided.
8. A signal processing device, wherein the signal processing device according to 8 is provided, and a desired signal is taken out from the entire output of the AD converter obtained from each signal processing device. 23. The frequencies of local signals input to the two mixers respectively provided in the two signal paths branched immediately after the input side are made equal to each other, and the phases thereof are different from each other. 23. The signal processing device according to claim 22, wherein: 24. The phase difference between local signals input to two mixers respectively provided in two signal paths branched immediately after the input side is 90 degrees. 23. The signal processing device according to 23. 25. The signal according to claim 22, wherein a phase shifter is provided before one of the two signal paths branched immediately after the input side or before input to both mixers. Processing equipment. 26. A phase shifter is provided in one or both of two signal paths branched immediately after the input side, and the phase difference between the RF signal or the IF signal input to the mixer of each path is 90. 23. The signal processing device according to claim 22, wherein the signal processing device is set in degrees. 27. The frequency of the local signal is set to be equal to a carrier frequency of a desired RF signal or a desired IF signal input to the mixer. Signal processing equipment. 28. The frequency of the local signal is equal to or higher than a lower limit frequency of a band of an RF signal or an IF signal input to the mixer, and a desired R signal input to the mixer.
27. The signal processing device according to claim 18, wherein the frequency is set to be equal to or lower than the upper limit frequency of the band of the F signal component or the desired IF signal component. 29. A harmonic mixer is used as the mixer, according to any one of claims 18 to 23 and 25.
The signal processing device according to any one of 1. 30. A value obtained by doubling the frequency of the local signal is an RF signal or IF input to the mixer.
30. The signal processing device according to claim 29, characterized in that it is made equal to the carrier frequency of the signal. 31. A value obtained by doubling the frequency of the local signal is equal to or higher than a lower limit frequency of a band of a desired RF signal component or a desired IF signal component input to the mixer,
30. The signal processing device according to claim 29, wherein the frequency is set to be equal to or lower than the upper limit frequency of the band of the desired RF signal component or the desired IF signal component input to the mixer.