JP2003152748A - Control/monitor signal transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control/monitor signal transmission system that superimposes first and second control signals and a monitor signal on a clock signal, uses the one for transmission of high-speed data, the other for transmission of low speed data and properly decides the cycle of the transmission. SOLUTION: A first control data signal and a first monitor data signal are updated by each high-speed data refresh time Tio between a master station and a slave station, a second control data signal and a second monitor data signal are updated by each low speed data refresh time Tcr between the master station and the slave station, and the master station and the slave station transmit them on data signal lines mutually. The master station generates a long start signal to decide the Tcr and a short start signal SS to decide the Tio. The first slave station transmits the first control signal and the monitor data signal by each Tio. The second slave station transmits the second control signal and the monitor data signal by each Tcr.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control / monitoring signal transmission system, and more particularly, to a controlled unit side of a device located at a remote position by converting a parallel control signal from the control unit into a serial signal and transmitting the serial signal. Serial / parallel conversion to drive the device, parallel / serial conversion of the monitoring signal of the sensor unit that detects the state of the device, transmission to the control unit side, serial / parallel conversion, and supply to the control unit. The present invention relates to a control / supervisory signal transmission system that superimposes the control signal on a clock signal and further superimposes the supervisory signal on them.

[0002]

2. Description of the Related Art A large number of controlled devices (for example, motors, solenoids, solenoid valves, relays, thyristors, lamps, etc.) located at remote positions by transmitting control signals from control units such as sequence controllers, programmable controllers, computers, etc. It is widely used in automatic control to transmit the monitoring signal from the sensor part (reed switch, micro switch, push button switch etc. ON / OFF state) that controls the drive of the device and detects the state of each device. Used in the technical field.

In such a technique, a plurality of wires such as a power supply line, a control signal line, and a ground line have conventionally been used for connecting the control unit and the controlled unit and the control unit and the sensor unit to each other. Wiring has become difficult to perform in high-density arrangement of devices as the size of controlled devices has decreased in recent years.
There is a problem that the wiring space is reduced and the cost is increased.

As a method for solving this problem,
"Signal serial-parallel conversion method" (Japanese Patent Application No. 62-229978)
No.) and “Serial transmission system for parallel sensor signals”
There are two inventions (Japanese Patent Application No. 62-247245).
According to these methods, one (1 bit) control signal (or sensor signal) corresponding to each clock can be superimposed on the line of the clock signal including the power supply, so that between the control device and the controlled device. The transmission system and the transmission system between the control device and the sensor device can be realized by a line with few wiring.

Further, according to the invention of "control / monitor signal transmission system" (Japanese Patent Application No. 1-140826), an input unit and an output unit are connected to a master station, and a clock signal superposed on a power source is supplied from the master station. By outputting to the common data signal line, bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit could be realized with a simple configuration. That is, it can be configured with a small number of lines, the cost of wiring is low, the connection arrangement of units can be simplified, and addresses can be arbitrarily assigned to each unit. Therefore, addition and deletion of units can be performed. Could be done freely at the required position.

[0006]

According to the above-mentioned conventional configuration, it is possible to realize bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit. However, since the signal from the control unit to the controlled unit (hereinafter, control signal) and the signal from the sensor unit to the control unit (hereinafter, monitoring signal) are output to the common data signal line, they are transmitted at the same time. I couldn't. That is, the control signal and the monitoring signal are
It was possible to transmit only mutually mutually, and it was not possible to simultaneously transmit in both directions. Therefore, it is necessary to separately provide a period for transmitting the control signal and a period for transmitting the monitor signal as the transmission time on the common data signal line.

Further, the control signal and the supervisory signal are, in fact, a transmission signal (hereinafter, high-speed data) to be transmitted in a short cycle (high speed or real time) and a transmission signal (a high-speed data) which is sufficient in a long cycle (low speed). Hereinafter, it is roughly divided into two types, low speed data). The high-speed data includes, for example, a control signal (output signal) to the actuator in the controlled part and an input signal from the input sensor. That is, it is an original input / output signal (I / O data). The low-speed data is, for example, a signal obtained by converting an analog signal (information signal) indicating various control values or measured values in the controlled unit into a digital signal for transmission. That is, information signal (character data)
Is. According to the above-mentioned conventional configuration, bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit can be realized. However, during transmission of high-speed data, low-speed data had to be inserted at a constant rate (see FIG. 2B described later). That is, high-speed data and low-speed data are mixed, and the cycle time of transmission has to be significantly lengthened. In other words, the transmission speed (cycle) of high-speed data to be transmitted in a short cycle was insufficient. In addition, the high-speed data transmission cycle and the low-speed data transmission cycle must be determined separately.

According to the present invention, the first and second control signals and the first and second supervisory signals are superposed on the clock signal, and one is used for high speed data transmission and the other is used for low speed data transmission. It is an object of the present invention to provide a control / monitor signal transmission system in which a transmission cycle is appropriately determined.

[0009]

A control / monitoring signal transmission system according to the present invention comprises a control unit and a plurality of controlled devices each including a controlled unit and a sensor unit for monitoring the controlled unit. The control signal from the control unit is transmitted to the controlled unit and the monitoring signal from the sensor unit is transmitted to the control unit via a data signal line common to the controlled device. In addition, it includes a master station connected to the control unit and the data signal line, and a plurality of slave stations provided corresponding to the plurality of controlled devices and connected to the data signal lines and the corresponding controlled devices. Then, between the master station and the plurality of slave stations, the first control data signal and the first monitoring data signal having a short transmission cycle are updated at high speed data refresh times determined by a plurality of clocks, and mutually updated on the data signal line. The second control data signal and the second supervisory data signal having a long transmission cycle are updated every low-speed data refresh time, which is longer than the high-speed data refresh time, and mutually transmitted on the data signal line. The master station includes a timing generating means for generating a predetermined timing signal synchronized with a clock, a master station output section, a master station input section, and control data signal generating means. The master station output unit converts the first control data signal and the second control data signal input from the control unit into serial pulse voltage signals under the control of the timing signal, and outputs these to the data signal line. The master station input unit, under the control of the timing signal, extracts the value of each data of the first monitoring data signal and the second monitoring data signal superimposed on the serial pulse voltage signal transmitted through the data signal line. Then, these are converted into monitoring signals and input to the control unit. The control data signal generating means generates a long start signal that defines the beginning of the low speed data refresh time and a short start signal that defines the beginning of the high speed data refresh time other than the occurrence of the long start signal. The plurality of slave stations are of two types, a first slave station and a second slave station. Under the control of the timing signal, the first slave station extracts the value of each data of the first control data signal at each high-speed data refresh time, and the data corresponding to the slave station in the value of each data is extracted. Under the control of the slave station output section for supplying the corresponding controlled section and the timing signal,
A slave station that forms a first monitoring data signal according to the value of the corresponding sensor unit for each high-speed data refresh time, and superimposes the first monitoring data signal on the serial pulse voltage signal as the data value of the first monitoring data signal. And an input unit. The second slave station, under the control of the timing signal, extracts the value of each data of the second control data signal at each low speed data refresh time, and extracts the data corresponding to the slave station in the value of each data. Under the control of the slave station output section which supplies the corresponding controlled section and the timing signal, the second monitoring data signal is formed according to the value of the corresponding sensor section for each low-speed data refresh time, and this is generated. As a data value of the second monitoring data signal, a slave station input unit for superimposing the serial pulse voltage signal is provided.

According to the control / monitoring signal transmission system of the present invention, the first and second control signals and the first and second monitoring signals can be superimposed on the clock signal. Therefore, it is possible to realize bidirectional high-speed signal transmission between the control unit, the controlled unit, and the sensor unit, and to output the duplicated control signal and the duplicated monitoring signal to the common data signal line. , And these can be transmitted simultaneously in both directions. That is, the control signal and the supervisory signal can be completely duplicated. Further, one of the duplicated control signal and supervisory signal is used for transmission of high-speed data (first control and supervisory data signal) which should be transmitted in a short cycle, and the other is used for transmission of a low-speed data in a long cycle. Second control and monitoring data signal). Further, by forming the short start signal and the long start signal, it is possible to easily determine the high-speed data transmission period (high-speed data refresh time) and the low-speed data transmission period (low-speed data refresh time) while distinguishing them. Therefore,
It is possible to eliminate the need to insert low-speed data during the transmission of high-speed data, prevent the cycle time of high-speed data transmission from increasing, and transmit high-speed data at a satisfactory transmission speed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1, 5, 6 and 7 are basic configuration diagrams of the present invention, and FIGS. 2 to 4 are signal transmission explanatory diagrams of the present invention.

As shown in FIG. 1, the control / monitor signal transmission system includes a control unit 10 and a plurality of controlled devices 12 each including a controlled unit 16 and a sensor unit 17 for monitoring the controlled unit 16. Become. The control unit 10 includes, for example, a sequence controller, a programmable controller, a computer, and the like. The controlled unit 16 and the sensor unit 17 are referred to as the controlled device 12. The controlled unit 16 includes various components of the controlled device 12, such as an actuator, a (stepping) motor, a solenoid, an electromagnetic valve, a relay, a thyristor, and a lamp. The sensor unit 17 is selected according to the corresponding controlled unit 16, and is composed of, for example, a reed switch, a micro switch, a push button switch, etc., and outputs an on / off state (binary signal).

Here, the plurality of controlled devices 12 are of two types, a first (high speed data) controlled device 12A and a second (low speed data) controlled device 12B. In response thereto, the plurality of slave stations 11 include the first (high speed data) slave station 11A corresponding to the first controlled device 12A and the second (low speed data) corresponding to the second controlled device 12B. Child station 11B
It consists of two types. The control unit 10 is provided with a high speed data input unit 101A and a high speed data output unit 102A corresponding to the high speed data slave station 11A.
A low speed data input unit 101B and a low speed data output unit 102B are provided corresponding to B. In each case, the "high speed" side transmits high speed data to be transmitted in a short cycle (high speed or real time), and the "low speed" side transmits sufficient low speed data in a long cycle (low speed). The circuits to which the codes A and B are added like the slave stations 11A and 11B transmit high speed data and low speed data, respectively. Code A as in slave station 11
In the case of not adding "etc.", both the high-speed data slave station 11A and the low-speed data slave station 11B are referred to. The same applies to the other cases. Further, the slave station power supply unit 20 has no distinction between high speed and low speed.

The control / monitoring signal transmission system includes a control unit 1 through a data signal line common to a plurality of controlled devices 12.
A control signal from the output unit 102 of 0 is transmitted to the controlled unit 16 and a monitoring signal (sensor signal) from the sensor unit 17 is transmitted.
Is transmitted to the input unit 101 of the control unit 10. As shown in FIG. 1, the control signal and the monitoring signal input / output by the control unit 10 are a plurality of bits of parallel signals. on the other hand,
The control signal and the supervisory signal transmitted on the data signal line are serial signals. Master station (main station) 13
Performs the parallel / serial conversion for the control signal and the serial / parallel conversion for the supervisory signal. The data signal line is
It is composed of first and second data signal lines D + and D-. The first data signal line D + has a power supply voltage V
It is used for supplying x, supplying clock signal CK, and simultaneously transmitting bidirectional control signals and supervisory signals. The second data signal line D- is set to the ground level (for signals) common to the master station 13 and the plurality of slave stations 11.

In this example, a power line P is provided for supplying a power supply voltage Vx to each of (slave station power supply section 20 of) a plurality of slave stations 11. The power line P is the first and second power lines P.
₂₄ and P ₀ . First and second power lines P ₂₄ and P
₀ supplies a power supply voltage Vx (= 24V) and a common (power supply) ground level (= 0V) to a plurality of slave stations 11, and is connected to the local power supply 21 at one end (or both ends). . The configuration of the power line P is, for example, Japanese Patent Application No. 1-140.
It may be configured as shown in No. 826.

For such signal transmission, the control / monitoring signal transmission system includes a master station 13 and a plurality of slave stations 11, as shown in FIG. The master station 13 is connected to the control unit 10 and the data signal line. The plurality of slave stations 11 are provided corresponding to the plurality of controlled devices 12, are connected to the data signal lines at arbitrary positions, and are also connected to the corresponding controlled devices 12. Each of the plurality of slave stations 11 includes a slave station output unit 14 and a slave station input unit 15. The slave station output unit 14 and the slave station input unit 15 correspond to the controlled unit 16 and the sensor unit 17, respectively. As shown in FIG. 1, the control signal and the supervisory signal input / output to / from the slave station input unit 15 and the slave station output unit 14 are parallel signals of a plurality of bits. The slave station output unit 14 performs serial / parallel conversion on the control signal, and the slave station input unit 15 performs parallel / serial conversion on the supervisory signal.

As shown in FIG. 5, the master station 13 includes a master station output section 135 and a master station input section 139. Master station output section 1
Reference numeral 35 denotes a serial connection of a first control data signal input from the control unit 10 via the control high speed data unit 134A and a second control data signal input via the control low speed data unit 134B under the control of the timing signal. It is converted into a pulse voltage signal and is output to the data signal line. Master station input section 1
Reference numeral 39 is, under the control of the timing signal, extracting the value of each data of the first monitoring data signal and the second monitoring data signal superimposed on the serial pulse voltage signal transmitted through the data signal line, Is converted into a monitoring signal and input to the control unit 10 via the monitoring high-speed data unit 138A and the monitoring low-speed data unit 138B, respectively.

The master station 13 includes an oscillator (OSC) 131, a timing generating means 132, and a master station address setting means 13.
3, a word address data section 1313 is provided. The timing generating means 132 generates a predetermined timing signal synchronized with the clock CK having a predetermined cycle based on the oscillation output of the oscillator 131. That is, the timing generation means 132 superimposes the power supply voltage V _X on the generated clock CK. To this end, the timing generation means 132 includes a power supply means (not shown) for generating the power supply voltage Vx at a predetermined constant level. For example, when the duty ratio is 50%, the first half of one cycle of the clock CK is the pseudo ground level (0+), and the second half is the level of the power supply voltage V _X. The clock CK including this power supply voltage is output to the terminal 13a in principle, and the first data signal line D
Is supplied to +. On the other hand, the ground level (GND) signal is output from the terminal 13b to the second data signal line D-.

The clock CK including the power supply voltage output from the timing generating means 132 and other various control signals are input to the master station output section 135. The master station output unit 135 includes a control data signal generation unit 136 and a line driver 137. The control high-speed data unit 134A and the control low-speed data unit 134B hold parallel control data signals input from the control unit 10, convert the control data signals into a serial data string, and output the serial data string. The control data signal generation means 136 superimposes the value of each data of the serial data string from the control high speed data section 134A and the control low speed data section 134B on the clock CK including the power supply voltage. The output of the control data signal generating means 136 is output onto the first data signal line D + via the line driver 137 which is an output circuit.

The control data signal generating means 136 (or the timing generating means 132) generates a long start signal LS and a short start signal SS. The long start signal LS is
It is a control signal (control information) that determines the beginning of the low-speed data refresh time and controls the transmission of the second control data signal and the second monitoring data signal. The short start signal SS is a control signal (control information) that determines the beginning of the high-speed data refresh time other than the generation of the long start signal LS and controls the transmission of the first control data signal and the first monitor data signal.

The word address data section 1313 generates word address data based on the long start signal LS and the short start signal SS and inputs it to the control section 10.
That is, word address data W0 to W7 (described later) are generated. The control unit 10 uses word address data W0 to W
7 is used to distinguish the second monitoring data signal. In practice, 3-bit word address data WA0 to WA2 representing "0 to 7" is generated by incrementing by +1 every time 16 clocks are counted,
It is input to the control unit 10. When the count value reaches "128", it is reset.

As shown in FIG. 2A, the master station output unit 13
5 is a low-speed data slave station 11 under the control of the timing signal.
Between the first control data signal and the first monitoring data signal (high-speed data signal I /
O) is updated every high-speed data refresh time Tio determined by a plurality of clocks, and the data is mutually transmitted on the data signal line. In addition, the master station output unit 135 sends the second control data signal and the second monitoring data signal (low speed data signal CR) having a long transmission cycle (4Tio in this example) to the high speed data refresh time under the control of the timing signal. Tio
The data is updated every low-speed data refresh time Tcr, which is a longer period, and mutually transmitted on the data signal line. Tcr is an integer (i) times Tio. In this example, i = 4, but i may be 2, 8, 16, 32, etc.

The high speed data refresh time Tio is
A high-speed data signal I / O (following the preceding short start signal SS or long start signal LS) and a subsequent short start signal SS or long start signal LS (end signal E
You may think that)). That is, Tio is distinguished by defining its head (or end) by the short start signal SS or the long start signal LS. Long start signal LS
Is also longer than the short start signal SS, and therefore also serves as the short start signal SS. Low speed data refresh time Tcr
Is an integer number of high-speed data refresh times Tio (following the preceding long start signal LS) (the last one does not have a short start signal SS) and the following long start signal LS (end signal E). You may think).
That is, Tcr is determined by the beginning (or end) of the Tcr determined by the long start signal LS. No end signal is required to mark the end of each of these periods.

As shown in the clock signal and the start signal in FIG. 3, the high-speed data refresh time Tio is n (32 in this example) following the start signal LS or SS.
Clocks). One for each clock (1
Since the first and second control signals of (bit) and the first and second supervisory signals (four in total) are superimposed, one high-speed data refresh time Tio is a total of 4n-bit data signal (serial signal). ) Can be included.

As shown in the high-speed data signal of FIG. 3, in high-speed data signal I / O transmission, one high-speed data refresh time Tio is n (32 in this case) output data (control data signal) and It includes n-bit input data (monitoring data signal). High-speed data signal I / O
Has an independent meaning as a control signal and a supervisory signal for each one bit thereof. The transmission cycle of the high speed data signal I / O is the high speed data refresh time Tio. That is, if a control signal for a certain slave station 14A is output at the 0th bit (address 0) of the high-speed data refresh time Tio, the control signal for the slave station 14A is always 0 for each high-speed data refresh time Tio. It is output at the bit position.

As shown in the low speed data signal of FIG. 3, in the transmission of the low speed data (or character data) signal CR, one low speed data refresh time Tcr is i.
It includes xn-bit output data (control signal) and i × n-bit input data (monitoring signal). In FIG. 2A, i = 4.

The low-speed data signal CR does not have an independent meaning as a control signal or a supervisory signal for each bit. That is, for example, the 12-bit low-speed data signal (and the added four control signals) CR has meaning only after being converted into one analog signal, and all are extracted in one low-speed data slave station 11B. It is input to the corresponding low speed data controlled device 12B. The reverse is also true.
The transmission cycle of the low speed data signal CR is the low speed data refresh time Tcr. That is, the low-speed data refresh time Tcr of a control signal to a certain slave station 14B is 0.
If it is output to a plurality of bits below the bit-th bit, the control signal to the slave station 14B is always output to the position of a plurality of bits below the 0-th bit of the low-speed data refresh time Tcr.

As described above, the high speed data signal I / O is
It is updated (refreshed) at each high-speed data refresh time Tio, and in one Tio (one refresh time), 32 (32-bit) high-speed control output data and high-speed monitoring input are synchronized with the clock. Data is transmitted in both directions. The low speed data signal CR is
It is updated (refreshed) at each low speed data refresh time Tcr, and W0 to W7 are synchronized with the clock at one Tcr (one cycle time).
8 (hereinafter referred to as 8 words) low speed control output data and low speed monitoring input data are transmitted bidirectionally. One word consists of 16 bits. In this example, the low speed data signal is transmitted in units of two words at one high speed data refresh time Tio.

In one cycle time, data input / output with 32 high-speed data slave stations 11A is repeated four times. One address (bit address) is assigned to the 1-bit high-speed data signal I / O. In this example, the bit addresses are B0 to B31. Therefore, the short start signal SS is generated by counting 32 clocks. Data input / output is performed once with the eight low-speed data slave stations 11B. This corresponds to eight outputs of the AD (or DA) converter with 12-bit resolution (with 4-bit control signal). One address (word address) is assigned to the low-speed data signal CR of one word. In this example, the word addresses are W0 to W7. Therefore, the long start signal LS is 1
It is generated by counting 28 clocks. No clock is transmitted during transmission of the short start signal SS and the long start signal LS (clock CK of FIG. 9).
See the waveform).

Incidentally, conventionally, as shown in the upper part of FIG. 2B, the cycle time Ta could theoretically be shortened when considering the transmission of only the signal I / O. However, in reality, the character data (signal C
Since R) has to be transmitted, the cycle time Tb becomes long as shown in the lower part of FIG. 2B, and as a result, the transmission speed of the signal I / O is reduced.

As shown in FIG. 4, the master station output section 135 is
Under the control of the timing signal, depending on the value of each data of the first control data signal # 1 (high-speed data or signal I / O) input from the control unit 10 to the control high-speed data unit 134A for each cycle of the clock. Then, the duty ratio between the period of the level other than the level of the predetermined power supply voltage and the period of the subsequent level of the power supply voltage Vx is changed (pulse width modulation). Similarly, the master station output unit 135 outputs other than the level of the power supply voltage according to the value of each data of the second control data signal # 2 (low speed data or signal CR) input from the control unit 10 to the control low speed data unit 134B. Is a predetermined level different from the power supply voltage Vx (for example, Vx / 2)
Alternatively, the pseudo ground level is 0+ (voltage modulation). As a result, the first control data signal and the second control data signal are converted into serial pulse voltage signals, and these are output to the data signal line. For example, 0 + = 2V.

For example, when the data value of the first control data signal # 1 is "0", the 3/4 cycle before the clock is set to a predetermined level different from the power supply voltage Vx and the clock after the clock is set. The 1/4 cycle is the level of the power supply voltage Vx.
In the case of "1", the 1/4 cycle before the clock is set to a predetermined level different from the power supply voltage Vx, and the 3/4 cycle after the clock is set to the level of the power supply voltage Vx.
Further, a predetermined level different from the power supply voltage Vx is set to the second level.
When the data value of the control data signal # 2 is “0”, V
The level is set to x / 2, and if it is "1", the pseudo ground level is 0+. Therefore, for example, when the data values of the first control data signal and the second control data signals # 1 and # 2 are “0011” and “1010”, respectively, the result is as shown in FIG. That is, according to the data value of the control data signal,
The clock duty ratio (which was originally 50%) is changed. As a result, the parallel control data signals are converted into serial pulse voltage signals and output to the data signal lines.
The address is assigned every one cycle of the clock CK.

On the other hand, the signal on the first data signal line D + is taken into the master station input section 139. Master station input unit 13
9 is a monitoring high-speed data signal detecting means 1311A, a monitoring high-speed data extracting means 1310A, a monitoring low-speed data signal detecting means 1311B, a monitoring low-speed data extracting means 1310B,
A line receiver 1312 common to high-speed and low-speed circuits is provided. The monitoring signal detection means 1311 is the line receiver 1
The signal on the first data signal line D + is taken in via 312, and the supervisory data signal superimposed on this is detected and output. The monitoring data extraction means 1310 outputs this detection output in synchronization with the clock CK including the power supply voltage from the timing generation means 132 (waveform shaping). The monitoring high-speed data unit 138A and the monitoring low-speed data unit 138B convert a serial data string composed of the detected monitoring data signals into parallel monitoring data signals and output them.

As shown in FIG. 4, the master station input section 139 is
Under the control of the timing signal, the first supervisory data signal # 1 (high-speed data or signal I / O, which is a frequency signal superposed on the serial pulse voltage signal transmitted through the data signal line, is provided every clock cycle. ) Is detected. Similarly, the master station input unit 139 outputs the second monitoring data signal # 2 (low-speed data or signal CR) superimposed on the serial pulse voltage signal transmitted through the data signal line to the monitoring data signal and the power supply voltage Vx. The presence or absence of the current signal Iis caused by the competition with is detected when the level of the power supply voltage Vx rises. As a result, the values of the respective data of the serial first monitoring data signal and the second monitoring data signal are extracted, these are converted into monitoring signals, and the monitoring high-speed data unit 138A and the monitoring low-speed data unit 138B are used to Input to the control unit 10.

For example, when the data value of the first monitor data signal # 1 is "0", the frequency signal is not superimposed and "1" is not superimposed.
In the case of, the frequency signal is superimposed. By identifying these, the value of each data of the first monitoring data signal # 1 is extracted. Further, when the data value of the second monitoring data signal # 2 is "0", a monitoring data signal that does not generate the current signal Iis due to competition with the power supply voltage Vx is superimposed.
Further, in the case of "1", a monitor data signal that causes the current signal Iis due to competition with the power supply voltage Vx is superimposed. By identifying these, the value of each data of the second monitoring data signal # 2 is extracted. Therefore, for example, when the data values of the first monitoring data signal and the second monitoring data signals # 1 and # 2 are “1100” and “0101”, respectively,
It becomes like FIG.

As described above, the control signal to be distributed to the plurality of slave stations 11 is transmitted from the master station 13 as a serial signal (serial pulse voltage signal) on the data signal line. An address counting method is used. That is, the total number of pieces of control data signal data to be transmitted (distributed) to the slave station 11 is predetermined. Therefore,
Addresses are assigned to the data of all control and supervisory data signals, as described above. The slave station 11 extracts the clock CK from the serial pulse-shaped voltage signal, counts the number, and in the case of the address (one or more) assigned to the data of the control data signal to be received by the own station, The data value of the serial pulse voltage signal at that time is taken in as a control signal. The same applies to the monitoring data signal.

A short start signal SS and a long start signal LS are formed to determine the beginning and the end for counting the address. The master station 13 forms the short start signal SS and the long start signal LS and outputs them to the first data signal line D + before the serial pulse voltage signal is output by the timing generation means 132. The short start signal SS and the long start signal LS are at the level of the power supply voltage Vx, and are clocked by the clock C so that they can be distinguished from the control signal.
The signal is longer than one cycle of K. That is, the short start signal SS and the long start signal LS are 2t0 and 5 respectively.
It is set to t0 (t0 is the time of one cycle of the clock). Further, the master station address setting means 133 holds the address assigned to the master station 13. The master station 13 counts the clock CK extracted from the serial pulse voltage signal and extracts an address previously assigned to itself. That is, when the 128 clocks are counted, the long start signal LS is output to the first data signal line D +.

Each of the plurality of slave stations 11 has a slave station output unit 14
And a slave station input unit 15. The slave station output unit 14 extracts the value of each data of the first control data signal or the value of each data of the second control data signal under the control of the timing signal,
The data corresponding to the slave station in the value of each data is supplied to the corresponding controlled unit 12. The slave station input unit 15 forms a first monitoring data signal or a second monitoring data signal according to the value of the corresponding sensor unit 17 under the control of the timing signal, and outputs the first monitoring data signal or the second monitoring data signal. Is superimposed on the serial pulse voltage signal.

As described above, the plurality of slave stations 11 are of two types: the (second) low speed data slave station 11B shown in FIG. 6 and the (first) high speed data slave station 11A shown in FIG. Become.
As can be seen from the comparison between FIG. 6 and FIG. 7, the difference between the two is that the slave station word address setting means 143B and 153B are provided or the slave station bit address setting means 143A and 153A are provided as means for detecting its own address. It is only prepared.

In FIG. 6, the low speed data slave station 11B is
When the own station is designated, the value of each data of the second control data signal is extracted and the value of the data of the second monitoring data signal is superimposed. That is, in the low speed data slave station 11B,
The low-speed data slave station output unit 14B starts counting the clocks extracted from the serial pulse-shaped voltage signal from the reception of the long start signal LS, extracts the address previously assigned to itself, and handles the data of the address. The data is supplied to the low speed controlled device 12B. The count value of the clock is reset by receiving the long start signal LS.
Also, within the period, the low-speed data slave station input unit 15B
Similarly, the address assigned to itself is extracted, and the monitoring signal for the low-speed data controlled device 12B is superimposed on the address of the serial pulse voltage signal. That is, the low-speed data slave station output unit 14B extracts the value of each data of the second control data signal under the control of the timing signal, and associates the data corresponding to the slave station in the value of each data. It is supplied to the low speed data controlled unit 16B. The low-speed data slave station input unit 15B, under the control of the timing signal, according to the value of the corresponding low-speed data sensor unit 17B,
A second monitor data signal is formed, and this is superposed on the serial pulse voltage signal as the data value of the second monitor data signal.

As shown in FIG. 6, the low speed data slave station output unit 14B includes a power supply voltage generating means (CV) 140, a line receiver 141B, and a control low speed data signal extracting means 142.
B, slave station word address setting means 143B, address extracting means 144B, and output low-speed data section 145B.

The power supply voltage generating means 140 of the slave station output section 14 and the power supply voltage generating means (CV) 150 of the slave station input section 15 which will be described later constitute a slave station power supply section 20. The power supply voltage generating means (CV) 140 is a DC (direct current) -DC converter, and electrically connects the low-speed data slave station output unit 14B (and the low-speed data controlled unit 16B of the corresponding low-speed data controlled device 12B) electrically. Power supply voltage Vc for driving
c is generated from the power line. That is, mainly the power line P ₂₄
By smoothing and stabilizing the power supply voltage Vx of (1) by known means, a stabilized power supply voltage Vcc (5V) and an output (12V) to the line receiver 141B are obtained.

Line receiver 141B which is an input circuit
Takes in the signal transmitted on the first data signal line D + and outputs it to the control low speed data signal extraction means 142B. The control low speed data signal extraction means 142B extracts the control data signal from the signal, and the address extraction means 14
4B and the output low speed data section 145B. The slave station word address setting means 143B holds the own station address assigned to the low speed data slave station output unit 14B. The address extracting means 144B extracts an address that matches the own station address held in the slave station word address setting means 143B and outputs it to the output low speed data section 145B. The output low-speed data section 145B is the address extracting means 1
When an address is input from 44B, one or a plurality of data values held at that point in the (serial) signal transmitted on the first data signal line D + are handled as parallel signals. Output to the low speed data controlled unit 16B. That is, the output low-speed data unit 145B performs serial / parallel conversion on the control signal.

As shown in FIG. 4, under the control of the timing signal, the low-speed data slave station output unit 14B is in a period of a level other than the level of the power supply voltage of the serial pulse voltage signal for each cycle of the clock. By identifying whether the level is a predetermined voltage level different from the power supply voltage Vx (for example, Vx / 2) or a pseudo ground level, the value of each data of the second control data signal is extracted, and the value of each data is extracted. The data corresponding to the slave station in the value is supplied to the corresponding low speed data controlled unit 16B.

On the other hand, the low-speed data slave station input unit 15B, as shown in FIG. 6, has a power supply voltage generating means (CV) 150, a line receiver 151B, and a control low-speed data signal extracting means 1.
52B, slave station word address setting means 153B, address extracting means 154B, input low speed data section 155B, monitoring data signal generating means 156B, line driver 157B.
Equipped with.

As can be seen from FIG. 6, the power supply voltage generation means 150 to the address extraction means 154B have substantially the same configuration as the power supply voltage generation means 140 to the address extraction means 144B, and operate in almost the same manner. The power supply voltage generation means 150 electrically drives the circuit that constitutes the slave station input unit 15B and electrically drives the low speed data sensor unit 17B of the corresponding low speed data controlled device 12B.
cc is generated from the power line P ₂₄ .

The input low speed data section 155B holds a monitoring signal composed of one or a plurality of (bit) data values input from the corresponding low speed data sensor section 17B.
The input low-speed data section 155B has the address extracting means 154.
When the address is input from B, the value of one or a plurality of held data is output to the monitoring data signal generation means 156B as a serial signal in a predetermined order. That is,
The input low-speed data unit 155B performs parallel / serial conversion on the monitor signal. Monitoring data signal generating means 156B
Outputs the second monitoring data signal according to the data value of the second monitoring signal. The second monitor data signal output from the monitor data signal generating means 156B is output onto the first data signal line D + by the line driver 157B which is an output circuit. Therefore, the second monitoring data signal is superposed on the value of the data of the control signal output on the first data signal line D + at that time. That is, the second monitoring data signal is superimposed on the position of the data corresponding to the slave station 11B of the serial pulse voltage signal. In other words, the value of the data of the second supervisory signal at the same address is superimposed on the value of the data of the second control signal at the same address.

As shown in FIG. 4, the low speed data slave station input unit 15B has a binary level different from the power supply voltage Vx according to the value of the corresponding low speed data sensor unit 17B under the control of the timing signal. 2 monitoring data signal # 2 is formed, and this is used as the data value of the second monitoring data signal and superposed on a predetermined position of the serial pulse voltage signal. For example, when the data value of the monitoring data signal is “1”,
The monitoring data signal is formed and superposed at a predetermined position in one cycle of the clock CK, and in the case of "0", the monitoring data signal is not formed and is not superposed. Therefore,
For example, when the data value of the monitoring data signal is "0101", as a result of superimposition of the monitoring data signal by the line driver 157B, the output (detection current) of the monitoring low-speed data signal detecting means 1311B is as shown in FIG. Like

On the other hand, in FIG. 7, the high speed data slave station 11
When the own station is designated, A extracts the value of each data of the first control data signal and superimposes the data value of the first monitor data signal. That is, in the high-speed data slave station 11A, the high-speed data slave station output unit 14A starts counting the clocks extracted from the serial pulse-shaped voltage signal from the reception of the short start signal SS, and outputs the address previously assigned to itself. The data of the address is extracted and supplied to the corresponding high-speed data controlled device 12A. The count value of the clock is reset by receiving the short start signal SS. Further, the high-speed data slave station input unit 15A extracts the address assigned to itself in the same manner, and superimposes the monitoring signal for the high-speed data controlled device 12A on the address of the serial pulse voltage signal. That is, the high-speed data slave station output unit 14A extracts the value of each data of the first control data signal under the control of the timing signal, and corresponds the data corresponding to the slave station in the value of each data. The data is supplied to the high speed data controlled unit 16A. The high-speed data slave station input unit 15A forms a first monitor data signal according to the value of the corresponding high-speed data sensor unit 17A under the control of the timing signal, and uses this as the data value of the first monitor data signal. , Superimposed on the serial pulsed voltage signal.

The high-speed data slave station output unit 14A, under the control of the timing signal, supplies a period of a level other than the level of the power supply voltage of the serial pulse voltage signal and the power supply voltage Vx subsequent thereto for each cycle of the clock. By identifying the duty ratio with the level period, the value of each data of the first control data signal is extracted, and the high-speed data controlled unit corresponding to the data corresponding to the slave station in the value of each data is controlled. Supply to 16A.

The high-speed data slave station input unit 15A controls the corresponding high-speed data sensor unit 17A under the control of the timing signal.
A first monitoring data signal # 1 composed of a frequency signal is formed according to the value of, and this is superposed on a predetermined position of the serial pulse voltage signal as a data value of the first monitoring data signal.

Hereinafter, the specific configuration and operation of this example will be described step by step from the output of the control signal from the control unit 10 to the input of the monitoring signal to the control unit 10 with reference to FIGS. .

In FIG. 8 and FIG. 9, in addition to the (first) high speed data control signals OUT0p to OUT31p, the master station 13 (second) low speed data control signals OUT0v to OUT0p.
The UT 31v is superimposed on the clock CK. The master station 13
In addition to the (first) high speed data monitoring signals IN0f to IN31f, the (second) low speed data monitoring signals IN0i to IN
31i is extracted.

First, the master station output unit 135 will be described. 8 and 9, the timing generating means 132
Outputs a start signal ST (and a long start signal LS) and a predetermined number of clocks CK. Start signal ST
Is output (set to a high level) according to the input of a predetermined command (not shown) from the control unit 10, for example. In addition, similarly, by inputting another predetermined command (not shown) from the control unit 10, the timing generation unit 1
32 is stopped. In the start signal ST, the output period of the short start signal SS is set to 2t0, and the output period of the long start signal LS is set to 5t0. t0 is the time of one cycle of the clock CK. The clock CK divides the oscillation output from the oscillator 131 to form a predetermined cycle. The clock CK is output continuously from the start signal ST and thereafter in synchronization with the falling thereof, and is output by a predetermined number (the number of addresses). To this end, the timing generating means 132 comprises first and second counting means (not shown). The counting means uses the start signal S
Counting starts at the rising edge of T. When the count output of the counting means reaches a predetermined value, the output of the clock CK is stopped (as shown by the clock CK in FIG. 9, the low level is maintained). To this end, the timing generating means 132 comprises first and second comparing means (not shown). That is, the first comparing means compares the count output of the first counting means with the address (“128 address”) set in the master station address setting means 133, and when both match, a predetermined period, The long start signal LS is output. The long start signal LS resets the first counting means. The second comparing means compares the count output of the counting means with a predetermined value (in this case, "32 (address)"), and outputs the short start signal SS for a predetermined period when the both match. Second by short start signal SS
Counting means is reset.

For example, assuming that the bit address (that is, the number of data of the above-mentioned control signal) is from 0 to 31, 32
Control signals OUT0p to O which are bit parallel data
The UT 31p is input from the high speed data output unit 102A to the control high speed data unit 134A. Control high-speed data section 13
4A is triggered by the fall of the start signal ST,
Control signals OUT0p to OUT3 in synchronization with the clock CK
1p is shifted and output as the output Dops in this order. The addresses are 0 to 63, 127, 255, ...
・ May be Control signals OUT0p to OUT31p
Is switched (updated) in synchronization with the start signal ST, for example. The master station address setting means 1
As shown in FIG. 8, the address 33 is set to the 128th address by closing the weighted switch by seven digits from the left (the same applies to other cases).

The output Dops is the control signal OUT0p-O.
Depending on the data value of the UT 31p, it is set to a high level (or "1") or a low level (or "0") every clock. As a result, for example, "0011 ..." Is output. The output Dops is input to the control data signal generation means 136. The start signal ST is also input to the control data signal generating means 136. The same applies to the output Dovs.

The timing generating means 132 includes the oscillator 13
By dividing the oscillation output of 1, the clock 4CK having a frequency (4f0) which is four times the frequency f0 of the clock CK is formed. The control data signal generating means 136 counts the clock 4CK by a counter (not shown), and when the value (signal Dops) of the control signals OUT0p to OUT31p is “1”, the first data signal line D + is first Of 1
0V (low level) is output only in the cycle of the four clocks 4CK, and 5V (high level) is output in the cycle of the remaining three clocks 4CK. On the contrary, in the case of “0”, the first 3
0V is output in the cycle of each clock 4CK, and the remaining 1
5V is output only for the period of each clock 4CK. As a result, the control data signal generation means 136 causes the clock CK
Based on the control signals OUT0p to OUT31p (PW
M) Modulate.

One output (PWM-modulated output) of the control data signal generator 136 is binary (+ 5V and 0V).
Signal, and is output to one signal line Pck. The signal output to the signal line Pck is input to the line driver 137 via the comparator COMP1, and the data signal line D
It is output to + (and D-). Line driver 137
Is composed of transistors TR1 to TR3 and the like. The transistors TR1 and TR3 and TR2 are complementarily connected, and can be driven with low impedance. The transistor TR1 is for outputting the voltage Vx, and the transistor TR2 is a pseudo ground level 0+ (2V).
To output voltage Vx
It is for outputting / 2. Transistor TR1
A photocoupler PC, which is the monitoring signal detecting means 1311, is connected to the emitter of the. Comparator COMP1 outputs P
ck is inverted, and the line driver 137 outputs the signal (output Pc
level conversion and inversion of the inverted signal of k). The amplitude of the output of the line driver 137 is limited to 2V to 24V and outputs a signal similar to the signal line Pck. Therefore,
The signal on the first data signal line D + is also binary (level Vx
And 0+) signals. The second data signal line D-
Has a potential of 0 V (ground level 0−). Further, the start signal ST is output as a signal at the level of the power supply potential Vx on the first data signal line D +.

Similarly to the signal Dops for the first control signals OUT0p to OUT31p, the second control signal OUT0 is used.
A signal Dovs for v-OUT31v is formed. The control data signal generator 136 outputs the signal Dovs.
The signals Dvh and Dvl are formed based on (and Pck). That is, if the second control signal is at the low level during the period when the signal Pck is at the low level, the signal Dvh0
(“1” of) is formed, and if the second control signal is at high level, the signal Dvh1 (“1” of) is formed.

Therefore, the signal Pck pulse-width-modulated according to the signal Dops turns on the transistor TR1 for a predetermined period to output the voltage Vx (24 V), and turns off the transistor TR1 during the other period. Transistor T
During the off period of R1, the transistor TR2 or TR3 is turned on. That is, the transistor TR2 is turned on by the high level of the signal Dvh0 formed according to the high level of the signal Dovs, and the pseudo ground level 0+ (2V).
Is output. Further, the high level of the signal Dvh1 formed according to the low level of the signal Dovs turns on the transistor TR3 and outputs the voltage Vx / 2 (12V). This causes the pseudo ground level 0+ and the voltage Vx / according to the high level and the low level of the signal Dovs.
A voltage-modulated signal of 2 is formed.

Output Pc of control data signal generating means 136
k, Dvl and Dvh are comparators COMP1 to COMP
3 is input to the line driver 137. The line driver 137 includes transistors TR1 to TR3 and the like.

Based on the inputs of the outputs Pck, Dvl and Dvh, the line driver 137 causes the transistor TR1 to supply the power source voltage V during the period when the output Pck is at the high level.
While superimposing x, level conversion of the signals (Dvl and Dvh) is performed and this is also superposed. That is, “1 (Vcc = 5V)” of the signal Dvl is converted into a voltage Vx / 2 (12V), and “1 (Vcc = 5V)” of the signal Dvh is converted into a pseudo ground level 0+ (for example, 2V). To do. The voltage Vx / 2 or the pseudo ground level 0+ is superimposed during the period when the signal Pck is low level.

As described above, there are two types of slave stations 11. In the low-speed data slave station 11B, the low-speed data slave station output unit 14B configured as shown in FIG. 10 detects and outputs the voltage-modulated second control data signal # 2 (OUT0v to OUT31v), and the low-speed data slave station configured as shown in FIG. The slave station input unit 15B receives the current-modulated second monitor data signal # 2 (IN0i to I0).
N31i) is transmitted to the master station 13. High-speed data slave station 11
In A, the high-speed data slave station output unit 14 having the configuration of FIG.
A detects the pulse width modulated (or phase modulated) first control data signal # 1 (OUT0p to OUT31p), and the high speed data slave station input unit 15A of the configuration of FIG. 16 uses the frequency modulated first monitoring data signal. # 1 (IN0f to IN31
f) is transmitted to the master station 13.

First, the low speed data slave station output unit 14B will be described. In FIGS. 10 and 11, the signals on the first data signal line D + are mainly the line receiver 141.
Input to B. The line receiver 141B is connected to the data signal line and detects and outputs the state according to the serial pulse voltage signal. Considering the control signals out0 to out31 (serial pulse voltage signals) on which the clock CK is superimposed, the transmission clock extraction circuit 1421B is
A high level signal is output when the signal on the first data signal line D + is 16 V or higher, and a low level signal is output otherwise. This is the signal d0. That is, it is the value of the data of the demodulated control signal. This may be considered to include the phase modulated clock CK. The signals d0 and the like are transferred to the preset addition counter 144B and the shift register 14
It is input to 51B. The waveform of the signal d0 is based on the control signals out0 to out31 as shown in FIG.
The waveform of the WM) modulated clock CK is obtained. Note that C
Since the power supply Vcc is supplied from V, the value of the high level signal of the signal d0 is 5V.

Similarly, the transmission level extraction circuit 1422B which receives the output from the line receiver 141B outputs a low level signal when the signal on the first data signal line D + is 8V or less, and otherwise outputs a high level signal. Output a signal. This is the data value of the control signal before modulation. The inverted signal of this is the signal d1.

Prior to this, the start signal ST is similarly detected as the high level of the signal d0, and is input to the long start signal extraction circuit 1423B including an on-delay timer. The delay is 3t0. That is, the output s
The rising edge of t is delayed by 3t0 and the falling edge is synchronized with the original signal ST. Therefore, the short start signal SS
With respect to the clock CK and the clock CK, since the high level time is short, the output st does not appear. The output st is input to the differentiating circuit ∂, and the differential signal is input to the preset addition counter 144B and the shift register (SR) 1 at the rising edge of the output st.
451B and is used as the reset signal R thereof. The signal d0 (hence, the extracted clock CK) is also input to these. Therefore, the preset addition counter 144B is reset by the long start signal LS.

In the slave station word address setting means 143B, the addresses assigned to the low speed data slave station output unit 14B, for example, addresses 0 to 8 are set. The preset addition counter 144B counts the extracted clock CK at the rising edge after being reset by the rising differential signal of the output st, and outputs while the count value matches the address of the slave station word address setting means 143B. Output dc. That is, the clock CK in the cycle of the previous address is set to the high level in synchronization with the rising edge of the clock CK, and
It goes low in synchronization with the rising edge of. Also, 0
Since the address is set to the high level in synchronization with the rising of the output st, it becomes as shown in FIG. The output dc is input to the shift register 1451B.

Specifically, the slave station word address setting means 143B (same for 153B) is set with 3-bit word address data WA0 to WA2 representing the above-mentioned word address data W0 to W7. Therefore, when the slave station word address setting means 143B is composed of a well-known dip switch, it can be composed of only three, and can be mounted in a small mounting space. Since WA0 to WA2 are "0" in FIG. 10, the word address data W0 is used. Address extracting means 144B according to the configuration of the slave station word address setting means 143B
(The same applies to 154B) is a hexadecimal counter.

The shift register 1451B outputs the extracted clock CK while the output dc is at the high level.
"1 (or high level)" is shifted in synchronization with the rising edge of. That is, “1” is the shift register 1451.
The B unit circuits Sr1 to Sr16 are shifted in this order. Therefore, the output s of the shift register 1451B
r1 to sr16 are, in the cycle of the clock CK,
In synchronization with the rising edge, the high level is sequentially set (until the rising edge of the next cycle). The outputs sr1 to sr16 are
Each is input as a clock to the D-type flip-flop circuits FF1 to FF16.

The flip-flop circuits FF1 to FF16, which are the output low-speed data section 145B, receive the signal d1 (ie,
The data value of the demodulated control signal) is input. Therefore, for example, the flip-flop circuit FF1 outputs the output sr1.
In synchronization with the rising edge of, the value of the signal d1 at that time is fetched and held, and this is output. In this case, a low level is output. Other flip-flop circuits FF2 to FF
Similarly, 16 also captures and holds the value of the signal d1 at that time, and outputs it. This causes the address 0
The value of the control signal data at address # 15 "0011 ..."
Are demodulated as signals out0 to out15, and D / A
Input to the converter DAC. The D / A converter DAC uses predetermined 4 bits of the input 16-bit signal as a control signal, converts predetermined 12 bits into an analog signal (for example, voltage signal), and controls the low-speed data controlled unit. 1
Output to 6B.

Next, the low speed data slave station input unit 15B will be described. 12 and 13, as can be seen from FIG. 6 and comparison with FIG. 10, the power supply voltage generating means 15
The 0 to address extracting means 154B has substantially the same configuration as the power supply voltage generating means 140 to the address extracting means 144B. That is, the output low speed data section 145B is omitted, while the input low speed data section 155B and the line driver 15 are omitted.
7B is added. The assigned address is, for example, the same as the low-speed data slave station output unit 14B (that is, addresses 0 to 15 in this case). Further, the same number of pieces of supervisory signal data as the number of extracted control signal data (16 pieces) are input.

The A / D converter ADC of the input low speed data section 155B converts the analog signal (for example, voltage signal) input from the low speed data sensor section 17B into a 12-bit digital signal with a 4-bit control signal. , Signal in0
~ In15 is output. The input low speed data section 155B is
16 of the same number as the assigned addresses 0 to 15
It is composed of a plurality (two or more) of two-input AND gates and an OR gate which receives these outputs. Each of the 16 AND gates has a shift register 1551B as shown in FIG.
The outputs sr1 to sr16 of are input. Outputs sr1 to s
As described above, r16 is sequentially set to the high level in synchronization with the falling edge of the clock CK (until the falling edge of the next cycle). Therefore, the output sr1
During the high level period of ~ sr16, each of the 16 AND gates is opened, and the monitor signals in0 to in15 are output from the OR gate through the AND gate in this order. The monitoring signals in0 to in15 are the control signals ou of FIG.
Corresponds to t0 to out15.

The output of the OR gate is input to the 2-input NAND gate 1562B. NAND gate 1562B
An output of the inverter INV2, that is, an inverted signal of the signal d0 is input to the. The NAND gate 1562B constitutes the monitor data signal generating means 156B. Monitoring signal in
0 to in15 take values as shown in FIG. 13 during the high level period of the outputs sr1 to sr16, for example. Therefore, while the monitor signals in0 to in15 are being output, the NAND gate 1 is synchronized with the fall of the signal d0.
562B is opened, and the monitoring signals in0 to in15 are output as the output dip.

The output dip is level-converted via the line driver 157B and then converted into the first data signal line D +.
Is output to. That is, the output dip is the photocoupler PC
After being electrically separated from the clock extraction unit by 2, the signal is input to the transistor TRp forming the level conversion circuit and further input to the output transistor TRi. That is, when the photocoupler PC2 is turned on, the transistor T
Rp and TRi are turned on. As a result, a signal proportional to the signal dip is output to the first data signal line D +. The high level of this monitoring signal indicates that the transistor TRi
Becomes high resistance when it is turned off, so the data signal line D
Since the transistor TRi has a low resistance due to the ON state of the transistor TRi, the low level is made to depend on the + signal potential.
It is set to 4V (because the breakdown voltage of the Zener diode ZD2 is 3V).

As can be seen from the above, the supervisory signal is the clock d (extracted) from the low speed data slave station input unit 15B.
In one cycle of 0, it is output (superimposed) on the first data signal line D +. However, the first data signal line D
The voltage value of the + signal is forcibly set to the voltage value of the control signal regardless of the voltage value of the monitoring signal. For this,
The line driver 137 of the master station output unit 135 has a sufficiently large drive capability (current supply capability) that cancels the monitoring signal and allows the first data signal line D + to have the voltage value of the control signal.

The current flowing through the transistor TRi is limited. For this purpose, the transistor TRi
As shown in FIG. 12, the Zener diode ZDi and the resistor R are connected to the base side of the. As a result, the current flowing through the transistor TRi is limited to, for example, 100 mA (milliampere) or less. Therefore, by turning on the transistor TR1 of the master station output unit 135 described above, the potential of the first data signal line D + can be easily pulled up to near Vx = 24V. At the time of this pull-up, since the transistor TRi is ON, a current of about 100 mA also temporarily flows to the emitter of the transistor TR1. The flowing time is, for example, 2 μsec. This is detected as Iis.

Next, the high speed data slave station output unit 14A will be described. 14 and 15, as can be seen from comparison with FIGS. 10 and 11, the high-speed data slave station output unit 1
4A is from the low-speed data slave station output unit 14B of FIG.
The configuration is almost the same as that of the A converter DAC.

The high-speed data slave station output unit 14A shown in FIG.
With the same configuration as the low-speed data slave station output unit 14B in FIG. 10, the signal d0 is obtained, and further the outputs sr1 to sr4 are obtained from the unit circuits Sr1 to Sr4 of the shift register 144B. Here, it is assumed that, for example, addresses 0 to 3 (showing 0 in the figure) are designated as the address of the slave station 11A in the slave station bit address setting means 143A. On the other hand, the signal d1 is the long / short start signal extraction circuit 1423A (14
23B) Phase data signal demodulation circuit 1 having almost the same configuration
It is formed by 424A as shown in FIG. That is, the signal on the first data signal line D + is 3/4 (or 1 /
2) Levels other than the level Vx for the period CK or more (that is, V
When it becomes x / 2 or pseudo ground level), a low level signal is output, and in other cases, a high level signal is output. Therefore, the signal d1 is almost the data value of the control signal before modulation.

The slave station bit address setting means 143
A (the same applies to 153A) includes 5-bit bit address data B0 to B representing the aforementioned 32 bit addresses.
31 is set. In FIG. 14, since all are “0”, they are bit address data B0. Depending on the configuration of the slave station word address setting means 143A, the address extracting means 144A (also for 154A) is a normal counter.

Further, the high level of the signal d0 is a long / short start signal extraction circuit 1423 composed of an on-delay timer.
Input to A. Since the delay is t0, the high level time of the clock CK is short and the output st does not appear. Therefore, the preset addition counter 1
44A is a long start signal LS and a short start signal SS
Is reset by.

The signal d1 (that is, the value of the data of the demodulated control signal) is input to the flip-flop circuits FF1 to FF4 which are the output data section 145A. Therefore, for example, the flip-flop circuit FF1 takes in and holds the value of the signal d1 at that time in synchronization with the rising of the output sr1, and outputs it. In this case, a high level is output. The same applies to the other flip-flop circuits FF2 to FF4. As a result, the data value “0011” of the control signal at the addresses 0 to 3 is changed to the signals out0p to out.
Demodulated as 3p.

Next, the high speed data slave station input unit 15A will be described. 16 and 17, as can be seen from comparison with FIGS. 12 and 13, the high speed data slave station input unit 1
5A is from the low-speed data slave station input unit 15B of FIG.
The configuration is almost the same as that of the D converter ADC. Further, the configuration of the input high speed data section 155A is different from the configuration of the input low speed data section 155B. In addition, the slave station input unit 15
There is no concern about whether the supervisory signals in0 to in3 to be superimposed are the first or second supervisory signals,
There is no need for that.

The high-speed data slave station input unit 15A shown in FIG.
With the same configuration as that of the low-speed data slave station input unit 15B in FIG. 12, a serial signal of the monitor signals in0 to in3 synchronized with the extracted clock CK is obtained as the output of the OR circuit. The output of the OR circuit is the 2-input AND gate circuit 156.
Input to one of 2A. AND gate circuit 1562A
The oscillation output of the oscillator (OSC) 1561 is input to the other. The frequency of this oscillation output is set to 8f0, for example. f0 is the frequency of the clock CK. The frequency of the oscillation output is not limited to 8 times the frequency of the clock CK, but may be a higher frequency, for example 16 times.
The AND gate circuit 1562A and the oscillator 1561 are monitoring data signal generating means 156A which is frequency signal superimposing means.
Make up. The monitoring signals in0 to in3 take the value "1100" as shown in FIG. 17 during the high level period of the outputs sr1 to sr4, for example. Therefore, the AND gate circuit 1562A opens during the period in which the monitoring signals in0 and in1 are output, and the oscillation output 8f0 of the oscillator 1561 is output.
Is output as the output difp. On the other hand, the monitoring signal i
While n2 and in3 are being output, the AND gate circuit 1562A is closed and the oscillation output 8f0 of the oscillator 1561 is not output.

The output difp is output to the line transformer T via the driver (two inverters), and further,
From line transformer T to line driver power MOSF
It is applied as a signal dif to the gate electrode of ET. Since the FET is repeatedly turned on / off in accordance with this signal dif, a signal proportional to the signal dif is output to the first data signal line D +. That is, as shown in FIG. 17, the first supervisory signal is superimposed on the first control signal. The amplitude of the first supervisory signal to be superimposed is the diode connected in series,
It is limited by the resistance value of the FET and the resistor. When the control signal is the pseudo ground level 0+ (2V), the signal has an amplitude within the difference between the true ground level (0V) and the pseudo ground level 0+ (in this case, within 2V). Since the supervisory signal is superimposed on the control signal, it should not be a signal that affects it, and should be distinguishable from it.

Next, the master station input section 139 will be described. Again, in FIGS. 8 and 9, the first and second monitoring data signals output onto the first data signal line D + are
It is input to the line receiver 1312 and its detection signal is output. This detection signal is the monitoring low speed data signal detecting means 1311B and the monitoring high speed data signal detecting means 1311.
Input to A. Up to this point, the data of the supervisory signal corresponding to the address position of the data of the supervisory signal exists at the same address position as the address position of the data of the control signal.

The master station input section 139 is a low speed data monitoring signal detecting means 1311B for detecting the second monitoring data signal.
As a result, a current detection circuit that detects and outputs a current change on the first data signal line D + is provided. That is, as shown in FIG. 8, the photocoupler PC is inserted on the emitter side of the transistor TR1 that constitutes the line driver 137 of the master station output unit 135. The emitter of the transistor TR2 forming the line driver 137 is connected to a predetermined potential (pseudo ground level 0+, for example, 2V) without passing through the Zener diode. The photocoupler PC which is the monitoring low speed data signal detecting means 1311B is shown in FIG.
The current Iis shown in (and FIG. 4) is detected. That is, the current flowing to the emitter side of the transistor TR1 at the rise of the power supply voltage Vx is detected. The value of the emitter current Iis is as follows when the power supply voltage Vx rises.
Depending on the presence or absence of competing current between this and the monitoring signal, by setting a predetermined threshold value, the monitoring signal "0" or "1" is set.
It is said that Therefore, in FIG. 9, the current Iis is shown by an arrow in the falling direction (competition direction) and a “*” mark (the same applies to the following figures). If the current flowing through the photocoupler PC is equal to or greater than the constant value Ith during the output from the slave station input unit 15B, the photocoupler PC is turned on.

As shown in FIG. 18, there are two states based on the monitor signal of "0" or "1", and the magnitude of the current signal Iis is determined. The emitter current Iis of the transistor TR1 becomes a current of about 100 mA when the monitor signal is "1" because a competing current flows between this and the power supply voltage Vx. On the other hand, when the monitoring signal is “0”,
Since no competing current flows between this and the power supply voltage Vx,
The current Iis is equal to the current ip flowing through the slave station output unit 14, the line receiver of the slave station input unit 15, and the power supply voltage generating means. That is, when the potential on the first data signal line D + is forcibly set to the power supply voltage Vx (= 24V), the slave station input unit 15B (transistor thereof) changes from ON to OFF because there is no data signal. To do. Therefore, when the monitor signal is "1", the pulse current Iis flows when the power supply voltage Vx is forcibly supplied. In addition, slave station 1
It is assumed that the circuit on the first side consumes a small amount of current and the current ip is small.

Here, the threshold value Ith = is for detecting the value of the current Iis is set. The threshold is the slave station input unit 15
It is set to an intermediate value between the limiting current (about 100 mA) of the B transistor TRi and the current ip. As a result, the current Ii
When the value of s is larger than the threshold value, the monitor signal "1" is detected, and in the opposite case, the monitor signal "0" is detected.
Actually, this threshold value is realized by setting the value of the resistor R1 connected to the photocoupler PC to an appropriate value.

As shown in FIG. 9, when the monitor signal is "1" at the rise of the power supply voltage Vx, the transistor of the photocoupler PC is turned on, and the low level is caused by the voltage drop of the collector resistance connected to this. Inverter INV
Entered in. Therefore, the high-level pulse signal is input to the input data unit 138 as the signal Diis. The monitoring low-speed data section 138B outputs the high-level signal Diis.
Take in. Therefore, the monitoring signal "1" can be reliably detected. On the other hand, when the monitor signal is “0” at the rise of the power supply voltage Vx, the transistor of the photocoupler PC is turned off and the high level causes the inverter IN.
Input to V. Therefore, the monitoring low speed data section 138B
Takes in the low-level signal Diis. That is, the monitoring signal "0" is detected.

Current signal Iis flowing through the photocoupler PC
Is converted into a voltage signal by the voltage drop in the collector resistance R1 connected to it, and is input to the flip-flop FF of the monitoring low-speed data extraction means 1310B via the inverter INV. A signal Dick which is a clock delayed by one cycle from the clock CK is input from the timing generation means 132 to the flip-flop FF as its clock. Therefore, the signal Diis output from the flip-flop FF outputs the value of only the monitoring data signal at a timing delayed by one cycle from the original clock CK for a period equal to 1/4 cycle or 3/4 cycle of the clock CK. Become a signal. The signal Diis is input to the monitoring low speed data section 138B.

The monitoring low-speed data section 138B takes in the input signal Diis into a predetermined bit in a predetermined order,
This is held and output until a new data value is input. For this reason, the signal Dick is monitored by the monitoring low-speed data unit 13
Input to 8B. As a result, in the next one cycle of the original clock CK, the signal Diis changes to the monitoring low-speed data section 1
It is taken into a predetermined bit position of the 38B register.
Therefore, in the end, 32 from address 0 to address 31
Monitoring signals IN0i to IN which are bit parallel data
31i is serial / parallel converted, and monitoring low-speed data unit 13
8B is input to the low speed data input unit 101B. As a result, the monitoring signal is input, for example, "0101 ...".

On the other hand, the first monitor signal superimposed on the control signal on the first data signal line D + is output from the line transformer T. The signal from the line transformer T is the amplifier AMP of the monitoring high speed data signal detecting means (frequency signal detecting means) 1311A for detecting the first monitoring data signal.
To the comparator COMP4, the waveform is shaped (wave heights are aligned), and the output Difp
Is output as. In the output Difp, the data of the supervisory signal corresponding to the data of the control signal exists at the same address position as the address position of the data of the control signal. The output Difp is supplied to the counter C of the monitoring high-speed data extraction means 1310A via the 2-input OR gate circuit OR3.
Input to NT.

The counter CNT counts the number of pulses in the input output Difp for each cycle of the clock CK, and outputs the result as a signal Difs. Therefore, the signal D is applied to the reset input of the counter CNT.
ick is input via the differentiating circuit ∂, and the count output Difs of the counter CNT is input via the 2-input OR gate circuit OR3. The counter CNT outputs the signal D
It is reset by ick, reset every 1 clock of the signal Dick, and outputs the count result. In this counting, the threshold value N held in the holding means (register, not shown) is used. For example, N = 5. That is, as will be described later, since the frequency of the first monitor signal is eight times that of the control signal (8f0), eight pulses should be counted in the cycle of one clock CK. Therefore, a value slightly larger than 1/2 thereof is set as the threshold value N. For example, since the data of the monitoring signal at the address 0 of the control signal is "1", the count value becomes eight, and "1 (or high level)" is output as the signal Difs. Further, since the data of the monitoring signal at the address 3 of the control signal is "0", the count value becomes 4 or less, and "0 (or low level)" is output as the signal Difs. However, in order to count the data of the supervisory signal, the output of the signal Difs as the result is shifted from the control signal by one address. For example, the signal Difs for the supervisory signal superimposed on address 0 of the control signal is 1 for the control signal.
It is output at the address timing. In other words, this is address 0 of the supervisory signal. Since the period of the short start signal SS is 2 to, the count result can be output also for the last address (address 31).

The monitoring high-speed data section 138A, similarly to the monitoring low-speed data section 138B, is a monitoring signal IN0 which is 32-bit parallel data from addresses 0 to 31.
f to IN31f are serial / parallel converted and input from the monitoring high speed data unit 138A to the high speed data input unit 101A. As a result, the monitoring signal is input, for example, "1100 ...".

The present invention has been described above according to the embodiments thereof, but the present invention can be variously modified within the scope of the gist thereof.

For example, as shown in FIG. 19, it is preferable to provide termination units 18 and / or 19 at one or both ends of the first data signal line D + and the second data signal line D-. The terminating units 18 and 19 may be configured as shown, for example, in Japanese Patent Application No. 1-140826.

Further, for example, as shown in FIG. 19, the master station 13 may be provided with an error check circuit. The error check circuit monitors the first data signal line D + to check the state of the line (short circuit or the like). The configuration of the error check circuit may be that shown in Japanese Patent Application No. 1-140826.

Further, for example, as shown in FIG. 19, when the power supply capacity of the slave station 11 can be satisfied with 24 V superimposed on the first data signal line D + output from the master station 13, the external power source is used as the slave station. 11, the power lines P (P ₂₄ and P ₀ ) for supplying the controlled device 12 may be omitted.

Although not shown, for example, Japanese Patent Application No. 1-
As shown in No. 140826, the master station output unit 1 of the master station 13
35 and a plurality of master station input units 139 may be provided to correspond to a specific slave station. In this case, the master station output unit 135 and the slave station output unit 14 are provided in m units (m ≧ 1), respectively, are associated with each other in a one-to-one correspondence, and have a predetermined sequence on the data signal line. Connected. On the other hand, the master station input unit 139 and the slave station input unit 15 each have n (n ≧
1) are provided one by one and are associated with each other in a one-to-one correspondence,
The data signal lines are connected in a predetermined sequence. Each associated part is sequentially actuated under the control of a timing signal for transmission of control data to the associated controlled part 16 and monitoring signals from the sensor part 17. Further, such a configuration may be one group, and a plurality of groups may be provided. The number of stations in each group may be different.

Further, although not shown, the operations in the master station 13 and the slave station 11 are realized by executing the processing programs for executing the above-described processings in respective CPUs (Central Processing Units) provided therein. You may.

[0101]

According to the present invention, in the control / monitoring signal transmission system, the first and second control signals and the first and second monitoring signals can be superposed on the clock signal. It is possible to realize bi-directional high-speed signal transmission between the controlled part and the sensor part, output the dualized control signal and the dualized monitoring signal to the common data signal line, and It is possible to transmit in both directions at the same time. Furthermore, since the control signal and the supervisory signal can be duplicated, one of the duplicated control signal and supervisory signal is used for high-speed data transmission that should be transmitted in a short cycle,
The other can be used for transmission of low-speed data that is sufficient for long-cycle transmission, and as a result, it is not necessary to insert low-speed data during high-speed data transmission, and the cycle time of high-speed data transmission becomes longer. And high-speed data can be transmitted at a satisfactory transmission rate. Also, by forming a short start signal and a long start signal,
The high-speed data refresh time and the low-speed data refresh time can be easily determined while distinguishing from each other, and the high-speed data and the low-speed data can be transmitted while maintaining a fixed correspondence relationship with each other.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is an explanatory diagram of signal transmission of the present invention.

FIG. 3 is an explanatory diagram of signal transmission of the present invention.

FIG. 4 is an explanatory diagram of signal transmission of the present invention.

FIG. 5 is a basic configuration diagram of the present invention.

FIG. 6 is a basic configuration diagram of the present invention.

FIG. 7 is a basic configuration diagram of the present invention.

FIG. 8 is a block diagram of an example of a master station.

9 is a waveform diagram in the master station of FIG.

FIG. 10 is a configuration diagram of an example of a low-speed data slave station output unit.

11 is a waveform diagram in the low speed data slave station output unit of FIG.

FIG. 12 is a configuration diagram of an example of a low-speed data slave station input unit.

13 is a waveform diagram in the low-speed data slave station input unit of FIG.

FIG. 14 is a configuration diagram of an example of a high-speed data slave station output unit.

15 is a waveform diagram in the high-speed data slave station output unit in FIG.

FIG. 16 is a configuration diagram of an example of a high-speed data slave station input unit.

17 is a waveform chart in the high-speed data slave station input unit of FIG.

FIG. 18 is an explanatory diagram of detection of a supervisory signal.

FIG. 19 is another basic configuration diagram of the present invention.

[Explanation of symbols]

10: control unit 11: slave station 12: controlled device 13: master station 14: slave station output unit 15: slave station input unit 16: controlled unit 17: sensor unit D +: first data signal line D-: second Data signal lines P ₂₄ and P ₀ : Power line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04Q 9/00 311 H04Q 9/00 321E 321 9/06 9/06 9/14 A 9/14 D G05B 19 / 05 D (72) Inventor, Kazuo Inani, Inouchi, Inouchi, Naganokyo-Kyoto, Kyoto Prefecture, 1-8, Anywire Co., Ltd. (72) Hideki Kakiyama, Inoshita, Inoda, 8-share, Nagaokakyo, Kyoto, Incorporated, Anywire, 72 (72) Inventor Yasushi Mori 8 Inouchi Inodauchi Nagaokakyo-shi, Kyoto Prefecture 1-shares F-term in Anywire (Reference) 5H220 AA04 BB01 BB05 BB11 CC03 CC07 CC09 CX01 CX05 EE09 FF10 JJ06 JJ12 JJ34 DD08 CC09 DD07 CC08 DD08 CC07 DD08 CC08 DD07 CC08 5K032 BA08 CA01 CD01 DA01 5K048 AA01 AA08 BA23 DA02 DA05 EA01 EA03 EA14 EA21 EB12

Claims (3)

[Claims] 1. A control unit and a plurality of controlled devices each including a controlled unit and a sensor unit for monitoring the controlled unit, and a data signal line common to the plurality of controlled devices. In a control / monitoring signal transmission system for transmitting a control signal from the control unit to the controlled unit and transmitting a monitoring signal from the sensor unit to the control unit, a parent connected to the control unit and a data signal line. A station and a plurality of slave stations provided corresponding to the plurality of controlled devices and connected to the data signal lines and the corresponding controlled devices, between the master station and a plurality of slave stations. A first control data signal and a first supervisory data signal having a short transmission cycle are updated at every high-speed data refresh time determined by a plurality of clocks, and are mutually transmitted on the data signal line, and a second control data signal having a long transmission cycle. And the second monitoring data signal are updated at each low-speed data refresh time that is longer than the high-speed data refresh time and transmitted mutually on the data signal line, and the master station has a predetermined timing synchronized with the clock. Timing generating means for generating a signal, and under the control of the timing signal, converts the first control data signal and the second control data signal input from the control unit into a serial pulse voltage signal, A master station output section that outputs these to the data signal line; and, under the control of the timing signal, the first monitoring data signal and the first monitoring data signal that are superimposed on the serial pulse voltage signal transmitted through the data signal line. The value of each data of the second control data signal is extracted, these are converted into the monitoring signal,
A master station input unit to be input to the control unit, a long start signal defining the beginning of the low speed data refresh time, and a short start signal defining the beginning of the high speed data refresh time other than the generation of the long start signal. And a control data signal generating means for generating, the plurality of slave stations are composed of two types of first slave station and second slave station, the first slave station, under the control of the timing signal, A slave station that extracts the value of each data of the first control data signal for each high-speed data refresh time and supplies the data corresponding to the slave station in the value of each data to the corresponding controlled unit. Under the control of the output unit and the timing signal, a first monitoring data signal is formed according to the value of the corresponding sensor unit at each high-speed data refresh time, and the first monitoring data signal is generated by the first monitoring data signal. As a data value of the monitoring data signal, a slave station input unit that superimposes on the serial pulse voltage signal is provided, and the second slave station is under the control of the timing signal at each low-speed data refresh time. A slave station output unit that extracts a value of each data of the second control data signal and supplies data corresponding to the slave station in the value of each data to the corresponding controlled unit; Under the control of, the second monitoring data signal is formed for each of the low speed data refresh times according to the value of the corresponding sensor unit, and this is used as the data value of the second monitoring data signal for the serial A control / monitoring signal transmission system, comprising: a slave station input unit that is superimposed on a pulsed voltage signal. 2. The first slave station according to claim 1, wherein in the high-speed data refresh time, the slave station output unit counts clocks extracted from the serial pulsed voltage signal and performs self-operation in advance. The address assigned to the control unit is extracted, the data of the address is supplied to the corresponding controlled unit, and the slave station input unit counts the clock extracted from the serial pulsed voltage signal and assigns it to itself in advance. Extracted address, superimposes a supervisory signal for the controlled unit on the address of the serial pulse voltage signal, and outputs the slave station in the second slave station within the low-speed data refresh time. The unit counts the clocks extracted from the serial pulsed voltage signal to extract the address previously assigned to itself, The data of the dress is supplied to the corresponding controlled unit, and the slave station input unit counts the clocks extracted from the serial pulsed voltage signal to extract the address previously assigned to itself, and the serial A control / supervisory signal transmission system, wherein a supervisory signal for the controlled part is superimposed on the address of the pulsed voltage signal. 3. The value of each data of the first control data signal input from the control unit for each cycle of the clock under the control of the timing signal, according to claim 1. Value of each data of the second control data signal input from the control unit by changing the duty ratio between the period of the level other than the level of the predetermined power supply voltage and the period of the level of the power supply voltage subsequent to the predetermined period. The first control data signal and the second control data signal in series by setting the level in a period other than the power supply voltage level to a predetermined level different from the power supply voltage or a pseudo ground level. And outputs them to the data signal line, and the master station input unit controls the data signal every one cycle of the clock under the control of the timing signal. A first monitoring data signal composed of a frequency signal superimposed on the serial pulse-shaped voltage signal transmitted through a signal line is detected, and a first monitoring data signal superimposed on the serial pulse-shaped voltage signal transmitted through the data signal line is detected. 2 By detecting the monitor data signal as the presence or absence of a current signal generated by the competition between the monitor data signal and the power supply voltage, at the time of rising of the level of the power supply voltage,
The data values of the first monitoring data signal and the second monitoring data signal in series are extracted, these are converted into the monitoring signal, and the monitoring signal is input to the control unit. Under the control of a signal, for each cycle of the clock, a duty ratio between a period of a level other than the level of the power supply voltage of the serial pulsed voltage signal and a subsequent period of the level of the power supply voltage is identified. To extract the value of each data of the first control data signal or to identify whether the level in a period other than the level of the power supply voltage is a predetermined voltage level different from the power supply voltage or a pseudo ground level. By extracting the value of each data of the second control data signal,
The data corresponding to the slave station in the value of each data is supplied to the corresponding controlled unit, and the slave station input unit, under the control of the timing signal, responds to the value of the corresponding sensor unit. To form a first monitor data signal composed of a frequency signal or a second monitor data signal composed of different binary levels of current, and using these as the data value of the first or second monitor data signal, the serial pulse form A control / monitor signal transmission system characterized by being superimposed on a predetermined position of a voltage signal.