JP2003037205A - Multilayer substrate with built-in ic-chip, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer substrate with built-in IC-chip which can suitably form an IC chip in the form of a thin film, and also to provide a method for manufacturing the substrate. SOLUTION: The multilayer substrate includes an IC chip, an IC chip-mounted substrate which is mounted so as to embed the IC chip therein, an inter-substrate insulating layer provided on a chip burial side of the chip-mounted substrate, a circuit substrate as an outer layer provided a chip non-embedded side of the chip mount substrate, and a circuit substrate an inner layer laminated, so as to sandwich the chip-mounted substrate and inter-substrate layer together with the outer circuit substrate. Since the chip-mounted substrate is blasted at embedding of the IC chip in the mounted substrate so that the predetermined thickness of the IC chip is adjusted to be specified to the thickness of the mounted substrate, the multilayered substrate can be made in the form of a thin film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit chip (hereinafter referred to as an IC chip) such as a memory or a CPU.
Suitable for applying to high-density packaging of mobile terminals such as I
The present invention relates to a C-chip built-in multilayer substrate and a method for manufacturing the same. More specifically, an IC chip mounting board is configured by thinning an IC chip having a predetermined thickness so as to be aligned with the thickness of the mounting board. The IC chip mounting board together with an inter-board insulating layer is used for an outer layer circuit board and an inner layer. Sandwiched between the circuit board and
Further, the mounting area of the IC chip can be increased three-dimensionally in the stacking direction, and the IC chips can be mounted at a high density.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit device in a bare chip state (hereinafter simply referred to as an IC chip) is applied to a mobile terminal device such as a mobile phone or a portable personal computer.
An IC chip mounting board on which is mounted has come to be used. On this type of mounting substrate, electronic components such as a plurality of IC chips, resistors and capacitors are mixed and mounted in a planar manner without molding individual IC chips.

By the way, according to the conventional IC chip mounting substrate, since the IC chips are arranged side by side in a plane, the component mounting area has reached a limit in response to high density mounting requirements of electronic components. . Therefore, it has become impossible to satisfy the recent demand for miniaturization of printed wiring boards, that is, miniaturization of electronic devices.

To solve this kind of problem, in the technical document, Japanese Patent Laid-Open No. 2-164096, "Multilayer Electronic Circuit Board and Manufacturing Method Thereof", circuit elements constituting an electronic circuit are arranged between layers of a printed wiring board. It is described that it is built-in to achieve high-density mounting of electronic circuits. In addition, JP-A-5-343
In Japanese Patent No. 856, "Multilayer Printed Wiring Board and Manufacturing Method Thereof", it is described that a hybrid module that constitutes an electronic circuit or the like is sandwiched between the printed wiring boards and the electronic circuits or the like are mounted at high density.

Further, in the "multilayer high-density mounting module" of Japanese Patent Laid-Open No. 14293/1993, platinum or palladium is placed on the surface in contact with the solder bump when a printed wiring board containing an electronic circuit or the like as an intermediate layer is laminated. It is described that plating is performed. In each of the technical documents, a thinned IC chip is mounted in advance. There is a limit to the thinning of an IC chip alone, which hinders further high-density mounting of IC chips.

Therefore, in order to solve such a conventional problem, the applicant of the present invention devised a method for thinning the multilayer circuit board to further increase the mounting area of the IC chip in the stacking direction three-dimensionally. In order to provide an IC chip-embedded multi-layer substrate and a method of manufacturing the same, the IC chip and the IC chip are mounted so as to be embedded therein. I
C chip mounting board, inter-substrate insulating layer provided on the chip embedding surface side of this IC chip mounting board, circuit board for outer layer provided on the chip non-embedding surface side of IC chip mounting board, and this outer layer An IC chip mounting substrate and an inner layer circuit substrate laminated so as to sandwich the inter-substrate insulating layer with respect to the circuit board for use in the IC chip mounting substrate. A multilayer substrate with a built-in IC chip is proposed, which is polished so as to be aligned with the thickness of the mounting substrate (Japanese Patent Laid-Open No. 2001-11914).
8). Further, an inter-board insulating layer is provided on the chip embedding surface side of the IC chip mounting board mounted so as to embed the IC chip in the board, and a circuit board for an outer layer is provided on the chip non-embedding surface side. To be Moreover, the IC chip mounting board is formed by polishing so that the IC chip having a predetermined thickness is aligned with the thickness of the circuit board. IC for the circuit board for this outer layer
This is a multilayer structure in which circuit boards for inner layers are laminated so as to sandwich the chip mounting board and the inter-board insulating layer.

Therefore, in the step of embedding the IC chip, the IC chip, which is thinned from the beginning and is not the IC chip, is handled as it is, which is a state in which the semiconductor wafer before the thinning is cut and which includes many circuit element non-forming regions. You can Moreover, the IC is formed for each hole of a predetermined depth formed on the circuit board.
Chip height can be adjusted and further IC
Three-dimensionally increasing the mounting area of the chip in the stacking direction,
Also, high-density mounting of IC chips can be performed.

The first method of manufacturing a multilayer substrate with a built-in IC chip in the above publication is to mount an IC chip on a circuit board, confine the IC chip with an insulating layer, and stack the circuit boards one after another by stacking the IC chips. In the manufacturing method of step 1, the step of polishing so that a predetermined portion of the IC chip mounted through the insulating layer is aligned with the thickness of the circuit board, and the height of the IC chip is reduced, and then the IC chip mounting is performed. And a step of stacking the board and another circuit board to form a multilayer structure.

According to the first manufacturing method described above, not the thinned IC chip from the beginning, but the IC chip containing a large number of circuit element non-formed regions of the semiconductor wafer before thinning is handled as it is. be able to. Moreover, the IC chip can be thinned and flattened so as to be aligned with the surface position of the insulating layer while the periphery of the IC chip is protected by the insulating layer. As a result, the IC chip can be adjusted in height for each insulating layer of a predetermined thickness formed on the circuit board, and the memory or CPU
It is possible to reproducibly form a thin IC chip-embedded multilayer substrate in which the IC chip is sealed.

In the second method of manufacturing the IC chip-embedded multilayer substrate in the above publication, the IC chips are confined and mounted in the insulating layer of the circuit board, and the circuit boards are sequentially laminated I
In a method of manufacturing a multilayer substrate with a built-in C chip, a step of forming a hole for embedding an IC chip in an insulating layer of a circuit board having a desired thickness, and embedding an IC chip having a thickness higher than the depth of the hole And a step of polishing a predetermined portion of the IC chip protruding from the hole so as to be aligned with the thickness of the circuit board to form an IC chip mounting board.

According to the second manufacturing method described above, not the thinned IC chip from the beginning, but the IC chip containing a large number of circuit element non-formed regions of the semiconductor wafer before thinning is handled as it is. be able to. Moreover, with the periphery of the IC chip protected by the side wall of the hole,
The IC chip can be thinned and flattened so as to match the surface position of the circuit board. This allows
The height of the IC chip can be adjusted for each hole of a predetermined depth formed on the circuit board, and a thin IC chip-embedded multilayer substrate is formed with good reproducibility in the same manner as the first manufacturing method. can do. It is possible to reduce the size and increase the number of functions of an electronic device to which the IC chip-embedded multilayer substrate is applied.

An embodiment of an IC chip-embedded multilayer substrate and a method of manufacturing the same according to the above invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view showing a structural example of an IC chip built-in multilayer substrate as an embodiment. In this embodiment, an IC chip having a predetermined thickness is ground to the same height as the thickness of the circuit board to form an IC chip mounting board.
A chip mounting board is laminated together with an inter-board insulating layer so as to be sandwiched between an outer layer circuit board and an inner layer circuit board, so that the mounting area of a further IC chip can be three-dimensionally increased in the stacking direction. At the same time, the IC chips can be mounted at high density.

A multi-layer substrate 100 with a built-in IC chip shown in FIG.
Is a semiconductor integrated circuit device (hereinafter referred to as an IC chip) 3A,
3B is mounted in high density. IC chip 3A,
3B has a thickness of about several hundred μm. The thickness of the IC chip built-in multilayer substrate 100 is t0, and the thickness t0 depends on the number of stacked IC chips 3A and 3B, but is about 1 mm to several mm.
It is a degree.

A multi-layer substrate 100 with a built-in IC chip shown in FIG.
In the example, the IC chip mounting board 1A having a thickness t1 mounted so as to embed the IC chip 3A on one surface of the IC chip mounting board 1A is a circuit board for an inner layer with a prepreg 4 for multi-layer bonding as an inter-board insulating layer sandwiched therebetween. Inner wiring board 2 having thickness t2 as
The IC chip mounting board 1 is laminated on one surface of the
A and the inner layer wiring board 2 are bonded by the prepreg 4, and a printed wiring board 6A having a thickness t3 as a circuit board for the outer layer is laminated on the chip non-embedding surface side of the IC chip mounting board 1A.

In this example, another inner prepreg 5 is sandwiched on the other surface of the inner wiring substrate 2 to have the same thickness,
Another IC chip mounting board 1B is stacked and the IC
The chip mounting board 1B and the inner layer wiring board 2 are adhered to each other by the prepreg 5, and another printed wiring board 6 for the outer layer is provided on the chip non-embedding surface side of the IC chip mounting board 1B.
B is laminated and is a conductive substrate so as to penetrate the prepregs 4 and 5 between the IC chip mounting substrate 1A and the inner layer wiring substrate 2 and between the inner layer wiring substrate 2 and the IC chip mounting substrate 1B. The inter-wiring members 7 and 8 are provided, and the inter-wiring members 7 and 8 form a multilayer structure electrically connected to each other.

Here, the term "multilayer" means a layer in which a wiring pattern is formed. In this example, the IC chip built-in multilayer substrate 100 has a six-layer structure. For the prepregs 4 and 5, glass cloth impregnated with epoxy resin or polyimide polyimide resin material is used. Copper, silver, or the like is used for the inter-substrate wiring members 7 and 8.

In this example, the IC chip mounting board 1A is formed by polishing the IC chip 3A having a predetermined thickness so as to be aligned with the thickness of the IC chip mounting board 1A when the chip is embedded. The chip mounting board 1B is formed by polishing the IC chip 3B having a predetermined thickness so as to be aligned with the thickness of the IC chip mounting board 1B when the chip is embedded. Usually, circuit elements such as transistors and capacitors are often formed on one surface of a semiconductor wafer. Here, when one surface of the semiconductor wafer is a circuit element forming area, the surface on the opposite side is defined as a circuit element non-forming area.

That is, the IC chips 3A and 3B of this example have a circuit element non-forming region (not shown), and the circuit element non-forming region has a polishing allowance of a predetermined thickness. This polishing allowance is provided in order to flatten the portion protruding from the circuit board for mounting the IC chip to the thickness of the circuit board when the chip is embedded. This is because the so-called handling between parts is provided.

As described above, according to the IC chip built-in multilayer substrate 100 according to the first embodiment of the above publication,
Mounted so that the IC chip 3A is embedded in the substrate,
A prepreg 4 is provided on the chip embedding surface side of the IC chip mounting board 1A, and a printed wiring board 6A for an outer layer is provided on the chip non-embedding surface side. Furthermore, IC chip 3
A prepreg 5 is provided on the chip embedding surface side of the IC chip mounting board 1B mounted so that B is embedded in the board, and a printed wiring board 6B for an outer layer is provided on the chip non-embedding surface side. . Moreover, the IC chip mounting board 1
A and 1B are formed by polishing IC chips 3A and 3B having a predetermined thickness so as to be aligned with the thickness of each circuit board for mounting the IC chips. Printed wiring boards 6A, 6B for this outer layer
On the other hand, the inner layer wiring board 2 is laminated so as to sandwich the IC chip mounting boards 1A and 1B and the prepregs 4 and 5 to form a multilayer structure.

Therefore, at the time of embedding the IC chips 3A, 3B, not the IC chip thinned from the beginning, but the IC chip 3A including many circuit element non-forming regions in a state in which the semiconductor wafer before thinning is cut. 3B can be handled as it is. Moreover, the heights of the IC chips 3A and 3B can be adjusted for each insulating layer penetrating the 3A and 3B, and the mounting area of the further IC chips 3A and 3B can be three-dimensionally increased in the stacking direction, and , IC chip 3
It can be mounted at a high density of A and 3B.

As a result, a larger number of IC chips can be mounted, and at the same time, the IC chip built-in multilayer substrate 100.
The size of the electronic device can be reduced, and the electronic device to which the device is applied can be downsized and multifunctional.

Next, a first manufacturing method for the IC chip built-in multilayer substrate 100 will be described. 4A to 4
5A to 5C are process cross-sectional views showing an example of forming the IC chip built-in multilayer substrate 100 according to the first embodiment. FIG. 6 is an image diagram showing an operation inspection example of the IC chip mounting substrate 1 when the IC chip built-in multilayer substrate 100 is formed. FIG. 7 shows the multi-layer substrate 1 with a built-in IC chip.
FIG. 6 is a process cross-sectional view showing a formation example of No. 00.

In this example, it is assumed that the IC chip built-in multi-layer substrate 100 having a six-layer structure in which the two IC chips 3A and 3B shown in FIG. 3 are mounted is formed. For example, an IC chip built-in multilayer substrate 100 in which an outer layer printed wiring board 6A, an IC chip mounting board 1A, a prepreg 4, an inner layer wiring board 2, a prepreg 5, an IC chip mounting board 1B, and an outer layer printed wiring 6B are sequentially laminated is provided. Take the case of forming as an example. In addition, two printed wiring boards 6A for outer layers,
6B, one inner wiring board 2 and two prepregs 4,
5 is prepared in advance, and the IC is mounted on the circuit board 1.
It is assumed that the chip 3 is mounted, then the IC chip 3 is enclosed by an insulating layer, and the circuit boards 1 are sequentially laminated.

On the premise of this, first, as shown in FIG.
The circuit board 1 for C chip mounting is prepared. The circuit board 1 has a copper foil 11 on one surface of an insulating material 18, for example, a glass cloth base material epoxy resin copper clad laminate (FR-).
4) etc. are used. The circuit board 1 is formed by processing this board to form predetermined wiring patterns, electrodes (rounds), and the like.
To create.

For example, a resist material is applied to the copper foil surface of a substrate, and then the resist material is exposed using a reticle (eg, negative film or dry plate) having a shape such as a wiring pattern or an electrode, and then the resist material is exposed. By etching the copper foil 11 using this resist film as a mask, wiring patterns, electrodes, etc. are formed. For the single-sided copper foil substrate, a polyimide resin copper clad laminate or a bismaleimide-triazine (BT resin) resin copper clad laminate may be used in addition to the epoxy type. These substrates are excellent in heat resistance and dimensional stability.

Thereafter, openings 9A and 9B for drawing out terminals are formed in the circuit board 1 shown in FIG. 4B. This opening 9
A and 9B are for electrically and structurally connecting to a plurality of electrodes provided on the back surface (or end portion) of the IC chip 3 and wiring patterns and electrodes provided on the back surface of the IC chip mounting substrate 1A and the like. It is provided in. The openings 9A and 9B are formed by punching with a laser or the like.

Thereafter, by mounting the IC chip 3 on the circuit board 1 so that the surface on which the copper foil 11 shown in FIG. 4C is not formed faces upward, the IC chip as shown in FIG. The mounting boards 1A and 1B are formed. In this example, the IC chip 3 having a circuit element non-forming region before thinning is used, and a polishing margin having a predetermined thickness is provided in the circuit element non-forming region. The IC chip 3 of this example has an initial thickness of about 300 μm to 400 μm.
Then, the conductive member 12A is formed in the IC chip mounting substrate 1A and the like in the preformed opening 9A for drawing out terminals.
12B is filled and the IC chip 3 is bonded to the wiring pattern, electrodes, etc. on the back surface. Copper, silver, or the like is used for the conductive members 12A and 12B. Conductive material 12A, 12B at this time
The order of the filling and the IC chip connection may be reversed. The conductive materials 12A and 12B are not limited.

Thereafter, a single-sided copper foil substrate 15 for embedding a chip having a thickness of about 100 to 200 μm is formed on the IC chip mounting substrate 1A shown in FIG. 5A. At this time, the opening 16 having a size that allows the IC chip 3 to pass through is previously formed in the single-sided copper foil substrate 15.
To form. Then, the copper foil 21 of the single-sided copper foil substrate 15
The single-sided copper foil substrate 15 is laminated on the IC chip mounting substrate 1 so that the surface of the IC chip 3 faces upward and the IC chip 3 projects from the opening 16.

After that, the portion of the IC chip 3 protruding from the single-sided copper foil substrate 15 shown in FIG. 5B is polished and flattened. For polishing at this time, a grinding method is applied. According to this grinding method, the IC chip mounting substrate 1 is mounted on the rotary drive portion of a polishing device (not shown) with the polishing surface facing downward, and the IC chip mounting substrate 1 is pressed from the upper part to the lower part of the device to While the chip mounting substrate 1 is rotationally driven, a predetermined portion of the IC chip 3 is polished by the polishing paper 17 that moves in the horizontal direction.

The polishing condition at that time is that the processing pressure is about 2 × 1.
0 ⁵ Pa or so, the rotational speed of the rotary drive unit 30 to 40 sec /
It is about one rotation. The abrasive paper 17 is changed several times on the way. The roughness of the polishing paper 17 is # 400 (coarse)
# 800 (finish). When polishing, use pure water for running. The working time is about 15 minutes / sheet. At this time, the copper foil 21 applied to the polishing side of the single-sided copper foil substrate 15 for penetrating the IC chip may be used as a metal foil for detecting polishing completion. For example, in the initial stage, the single-sided copper foil substrate 15
Abrasive particles of the IC chip 3 at the portion protruding from are observed, but when the polishing progresses gradually and reaches the polishing end stage, the abrasive particles of the copper foil 21 are observed.
Further, as the polishing progresses, the polishing particles of the insulating material of the single-sided copper foil substrate 15 are observed together with the polishing particles of the IC chip 3.

In this example, after the polishing particles of the copper foil 21 are observed, the polishing is terminated when the polishing particles of the insulating material are observed in combination with the polishing particles of the IC chip. In this state, the copper foil is all polished, and the single-sided copper foil substrate 1 shown in FIG. 5C is shown.
The surface of the insulating material of No. 5 and the surface of the IC chip 3 are aligned in the same plane position, which is a good base for the prepregs 4 and 5. The IC chip 3 has a thickness of 100 to 200 μ.
It will be about m.

Then, after the height of the IC chip 3 is reduced, the operation inspection electrodes are drawn out from the IC chip mounting substrate 1. The electrodes for operation inspection are used for applying a test voltage, supplying test data, and drawing out the result data. A terminal may be provided for this test only as a test electrode, but from the viewpoint of minimizing the number of terminals, the electrode connected to the original signal input line or signal output line,
For example, the inter-substrate wiring members 7 and 8 are formed to penetrate the prepregs 4 and 5. The inter-substrate wiring members 7 and 8 are also used as electrodes for operation inspection. Figure 5
The inter-substrate wiring member 7 is shown in C. The inter-substrate wiring member 7 is formed by a printing method or the like so that a metal such as copper or silver is projected in a convex shape on a round electrode or the like.

After the IC chip mounting boards 1A, 1B, etc. have been formed, the IC shown in FIG. 6 is formed before the IC chip mounting boards 1A, 1B and another circuit board are laminated to form a multilayer structure.
An electrical inspection is performed for each mounting board by the tester 10 or the like. In this example, one IC chip mounting board 1 can be handled as one circuit block, and before the IC chip built-in multilayer board 100 is stacked, the IC chip mounting board 1 is processed.
When a failure occurs in the IC chip, only the IC chip mounting board 1 in which the failure has occurred can be replaced, and maintenance and repair thereof are facilitated.

In this example, the inter-substrate wiring member 7 penetrating the prepregs 4 and 5 is used as the electrode for the operation inspection. The probes 13 and 14 of the IC tester 10 are brought into contact with the plurality of inter-board wiring members 7 and 8, and a local mounting test is performed for each circuit block. The test data created exclusively for is used.

Therefore, before the IC chip mounting board 1 and the inner layer wiring board 2 are laminated, the defects of the IC chip mounting board 1 can be removed at an early stage. Only the IC chip mounting substrate 1 and the inner layer wiring substrate 2 which are determined to be non-defective by this inspection result can be laminated with the prepregs 4 and 5 interposed. I
The production yield of the IC chip-embedded multilayer substrate 100 can be improved as compared with the case where an electrical inspection is performed after the C chip mounting substrate 1 and the inner layer wiring substrate 2 are all stacked.

Thereafter, as shown in FIG. 7, the printed wiring board 6A for the outer layer, the IC chip mounting board 1A, the prepreg 4, the inner wiring board 2, the prepreg 5, the IC chip mounting board 1B, and the printed wiring board for the outer layer. 6B is aligned and laminated. At this time, the inter-board wiring members 7 and 8 are aligned so as to pierce the prepreg 4, and the inter-board wiring members 7 and 8 are aligned so as to pierce the prepreg 5.

Then, the prepreg 4 is sandwiched between the IC chip mounting substrate 1A and the inner layer wiring substrate 2, and the prepreg 5 is sandwiched between the inner layer wiring substrate 2 and the IC chip mounting substrate 1B. In this state, the IC chip mounting board 1A
And the inner layer wiring board 2 are structurally joined by the prepreg 4, and the IC chip mounting board 1A and the inner layer wiring board 2 are electrically joined by the inter-board wiring members 7, 8. At the same time, the inner layer wiring board 2 and the IC chip mounting apparatus 1B are structurally joined by the prepreg 5, and the inner layer wiring board 2 and the IC are mounted.
The chip mounting board 1B is electrically joined by the inter-board wiring members 7 and 8.

In this case, the IC chip mounting board 1
A, 1B, the inner layer wiring board 2, the prepregs 4, 5, and the printed wiring boards 6A, 6B for outer layers are pressure-heat bonded in the same heat treatment step. For example, a laminate including the outer layer printed wiring board 6A, the IC chip mounting board 1A, the prepreg 4, and the inner layer wiring board 6B is heated at about 170 ° C. Then, using a vacuum press or the like,
Pressurize to about 0 kg / cm ² .

As a result, the metal forming the inter-board wiring members 7 and 8 is crushed and the boards are electrically connected to each other, and the respective members are thermally bonded to each other, and the IC chip built-in multilayer board shown in FIG. 100 can be formed. Components such as resistors and capacitors are further mounted on the outer surface of the IC chip-embedded multilayer substrate 100 thus obtained.

As described above, according to the method of manufacturing the IC chip built-in multilayer substrate according to the first embodiment of the present invention,
The IC chips 3A, 3A having a thickness of about 300 μm and including not a thinned IC chip from the beginning but a large number of circuit element non-forming regions in a state where the semiconductor wafer before thinning is cut
B can be handled as it is.

Moreover, with the periphery of the IC chips 3A, 3B protected by the single-sided copper foil substrate 15, the single-sided copper foil substrate 1 is formed.
The IC chips 3A and 3B can be thinned and flattened so as to be aligned with the surface position of the insulating material of No. 5. As a result, the heights of the IC chips 3A and 3B can be adjusted for each of the IC chip mounting boards 1A and 1B, and a thin IC chip built-in multilayer board in which the IC chips 3A and 3B such as a memory and a CPU are sealed. 100 can be formed with good reproducibility. More IC chips 3A,
3B can be mounted, and the printed circuit board can be downsized.

Further, in this embodiment, the IC chip mounting boards 1A and 1B, the inner wiring board 2, the prepregs 4 and 5 and the printed wiring boards 6A and 6B for outer layers are pressure-heat bonded in the same heat treatment step. Therefore, the production yield due to repair and rework during the process is improved, and the cost can be reduced accordingly. In the stacking process, the metal projections are used to electrically connect the layers, so
It is possible to manufacture a simpler and cheaper IC chip-embedded multilayer substrate 100.

According to the results of the present inventors simulating the board area, when five IC chips are surface-mounted on a mounting board in a plane (current CSP: Chip Size).
Compared with the case of using the Package), the method of the present invention in which five LSI chips are built in the substrate is 40
It became clear that the size can be reduced by 50%. Therefore, it is possible to reduce the size of an electronic device to which the IC chip-embedded multilayer substrate 100 is applied.

In this embodiment, after the chip is mounted, the IC
Although the case of inserting the single-sided copper foil substrate 15 for penetrating the chip has been described, the present invention is not limited to this, and the circuit board 1 for mounting the IC chip 3 and the depth of a shallower depth than the thickness of the IC chip 3 are provided. It is stated that the IC chip 3 may be mounted after the holes are formed by first joining the single-sided copper foil substrate 15 having the openings 16 to each other.

However, the inventions in the above publications have the following problems. That is,
To realize easy handling before mounting the LSI, reliability after mounting and thinning after mounting, and high density of the completed multilayer board, the LSI is mounted on the inner layer board and the LSI is confined in the insulating layer between the board layers. In a multilayer substrate, the thickness of the inner layer substrate is thinned by previously polishing it together with the LSI exterior portion.

In the surface grinding method shown in the embodiment, when there is a variation in parallelism due to uneven bias of the inner layer circuit board on which the built-in IC chip is mounted, the reference surface of the polishing surface is taken as the processed surface. In most cases, however, undulations are present at the same time, which makes accurate polishing extremely difficult.

Further, due to the presence of a step between the surface of the inner layer circuit board at the initial stage of polishing and the IC chip to be polished, it is difficult to form a uniform contact surface, and the polishing proceeds to the wiring portion of the IC chip or the inner layer substrate. , There is a possibility of wiring loss. By increasing the thickness of the insulating layer, which is the polishing allowance on the circuit element non-formation area side, it is possible to suppress the above-mentioned wiring loss, but it cannot be thick enough to detect the end point using a metal foil. In this case, the amount of polishing is inevitably reduced, the end point detection becomes difficult, and it becomes difficult to avoid the above-mentioned problem of wiring loss. Further, since the polishing speeds of the copper foil and the IC chip do not match (the copper foil is slower), if the polishing paper is not sufficiently rigid, a part of the IC chip may disappear before the end point is detected. .

This problem is illustrated and explained as follows. As shown in FIG. 8, when the thickness of the insulating material A is uneven, if the processing reference plane is taken as shown in the figure, the IC will be damaged due to excessive polishing. On the other hand, if the processing reference plane is taken as shown in FIG. 9, the IC is prevented from being damaged, but it is extremely difficult to set such a processing reference plane. Further, in reality, as shown in FIG. 10, undulations are also present in the insulating material A, so that the reference surface cannot be taken and polishing becomes very difficult. Further, if the abrasive material is very hard like a grindstone, the abrasive material can be polished in parallel without bending as shown in FIG. However, if the abrasive material is flexible (like abrasive paper) and there is room for bending, the easily eroded IC part will be scooped out first.

[0049]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an IC chip-embedded multilayer substrate and a method for manufacturing the same, which solves the above problems.

[0050]

[Means for Solving the Problems] The above-mentioned problems are solved by an IC chip and an IC mounted so as to embed the IC chip.
A chip mounting board; an inter-board insulating layer provided on the chip embedding surface side of the IC chip mounting board; an outer layer circuit board provided on the chip non-embedding surface side of the IC chip mounting board; An IC chip mounting board and an inner layer circuit board stacked so as to sandwich the inter-board insulating layer with respect to an outer layer circuit board;
A multi-layer substrate with a built-in IC chip, characterized in that when a chip is embedded, an IC chip having a predetermined thickness is thinned by blasting so as to be aligned with the thickness of a mounting substrate, or
In a method for manufacturing an IC chip-embedded multilayer substrate, wherein an IC chip is mounted on a circuit board, the IC chip is confined by an insulating layer, and the circuit boards are sequentially stacked, the IC chip being mounted through the insulating layer. A step of forming a thin film by blasting so that a predetermined portion is aligned with the thickness of the circuit board, and after reducing the height of the IC chip, the IC chip mounting board and another circuit board are laminated to form a multilayer structure. Or a method of manufacturing a multi-layer substrate with a built-in IC chip, or an IC in an insulating layer of a circuit board.
In a method of manufacturing an IC chip-embedded multilayer substrate in which chips are confined and mounted and the circuit boards are sequentially laminated, a step of forming a hole for embedding an IC chip in an insulating layer of a circuit board having a desired thickness; A step of embedding and mounting an IC chip having a thickness higher than the depth of the portion, and a step of thinning the IC chip by blasting so that a predetermined portion of the IC chip protruding from the hole is aligned with the thickness of the circuit board. And a method of manufacturing a multilayer substrate having a built-in IC chip, the method including the step of forming a substrate.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiment of the present invention differs from the applicant's previous proposal (Japanese Patent Laid-Open No. 2001-119148) only in the step of thinning an IC chip. A description will be given with reference to 1F. Figure 1
As shown in A, a circuit board 31 for mounting an IC chip is prepared. This is a glass cloth cloth base material epoxy resin copper clad laminate (FR-4) 32 and uses a thermosetting resin. A predetermined wiring pattern, electrodes, etc. are formed by the photolithography method as in the ordinary substrate manufacturing process using FR-4. In FIG. 1A, the circuit pattern 33 is formed from such a copper foil or a conductive member only on one side of the insulating material 32.

Next, as shown in FIG. 1B, in order to electrically connect the mounted IC chip 34 and the circuit pattern 33,
The opening 35 is formed in the circuit board 31. This is formed using a laser or the like.

As shown in FIG. 1C, the opening 35 is filled with the conductive member 36, and from the surface facing the circuit pattern 33, I
The C chip 34 is mounted on the conductive member 36 (this is referred to as the A layer). The wiring surface of the inner layer circuit does not exist on the surface to be thinned later.

Next, as shown in FIG. 1D, the IC chip 34
An insulating material 38 having an opening 37 that is the same as or slightly larger than the outer size is prepared (this is referred to as layer B). A
The layer and the B layer are aligned with each other so that the IC chip 34 is fitted in the opening 37 and are laminated by an adhesive.

Next, as shown in FIG. 1E, a metal mask 40 having an opening 39 of the same size as the IC chip 34 or larger than the IC chip 34 is formed on the substrate to be processed, that is, A.
The assembly of the layer and the B layer is aligned and assembled. Next, the surface of the IC chip 34 is thinned by sandblasting. Although the sandblast process itself does not have the selectivity of the processed portion, the metal mask 40 allows the processing of only the selected portion to proceed. After processing to a predetermined thickness, the metal mask 40 is removed, and abrasive grains and residues are removed by washing. When handling IC chips having a low electrostatic breakdown voltage, it is desirable to use conductive abrasive grains as a countermeasure against static electricity. Furthermore, it is desirable that the water-soluble abrasive grains can be removed by washing after processing. In the stock state of the IC chip, since the thickness is controlled, it is determined how long the part protruding from the B layer of the IC chip is processed under a constant blast condition. There is no need for end point detection means such as using a metal foil or an insulating layer polishing allowance as in the polishing method disclosed in U.S. Pat. Further, since the polishing reference surface is not necessary, even if the inner layer substrates (A layer and B layer) do not have flatness or parallelism, it is possible to accurately reduce the thickness. Therefore, the problems of FIGS. 8 to 12 are solved at once. In addition, since the finished surface of the surface of the IC chip to be blast-ground can be adjusted by changing the abrasive grain size, it is also possible to control the adhesion with the resin during multilayer lamination. Further, since only the surface of the IC chip is selectively processed, there is no damage to the IC chip and the IC chip exterior part. The diameter of the jet nozzle of the sandblast machine is IC
Since it is much smaller than the chip, the nozzle is scanned several times over the size of the opening 39 of the metal mask 40. On the contrary, the metal mask 40 side may be moved.

After the IC chip is ground substantially flush, a through hole is formed in the laminate of A layer and B layer as shown in FIG. 1F, and the inter-board wiring member 41 is filled therein and projected. As in Japanese Patent Laid-Open No. 2001-119148, a surface layer wiring board, a prepreg, an inner layer wiring board, and another surface layer wiring board are laminated together with the other similarly sandblasted IC chip mounting board as shown in FIG. And become a finished product.

FIG. 2 shows a second embodiment of the present invention, in which a thermoplastic resin base material 50 is used as an insulating material.
A circuit pattern 51 made of copper foil is formed on this one surface. Thermoplastic resins such as PPS, LCP, PEEK, SPS and PES are applicable. By pressing the connection bumps 52 (conductive member) provided on the IC chip 34 ′ by a heater chip (not shown) hot pressing against the resin base material 50, the thermoplastic resin 50 is softened and the IC chip 34 ′ is formed. Is embedded as shown in FIG. 2B,
It is connected to the wiring pattern 51 and electrodes formed on the surface of the resin base material 50. Also in this embodiment, as in the first embodiment, the metal mask is used to form the IC chip 34 '.
Although the projecting portion is sandblasted, the step of forming the layer B in FIG. 1B is omitted as compared with the first embodiment. Therefore, a multilayer laminate can be produced at a lower cost. When a thermoplastic resin material is used for the circuit board, for example, the present applicant has previously proposed (Japanese Patent Application No. 2001-05).
It is also possible to form a wiring pattern groove directly by using the “transfer die” described above and form a wiring pattern by embedding a conductive member such as a metal paste in the groove. The same circuit pattern can be formed in a short time and at low cost as compared with the case where the circuit pattern is formed by the photolithography method.

The embodiments of the present invention have been described above. Of course, the present invention is not limited to these, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiments, the sand blast is used to process the IC chip, but the abrasives for the blast are not limited to this, and silica sand, river sand, cast iron grit, cast steel grit, and cut are used. Wire, alumina grit, silicon carbide grit, slag grit, or the like can be used.

In the above embodiments, the case where one IC chip is embedded in the insulating material has been described, but the present invention can be applied to the case where two or more IC chips are embedded. In this case, of course, a metal mask having openings corresponding to the number of embedded IC chips is prepared, the IC chips are aligned and aligned with these openings, and the IC chips are sandblasted as described above. Should be processed. In this case, the heights of the portions protruding from the insulating material may differ between the IC chips, but in this case, the sandblasting processing time may be determined according to the IC chip having the smallest amount of protrusion. Also, instead of the metal mask, sandblast grinding is
A synthetic resin mask that is worse than the C chip may be used.

[0061]

As described above, according to the IC chip-embedded multilayer substrate and the method of manufacturing the same of the present invention, the mounting area of the IC chips is three-dimensionally increased in the stacking direction to perform high-density mounting of the IC chips. In addition, the processing cost can be further reduced as compared with the conventional one, and a multi-layer structure having excellent quality can be provided.

[Brief description of drawings]

FIG. 1 shows a manufacturing process of an IC chip mounting substrate according to a first embodiment of the present invention, A is a sectional view of a circuit board, B is a sectional view of a circuit board having an opening formed therein, and C is a conductive member. Is a cross-sectional view showing a state where an IC chip is mounted on the IC chip, D is a cross-sectional view showing a relation between an insulating material having an opening and a circuit board on which the IC chip is mounted, and E is a metal mask. FIG. 4 is a cross-sectional view showing a situation in which sandblasting is performed by applying, and F is a cross-sectional view of the wiring board filled with the processed IC chip and the inter-board wiring member.

FIG. 2 shows a manufacturing process according to a second embodiment of the present invention, in which A is a cross-sectional view showing a state in which an IC chip is thermocompression-bonded to a thermoplastic resin base material, and B is embedded in the thermoplastic resin base material. FIG. 6 is a cross-sectional view showing a state in which the IC chip is electrically connected to the wiring pattern on the back surface.

FIG. 3 is a cross-sectional view showing a structural example of an IC chip built-in multilayer substrate 100 according to a first embodiment of JP 2001-119148 A.

4A to 4C are process cross-sectional views showing an example of forming the IC chip-embedded multilayer substrate 100 according to the first embodiment.

5A to 5C are process cross-sectional views showing an example of forming the IC chip built-in multilayer substrate 100 according to the first embodiment.

FIG. 6 is an image diagram showing an operation inspection example of the IC chip mounting substrate 1 when the IC chip-embedded multilayer substrate 100 is formed.

FIG. 7 is a process cross-sectional view showing a formation example of an IC chip built-in multilayer substrate 100 according to the first embodiment.

FIG. 8 is a schematic diagram showing a relationship between a processing surface and a processing reference surface when the thickness of the insulating material in which the IC chip is embedded is uneven.

FIG. 9 is a schematic diagram in the case where the processing surface is the processing reference surface in FIG.

FIG. 10 is a schematic diagram when the thickness of the insulating material in which the IC chip is embedded has undulations.

FIG. 11 is a schematic diagram showing that if the abrasive material is very hard like a grindstone, the abrasive material can be ground in parallel by bending.

FIG. 12 is a schematic diagram showing that an IC portion which is easily scraped when the abrasive material is flexible and bends is scooped out first.

[Explanation of symbols]

31 ... Circuit board, 32 ... Insulating material, 33 ... Circuit pattern, 34 ... IC chip, 38 ... Insulating material, 39
…… Aperture, 40 …… Metal mask.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 25/18 G06K 19/00 K H05K 3/46 H01L 25/08 Z F term (reference) 2C005 MA16 MA21 MA33 MA40 NB30 NB32 PA04 PA18 RA04 RA06 RA15 RA30 5B035 BA03 BB09 CA01 5E346 AA12 AA43 BB20 DD34 FF18 GG15 GG40

Claims (15)

[Claims] 1. An IC chip, an IC chip mounting substrate mounted so as to embed the IC chip, an inter-substrate insulating layer provided on the chip embedding surface side of the IC chip mounting substrate, and the IC chip mounting A circuit board for an outer layer provided on the chip non-embedded surface side of the board, and a circuit board for an inner layer laminated so as to sandwich the IC chip mounting board and the inter-board insulating layer on the circuit board for the outer layer. The IC chip mounting substrate comprises a thin film formed by blasting so that an IC chip having a predetermined thickness is aligned with the thickness of the mounting substrate when the chip is embedded. 2. An IC chip is mounted on a circuit board,
In a method of manufacturing an IC chip-embedded multilayer substrate in which C chips are confined by an insulating layer and the circuit boards are sequentially laminated, a predetermined portion of the IC chip mounted through the insulating layer is aligned with the thickness of the circuit board. And a step of stacking the IC chip mounting board and another circuit board to form a multi-layer after the height of the IC chip is reduced. Manufacturing method of chip-embedded multilayer substrate. 3. The IC chip built-in according to claim 2, wherein the IC chip has a circuit element non-forming region, and has a thinning margin of a predetermined thickness on the side of the circuit element non-forming region. Manufacturing method of multilayer substrate. 4. An IC chip mounting board and an inter-board insulating layer are sandwiched between at least an outer layer circuit board to which wiring is provided and an inner layer circuit board to form a multilayer structure. The method for manufacturing a multilayer substrate with a built-in IC chip according to claim 2. 5. A method of manufacturing a multi-layer substrate with a built-in IC chip, in which an IC chip is confined and mounted in an insulating layer of a circuit board, and the circuit boards are sequentially stacked, wherein an IC chip is provided in the insulating layer of the circuit board having a desired thickness. Forming a hole for embedding, embedding and mounting an IC chip having a thickness higher than the depth of the hole, and aligning a predetermined portion of the IC chip protruding from the hole with the thickness of the circuit board And a step of forming a thin film by blasting so as to form the IC chip mounting substrate. 6. The IC chip built-in according to claim 5, wherein the IC chip has a circuit element non-forming region, and has a thinning margin of a predetermined thickness on the side of the circuit element non-forming region. Manufacturing method of multilayer substrate. 7. The hole is formed by joining a circuit board for mounting the IC chip and an insulating layer having an opening having a depth shallower than the thickness of the IC chip. The method for manufacturing a multi-layer substrate with a built-in IC chip according to claim 5. 8. An IC chip mounting board and an inter-board insulating layer are sandwiched between at least an outer layer circuit board to which wiring is provided and an inner layer circuit board to form a multilayer structure. The method for manufacturing a multi-layer substrate with a built-in IC chip according to claim 5. 9. A step of forming a board-to-board insulating member on the chip embedding surface side of the IC chip-mounted board, and the IC chip-mounted board and the board-to-board insulating member with respect to the outer layer circuit board. 9. The method of manufacturing a multilayer substrate with a built-in IC chip according to claim 8, further comprising the step of forming a circuit board for an inner layer so as to sandwich it. 10. The circuit board for the outer layer, the IC chip mounting board, the insulating member for the board and the circuit board for the inner layer are pressure-heat bonded in the same heat treatment step. A method for manufacturing a multilayer substrate having a built-in IC chip as described above. 11. The IC chip-embedded multilayer substrate according to claim 8, wherein after the IC chips are mounted to form an IC chip mounting substrate, an electrical inspection is performed for each IC chip mounting substrate. Manufacturing method. 12. The method of manufacturing an IC chip-embedded multilayer substrate according to claim 8, wherein electrodes for operation inspection are drawn from the IC chip mounting substrate on which the IC chip is mounted. 13. The method of manufacturing an IC chip-embedded multilayer substrate according to claim 12, wherein the operation inspection electrode also serves as an electrode for electrically connecting to an inner layer circuit board. 14. The method of manufacturing a multi-layer substrate with a built-in IC chip according to claim 1, wherein the blasting is sandblasting. 15. The IC according to claim 14, wherein the insulating layer is made of a thermoplastic resin, a wiring pattern is formed on one surface by a transfer mold, and a conductive paste is embedded in the wiring pattern. Manufacturing method of chip-embedded multilayer substrate.