JP2003030125A - Serial interface control device and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial interface control device and a control method which can lighten the load of transmission/reception control over a command signal and a status signal through a serial interface in a state where the load on a CPU is heavy. SOLUTION: The serial interface control unit is equipped with a memory part 105 which previously holds status data to be sent back for command data and a decoder part which converts the command data into an address signal for reading out the status data previously held in the memory part 105. The received command data are converted into the address signal for reading out the status data previously held in the memory part 105 and the status data are read out of the memory part 105 according to the address signal outputted from the decoder part 103.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface control device and method.

[0002]

2. Description of the Related Art Generally, an image output device such as a printer is
Image data (print data) for which output instructions have been issued from a host computer, digital camera, etc. connected to this
Is composed of a controller unit for converting the image data into image data suitable for output, and an engine unit for receiving the image data output from the controller unit and outputting the image to a medium such as recording paper.

A laser beam printer will be described below as an example of the image output device.

A laser beam printer receives image data (print data) from a host computer via a serial line, a parallel line, or a network line such as Ethernet (registered trademark), and a controller unit for converting the image data into bitmap data. , An engine unit that controls and drives the recording paper conveyance and the electrophotographic process. In addition to the image signal for transferring the image data and the timing control signal of the image signal, these controller unit and engine unit receive a command signal for the controller unit to give an instruction to the engine unit and the engine unit for the controller unit. The control of the entire device is realized by transmitting and receiving a status signal for transmitting its own status via a serial interface.

Now, a serial interface control device for transmitting and receiving the above-mentioned command signal and status signal will be described.

FIG. 7 is a block diagram showing a schematic configuration of a conventional general serial interface control device.

In FIG. 7, the command signal transmitted by driving the clock line 301 and the data line 302 is converted into parallel data by the serial / parallel conversion unit 601, and then held in the reception buffer unit 602. When the data holding in the reception buffer unit 602 is completed, a signal for notifying this is given to the interrupt generation unit 603 to cause the CPU unit 200 of the host computer to generate an interrupt. The CPU unit 200, which has been notified of the reception of the command due to the occurrence of the interrupt, reads the command data held in the reception buffer unit 602, prepares the status data that is information such as the device state requested by the read command, and prepares the status data. Transfer to the transmission buffer unit 604. C
The status data transferred from the PU unit 200 to the transmission buffer unit 604 is input to the parallel / serial conversion unit 605, and is sent as a status signal to the data line 302 at a predetermined timing by a signal given from the timing generation unit 606.

The command signal defines a plurality of commands depending on the requested contents, and each command is identified by a command code. In addition, since the status data returned for each command is also defined for each command,
The CPU unit 200 needs to execute these processes each time a command reception interrupt occurs.

The engine section outputs an image signal (bitmap data) to a medium such as a recording sheet by using an electrophotographic process in accordance with a command signal received from the controller section, and printable recording sheet size, paper jam, etc. The error information of (1) is appropriately transmitted to the controller unit as a status signal.

Conventionally, in the development process and the operation verification process of the image output device composed of the controller unit and the engine unit, various print data are transmitted to the controller unit and the engine unit is actually operated to output. It was necessary to obtain an image, and the evaluation as to whether or not an abnormality occurred in the output image was repeatedly performed with the naked eye, but such a method caused some problems as described below.

To print out a large amount of images, a large amount of media such as recording paper and consumables such as toner and ink are consumed.

Since the output image is evaluated with the naked eye, the skill of the evaluator is required, and much time is spent even if the skilled evaluator performs the evaluation.

It is difficult for an image output apparatus, which has been advanced in high definition in recent years, to detect a fine output error such as a dot drop from a printing result only by the naked eye.

In order to obtain an output image, both the controller section and the engine section must be operated. If an output error can be detected by the naked eye, whether the error is caused by the controller section or the engine section, It is difficult to identify whether it is due to the department.

Therefore, when developing the image output apparatus, an image processing apparatus for visualizing image data generated by the controller section in real time is used instead of the engine section to verify the development process and operation of the image output apparatus as described above. Methods have been proposed to solve problems in the process.

According to this method, the image processing device connected to the expansion bus of the personal computer is used, and the image processing device is caused to communicate with the controller unit via a predetermined interface, and the image output by the controller unit is output. It is possible to capture a signal (bitmap data), store it in the image memory, read it out, and display it on the display unit. Therefore, the output image can be subjected to detailed verification work on the display device without actually operating the engine unit, which is effective in improving development efficiency and reducing development cost.

[0017]

However, when the above image processing apparatus is used, the following problems occur in the communication processing with the controller section.

That is, in order for the controller section to operate the above-mentioned image processing apparatus in place of the engine section,
In addition to the control related to the delivery of output image data, it is also necessary to execute the command signal and status signal transmission / reception performed by the controller unit and the engine unit via the serial interface at prescribed timings (FIG. 7).

That is, under the control of the personal computer, the image data transfer process for displaying the output image data held in the image processing device on the display device is executed, and at the same time, the command signal / status signal is executed via the serial interface. It is necessary to execute the transmission / reception control, and if the processing cannot be performed within a predetermined time, an operational inconvenience will occur.

For example, when the image data transfer process is not in time, a normal output image may not be displayed on the display device due to the lack of the image data, while the command signal / status signal is transmitted / received at the specified timing. If it is not processed, the controller unit may determine that an abnormality has occurred in the engine unit, execute error processing, or may stop.

The present invention has been made in view of the above problems, and can reduce the load on the transmission / reception control of the command signal / status signal via the serial interface under the heavy load of the CPU. An object is to provide a serial interface control device and a control method.

[0022]

In order to achieve the above object, a serial interface control device according to a first aspect of the present invention has a receiving means for receiving command data via a serial interface and a return means for the command data. Holding means for holding the desired status data, address signal converting means for converting the command data into an address signal for reading the held status data, and status data read out based on the address signal by the serial signal. And transmitting means for transmitting via an interface.

According to a second aspect of the present invention, there is provided the serial interface control device according to the first aspect, wherein the holding means holds the status data in advance.

A serial interface control device according to a third aspect of the present invention is the serial interface control device according to the first or second aspect, further comprising interrupt generating means for selectively generating an interrupt based on the received command data. And

According to a fourth aspect of the present invention, there is provided the serial interface control device according to the third aspect, wherein the interrupt generating means appropriately changes the held status data.

To achieve the above object, a serial interface control method according to a fifth aspect of the present invention holds a receiving step of receiving command data via a serial interface and a status data to be returned in response to the command data. A holding step, an address signal conversion step of converting the command data into an address signal for reading the held status data, and a status data read based on the address signal is transmitted through the serial interface. And a transmission step.

The serial interface control method according to a sixth aspect is the serial interface control method according to the fifth aspect, wherein the holding step holds the status data in advance.

The serial interface control method according to claim 7 is the serial interface control method according to claim 5 or 6, further comprising an interrupt generation step of selectively generating an interrupt based on the received command data. And

The serial interface control method according to claim 8 is characterized in that, in the serial interface control method according to claim 7, the interrupt generation step appropriately changes the held status data.

[0030]

DETAILED DESCRIPTION OF THE INVENTION A serial interface control device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a serial interface control device according to an embodiment of the present invention.

In FIG. 1, the serial interface control device 100 is connected to the CPU section 200 of the host computer via the expansion bus 201.

Serial interface controller 100
Is a serial / parallel conversion unit 101, a reception buffer unit 102, a decoder unit 103, and an interrupt generation unit 10.
4, a memory unit 105, a transmission buffer unit 106, a parallel / serial conversion unit 107, and a timing generation unit 1
08 and.

Further, the serial interface control device 100 includes a clock line 301 and a data line 30.
A serial communication process with a controller unit (not shown) is executed via 2, and a command signal / status signal is transmitted / received.

FIG. 2 is a time chart showing the operation of command signals and status signals transmitted and received through the serial interface control device 1 of FIG.

In the data line signal 302a of FIG. 2, 1
Following the command signal of the frame, the status signal corresponding to the command signal is transmitted in the second frame. As shown in the figure, each frame has a start bit 21, a command signal 22 (fixed length of 8 bits), and an end. The configuration is bit 23. In each frame, the command signal sending side and the status signal sending side perform communication by a half-duplex method in which the data lines are alternately driven, and data transfer is executed in synchronization with the clock signal 301a supplied from the clock line. When the start bit is detected, the receiving side sequentially captures the data that follows it, recognizes the captured data as a command (or status) when the transfer of 8 bits is completed, and executes the process.

The command signal 22 includes (n + 1) from command 0 to command n, as shown in FIG. 3 described later.
The number of command data is defined, and the status signal 24 includes (n +
1) The number of status data is defined.

FIG. 3 is a diagram showing a received command conversion table in the decoder unit 103 of FIG.

In FIG. 3, the decoder unit 103 receives a received command code consisting of received command codes 11, 21, 31, ..., Xy, and converts the converted code (memory address) 0, 1, 2 ,. It has a received command conversion table consisting of a code output.

The decoder section 103 includes a reception buffer section 10
The command code input from 2 is converted into an address signal (memory address) based on the received command conversion table, and is output to the memory unit 105 as a read address signal. For example, when the code 11 defined as the command 0 in the command data is input, it is converted into the address signal of the memory address 0 and output to the memory unit 105. Similarly, code 21 and command 2 defined as command 1
A code 31 defined as and a code 41 defined as command 3 are converted into respective address signals of memory address 1, memory address 2, and memory address 3, respectively.

FIG. 4 is a diagram showing the status of the status data held in the memory unit 105 of FIG.

In FIG. 4, the memory unit 105 has (n + 1) memory addresses from address 0 to address n, and holds status data to be returned to the command data corresponding to the memory address. To do. The status data is composed of (n + 1) pieces of status data from status 0 to status n.

That is, the status data to be returned when the command 0 is received is held at the memory address 0 of the memory unit 105 as the status 0,
Similarly, the status data to be returned when the command n is received is held as the status n at the memory address n of the memory unit 105.

In the memory unit 105, status data is read from the memory unit 105 based on the memory address of the address signal output from the decoder unit 103.
For example, when the memory address 1 is input, the status data of the status 1 held at the memory address 1 is read.

As shown in FIGS. 3 and 4, the status data to be returned with respect to the command data is stored in the memory unit 105 in advance, so that the status data to be returned with respect to the received command data is stored in the CPU. The memory unit 1 without performing the interrupt processing by the unit 200
It is possible to automatically read from 05.

Next, the control processing in the serial interface control device 100 of FIG. 1 will be described with reference to the flowchart of FIG.

FIG. 5 is a flow chart of control processing in the serial interface control device 100 of FIG.

In FIG. 5, first, it is determined whether or not the command signal 22 transmitted by driving the clock line 301 and the data line 302 is received from the controller section (step S501). As a result of this determination, when the command signal 22 is received (YES in step S501)
S), the received command signal 22 is converted into command data by the serial / parallel conversion unit 101 and held in the reception buffer unit 102 (step S502).

Next, the decoder unit 103 executes decoding for converting the command data held in the reception buffer unit 102 into an address signal for reading the status data held in advance in the memory unit 105 (step S5).
03). That is, the command data is converted into an address signal based on the received command conversion table of FIG. 4, and the address signal is output to the memory unit 105 as a read address signal.

Subsequently, the status data is read from the memory unit 105 based on the address signal output from the decoder unit 103, that is, the memory address (step S504). As described above, the memory unit 105 holds in advance status data to be returned with respect to the received command data, and the CPU unit 200 can appropriately change the status data according to the state change of the device. is there.

In step S505, step S504
The status data read from the memory unit 105 in step S1 is held in the transmission buffer unit 106. Next, the status data held in the transmission buffer unit 106 is input to the parallel / serial conversion unit 107, and the timing generation unit 108
The status signal 24 is transmitted to the external device via the data line 302 in accordance with a predetermined timing by the clock signal 301a given from (step S50).
6) Then, this process ends.

By this processing, it is possible to read the status data suitable for the received command signal from the memory section 105 and return it, without the processing relating to the transmission / reception of the command signal / status signal being interrupted to the CPU section 200. is there. Therefore, even when the image processing apparatus is operated instead of the engine unit, the CPU unit 2
00 can be dedicated to the transfer processing of the image data displayed on the display device, and as a result, the inconvenience caused by the load of the command signal / status signal transmission / reception control can be eliminated.

According to the above-described embodiment, the serial interface control device stores in advance the memory unit 105 that holds the status data to be returned in response to the command data.
And a decoder unit for converting the command data into an address signal for reading the status data previously held in the memory unit 105, and an address for reading the received command data in the status data previously held in the memory unit 105. Convert to signal (step S50
3) Since the status data is read from the memory unit 105 based on the address signal output from the decoder unit 103 (step S504), the status data is read through the serial interface under the condition that the load of the CPU that executes the processes in parallel is high. The load on the transmission / reception control of the command signal / status signal can be reduced.

In the above-described embodiment, the memory unit 105 which holds the status data corresponding to the command data in advance.
By the serial interface control device configured to read status data from the CPU and return it to the controller unit, it is possible to omit the processing related to the transmission / reception of the command signal / status signal, which has conventionally caused the interrupt processing to the CPU unit 200. .

However, the command signal 22 received
Among them, there are some that must be recognized by the CPU unit 200 at the time of reception, such as a request for urgently stopping the process being executed. Further, in the above embodiment,
Before receiving the command signal 22, the command signal 22,
That is, the status signal 24 returned to the command data, that is, the status data is
It was premised that the data was registered in the memory unit 105 by writing from 0, but in the command data that is actually defined, information that depends on the state at the time when the command signal 22 is received is included. There may be something that needs to be reflected in the status data. When such a command signal 22 is received, processing must be performed to notify the CPU section 200 at the time of reception and return appropriate status data.

The above-mentioned decoder section 103 has been described as converting the input command data into the address signal according to the received command conversion table of FIG. 4, but at the same time, the interrupt request signal according to the received command conversion table shown in FIG. 6 described later. Control the occurrence of.

FIG. 6 is a diagram showing another embodiment of the received command conversion table in the decoder section 103 of FIG.

In FIG. 6, the decoder section 103 has a received command code input and an interrupt generation request output. For example, when the code 21 defined as command 1 is input as the command signal 22, the CPU section 200. An interrupt generation request signal is output to generate an interrupt process, and it is not output in the case of other command signals 22.

As shown in FIG. 1, the interrupt generation request signal is output from the interrupt generation section 104 to the CPU section 200, and the CPU section 200 operates. Therefore, since the decoder unit 103 is configured to output the interrupt generation request signal only for the command that should be recognized by the CPU unit 200 at the time of reception, the CPU unit 2
It is possible to select whether to generate an interrupt to 00.

When it is necessary to reflect the information depending on the state at the time of reception in the status data, the data held in the memory unit 105 is rewritten in the interrupt process.

According to the above-described embodiment, the generation of interrupts to the CPU section 200 is selectively controlled based on the received command data, so that the frequency of processing relating to transmission / reception of command signals / status signals is suppressed. be able to. Also, if necessary, the memory unit 1 can be used when an interrupt occurs.
Since the data of 05 is rewritten, the inconvenience caused by the load of the command signal / status signal transmission / reception control can be eliminated.

In the above embodiment, the case where the system is configured by combining with a personal computer has been described, but the present invention is not limited to this, and may be realized by combining with various other devices.

[0063]

As described in detail above, according to the present invention, the status data to be returned is held for the command data received via the serial interface, and the status data holding the command data is read. Is converted into an address signal for transmission, and the status data read out based on the address signal is transmitted through the serial interface. Therefore, under a situation where the load of the CPU is high, the command signal / status signal of the serial interface The load on transmission / reception control can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a serial interface control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing command signals and status signals transmitted / received to / from the serial interface control device 1 of FIG.

FIG. 3 is a diagram showing a received command conversion table in a decoder unit 103 in FIG.

4 is a diagram showing a state of status data held in a memory unit 105 of FIG.

5 is a flowchart showing an operation sequence of the serial interface control device of FIG.

6 is a diagram showing another embodiment of a received command conversion table in the decoder unit 103 of FIG.

FIG. 7 is a block diagram showing a schematic configuration of a conventional general serial interface control device.

[Explanation of symbols]

100 Serial interface controller 101 Serial / parallel converter 102 receive buffer unit 103 decoder section 104 Interrupt generator 105 memory 106 transmission buffer unit 107 Parallel / serial converter 108 timing generator 200 CPU section 201 expansion bus 301 clock line 302 data line

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takeshi Shinomiya             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Isamu Ozawa             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation F term (reference) 5B014 EB03 HA14 HB05 HB27                 5B077 BB03 DD02 FF01 MM02 MM03                       NN02

Claims (8)

[Claims] 1. A receiving means for receiving command data via a serial interface, a holding means for holding status data to be returned to the command data, and a read means for reading the held status data from the command data. 2. A serial interface control device comprising: an address signal converting means for converting the address signal into the address signal; and a transmitting means for transmitting status data read based on the address signal through the serial interface. 2. The serial interface control device according to claim 1, wherein the holding unit holds the status data in advance. 3. The serial interface control device according to claim 1, further comprising an interrupt generation unit that selectively generates an interrupt based on the received command data. 4. The serial interface control device according to claim 3, wherein the interrupt generation means appropriately changes the held status data. 5. A receiving step of receiving command data via a serial interface, a holding step of holding status data to be returned with respect to the command data, and a step of reading the held status data of the command data. A serial interface control method, comprising: an address signal converting step of converting the address signal into the address signal; and a transmitting step of transmitting status data read based on the address signal via the serial interface. 6. The serial interface control method according to claim 5, wherein the holding step holds the status data in advance. 7. The serial interface control method according to claim 5, further comprising an interrupt generating step of selectively generating an interrupt based on the received command data. 8. The serial interface control method according to claim 7, wherein the interrupt generation step appropriately changes the held status data.