JP2003029718A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device in which generation of an EMI(electromagnetic intereference) or the like is suppressed. SOLUTION: Gradation data of a plurality of pixels are divided into a pair of first and second groups. When both groups have mutually different values, each of gradation data is outputted to a driving driver 4a from a control circuit substrate 2 and the driver 4a generates pixel data by converting the gradation data. When both groups have mutually the same value, the gradation data of the first group are outputted as they are from the substrate 2 and the same value of the previous output of the second group is outputted to the second group. Then, the driver 4a supplies the pixel data which are obtained by converting the gradation data of the first group to pixels of the first group and supplies the pixel data obtained by converting the data of the first group, that become the pair of the second group, to the pixels of the second group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which performs multi-gradation display in each pixel and performs high-definition color display.

[0002]

2. Description of the Related Art In recent years, flat panel displays are C
It has been adopted in various fields including monitors for personal computers instead of RTs. In particular, liquid crystal display devices are widely used from mobile phones to large-sized monitors, taking advantage of their features such as thinness, light weight, and low power consumption. Liquid crystal display devices used for large monitors and liquid crystal televisions are required to have high definition and high image quality, and the number of pixels becomes SXGA as they become 15 type and 18 type.
(1280 x RGB x 1024), UXGA (1600
XRGBx1200), and each pixel is also performing multi-gradation color display.

A conventional liquid crystal display device that performs multi-tone color display will be described with reference to the drawings. FIG. 6 is a diagram schematically showing the arrangement of the pixels 51 on the liquid crystal panel, and FIG. 7 is a diagram schematically showing the flow of signals to the driving driver 54. A plurality of signal lines 52 and scanning lines 53 are formed in a matrix on the display unit 50 of the liquid crystal panel, and the portions surrounded by the signal lines 52 and the scanning lines 53 correspond to the pixels 51, respectively. (R), green (G), and blue (B) color filters are arranged in a stripe pattern. Here, the pixel displaying red is 51R, the pixel displaying green is 51G, and the pixel displaying blue is 51B. A set of R, G, and B pixels 51R, 51G, and 51B constitutes one unit, and a combination of gradations of each pixel 51 displays various colors in one pixel group.

When displaying each pixel 51 based on gray scale data which is a 6-bit digital signal, each pixel 51 is
It can be reproduced with four gradations and one unit pixel group can display 260,000 colors. The driver 54 is electrically connected to the source control circuit on the printed circuit board on the input side and to the signal line 52 on the liquid crystal panel on the output side, and processes the gradation data and the like from the source control circuit. A source signal corresponding to a gradation is supplied to the signal line 52 of the pixel 51. Figure 7
In order to simplify the explanation, the gradation data and the clock signal input to the driving driver 54, the driving driver 54
Shows the flow of the source signal output from, and omits other signals. Also, the wide line for supplying the gradation data is 6
The data line 55 of the present (6 bits) is shown, and the thin line for supplying the clock signal and the source signal is one data line 56, 57.
Is shown.

From the source control circuit to the driving driver 54, two ports of one unit pixel group (odd data, eve)
(n data) gradation data are simultaneously supplied, and 36 (6 bits × RGB × 2 ports) data lines 55 are used for gradation data. In this conventional example, the data line 57 of the pixel group (6 pixels) for two units is output from one driving driver 54, but in reality, one driving driver 54 is connected to more pixels 51. ing. Then, the data line 55 for gradation data and the data line 56 for clock signal
Are respectively branched and connected to the driving driver 54, and the driving driver 54 receives the gradation data corresponding to each pixel based on the clock signal among the gradation data supplied via the data lines 55 and 56. There is. The driving driver 54 converts the grayscale data, which is a 6-bit digital signal, into a source signal, which is an analog signal corresponding to the grayscale, and supplies the source signal to the corresponding pixel 51. For example, as shown in FIG. 6, a pixel group for two units is sequentially arranged from the left end by 1CLK, 2CLK, 3CLK.
.., the data of two ports is supplied in one clock, so that there are up to 640 CLK in the case of SXGA and 800 CLK in the case of UXGA. FIG. 8 shows an example of grayscale data supplied from the source control circuit to the driving driver 54. The driving driver 54 is supplied with 6-bit digital signals representing the gradation of the corresponding pixel for each clock, and at the next clock, new gradation data corresponding to the next pixel is supplied. . That is, the driving driver 54 has gradation data “111111, 1” of pixels (RGB × 2 in FIG. 6) corresponding to odd and even of 1 CLK.
11111, 111110, 111110, 11111
1,111111 "is supplied at the same time as the first clock,
Next, the grayscale data “111110, 1 of the pixel (RGB × 2 in FIG. 6) corresponding to odd and even of 2 CLK”
11110, 111110, 111110, 11111
0, 111110 ″ is supplied at the same time as the second clock. This is sequentially repeated for each clock, and the driving driver 5
4 is supplied with the gradation data (640 CLK) of the pixels of one line.

[0006]

However, as the display device becomes larger and the definition becomes higher with the increase in the number of pixels, the amount of gradation data supplied to the driver for driving also increases,
The frequency of the clock signal also needs to be higher than ever. Further, in order to improve the image quality, each pixel has more gradation levels than ever. For example, the gradation data of one pixel is converted to a digital signal of 6 bits, and the gradation data of 8 bits or more is converted. Since the signal is used as a signal, the number of data lines for supplying the grayscale data is correspondingly increased.
Therefore, High (1), Low in the gradation data
Since switching of (0) is frequently performed in a very short period of time, the influence of electromagnetic interference called unnecessary radiation increases more than ever, and it is necessary to take measures against such EMI.

Therefore, an object of the present invention is to propose a display device which suppresses the influence of EMI and the like.

[0008]

In order to solve the above problems, the present invention provides a display device in which a plurality of pixels are arranged in a matrix and various images are displayed on the display part. Driving drivers for supplying the pixel data indicating the display state of the pixel to the signal line connected to the pixel, the video data indicating the display state of each pixel for generating the pixel data, and the video control data corresponding to the video data. And a plurality of data lines that are connected to the control circuit unit and the driver for driving and that supply the video data and the video control data of the plurality of pixels as a set from the control circuit unit to the driver for driving. And a display device that sequentially and repeatedly outputs video data and video control data of each set via a data line and supplies video data of pixels for one line of the display section to a driver. The control circuit section divides the video data of one set of a plurality of pixels into a first group and a second group which form a pair, and when the pair of video data of the first group and the second group has different values. Outputs the video data of the first group and the video data of the second group to the corresponding data lines and sets the video control data to the first level.
When the paired video data of the group and the second group have the same value, the video data of the first group is output to the corresponding data line, and the data line corresponding to the second group corresponds to the previous second group. Output the same value as the signal line output, and set the video control data to the second level,
When the video control data is at the first level, the driving driver converts the video data of the first and second groups into pixel data and supplies the pixel data to the corresponding signal lines, and when the video control data is at the second level. The pixel data obtained by converting the video data of the first group is supplied to the signal line corresponding to the first group, and the pixel data of the second group is supplied to the signal line corresponding to the second group.
It is characterized in that pixel data obtained by converting the video data of the first group paired with the video data of the group is supplied.

With this configuration, particularly the first group and the second group
When the video data of the group has the same value, the output of the data line corresponding to the second group does not change, so switching between High (1) and Low (0) in the output of the video data is reduced and the influence of EMI is reduced. Can be made.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view of a liquid crystal display device which is an embodiment of the present invention. In addition, although a liquid crystal display device is described in this embodiment, the present invention is not limited to the liquid crystal display device, and an organic EL (electroluminescenc)
A display device of a type such as e) or FED (field emission display) may be used.

Reference numeral 1 denotes a liquid crystal panel, which comprises a pair of glass substrates 1a and 1b bonded together in a hollow shape.
Liquid crystal is injected between 1b. In the case of a TFT-type liquid crystal display device, a plurality of scanning lines and a plurality of signal lines are arranged in a matrix on one glass substrate 1a, TFTs are formed at the intersections thereof, and an area surrounded by the scanning lines and the signal lines is formed. A pixel electrode is formed. In the TFT, the gate electrode is connected to the scanning line, the source electrode is connected to the signal line, and the drain electrode is connected to the pixel electrode. On the other glass substrate 1b, a color filter is formed facing the pixel electrodes, and a light shielding film is formed facing the scanning lines and the signal lines. A common electrode is laminated on the color filter and the light shielding film, and a predetermined voltage is applied. The pixel electrodes and the color filters have the same arrangement as in FIG. 6, and the red (R), green (G), and blue (B) color filters are arranged in a stripe shape, and the R, G, and B pixels arranged in the row direction are arranged. As a set to make one unit. By displaying each pixel in multi-gradation, multi-color display can be performed in this one unit.

Reference numeral 2 is a source control circuit board having a source control circuit mounted on a printed board, and 3 is a gate control circuit board having a gate control circuit mounted on the printed board.
Is a TCP interposed between the liquid crystal panel 1 and the source control circuit board 2, and 5 is a TCP interposed between the liquid crystal panel 1 and the gate control circuit board 3. The TCP 4 is provided with a driving driver 4a. The driving driver 4a has an input side electrically connected to the control circuit of the source control circuit board 2 and an output side electrically connected to the connection terminals arranged at one end on the long side of the glass substrate 1a. connection,
The connection terminal is connected to the signal line. The TCP 5 is provided with a driving driver 5 a, and the driving driver 5 a
The input side of a is electrically connected to the control circuit of the gate control circuit board 3, and the output side is electrically connected to the connection terminal arranged at one end on the short side of the glass substrate 1a, and the connection terminal is connected to the scanning line. Grayscale data and grayscale control data, which will be described later, are supplied from the source control circuit board 2 to the driving driver 4a, and the driving driver 4a converts the grayscale data and the like to generate a source signal which is pixel data, and corresponds to the grayscale data. The source signal is supplied to the pixel to be turned on. When the gate signal is supplied from the gate control circuit substrate to the scanning line of the scanning line and the source signal is supplied to each signal line, the source signal is supplied to the pixel electrode through the TFT in the ON state and the pixel electrode and An electric field corresponding to the source signal is generated between the common electrodes to control the transmittance of the liquid crystal. An external control circuit 6 supplies various control signals and gradation data to the source control circuit board 2 and the gate control circuit board 3. In this embodiment, the source control circuit board 2 corresponds to the control circuit section of the present invention, the driving driver 4a corresponds to the driving driver of the present invention, the gradation data corresponds to the image data of the present invention, and the floor data The tone control data corresponds to the image control data of the present invention.

FIG. 2 shows a driving driver 4 connected to a signal line.
It is a schematic diagram which shows the flow of the signal to a. 10 is a data line for clock signals, 11 is a data line for gradation data, 1
Reference numeral 2 is a data line for gradation control data, and 13 is a data line for a source signal. In this embodiment, since the grayscale data for one pixel is represented by a 6-bit digital signal, one pixel has 6
4 gradations can be reproduced, and a unit of a set of RGB pixels is about 26
All colors can be displayed. In this embodiment, the case of 6 bits is described for simplification of description, but grayscale data may be represented by an 8-bit digital signal. In this case, one pixel has 256 grayscales, and one pixel has approximately one grayscale level. Can reproduce 16.77 million colors.

Grayscale data is supplied from the source control circuit board 2 to the driving driver 4a at two ports, odd data is output to one port, and ev is output to the other port.
en data is output. In this embodiment, the pixels are arranged as shown in FIG. 6, and R, G, and
They are arranged in the order of B, R, G, B. Since R, G, and B are set as one set, the leftmost RGB pixel is odd,
The next RGB pixel corresponds to even, and in the same way RG is sequentially
Odd and even are repeated for each set of B. Also,
In this embodiment, the gradation data for 6 pixels is simultaneously supplied to the driving driver 4a through the data line 11, and the gradation data for 3 pixels, which is odd data, is supplied to the first group and the even data. The gradation data of 3 pixels is grouped into a second group. The first group includes RGB of odd data, and the second group includes e
Since the RGB data of the ven group is included, the grayscale data of the R pixels of the first group and the second group have a paired relationship, and the grayscale data of the G pixels of the first group and the second group have a paired relationship. , B of the first and second groups
The gradation data of the pixels have a paired relationship.

The data line 11 in FIG. 2 has a wide line width, but this shows a data line for 6 lines (6 bits), and the data line 11 for gradation data is provided from the source control circuit board 2 to the driving driver 4a. 36 of 6 bits × RGB × 2 ports are provided. The data line 11 of FIG. 2 is odd in order from the left side.
Data RGB and even data RGB gradation data are supplied, and the source control circuit board 2 drives the driver 4
The gradation data for 6 pixels (2 units) can be simultaneously supplied to a. At this time, a clock signal is also supplied from the source control circuit 2 at the same time, and the driving driver 4a receives the gradation data supplied based on the clock signal as the gradation data of the corresponding pixel. For example, since the pixels are arranged as shown in FIG. 6, when outputting the first clock signal to the data line 10, the data line 11 is used to output the first clock signal from the left side of the display unit.
The grayscale data of the sixth to sixth pixels is supplied, and when the second clock signal is output next, the grayscale data of the seventh to twelfth pixels from the left side of the display portion is supplied. In this way, the output of the (6n-5) th to 6nth grayscale data from the left side of the display unit is sequentially repeated when outputting the nth clock signal, and the grayscale data of the pixels on one line is driven. Can be supplied to the driver 4a.

The driving driver 4a generates a source signal to be supplied to each pixel based on a clock signal, gradation data, gradation control data, etc., and supplies the source signal to a corresponding signal line.

In FIG. 2, 6 is provided on the output side of the driver 4a for driving.
Although the data lines 13 are connected, for example, when 10 TCP4 are used in the SXGA liquid crystal display device, 3840 (1280 × RGB) signal lines are provided in the liquid crystal panel, so that one driving driver is provided. 4a is provided with 384 (128 × RGB) data lines 13 and UXG
In the case of A, 4800 (1600 × RGB) signal lines are provided, so that one drive driver 4a has 480 signal lines.
A data line 13 for the book (160 × RGB) is provided.

FIG. 3 is a schematic diagram showing the structure of the driving driver 4a. To the video data buffer 16, 36 data lines 11a of 6 bits × RGB × 2 ports for outputting gradation data and one data line 1 for outputting gradation control data
2a is provided. The shift register circuit 15 outputs a clock signal to each of the data registers 17a and 17b based on the clock signal or the like supplied from the source control circuit board 2. Grayscale data is input to the data registers 17a and 17b from one data line 11a corresponding to the clock signal from the shift register circuit 15, and holds the corresponding grayscale data based on the clock signal. Reference numeral 21 is a data register for gradation control data, which holds corresponding gradation control data based on a clock signal. The output side of the data register 17a for odd data, which is the first group, is branched into two, one is connected to the latch circuit 18 and the other is connected to the output side of the corresponding data register 17b for even data. On the output side of the data register 17b for even data, a switching element 22 for selecting an output according to the gradation control data is provided.
The output of either the data register 17a for data or the data register 17a for odds to be paired is output to the latch circuit 1
Supply to 8. When the gradation data of pixels for one line is held in the data register 17, the data is latched by the latch circuit 1.
8 to the D / A converter 19 from the latch circuit 18.
Is supplied to. The D / A converter 19 converts the 6-bit digital signal into a source signal (analog signal) indicating the gradation of one pixel and supplies the source signal to the output buffer 20. Then, the source signal is supplied from the output buffer 20 to the signal line of the liquid crystal panel 1 to perform various displays on the display unit.

FIG. 4 shows an embodiment of outputting the gradation data to the data line 11 and the gradation control data to the data line 12. In this embodiment, since grayscale data of 2 ports (6 pixels) is supplied to the driving driver 4a in 1 clock, 640 clocks are used for SXGA and 800 clocks are used for UXGA. Key data can be supplied. FIG. 4 shows the case of SXGA. A HIGH (1) or LOW (0) signal is supplied to the data lines 11 and 12 for each clock, and in FIG. 4, the gradation data (6 bits) of each pixel is divided and displayed. Then, for example, in the case of the first clock, the first group "1111"
11,111111,111110 "and the second group"
111110, 111111, 111111 "and gradation control data" 0 "are simultaneously supplied to the driving driver 4a via the data lines 11 and 12, and at the next second clock, the first group" 111110, 111110, 11 ".
1110 "and the second group" 111110, 11111 "
1, 111111 "and gradation control data" 1 "are simultaneously supplied to the driving driver 4a via the data lines 11 and 12. This process is repeated for 640 clocks to obtain the gradation data of pixels in one line portion. Supply.

According to the present invention, when the grayscale data (odd data) of the first group and the grayscale data (even data) of the second group at the same clock have different values, the odd data and the even data are respectively supplied to the data line 11. Then, LOW (0) which is the first level is output to the data line 12 as the gradation control data. When the grayscale data (odd data) of the first group and the grayscale data (even data) of the second group have the same value at the same clock, the odd data remains as they are in the corresponding data line 1.
1 and outputs the same value to the even data side data line 11 as the output of the even data data line 11 at the previous clock, and outputs the same value to the data line 12 as the second level HIGH signal as the gradation signal data. Output (1).
Since the grayscale data of the first group and the grayscale data of the second group each have a pair of data, whether the grayscale data of both groups are the same or not depends on whether all the data of the pair have the same value. Determine whether

For example, in the case of FIG. 4, since the gradation control data of the (n-1) th clock is "0", the first group and the second group
The grayscale data of the groups are not the same, and odd data “111111 and 11111 are assigned to the data lines 11, respectively.
0,111111 ", even data" 111111,
111110 and 111110 "are output. Next, the nth
In the clock, since the gradation control data is "1", the first
The gradation data of the group and the second group are the same, and the data indicating the gradation of each pixel is “111111”.
111111, 111111 ". However, the output to the data line 11 is odd to the data line 11 of the first group.
Data "111111, 111111, 111111"
Is output as it is, and the same output as the data line 11 of the second group at the time of the previous clock (n−1th clock) is output to the data line 11 of the second group “111111, 111”.
110, 111110 "are output. Similarly, even at the (n + 1) th clock, the gradation control data is" 1 ", so the first
The data indicating the actual pixel gradations of the group and the second group are both “000000, 000000, 00000”.
0 ″, but odd on the data line 11 of the first group
Data "000000,000000,000000"
Is output as it is, and the same output as that at the n-th clock is output to the data lines 11 of the second group "111111, 11111."
0,111110 "is output. In this way, the first group (odd data) and the second group (even data) are output.
By setting the output of the data line 11 on the second group side to be the same as the output at the previous clock when the values are the same, it is possible to reduce switching between HIGH (1) and LOW (0) in the output. , EM even if the number of pixels and the number of gradations increase
The influence of I can be reduced.

When each data shown in FIG. 4 is supplied from the video data buffer 16 to the data registers 17 and 21, the switching element 22 is controlled by the value of the gradation control data to switch the data supplied to the latch circuit 18. That is, when the grayscale control data is “0”, the grayscale data of the actual pixel is output to the data line 11 of the second group.
Since the appropriate grayscale data is held in the data register 17b corresponding to the group, the latch circuit 18 has the second grayscale data.
The output from the group data register 17b is supplied. When the grayscale control data is "1", the output of the data line 11 of the second group is different from the grayscale data of the actual pixel, and the actual grayscale data of the pixel corresponding to the second group is the first group. Since it becomes the same as the gradation data of the pair, the output from the corresponding data register 17a of the first group is supplied to the latch circuit 18 as the gradation data of the second group. Therefore, the true grayscale data is always input to the grayscale data supplied to the latch circuit 18, and proper display can be performed.

As described above, according to the present invention, it is possible to reduce the influence of EMI while always realizing proper display, and it is possible to realize a display device suitable for upsizing. Further, the grayscale data of the first group and the grayscale data of the second group are set to the grayscale data of the pixels arranged close to each other, so that the grayscale data of the first group and the grayscale data of the second group have the same value. The ratio increases, and the effect of the present invention can be more efficiently received.

In this embodiment, the data register 1
7 and the latch circuit 18, the switching element 22 for supplying proper grayscale data to the latch circuit 18 is provided. However, in the present invention, proper data among the grayscale data of the first group or the second group is provided. It is only necessary to be able to supply the voltage, and various circuits such as a logic circuit may be adopted instead of the switching element. Further, the present invention is only required to finally supply a proper signal to the signal line of the liquid crystal panel, and the location of the switching element, the logic circuit, etc. is not limited to between the data register 17 and the latch circuit 18. The operation of the switching element or the logic circuit will be described with reference to FIG. Also in this case, as in the above-described embodiment, 36 data lines for supplying the grayscale data and one data line for supplying the grayscale control data are provided, and the 18 data lines of the first group are odd. The data is output, and the even data is output to the 18 data lines of the second group. When data is input, the output of the 37th data line, which is gradation control data, is confirmed. When the 37th data is "0",
The odd data is output to the odd line, and the even data is output to the even line. When the 37th data is 1, the odd data is output to both the odd line and the even data. This odd data and even
The data means the data input to the element that selects the output, and the odd line and the even line mean the data line connected to the output side of this element.

It should be noted that forms other than the above-described embodiment are possible without departing from the scope of the present invention. For example, the combination of pixels corresponding to the first group and the second group may be other than one set of RGB, respectively, and the first group and the second group may be divided by a combination other than odd data and even data. Although each pixel has only two display states, that is, on and off, the display state of each pixel is shown between the control circuit unit and the driving driver in a mode in which multiple gradations are reproduced on the display unit in a plurality of frames. The present invention is also effective when there are many data lines for supplying video data. At this time, the video data supplied to the data line does not indicate the gradation state of the pixel but indicates the on / off display state. The driving driver may be formed not on the TCP but on the glass substrate of the liquid crystal panel, or the control circuit unit may be formed on the glass substrate.

[0026]

According to the present invention, the number of signals for switching between HIGH and LOW in video data can be reduced while realizing proper display, which is advantageous in terms of EMI.
In particular, it is very effective for a display device that requires high image quality and high definition as the display section becomes larger.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a signal flow to a driving driver connected to a signal line of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing a configuration of a driver for driving the liquid crystal display device according to the first embodiment.

FIG. 4 is a diagram for explaining output of gradation data to data lines and gradation control data to data lines of the liquid crystal display device according to the first embodiment.

FIG. 5 is a flowchart illustrating an operation of a logic circuit or the like.

FIG. 6 is a diagram schematically showing an arrangement of pixels on a liquid crystal panel.

FIG. 7 is a diagram schematically showing the flow of signals to a conventional driving driver.

FIG. 8 is a diagram illustrating grayscale data supplied from a source control circuit to a driving driver.

[Explanation of symbols]

1 LCD panel 2 Source control circuit board 4a Driver for driving 15 Shift register circuit 16 video data buffer 17 Data register 18 Latch circuit 22 Switching element

Continued front page    (72) Inventor Hiroshi Sano             3-201 Minamiyoshikata, Tottori City, Tottori Prefecture Tottori             Sanyo Electric Co., Ltd. (72) Inventor Kunihito Yamamura             3-201 Minamiyoshikata, Tottori City, Tottori Prefecture Tottori             Sanyo Electric Co., Ltd. F-term (reference) 2H093 NC11 NC34 ND02                 5C006 BB16 BC12 BC16 FA32                 5C080 AA10 BB05 CC03 DD12 EE29                       FF11 FF12 JJ02 JJ06 JJ07

Claims (7)

[Claims] 1. In a display device having a display unit in which a plurality of pixels are arranged in a matrix and displaying various images on the display unit, pixel data indicating a display state of each pixel is connected to the pixel. A plurality of driving drivers supplied to the signal line, a control circuit unit for outputting video data indicating a display state of each pixel for generating the pixel data, and video control data corresponding to the video data, and the control circuit And a plurality of data lines connected to the driving driver and supplying a plurality of pixels as a set with video data and video control data of the plurality of pixels from the control circuit unit to the driving driver. A display device which sequentially and repeatedly outputs video data and video control data of each set via a circuit to supply video data of pixels for one line of the display section to the driving driver. The control circuit section divides the video data of one set of a plurality of pixels into a first group and a second group which form a pair, and when the pair of video data of the first group and the second group has different values, , The video data of the first group and the video data of the second group are output to the corresponding data lines, and the video control data is set to the first level.
When the paired video data of the group and the second group have the same value, the video data of the first group is output to the corresponding data line, and the data line corresponding to the second group corresponds to the previous second group. Output the same value as the signal line output, and set the video control data to the second level,
When the video control data is at the first level, the driving driver converts the video data of the first and second groups into pixel data and supplies the pixel data to the corresponding signal lines, and when the video control data is at the second level. Supplies the pixel data obtained by converting the video data of the first group to the signal line corresponding to the first group, and the video data of the first group paired with the video data of the second group to the signal line corresponding to the second group. A display device, which supplies pixel data obtained by converting data. 2. In a display device having a display section in which a plurality of pixels are arranged in a matrix and displaying various images on the display section, pixel data indicating a display state of each pixel is connected to the pixel. A plurality of driving drivers supplied to the signal line, and a control circuit unit for supplying the driving driver with video data indicating a display state of each pixel for generating the pixel data and video control data corresponding to the video data. And dividing the video data into a first group and a second group that form a pair with a plurality of pixels as a set, and the driving driver is configured such that when the video control data is at the first level, the first and second groups are formed. Image data of each of the above is converted into pixel data and supplied to the corresponding signal line, and the image control data is converted into the second
When the level is set, the pixel data obtained by converting the video data of the first group is supplied to the signal line corresponding to the first group, and the signal line corresponding to the second group is paired with the video data of the second group. A display device, which supplies pixel data obtained by converting video data of the first group. 3. In a display device having a display section in which a plurality of pixels are arranged in a matrix and displaying various images on the display section, pixel data indicating a display state of each pixel is connected to the pixel. A plurality of driving drivers supplied to the signal line, a control circuit unit for outputting video data indicating a display state of each pixel for generating the pixel data, and video control data corresponding to the video data, and the control circuit And a plurality of data lines that are connected to the driving driver and that output video data and video control data for the plurality of pixels as a set from the control circuit unit to the driving driver. A display device which sequentially and repeatedly outputs video data and video control data of each set via a circuit to supply video data of pixels for one line of the display section to the driving driver. The control circuit section divides the video data of one set of a plurality of pixels into a first group and a second group which form a pair, and when the pair of video data of the first group and the second group has different values, , The video data of the first group and the video data of the second group are output to the corresponding data lines, and the video control data is set to the first level.
When the paired video data of the group and the second group have the same value, the video data of the first group is output to the corresponding data line, and the data line corresponding to the second group corresponds to the previous second group. A display device, which outputs the same value as the output of the signal line for controlling and sets the video control data to the second level. 4. A liquid crystal enclosed between a pair of substrates, a pixel electrode formed in each pixel of one substrate, a switching element connected to the pixel electrode, and a signal connected to the switching element. 4. The display device according to claim 1, further comprising a line, wherein pixel data is supplied to each signal line to control an alignment state of liquid crystals in the pixel. 5. The display device according to claim 1, wherein the video data is data indicating a gradation displayed in each pixel. 6. Each pixel is set to display one of red (R), green (G) and blue (B) colors, and at least one set of video data of the first group and the second group is set. 6. The display device according to claim 1, wherein the display device corresponds to the R, G, and B pixels. 7. The ODD data among the video data of the pixels lined up on one line on the display unit is set to the first group, and EVEN is set.
2. The data is grouped into a second group.
7. The display device according to claim 6.