JP2003018857A - Switching power supply device, control circuit used therefor, and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply device whose surge voltage generated in a light load state or in a no-load state can be reduced. SOLUTION: This switching power supply device has a transformer 38, a full-bridge type switching circuit 37 which is provided on the primary side of the transformer 38 and includes first and second arms, output cicuits 42 and 45 provided on the secondary side of the transformer 38, and a control circuit 46 which carries out the phase-shift control of the switching circuit 37. The control circuit 46 changes pulse widths of output signals Pulse-C and D driving the second arm according to the load conditions of the output circuits 42 and 45.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device and a control circuit used therein, and more particularly to a switching power supply device using a phase shift control method and a control circuit used therein. The present invention also relates to a switching power supply control method, and more particularly to a switching power supply control method using a phase shift control method.

[0002]

2. Description of the Related Art So-called DC / DC converters have been known as switching power supply devices. In a typical DC / DC converter, a DC input is once converted into an AC using a switching circuit, then this is transformed (boosted or stepped down) with a transformer, and then this is converted into DC using an output circuit. This is a device for producing a direct current output having a voltage different from the input voltage. Here, a so-called full-bridge circuit is generally used as a switching circuit of a switching power supply device that requires a large capacity, but as a drive system capable of reducing the switching loss generated in this type of switching circuit. A so-called phase shift control method is known.

FIG. 13 shows a conventional switching power supply device 1.
It is a circuit diagram which shows 0.

As shown in FIG. 13, a conventional switching power supply device 10 includes an input capacitor 12 connected between both ends of an input power supply 11 and a first to a fourth transistor 1.
A switching circuit 17 composed of 3 to 16 and a transformer 1
8 and a rectifying circuit 21 including diodes 19 and 20
A smoothing circuit 24 including an inductor 22 and a capacitor 23, and a control circuit 25 that controls the operation of the switching circuit 17, and the output of the smoothing circuit 24 is the load 2
Connected to 6. Further, a parasitic inductance 27 due to the wiring exists between the switching circuit 17 and the input capacitor 12.

The control circuit 25 is a circuit that monitors the output voltage Vo from the smoothing circuit 24 and controls the operation of the switching circuit 17 so that the output voltage Vo becomes a predetermined value based on the output voltage Vo. Its output signal P
pulse-A to Pulse-D are generated. As a control circuit for performing such phase shift control, for example,
The control circuit described in US Pat. No. 5,291,384 is known.

FIG. 14 shows a conventional switching power supply device 1.
FIG. 6 is a timing chart showing the operation of 0.

As shown in FIG. 14, in the phase shift control, Pulse-A and Pulse-B are alternately set to a high level across a predetermined dead time, and P-
Pulse-C is phase-shifted with respect to Pulse-B, and Pulse-D is phase-shifted with respect to Pulse-A. Here, the voltage Vm on the primary side of the transformer 18
The waveform of t is the amount of phase shift of Pulse-D with respect to Pulse-A, and the pulse with respect to Pulse-B.
It depends on the amount of phase shift of se-C. In particular,
As shown in FIG. 14, Pulse-A and Pulse-A
During the period in which both -D are at the high level, the first transistor 13 and the fourth transistor 1
Since both 6 are in the ON state, the voltage Vmt on the primary side of the transformer 18 becomes Vin, while Pulse-B and P
During the period in which both ulse-C are at the high level, both the second transistor 14 and the third transistor 15 are turned on, so that the voltage Vmt on the primary side of the transformer 18 becomes -Vin. . In other periods, the voltage Vmt on the primary side of the transformer 18 is zero.

Therefore, the power transmitted to the secondary side of the transformer 18 is Pulse-D for Pulse-A.
Phase shift amount and Pulse-B for Pulse-B
When the voltage Vin of the input power supply 11 becomes smaller depending on the phase shift amount of −C, the control circuit 25 causes the pulse
-Pulse-D phase shift amount with respect to -A and Pul
The amount of phase shift of Pulse-C with respect to se-B is reduced, whereby Pulse-A and Pulse-
Period when D is high level, and Pulse
The period in which both e-B and Pulse-C are at the high level is lengthened. On the other hand, when the voltage Vin of the input power supply 11 increases, the control circuit 25 increases the amount of phase shift of Pulse-D with respect to Pulse-A and the amount of phase shift of Pulse-C with respect to Pulse-B, thereby increasing the amount of Pulse-A. And Pulse-D are both at a high level, and Pulse-B and P
The period in which the pulse-C is at the high level is shortened. Therefore, when the load 26 is in the light load state or the no-load state, the period in which both Pulse-A and Pulse-D are high level, and the period in which both Pulse-B and Pulse-C are high level are It becomes zero, and no electric power is transmitted to the secondary side of the transformer 18.

FIG. 15 is a timing chart showing the operation of the conventional switching power supply device 10 in the light load state or the no load state.

As shown in FIG. 15, in the conventional switching power supply device 10, when a light load state or a no load state is set, the phase of Pulse-C is Pulse-C.
Shifted about 180 ° (about half a cycle) with respect to B
Since the phase of e-D shifts by about 180 ° with respect to Pulse-A, the period in which both Pulse-A and Pulse-D are at a high level, and both Pulse-B and Pulse-C are at a high level. There will be no period. As a result, the voltage Vm on the primary side of the transformer 18
t is fixed at zero. At this time, in the conventional switching power supply device 10, as shown in FIG.
Pulse-A and Pulse-C have substantially the same waveform, and Pulse-B and Pulse-D have substantially the same waveform.

[0011]

However, like the conventional switching power supply device 10, in the light load state or the no load state, Pulse-A and Pulse-C are used.
Waveforms are substantially the same, and Pulse-B and Pulse-B
If the waveform of se-D becomes substantially the same, Pulse-
B and Pulse-D change to high level (time t2), Pulse-A and Pulse-C
There is a problem that a large surge voltage is generated in the switching circuit 17 at the timing (time t3) when the voltage changes to the high level.

FIGS. 16A to 16C are schematic diagrams of the switching circuit 17 for explaining this.

First, Pulse-A and Pulse-C
Is high level, and Pulse-B and Pulse-
At the timing when D is at the low level (time t0), the voltage between both ends of the second and fourth transistors 14 and 16 is Vin, as shown in FIG.
The voltage is charged in the capacitance component C14 between both ends of the second transistor 14 and the capacitance component C16 between both ends of the fourth transistor 16.

Next, Pulse-A and Pulse-C
At the timing (time t1) when is changed from the high level to the low level, as shown in FIG.
Although the first and third transistors 13 and 15 change from the on-state to the off-state, the second and fourth transistors 14 and 16 are maintained in the off-state. Fourth transistor 14, 16
The state in which the voltage Vin is charged in the capacitance components C14 and C16 between both ends of is maintained.

Pulse-B and Pulse-
At the timing when D changes from the low level to the high level (time t2), as shown in FIG. 16C, the second and fourth transistors 14 and 16 change from the off state to the on state. , The capacitance component C14 across the second transistor 14 and the capacitance component C16 across the fourth transistor 16 are discharged substantially simultaneously. In this case, the electric charge charged in the capacitance component C14 between both ends of the second transistor 14 generates a current I1, and the capacitance component C1 between both ends of the fourth transistor 16 is generated.
The electric charge charged in 6 generates a current I2, so that the total current I1 + I2 flows through the parasitic inductance 27 existing between the switching circuit 17 and the input capacitor 12. This makes the first
A large surge voltage is generated between both ends of the third transistors 13 and 15.

Similarly, Pulse-A and Pulse-
Even at the timing when C changes from the low level to the high level (time t3), the capacitance component C13 between both ends of the first transistor 13 and the capacitance component C15 between both ends of the third transistor 15 are discharged substantially at the same time. As a result, a large surge voltage is generated across the second and fourth transistors 14 and 16.

Since such a surge voltage exerts a large stress on these first to fourth transistors 13 to 16, depending on the case, the surge voltage may cause the first stress.
-The fourth transistors 13 to 16 may be destroyed.

Therefore, an object of the present invention is to provide a switching power supply device in which the surge voltage generated in a light load state or a no load state is reduced.

Another object of the present invention is to provide a control circuit used in a switching power supply device, which is capable of reducing a surge voltage generated in a light load state or a no load state. is there.

Still another object of the present invention is to provide a control method of a switching power supply device capable of reducing a surge voltage generated in a light load state or a no load state.

[0021]

The object of the present invention is to:
A transformer, a full-bridge type switching circuit provided on the primary side of the transformer and including first and second arms, and an output circuit provided on the secondary side of the transformer,
A switching power supply device comprising a control circuit for performing phase shift control of the switching circuit, wherein the control circuit changes a pulse width of an output signal for driving the second arm based on a load state of the output circuit. It is achieved by the switching power supply device.

In a preferred aspect of the present invention, the control circuit sets the pulse width of the output signal for driving the second arm to the first pulse when the output circuit is in the first load state. The pulse width of the output signal for driving the arm is set to be substantially equal to the pulse width of the output signal for driving the arm, and the pulse width of the output signal for driving the second arm is set to the second width when the output circuit is in the second load state. The width is set to be different from the pulse width of the output signal for driving the first arm.

In a further preferred aspect of the present invention, the first load state is a normal load state, and the second load state is a light load state or a no load state.

[0024] In a further preferred aspect of the present invention, the control circuit sets the pulse width of the output signal for driving the second arm to the second pulse when the output circuit is in the second load state. The width is set to be shorter than the pulse width of the output signal for driving the first arm.

[0025] In a further preferred aspect of the present invention, the control circuit, when the output circuit is in the second load state, controls the high-side switch constituting the first arm after turning on. The high side switch forming the second arm is controlled to be turned on, and the low side switch forming the second arm is turned on after the low side switch forming the first arm is turned on. Control.

[0026] In a further preferred aspect of the present invention, the control circuit is configured such that, when the output circuit is in the second load state, the high-side switch and the second switch which constitute the first arm. Control is performed such that the high-side switches forming the first arm are turned off substantially at the same time, and the low-side switches forming the first arm and the low-side switches forming the second arm are substantially controlled. Control to turn off at the same time.

[0027] In a further preferred aspect of the present invention, the control circuit sets a timing for turning on the high-side switch forming the first arm when the output circuit is in the second load state. The time difference from the timing of turning on the high-side switch forming the second arm, the timing of turning on the low-side switch forming the first arm, and the low-side switch forming the second arm The time difference from the turn-on timing is the first
Set based on the dead time of the arm.

In another preferred aspect of the present invention, the control circuit turns on the high-side switch constituting the first arm when the output circuit is in the second load state. And a time difference between a timing for turning on the high-side switch forming the second arm, a timing for turning on the low-side switch forming the first arm, and the low-side switch forming the second arm. The time difference from the timing of turning on is set based on the clock signal.

In a further preferred aspect of the present invention, the control circuit generates an output signal for driving the first arm based on a clock signal and outputs an output signal for driving the second arm. It is generated based on an internal signal activated in the dead time of one arm.

In a further preferred aspect of the present invention, the control circuit comprises a sawtooth wave generating means for generating a sawtooth wave in response to the internal signal, and an output voltage of the output circuit or a voltage corresponding thereto. The first comparison signal and the second reference voltage are compared with each other, and the second comparison is performed based on the first comparison signal and the second reference voltage. First to generate a signal
And a second comparator that compares the first comparison signal with the sawtooth wave and generates a third comparison signal based on the comparator, at least the second comparison signal and the third comparison signal. Means for generating an output signal for driving the second arm based on the signal.

In a further preferred aspect of the present invention, the first comparator has a hysteresis.

In a further preferred aspect of the present invention, a plurality of capacitors and a plurality of snubber circuits respectively provided in parallel with each of the switches included in the switching circuit, the first arm and the transformer. And an inductor inserted between the two.

The object of the present invention is also a control circuit for controlling a phase shift of a switching power supply device including a full-bridge type switching circuit, which is a first circuit for driving a first arm of the switching power supply device. First means for generating an output signal and second means for generating a second output signal for driving a second arm of the switching power supply device
Means, a third means for detecting the output voltage of the switching power supply device, and a fourth means for changing the pulse width of the second output signal based on the output voltage detected by the third means. And a control circuit.

In a preferred embodiment of the present invention, the fourth means is generated by the second means when the output voltage detected by the third means is less than a predetermined voltage. When the pulse width of the second output signal is output without substantially changing the output voltage and the output voltage detected by the third means exceeds the predetermined voltage, the second means outputs the pulse voltage. The pulse width of the generated second output signal is shortened and output.

In a further preferred aspect of the present invention, the pulse width is shortened by the fourth means, but the second means is used.
This is done by deactivating the initial part of the activation period of the output signal of.

The above object of the present invention is also a control circuit for controlling a phase shift of a switching power supply device including a full-bridge type switching circuit, which generates a pair of first internal signals which are alternately at a high level. And a first means for receiving the first internal signal and giving a first dead time to the first internal signal to generate a pair of first output signals for driving the first arm of the switching power supply device. 2 means and 3rd means for generating a sawtooth wave,
Fourth means for generating a pair of second internal signals that alternately become high level based on at least the output voltage of the switching power supply device and the sawtooth wave; and the output voltage exceeding a predetermined voltage. In response, a fifth means for generating a pair of third internal signals by deactivating a predetermined period of the activation period of the second internal signal; and the third internal signal. And a sixth means for generating a pair of second output signals for driving the second arm of the switching power supply by receiving the second dead time.

In a preferred aspect of the present invention, the fifth means compares the output voltage or a voltage corresponding thereto with a first reference voltage, and based on this, the first reference voltage is used.
Error comparator for generating the comparison signal, a comparator for comparing the first comparison signal with the second reference voltage and generating a second comparison signal based on the error amplifier, and a comparator for receiving the first output signal. A first logic circuit that generates a fourth internal signal that is activated in the first dead time based on the above, the second comparison signal and the fourth internal signal, and based on these, A second logic circuit that generates a fifth internal signal indicating a predetermined period, a second logic circuit that receives the second internal signal and the fifth internal signal, and generates the third internal signal based on these signals. 3 logic circuits.

[0038] In a further preferred aspect of the present invention, the third means includes a ramp circuit which minimizes the sawtooth wave during a period in which the fourth internal signal is in an active state.

In a further preferred aspect of the present invention, the ramp circuit increases the level of the sawtooth wave during a period in which the fourth internal signal is inactive.

In another preferred embodiment of the present invention, the fifth means compares the output voltage or a voltage corresponding thereto with a first reference voltage, and based on this, the first comparison signal. For receiving the second comparison signal and the clock signal, and a comparator for comparing the first comparison signal with the second reference voltage and generating a second comparison signal based on the error amplifier. A first logic circuit that generates a fourth internal signal indicating the predetermined period based on these, a second internal signal and the fourth internal signal, and the third internal circuit based on these A second logic circuit for generating an internal signal.

The object of the present invention is also a control circuit for controlling a switching power supply device having first and second arms each of which is composed of a high-side switch and a low-side switch, and the output voltage of the switching power supply device. A pulse for controlling the high side switch of the first arm and a pulse for controlling the low side switch of the second arm, and a pulse for controlling the high side switch of the second arm based on And first means for controlling overlapping of pulses for controlling the low side switch of the first arm, a pulse for controlling the high side switch of the first arm and the low side of the second arm Overlapping pulses for controlling the switch and pulses for controlling the high side switch of the second arm and the low side switch of the first arm. A pulse for controlling the high-side switch of the second arm and a pulse for controlling the low-side switch of the second arm in response to the overlap of the pulses for controlling the switch H being zero. And a second control means.

[0042] In a preferred aspect of the present invention, the first means alternately turns on a high side switch forming the first arm and a low side switch forming the first arm. Means and fourth means for generating a sawtooth wave that starts to rise at a timing when a high-side switch that forms the first arm turns on and a timing that a low-side switch that forms the first arm turns on, It includes a fifth means for controlling a high-side switch forming the second arm and a low-side switch forming the second arm based on at least the output voltage of the switching power supply device and the sawtooth wave.

The object of the present invention is also a method of driving a switching power supply device including a full-bridge type switching circuit, wherein the first arm of the switching circuit is used in a light load state or a no load state. The high-side switch constituting the high-side switch and the high-side switch constituting the second arm of the switching circuit are continuously turned on, and the low-side switch constituting the first arm and the low-side side constituting the second arm are continuously turned on. This is achieved by a method of driving a switching power supply device, which is characterized by continuously turning on a switch.

The object of the present invention is also a method of driving a switching power supply device including a full-bridge type switching circuit, wherein the first arm of the switching circuit is used in a light load state or a no load state. This is achieved by a method of driving a switching power supply device, characterized in that a pulse width of an output signal to be driven and a pulse width of an output signal to drive the second arm of the switching circuit are different from each other by a predetermined width.

In a preferred aspect of the present invention, the predetermined width is substantially equal to either the dead time or the activation period of the clock signal.

[0046]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of the present invention will be described in detail.

FIG. 1 is a circuit diagram showing a switching power supply device 30 according to a preferred embodiment of the present invention.

As shown in FIG. 1, the switching power supply device 30 according to the present embodiment is a full power supply including an input capacitor 32 connected between both ends of an input power supply 31 and first to fourth transistors 33 to 36. Bridge type switching circuit 37, transformer 38, switching circuit 37
An inductor 39 inserted between the transformer 38 and the transformer 38,
A rectifying circuit 42 including diodes 40 and 41, and a smoothing circuit 45 including an inductor 43 and a capacitor 44.
And a control circuit 4 for controlling the operation of the switching circuit 37
6, the control circuit 46, and the first to fourth transistors 33 to
The output circuit including the rectifier circuit 42 and the smoothing circuit 45 is connected to the load 51.
Further, a parasitic inductance 68 due to the wiring exists between the switching circuit 37 and the input capacitor 32. Here, the first to fourth insulating circuits 47 to 50
The first to first output signals Pulse-A to Pulse-D output from the control circuit 46 while securing the insulation state between the primary side circuit and the secondary side circuit of the switching power supply device 30.
This is a circuit that supplies the gates of the fourth transistors 33 to 36, respectively.

Further, as shown in FIG. 1, the switching circuit 37 includes the first to fourth transistors 33 to 36.
Capacitors 5 to 5 connected in parallel to
5 is further included and these capacitors 52-55
Plays a role of reducing switching loss of the first to fourth transistors 33 to 36 by resonance with the inductor 39. Further, the switching circuit 37 includes the first to
Further included are snubber circuits 56-59 connected in parallel to the fourth transistors 33-36, respectively.
˜63 and capacitors 64 to 67 are connected in series. The snubber circuits 56 to 59 play a role of reducing the surge voltage applied to the first to fourth transistors 33 to 36.

The control circuit 46 is a circuit that monitors the output voltage Vo from the smoothing circuit 45 and controls the operation of the switching circuit 37 based on the output voltage Vo so that the output voltage Vo reaches a predetermined value. Its output signal P
pulse-A to Pulse-D are generated.

FIG. 2 is a circuit diagram of the control circuit 46.

As shown in FIG. 2, the control circuit 46 is
The oscillator 70 for generating the clock signal CLK is provided, and the clock signal CLK is supplied to the clock input terminal (CK) of the data latch circuit 71. Here, the oscillator 70
The frequency of the clock signal CLK generated by the frequency setting signal FREQ. It can be set by SET. Since the inverted output terminal (inverted Q) of the data latch circuit 71 is connected to the data input terminal (D), the internal signal Pulse-A output from the inverted output terminal (inverted Q) of the data latch circuit 71. The logic level of the internal signal Pulse-B output from the non-inverting output terminal (Q) and the logic level of the clock signal CLK
It will be inverted in response to the rising edge of.

The internal signal Pulse-A 'and the internal signal Pulse-B' are supplied to the first dead time generation circuit 72 and the second dead time generation circuit 73, respectively, and these first dead time generation circuit 72 is supplied. And the output signal Pulse− of the second dead time generation circuit 73.
A and the output signal Pulse-B are supplied to the first and second insulating circuits 47 and 48 shown in FIG. 1, respectively.

The control circuit 46 also includes a ramp circuit 74, and a transistor 75 whose gate receives the clock signal CLK is connected between the input terminal 74a of the ramp circuit 74 and the ground potential GND. As a result, the input terminal 74a of the ramp circuit 74 is grounded each time the clock signal CLK goes high, and in response to this, the ramp circuit 7 is grounded.
4 can generate the sawtooth wave RAMP-1 in response to the cycle of the clock signal CLK.

Further, the control circuit 46 includes a voltage dividing circuit 78 including resistors 76 and 77, and the voltage dividing circuit 78 generates an error voltage E / A- obtained by dividing the output voltage Vo. The error voltage E / A− is supplied to the inverting input terminal (−) of the error amplifier 79 and compared with the reference voltage Vref, and based on the result, the first comparison signal COMP-1.
Is generated. That is, the voltage level of the first comparison signal COMP-1 output from the error amplifier 79 is determined according to the magnitude relationship between the error voltage E / A- and the reference voltage Vref and the voltage difference between them, and the error voltage E / A- is the reference voltage Vr
The higher it is than ef, the first comparison signal COMP-
1 becomes lower, and conversely, the lower the error voltage E / A− is than the reference voltage Vref, the first comparison signal CO
The voltage of MP-1 will be high. Here, the reference voltage Vref
Is a voltage generated inside the control circuit 46 and is set based on the target value of the output voltage Vo.

The first comparison signal COMP-1 is supplied to the inverting input terminal (-) of the first comparator 80 and the non-inverting input terminal (+) of the second comparator 81. First
The output voltage V82 of the voltage source 82 is supplied to the non-inverting input terminal (+) of the comparator 80 of
In the first comparator 80, the first comparison signal C
When the level of OMP-1 is higher than the output voltage V82 of the voltage source 82, the output of the second comparison signal COM
P-2 becomes low level and the first comparison signal COMP-
When the level of 1 is lower than the output voltage V82 of the voltage source 82, the output of the second comparison signal COMP-2 becomes high level. In this specification, the level of the first comparison signal COMP-1 is the output voltage V82 of the voltage source 82.
The higher state is called the "normal load state", and conversely the first
A state in which the level of the comparison signal COMP-1 is lower than the output voltage V82 of the voltage source 82 may be referred to as a “light load state” or a “no load state”.

On the other hand, the inverting input terminal (-) of the second comparator 81 has a sawtooth wave RAMP-1 and a voltage source 83.
The signal RAMP-2 superimposed with the DC voltage V83 is supplied to the second comparator 81. Therefore, in the second comparator 81, when the level of the first comparison signal COMP-1 is higher than the level of the signal RAMP-2. The output of the third comparison signal COMP-3 becomes high level,
The level of the first comparison signal COMP-1 is the signal RAMP-
When it is lower than the level of 2, the output of the third comparison signal COMP-3 is low level. In this embodiment, the output voltage V82 of the voltage source 82 and the voltage source 83
The output voltage V83 of each is set to be substantially equal.

The second comparison signal COMP-2 is supplied to one input end of the non-OR circuit (NOR) 84, and the other input end of the non-OR circuit (NOR) 84 is clocked by the inverter 85. An inverted signal of the signal CLK is supplied.
Further, the third comparison signal COMP-3 is supplied to one input end of the non-OR circuit (NOR) 86, and the clock signal C is supplied to the other input end of the non-OR circuit (NOR) 86.
LK is supplied.

Further, the control circuit 46 includes a PWM latch circuit 87 composed of an RS flip-flop,
The reset input terminal (R) has a non-OR circuit (NO
The signal RESET, which is the output of R) 84, is supplied to the set input terminal (S) of the non-OR circuit (NOR) 86.
The signal SET which is the output of is supplied. The internal signal PWM output from the inverted output terminal (inverted Q) of the PWM latch circuit 87 is commonly supplied to one input terminal of the exclusive non-OR circuit (XNOR) 88 and the exclusive OR circuit (XOR) 89. The other input ends of the exclusive non-OR circuit (XNOR) 88 and the exclusive OR circuit (XOR) 89 are
The internal signal Pulse-A ′ is commonly supplied.

Further, the control circuit 46 outputs the output signal Plus.
A non-logical sum circuit (NOR) 90 that receives e-A and the output signal Plus-B is provided, and an internal signal DELAYA-B that is an output thereof is supplied to one input end of a non-logical product circuit (NAND) 91. To be done. Non-logical product circuit (NAND)
The second comparison signal COMP-2 is supplied to the other input terminal of 91. In addition, a non-logical product circuit (NAND) 91
Of the non-logical product circuit (NAND) 92 and 93 is commonly supplied to the non-logical product circuit (NAND)
At the other input terminals of 92 and 93, the output of the exclusive non-OR circuit (XNOR) 88 and the exclusive OR circuit (XO
R) 89 outputs are respectively supplied.

The internal signal Pulse-C 'which is the output of the non-logical product circuit (NAND) 92 and the non-logical product circuit (NAN)
The internal signal Pulse-D ′, which is the output of D) 93, is supplied to the third dead time generation circuit 94 and the fourth dead time generation circuit 95, respectively, and the third dead time generation circuit 94 and the fourth dead time generation circuit 94 are supplied. Dead time generation circuit 9
5 output signal Pulse-C and output signal Pulse-
D is the third and fourth insulating circuits 4 shown in FIG. 1, respectively.
9 and 50 are supplied.

FIG. 3 is a circuit diagram showing a concrete circuit configuration of the first to fourth dead time generation circuits 72, 73, 94 and 95.

As shown in FIG. 3, each of the first to fourth dead time generation circuits 72, 73, 94 and 95 includes a delay circuit 96 and a non-logical sum circuit (NOR) 97, and The corresponding internal signals Pulse-A ′ to Pulse- are connected to one input terminal of the logical sum circuit (NOR) 97.
D'is directly supplied to the other input terminal of the non-OR circuit (NOR) 97 by the delay circuit 96 and the internal signal Pul.
delay signal P obtained by delaying se-A 'to Pulse-D'
pulse-A "to Pulse-D" are supplied. Here, the delay amount by the delay circuit 96 can be set by the delay amount setting signal DELAYSETA-B for the first and second dead time generation circuits 72, 73.
The third and fourth dead time generation circuits 94 and 95 can be set by the delay amount setting signal DELAYSETC-D. Delay amount setting signal DELAYSET
A delay amount set by A-B (TdelayA-
B) is the first and second dead time generation circuits 72, 7
3 is substantially equal to each other, and similarly, the delay amount (TdelayC-D) set by the delay amount setting signal DELAYSETC-D is substantially equal to each other in the third and fourth dead time generation circuits 94 and 95. .

FIG. 4 is a timing chart showing the operation of the first to fourth dead time generation circuits 72, 73, 94 and 95.

As shown in FIG. 4, the delay signal Puls
The waveforms e-A "to Pulse-D" are output because they are delayed by the delay amount (TdelayA-B or TdelayC-D) by the delay circuit 96 with respect to the corresponding internal signals Pulse-A 'to Pulse-D', respectively. Signal Pu
lse-A to Pulse-D are corresponding internal signals Pu.
lse-A 'to Pulse-D' and the delayed signal Pulses
All of e-A "to Pulse-D" are high level during the low level period. Therefore, the output signal P
pulse-A to Pulse-D are corresponding delayed signals P.
pulse-A "to Pulse-D" rising in response to the falling edges of the corresponding internal signal Pulse-
The waveform has a falling edge in response to the rising edges of A ′ to Pulse-D ′.

Next, the operation of the control circuit 46 will be described.

FIG. 5 shows the control circuit 4 in the normal load state.
6 is a timing chart showing the operation of No. 6. In FIG. 5, "88OUT" is an exclusive non-OR circuit (XNO
R) means the output level of 88, "89OUT" means the output level of the exclusive OR circuit (XOR) 89,
“91 OUT” means the output level of the non-logical product circuit (NAND) 91.

As shown in FIG. 5, in the normal load state, the level of the first comparison signal COMP-1 is higher than the output voltage V82 of the voltage source 82, and therefore the output of the first comparator 80. Second comparison signal COMP-2
The level of is fixed to low level. On the other hand, the third comparison signal COMP-3 which is the output of the second comparator 81.
Has a level of RAMP-2 equal to the first comparison signal COMP-.
The level of RAMP-2 is higher than the level of the first comparison signal COMP-1 during the period when the level is lower than 1, that is, during a predetermined period (first half of the clock cycle) from the rising of the clock signal CLK. During the period, that is, in the latter half of the clock cycle, it becomes low level.

Therefore, the PWM latch circuit 87 is reset in response to the rising edge of the clock signal CLK, and the level of the RAMP-2 is the first comparison signal COMP.
It will be set at the timing exceeding the level of -1. As a result, the exclusive OR circuit (XNO
The output (88OUT) of the R) 88 and the output (89OUT) of the exclusive OR circuit (XOR) 89 are the RAMP-2.
Has a waveform that is inverted at the timing when the level of exceeds the level of the first comparison signal COMP-1.

Since the level of the second comparison signal COMP-2 is fixed at the low level, the output (91OUT) of the non-logical product circuit (NAND) 91 is fixed at the high level. Therefore, the internal signal Pulse-C '
Is the output (88) of the exclusive OR circuit (XNOR) 88.
OUT) and the internal signal Pulse-D '
Is the output (89OU) of the exclusive OR circuit (XOR) 89.
It becomes an inverted signal of T). The internal signals Pulse-C 'and Pulse-D' thus generated are given dead times by the third and fourth dead time generation circuits 94 and 95, and output signals P as shown in FIG.
pulse-C and pulse-D are obtained. Referring to FIG. 5, output signals Pulse-C and Pulse-D
Of the output signals Pulse-A and Pulse-B
On the other hand, it can be seen that the waveforms are each phase-shifted by a predetermined amount.

The output signals Pulse-A to Pulse-D thus generated by the control circuit 46 are transmitted through the first to fourth insulating circuits 47 to 50 as described above.
It is supplied to the gate electrodes of the first to fourth transistors 33 to 36, respectively. This enables Pulse-A and Pu
During a period in which all of lse-D are at the high level, both the first transistor 33 and the fourth transistor 36 are in the ON state, so that the transformer 38
The voltage Vmt on the next side becomes Vin, and Pulse-B and P
During the period in which both ulse-C are at the high level, both the second transistor 34 and the third transistor 35 are turned on, so that the voltage Vmt on the primary side of the transformer 38 becomes -Vin. . In other periods, the voltage Vmt on the primary side of the transformer 38 is zero.

As a result, Pulse-A and Pulse-A
-Pul and D are both high level
Power corresponding to the period when both se-B and Pulse-C are at high level is transmitted to the secondary side of the transformer 38. As apparent from FIG. 5, Puls
During a period in which both e-A and Pulse-D are at a high level and a period in which both Pulse-B and Pulse-C are at a high level, the level of RAMP-2 is the first comparison signal COMP-. These periods are determined based on the level of the first comparison signal COMP-1 because it depends on the timing of exceeding the level of 1.
Specifically, the lower the level of the first comparison signal COMP-1 (the higher the output voltage Vo), the shorter the period, and the smaller the power transmitted to the secondary side of the transformer 38, and vice versa. , The higher the level of the first comparison signal COMP-1 (the lower the output voltage Vo), the longer the period, and the larger the power transmitted to the secondary side of the transformer 38. As a result, the output voltage Vo is maintained at the predetermined voltage.

In such operation, the switching losses of the first to fourth transistors 33 to 36 are caused by the capacitors 52 to 55 and the inductors connected in parallel to the first to fourth transistors 33 to 36, respectively. 39
It is reduced by resonance with.

As described above, the switching power supply device 30 according to the present embodiment can transmit appropriate power to the secondary side of the transformer 38 under the normal load condition by the phase shift control by the control circuit 46.

Next, the operation of the control circuit 46 in the light load state or the no load state will be described.

FIG. 6 is a timing chart showing the operation of the control circuit 46 in the light load state or the no load state.

As shown in FIG. 6, in the light load state or the no load state, the first comparison signal COMP-1
Is lower than the output voltage V82 of the voltage source 82, the level of the second comparison signal COMP-2, which is the output of the first comparator 80, is fixed to the high level.
Similarly, when the level of the first comparison signal COMP-1 is RAM
Since it is always lower than the level of P-2, the level of the third comparison signal COMP-3, which is the output of the second comparator 81, is fixed to the low level.

Therefore, the PWM latch circuit 87 is not reset, and therefore the internal signal PWM output from its inverting output terminal (inversion Q) is fixed to the low level. As a result, the exclusive OR circuit (X
The output (88OUT) of NOR) 88 is the internal signal Pulse.
An exclusive OR circuit (XOR) that matches the waveform of e-B '
The output of 89 (89OUT) is the internal signal Pulse-
It matches the waveform of A '.

Since the level of the second comparison signal COMP-2 is fixed at the high level, the output (91OUT) of the non-logical product circuit (NAND) 91 is output from the non-logical sum circuit (NOR) 90. Output internal signal DELAYA
The waveform is the inverse of -B. Therefore, the internal signal Pul
se-C ′ becomes a low level during a period in which the output (88OUT) of the exclusive non-logical sum circuit (XNOR) 88 and the output (91OUT) of the non-logical product circuit (NAND) 91 are both at a high level, and an internal signal Pulse-D '
Is the output (89OU) of the exclusive OR circuit (XOR) 89.
T) and the output of the non-logical product circuit (NAND) 91 (91OU
Both T) are at a low level while they are at a high level.

The internal signal Pul generated in this way
se-C 'and Pulse-D' are given dead times by the third and fourth dead time generation circuits 94 and 95, and output signals Pulse- as shown in FIG.
C and Pulse-D are obtained. Referring to FIG.
There is no period in which both the output signal Pulse-C and the output signal Pulse-B are at a high level, and there is no period in which both the output signal Pulse-D and the output signal Pulse-A are at a high level. I understand. Furthermore, the rising edge of the output signal Pulse-C is
T for the rising edge of the output signal Pulse-A
delay C-D, and the output signal Pu
The rising edge of lse-D is the output signal Pulse.
It can be seen that there is a delay of TdelayC-D with respect to the rising edge of -B.

The output signals Pulse-A to Pulse-D generated by the control circuit 46 in this manner are transmitted through the first to fourth insulating circuits 47 to 50 as described above.
It is supplied to the gate electrodes of the first to fourth transistors 33 to 36, respectively, but as described above, since there is no period in which both Pulse-A and Pulse-D are at the high level, the first transistor Both 33 and the fourth transistor 36 are not turned on at the same time, and since there is no period in which both Pulse-B and Pulse-C are at the high level, the second transistor 34 and the fourth transistor 36 Both of the three transistors 35 are not turned on at the same time.

As a result, no voltage is generated on the primary side of the transformer 38, so that the power transmitted to the secondary side of the transformer 38 becomes zero and the output voltage Vo is maintained at a predetermined voltage. Become.

Moreover, as described above, the output signal Pulse
The rising edge of e-C is the output signal Pulse-A.
Of the output signal Pulse-D appears later than the rising edge of the output signal Pulse-B by TdelayC-D. The voltage generation is temporally dispersed, and the stress applied to the first to fourth transistors 33 to 36 included in the switching circuit 37 is significantly reduced as compared with the conventional switching power supply device 10.

FIGS. 7A to 7D are schematic diagrams of the switching circuit 37 for explaining this.

First, Pulse-A and Pulse-C
Is high level, and Pulse-B and Pulse-
At the timing when D is at the low level (time t10), as shown in FIG. 7A, the voltage across the second and fourth transistors 34 and 36 is Vin,
The voltage is charged in the capacitance component C34 between both ends of the second transistor 34 and the capacitance component C36 between both ends of the fourth transistor 36. Here, the capacitance component C34 between both ends of the second transistor 34 includes the source-drain capacitance of the second transistor 34, the capacitance of the capacitor 53, and the capacitance of the capacitor 65. Similarly, the capacitance component C36 across the fourth transistor 36 is
Is composed of the source-drain capacitance of the fourth transistor 36, the capacitance of the capacitor 55, and the capacitance of the capacitor 67.

Next, Pulse-A and Pulse-C
At the timing (time t11) when is changed from the high level to the low level, as shown in FIG.
Although the first and third transistors 33 and 35 change from the on-state to the off-state, the second and fourth transistors 34 and 36 are maintained in the off-state. Fourth transistors 34, 3
The state that the voltage Vin is charged in the capacitance components C34 and C36 between both ends of 6 is maintained.

Next, at the timing (time t12) when Pulse-B changes from the low level to the high level, as shown in FIG. 7C, the second transistor 34 changes from the off state to the on state. From doing the second
The capacitance component C34 across the transistor 34 is discharged. As a result, the electric charge charged in the capacitance component C34 across the second transistor 34 generates the current I11, so that the parasitic inductance 68 existing between the switching circuit 37 and the input capacitor 32 is
This current I11 will flow. As a result, a surge voltage is generated between both ends of the first transistor 33, but the voltage value is suppressed to be lower than the surge voltage generated in the conventional switching power supply device 10.

Then, from time t12, TdelayC-
At the timing (time t13) when the Pulse-D changes from the low level to the high level after the lapse of D, as shown in FIG. 7D, the fourth transistor 36 changes from the off state to the on state. From doing, the fourth
The capacitance component C36 across the transistor 3 is discharged. As a result, the electric charge charged in the capacitance component C36 between both ends of the fourth transistor 36 generates the current I12, so that the parasitic inductance 68 existing between the switching circuit 37 and the input capacitor 32 is applied. The current I12 will flow. This makes the third
Although a surge voltage is generated between both ends of the transistor 35, the voltage value thereof can be suppressed to be lower than the surge voltage generated in the conventional switching power supply device 10.

Similarly, Pulse-A and Pulse-A
Even when C changes from the low level to the high level, Pulse-A changes from the low level to the high level (time t14), and then Pulse-C changes from the low level to the high level (time t15).

As described above, in the switching power supply device 30 according to the present embodiment, the rising edge of the output signal Pulse-C in the light load state or the no-load state is TdelayC-D with respect to the rising edge of the output signal Pulse-A. Appears with a delay, and the output signal Pul
The rising edge of se-D is the output signal Pulse-
Since it appears with a delay of TdelayC-D with respect to the rising edge of B, the generation of the surge voltage in the switching circuit 37 is dispersed in time, whereby the first to fourth transistors 33 to 33 included in the switching circuit 37. The stress on 36 is reduced. Therefore, destruction of the first to fourth transistors 33 to 36 due to surge voltage can be effectively prevented without adding a large-capacity capacitor to the first to fourth transistors 33 to 36. .

Next, another preferred embodiment of the present invention will be described.

A switching power supply device 100 according to another preferred embodiment of the present invention is shown in FIG. 1. In the switching power supply device 30 according to the above embodiment, the control circuit 46 is replaced with a control circuit 101. They differ in points. The other components are the same as those of the switching power supply device 30 according to the above-described embodiment, and thus the overlapping description will be omitted.

FIG. 8 is a circuit diagram of the control circuit 101.

As shown in FIG. 8, the control circuit 101
Is a non-OR circuit (NO
R) 90 is deleted, and the clock signal CLK is used instead of the internal signal DELAYA-B generated by the non-OR circuit (NOR) 90, which is different from the control circuit 46. The other components are the same as those of the control circuit 46, and a duplicate description will be omitted.

The control circuit 101 having such a configuration can also perform substantially the same operation as the control circuit 46 already described. Specifically, the control circuit 101 outputs the output signal P in the light load state or the no load state.
The rising edge of pulse-C is the output signal Pulse
Clock signal CLK for the rising edge of e-A
Appears with a delay for a period of high level, and the output signal Pu
The rising edge of lse-D is the output signal Pulse
It appears after the rising edge of -B by a period in which the clock signal CLK is at the high level. This allows
Similar to the switching power supply device 30 according to the above-described embodiment, the generation of the surge voltage in the switching circuit 37 is dispersed in terms of time, whereby the first surge voltage is generated.
~ The destruction of the fourth transistors 33 to 36 can be effectively prevented.

Next, still another preferred embodiment of the present invention will be described.

A switching power supply device 110 according to still another preferred embodiment of the present invention is shown in FIG. 1. In the switching power supply device 30 according to the above embodiment, the control circuit 46 is replaced with a control circuit 111. Differ in that there is. The other components are the same as those of the switching power supply device 30 according to the above-described embodiment, and thus the overlapping description will be omitted.

FIG. 9 is a circuit diagram of the control circuit 111.

As shown in FIG. 9, the control circuit 111
Is that the internal signal DELAYA-B is used instead of the clock signal CLK as a signal supplied to the gate of the transistor 75, the input end of the inverter 85, and one input end of the non-OR circuit (NOR) 86. In the control circuit 46. The other components are the same as those of the control circuit 46, and a duplicate description will be omitted.

Also in the control circuit 111 having such a configuration, similarly to the control circuit 46 already described, the output signal Pulse-C is set in the light load state or the no load state.
Of the output signal Pulse-A appears with a delay of TdelayC-D with respect to the rising edge of the output signal Pulse-A, and the rising edge of the output signal Pulse-D is Td with respect to the rising edge of the output signal Pulse-B.
Appears delayed by elayC-D. As a result, similarly to the switching power supply device 30 according to the above-described embodiment, the generation of the surge voltage in the switching circuit 37 is dispersed over time, and thus the first to fourth transistors 33 to 36 are effectively destroyed by the surge voltage. Can be prevented.

Further, in the control circuit 111, since the internal signal DELAYA-B is used instead of the clock signal CLK as the signal supplied to the gate of the transistor 75, the first comparator 81 outputs the first signal. The comparison between the level of the comparison signal COMP-1 and the level of RAMP-2 is performed by comparing the minimum level of RAMP-2 (= V8).
It becomes possible to effectively carry out from 3) to substantially the entire region of the maximum level, and the primary side voltage V of the transformer 38 is increased.
It is possible to control the minimum value (minimum width of the output pulse) of the period in which mt should be the input voltage Vin (-Vin) to a substantially infinitesimal value. Hereinafter, regarding this, the control circuit 46
, The level region of RAMP-2 that can be compared with the level of the first comparison signal COMP-1, and the control circuit 46.
Will be described in detail in comparison with the minimum width of the output pulse.

FIG. 10 shows the first comparison signal in the control circuit 46 when the pulse width (high level period) of the internal signal DELAYA-B is longer than the pulse width (high level period) of the clock signal CLK. FIG. 9 is a timing diagram for explaining a level region of RAMP-2 that can be compared with the level of COMP-1 and a minimum width of an output pulse.

As shown in FIG. 10, in the control circuit 46, when the pulse width (high level period) of the internal signal DELAYA-B is longer than the pulse width (high level period) of the clock signal CLK, the internal signal DELAYA-
Since the level of RAMP-2 starts to rise during the period when B is at the high level, the internal signal DELAYA-B
When the falling edge of appears,
The level of RAMP-2 is already higher than the minimum level (= V83) of RAMP-2 by a predetermined level Vt.

However, as is apparent from FIG. 5, the output pulse, which is the primary side voltage of the transformer 38, has the level of RAMP-2 at the first level after the falling edge of the internal signal DELAYA-B appears. 1 comparison signal COMP-
Since it is generated in the period until the level exceeds 1, the output pulse is not generated when the level of the first comparison signal COMP-1 is equal to or lower than the predetermined level Vt.
That is, in the control circuit 46, the level of the first comparison signal COMP-1 by the second comparator 81 and R
The comparison with the level of AMP-2 is not effectively performed in the area from the minimum level (= V83) of RAMP-2 to the predetermined level Vt, and the comparison is made only in the area where RAMP-2 exceeds the predetermined level Vt. Can be effectively performed.

As described above, in the control circuit 46, the pulse width (high level period) of the internal signal DELAYA-B is larger than the pulse width (high level period) of the clock signal CLK.
It is understood that when is longer, the level of the RAMP-2 that can be compared with the level of the first comparison signal COMP-1 is limited to a predetermined area (> Vt). On the other hand, the minimum width of the output pulse can be controlled to a practically infinitesimal size.

FIG. 11 shows the first comparison signal in the control circuit 46 when the pulse width (high level period) of the internal signal DELAYA-B is shorter than the pulse width (high level period) of the clock signal CLK. FIG. 9 is a timing diagram for explaining a level region of RAMP-2 that can be compared with the level of COMP-1 and a minimum width of an output pulse.

As shown in FIG. 11, in the control circuit 46, when the pulse width (high level period) of the internal signal DELAYA-B is shorter than the pulse width (high level period) of the clock signal CLK, the RAMP- In the period in which the level of 2 is the minimum level (= V83), the falling edge of the internal signal DELAYA-B appears.
Therefore, in this case, the level of the first comparison signal COMP-1 by the second comparator 81 and the RAMP-
2 is compared with the minimum level of RAMP-2 (=
It becomes possible to effectively carry out from V83) to substantially the entire area of the maximum level.

However, as described above, the output pulse, which is the primary side voltage of the transformer 38, receives the internal signal DELAYA.
Since it occurs in the period from the appearance of the falling edge of -B until the level of RAMP-2 exceeds the level of the first comparison signal COMP-1, the minimum width of the output pulse is the internal signal DELAYA-B. Is limited to the period from the appearance of the falling edge of the clock signal to the appearance of the falling edge of the clock signal CLK, and it is not possible to generate an output pulse having a width smaller than that.

As described above, in the control circuit 46, the pulse width (high level period) of the internal signal DELAYA-B is larger than the pulse width (high level period) of the clock signal CLK.
Is shorter, the minimum width of the output pulse is limited,
It cannot be controlled to infinity. On the other hand, the comparison between the level of the first comparison signal COMP-1 and the level of RAMP-2 by the second comparator 81 is performed over the substantially entire area of the minimum level (= V83) of RAMP-2 to the maximum level. It can be done effectively.

As is apparent from the above, in the control circuit 46, if the pulse width of the clock signal CLK (high level period) and the pulse width of the internal signal DELAYA-B (high level period) are equal, the second comparator. 81 and the level of the first comparison signal COMP-1 and RAMP-
The minimum level of RAMP-2 (= V
83) to substantially the entire range of the maximum level, and the minimum width of the output pulse can be controlled to a substantially infinitesimal size. However, the pulse width (high level period) of the clock signal CLK cannot be freely changed by the user, while the pulse width (high level period) of the internal signal DELAYA-B is a factor that determines the dead time. This cannot be freely set only in relation to the pulse width (high level period) of the clock signal CLK. Therefore, in the control circuit 46, it is difficult to completely match the pulse width (high level period) of the clock signal CLK and the pulse width (high level period) of the internal signal DELAYA-B.

FIG. 12 shows the first circuit in the control circuit 111.
RAMP that can be compared with the level of the comparison signal COMP-1 of
2 is a timing diagram for explaining a level region of −2 and a minimum width of an output pulse. FIG.

As shown in FIG. 12, the control circuit 111
, The internal signal DE is applied to the gate of the transistor 75.
Since LAYA-B is supplied, the internal signal DE
RAMP- in response to the falling edge of LAYA-B
Level 2 starts rising. Therefore, referring to FIG. 12, regardless of the pulse width (high level period) of the clock signal CLK, the first comparator 81
The comparison between the level of the comparison signal COMP-1 and the level of the RAMP-2 is performed by comparing the minimum level of the RAMP-2 (= V83).
It can be seen from the above that it can be effectively performed over substantially the entire region of the maximum level, and the minimum width of the output pulse can be controlled to a substantially infinitesimal size.

Therefore, in the switching power supply device 110 having such a control circuit 111, in addition to the effects of the switching power supply devices 30 and 100 according to the above-described embodiments, the switching circuit 37 can be controlled with higher accuracy. Is possible.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. It goes without saying that it is a thing.

For example, in the switching power supply devices 30, 100, 110 according to the above embodiments, the output voltage V82 of the voltage source 82 and the output voltage V83 of the voltage source 83 are set to be substantially equal. In the above, it is not essential that they have the same voltage, and they may be different from each other.

Further, the first comparator 80 included in the switching power supply device 30, 100, 110 according to each of the above embodiments may be provided with hysteresis. When the first comparator 80 has hysteresis, the switching circuit 37 in the case where the level of the first comparison signal COMP-1 is substantially equal to the output voltage V82 of the voltage source 82.
It becomes possible to more stably control.

Further, in the switching power supply device 30, 100, 110 according to each of the above-mentioned embodiments, the diode rectifier circuit including the diodes 40, 41 is used as the rectifier circuit 42 provided on the secondary side of the transformer 38. However, a synchronous rectification circuit composed of rectification transistors may be used.

Further, in the switching power supply device 30, 100, 110 according to each of the above-mentioned embodiments, the control circuits 46, 101, 111 belong to the secondary side of the transformer 38. First to fourth insulation circuits 47 to 50 are provided between the switching circuit 37 and the switching circuit 37.
These control circuits 46, 10 are insulated by
By isolating between 1, 111 and the output circuit,
The control circuits 46, 101 and 111 may belong to the primary side of the transformer 38.

Further, in the switching power supply device 30, 100, 110 according to each of the above-described embodiments, the output voltage Vo is divided by using the voltage dividing circuit 78, and the obtained error voltage E / A− and the reference voltage Vref are obtained. Are compared by an error amplifier 79 to obtain a first comparison signal COMP-1
However, the first comparison signal C is obtained by comparing the output voltage Vo and the reference voltage Vref ′ by the error amplifier 79 without using such a voltage dividing circuit 78.
OMP-1 may be generated.

In the present invention, the means does not necessarily mean a physical means but also includes a case where the function of each means is realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.

[0121]

As described above, according to the present invention,
Provided are a switching power supply device in which a surge voltage generated in a light load state or a no load state is reduced, and a control circuit capable of reducing a surge voltage generated in a light load state or a no load state. Further, according to the present invention, there is provided a control method of a switching power supply device capable of reducing a surge voltage generated in a light load state or a no load state.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a switching power supply device 30 according to a preferred embodiment of the present invention.

FIG. 2 is a circuit diagram of a control circuit 46.

FIG. 3 shows first to fourth dead time generation circuits 72 and 7.
It is a circuit diagram which shows the concrete circuit structure of 3,94,95.

FIG. 4 illustrates first to fourth dead time generation circuits 72 and 7.
It is a timing diagram which shows operation | movement of 3,94,95.

FIG. 5 is a timing diagram showing an operation of the control circuit 46 in a normal load state.

FIG. 6 is a timing diagram showing an operation of the control circuit 46 in a light load state or a no load state.

FIG. 7 is a schematic diagram for explaining the operation of the switching circuit 37 in a light load state or a no load state.

FIG. 8 is a circuit diagram of a control circuit 101.

9 is a circuit diagram of a control circuit 111. FIG.

FIG. 10 shows a clock signal CLK in the control circuit 46.
Internal signal DELA than the pulse width (high level period) of
To explain the level region of RAMP-2 that can be compared with the level of the first comparison signal COMP-1 and the minimum width of the output pulse when the pulse width (high level period) of YA-B is longer. FIG.

FIG. 11 shows a clock signal CLK in the control circuit 46.
Internal signal DELA than the pulse width (high level period) of
To explain the level region of RAMP-2 that can be compared with the level of the first comparison signal COMP-1 and the minimum width of the output pulse when the pulse width (high level period) of YA-B is shorter. FIG.

FIG. 12 shows the first comparison signal C in the control circuit 111.
FIG. 6 is a timing chart for explaining a level region of RAMP-2 that can be compared with the level of OMP-1 and a minimum width of an output pulse.

FIG. 13 is a circuit diagram showing a conventional switching power supply device 10.

FIG. 14 is a timing diagram showing an operation of the conventional switching power supply device 10 in a normal load state.

FIG. 15 is a timing diagram showing an operation of the conventional switching power supply device 10 in a light load state or a no load state.

FIG. 16 is a schematic diagram for explaining the operation of the switching circuit 17 in a light load state or a no load state.

[Explanation of symbols]

10 Switching power supply 11 Input power 12 input capacitors 13 First transistor 14 Second transistor 15 Third transistor 16 Fourth transistor 17 Switching circuit 18 transformers 19,20 diode 21 Rectifier circuit 22 Inductor 23 Capacitor 24 Smoothing circuit 25 Control circuit 26 load 27 Parasitic inductance 30 switching power supply 31 Input power 32 input capacitors 33 First transistor 34 Second transistor 35 Third Transistor 36 Fourth Transistor 37 Switching circuit 38 transformers 39 Inductance 40, 41 diode 42 Rectifier circuit 43 inductor 44 capacitor 45 smoothing circuit 46 Control circuit 47 First isolation circuit 48 Second insulation circuit 49 Third Insulation Circuit 50 Fourth insulation circuit 51 load 52-55 capacitors 56-59 snubber circuit 60-63 resistance 64-67 capacitors 68 Parasitic inductance 70 oscillator 71 Data latch circuit 72 First Dead Time Generation Circuit 73 Second Dead Time Generation Circuit 74 lamp circuit 75 transistor 76,77 resistance 78 voltage divider 79 Error amplifier 80 First Comparator 81 Second comparator 82,83 Voltage source 84,86 Non-OR circuit (NOR) 85 inverter 87 PWM latch circuit 88 Exclusive NOR circuit (XNOR) 89 Exclusive OR circuit (XOR) 90 Non-OR circuit (NOR) 91-93 Non-logical product circuit (NAND) 94 Third Dead Time Generation Circuit 95 Fourth Dead Time Generation Circuit 96 delay circuit 97 Non-OR circuit (NOR) 100 switching power supply 101 control circuit 110 Switching power supply 111 Control circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuhiro Murai             1-13-1, Nihonbashi, Chuo-ku, Tokyo             -In DC Inc. (72) Inventor Kunihiro Sato             1-13-1, Nihonbashi, Chuo-ku, Tokyo             -In DC Inc. (72) Inventor Masanori Inamori             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company (72) Inventor Toshiya Fujiyama             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F-term (reference) 5H007 AA01 AA04 BB06 CA01 CB05                       CB09 CC09 DB01 DB12 DC05                       EA02

Claims (25)

[Claims] 1. A transformer, a full-bridge type switching circuit provided on the primary side of the transformer and including first and second arms, an output circuit provided on the secondary side of the transformer, A switching power supply device comprising a control circuit for controlling a phase shift of a switching circuit, wherein the control circuit changes a pulse width of an output signal for driving the second arm based on a load state of the output circuit. A switching power supply device characterized by the above. 2. The control circuit, when the output circuit is in the first load state, sets the pulse width of the output signal for driving the second arm to that of the output signal for driving the first arm. When the width is set to be substantially equal to the pulse width and the output circuit is in the second load state, the pulse width of the output signal that drives the second arm is the output that drives the first arm. The switching power supply device according to claim 1, wherein the switching power supply device is set to a width different from the pulse width of the signal. 3. The switching power supply device according to claim 2, wherein the first load state is a normal load state, and the second load state is a light load state or a no load state. . 4. The control circuit, when the output circuit is in the second load state, sets the pulse width of the output signal for driving the second arm to the output signal for driving the first arm. 4. The switching power supply device according to claim 3, wherein the switching power supply device is set to have a width shorter than the pulse width. 5. The control circuit, when the output circuit is in the second load state, the high-level switch forming the second arm after the high-side switch forming the first arm is turned on. The side switch is controlled to be turned on, and the low side switch constituting the second arm is controlled to be turned on after the low side switch constituting the first arm is turned on. Item 4. The switching power supply device according to Item 4. 6. The control circuit, when the output circuit is in the second load state, the high-side switch forming the first arm and the high-side side forming the second arm. The switch is controlled to be turned off substantially at the same time, and the low side switch constituting the first arm and the low side switch constituting the second arm are controlled to be turned off substantially simultaneously. The switching power supply device according to claim 5, wherein: 7. The control circuit configures the second arm and the timing of turning on the high-side switch configuring the first arm when the output circuit is in the second load state. The time difference from the timing of turning on the high-side switch and the first
Setting the time difference between the timing of turning on the low-side switch forming the second arm and the timing of turning on the low-side switch forming the second arm based on the dead time of the first arm. 7. The switching power supply device according to claim 5, which is characterized in that. 8. The control circuit configures the second arm and the timing of turning on the high-side switch configuring the first arm when the output circuit is in the second load state. The time difference from the timing of turning on the high-side switch and the first
6. The time difference between the timing of turning on the low-side switch forming the second arm and the timing of turning on the low-side switch forming the second arm is set based on a clock signal. Alternatively, the switching power supply device according to item 6. 9. The control circuit generates an output signal for driving the first arm based on a clock signal, and activates an output signal for driving the second arm during a dead time of the first arm. 9. The method according to claim 1, wherein the signal is generated based on the internalized signal.
The switching power supply device according to the item. 10. A sawtooth wave generating means for generating a sawtooth wave in response to the internal signal, an output voltage of the output circuit or a voltage corresponding thereto,
Of the first comparison signal and an error amplifier that generates a first comparison signal based on the comparison result and the first comparison signal and the second reference voltage, and the second comparison signal based on the comparison result. And a second comparator that compares the first comparison signal with the sawtooth wave and generates a third comparison signal based on the first comparator and at least the second comparison signal and 10. The switching power supply device according to claim 9, further comprising means for generating an output signal for driving the second arm based on the third comparison signal. 11. The switching power supply device according to claim 10, wherein the first comparator has a hysteresis. 12. A plurality of capacitors and a plurality of snubber circuits respectively provided in parallel with each of the switches included in the switching circuit, and an inductor inserted between the first arm and the transformer. 12. The method according to claim 1, further comprising:
The switching power supply device according to the item. 13. A control circuit for controlling a phase shift of a switching power supply device including a full-bridge type switching circuit, the control circuit generating a first output signal for driving a first arm of the switching power supply device. 1 means, a second means for generating a second output signal for driving a second arm of the switching power supply device, a third means for detecting an output voltage of the switching power supply device, and the third means. And a fourth means for changing the pulse width of the second output signal based on the output voltage detected by the means. 14. The fourth means outputs the second output signal generated by the second means when the output voltage detected by the third means is less than a predetermined voltage. When the output voltage detected by the third means exceeds the predetermined voltage without changing the pulse width, the second means generated by the second means is used. 14. The control circuit according to claim 13, wherein the pulse width of the output signal is shortened before output. 15. The pulse width reduction by the fourth means is performed by deactivating an initial portion of an activation period of the second output signal. Control circuit. 16. A control circuit for performing a phase shift control of a switching power supply device including a full-bridge type switching circuit, wherein a pair of first circuits are alternately set to a high level.
And a pair of first outputs for driving the first arm of the switching power supply device by receiving the first internal signal and giving a first dead time to the first internal signal. A second means for generating a signal, a third means for generating a sawtooth wave, and a pair of second internal signals that are alternately at a high level based on at least the output voltage of the switching power supply device and the sawtooth wave. A fourth means for generating and a pair of means for responding to the output voltage exceeding a predetermined voltage by deactivating a predetermined period of the activation period of the second internal signal. Means for generating a third internal signal, and a pair of means for receiving the third internal signal and applying a second dead time to the third internal signal to drive the second arm of the switching power supply device. Control circuit and a sixth means for producing a second output signal. 17. The fifth means compares the output voltage or a voltage corresponding thereto with a first reference voltage,
An error amplifier that generates a first comparison signal based on this is compared with the first comparison signal and a second reference voltage,
A comparator for generating a second comparison signal based on this, and a first logic circuit for receiving a first output signal and generating a fourth internal signal activated at the first dead time based on this comparator. A second logic circuit that receives the second comparison signal and the fourth internal signal and generates a fifth internal signal indicating the predetermined period based on the second comparison signal and the fourth internal signal; The control circuit according to claim 16, further comprising: a third logic circuit that receives the fifth internal signal and generates the third internal signal based on the fifth internal signal. 18. The ramp circuit according to claim 17, wherein the third means includes a ramp circuit that minimizes the sawtooth wave during a period when the fourth internal signal is in an active state. Control circuit. 19. The control circuit according to claim 18, wherein the ramp circuit raises the level of the sawtooth wave during a period in which the fourth internal signal is inactive. 20. The fifth means compares the output voltage or a voltage corresponding thereto with a first reference voltage,
An error amplifier that generates a first comparison signal based on this is compared with the first comparison signal and a second reference voltage,
A comparator that generates a second comparison signal based on this, and a first logic circuit that receives the second comparison signal and a clock signal and generates a fourth internal signal indicating the predetermined period based on these And a second logic circuit that receives the second internal signal and the fourth internal signal and generates the third internal signal based on the second internal signal and the fourth internal signal. Control circuit. 21. A control circuit for controlling a switching power supply device comprising first and second arms each of which is composed of a high-side switch and a low-side switch, the control circuit comprising: A pulse for controlling the high-side switch of the first arm and a pulse for controlling the low-side switch of the second arm overlap, and a pulse for controlling the high-side switch of the second arm and the first arm Means for controlling the overlap of pulses for controlling the low side switch of the
Of the pulse for controlling the high side switch of the second arm and the pulse for controlling the low side switch of the second arm, and the pulse for controlling the high side switch of the second arm and the pulse of the first arm A pulse for controlling the high side switch of the second arm and a pulse for controlling the low side switch of the second arm in response to the overlapping of the pulses for controlling the low side switch becoming zero. And a second means for shortening the control circuit. 22. Third means for causing the first means to alternately turn on a high-side switch forming the first arm and a low-side switch forming the first arm,
Fourth means for generating a sawtooth wave that starts rising at the timing when the high-side switch forming the first arm turns on and the timing when the low-side switch forming the first arm turns on, and at least the switching means 5. A fifth means for controlling a high-side switch forming the second arm and a low-side switch forming the second arm based on an output voltage of a power supply device and the sawtooth wave. Item 21
The control circuit described in. 23. A method of driving a switching power supply device including a full-bridge type switching circuit, comprising a high-side switch forming a first arm of the switching circuit when in a light load state or a no load state. The high-side switch forming the second arm of the switching circuit is continuously turned on, and the low-side switch forming the first arm and the low-side switch forming the second arm are continuously turned on. A method for driving a switching power supply device, comprising: 24. A method of driving a switching power supply device including a full-bridge type switching circuit, wherein a pulse of an output signal for driving a first arm of the switching circuit in a light load state or a no load state. A method of driving a switching power supply device, wherein a width and a pulse width of an output signal for driving the second arm of the switching circuit are different from each other by a predetermined width. 25. The method of driving a switching power supply device according to claim 24, wherein the predetermined width is substantially equal to either the dead time or the activation period of the clock signal.