JP2003018555A - Data service signal detecting apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data service signal detecting apparatus capable of detecting a data service signal always stably by preventing wrong detection of a positive period of a ternary synchronizing signal as a data service signal. SOLUTION: The data service signal detecting circuit starts to detect the data service signal at the time when a horizontal synchronizing signal finish position is detected by a horizontal synchronizing signal finish position detecting circuit. If a ternary synchronous signal is detected by a ternary signal detecting circuit, the result of detection in the data service signal obtained from the horizontal synchronizing signal finish position up to now is made to be invalid, and the detection of the data service signal is started at the time of detecting the finish position of the positive period of the ternary synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data service signal detecting device for detecting a data service signal inserted within a vertical blanking period of a component video signal.

[0002]

2. Description of the Related Art In a vertical blanking period of a component video signal output from a BS digital broadcast receiver, a DVD player, etc., data indicating the aspect ratio of the video signal, etc.
Service signal is inserted. A circuit for detecting such a data service signal decodes the data service signal using a predetermined threshold value.

Conventionally, as the threshold level, the positive period of the ternary synchronizing signal is set larger than the maximum level of the positive period of the ternary synchronizing signal so as not to be mistakenly detected as a data service signal. There is.

However, in the conventional detection method, the positive period of the ternary sync signal is erroneously used as a data service signal due to fluctuations in the amplitude level of the input video signal and deterioration of the signal quality (overshoot, undershoot). It was not possible to completely prevent such things as detection.

[0005]

SUMMARY OF THE INVENTION According to the present invention, it is possible to prevent the positive period of a ternary sync signal from being erroneously detected as a data service signal, and to always stably detect a data service signal. It is an object of the present invention to provide a data service signal detection device that can be used.

[0006]

Data according to the present invention
The service signal detection device includes a sync separation circuit that separates a horizontal sync signal and a vertical sync signal from an input video signal, a clock generation circuit that generates a sampling clock synchronized with the horizontal sync signal obtained by the sync separation circuit, and an input video signal. A / D conversion circuit for sampling based on the sampling clock obtained by the clock generation circuit, a horizontal sync signal end position detection circuit for detecting the end position of the horizontal sync signal obtained by the sync separation circuit, and an A / D
A first slice circuit for slicing image data output from the conversion circuit with a threshold value for detecting a three-valued synchronization signal, and a three-valued synchronization signal for detecting the presence or absence of a three-valued synchronization signal based on the output of the first slice circuit Based on the outputs of the detection circuit and the first slice circuit, the ternary sync signal end position detection circuit that detects the end position of the positive period of the ternary sync signal, and the image data output from the A / D conversion circuit A data service signal detection circuit comprising a second slice circuit for slicing with a service signal detection threshold value and a data service signal detection circuit for detecting a data service signal based on the output of the second slice circuit. Starts detecting the data service signal when the horizontal sync signal end position is detected by the horizontal sync signal end position detection circuit. When the signal detection circuit detects the ternary sync signal, the detection result of the data service signal obtained from the horizontal sync signal end position to that time is invalidated, and the ternary sync signal end position detection circuit detects the ternary sync signal. The detection of the data service signal is started from the time when the end position of the positive period of is detected.

The data service signal detecting circuit includes, for example, a circuit for measuring the width of the reference signal of the data service signal, a circuit for detecting that bit0 of the data service signal is low, and bits 1 to 1 of the data service signal. bi
The circuit that detects the data of t20 and the CRC check for the detected data service signal, update the data service signal detection result only when no error is detected, and when the error is detected Is provided with a circuit for holding the previous data service signal detection result.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a data service signal detector.

FIG. 2 shows a data service signal inserted in the vertical blanking period of the Y signal when the horizontal synchronizing signal is a binary synchronizing signal.

FIG. 3 shows a data service signal inserted in the vertical blanking period of the Y signal when the horizontal synchronizing signal is a ternary synchronizing signal.

The data service signals are shown in FIGS.
As shown in, it consists of the Ref signal (reference signal) and the following bit signals of bit1 to bit20. Re
The f signal defines the width of each bit signal. bit0
The signal of is always LOW, that is, "0". The signal of bits 1 to 20 is either Low ("0") or High ("1").

The sync separation circuit 1 separates and outputs a horizontal sync signal HSYNC and a vertical sync signal VSYNC from the Y signal (luminance signal) of the component video signals Y, U and V. As shown in FIGS. 2 and 3, the waveform of the horizontal sync signal HSYNC obtained by the sync separation circuit 1 does not change regardless of whether the horizontal sync signal is a binary sync signal or a ternary sync signal.

The PLL clock generation circuit 2 is based on the horizontal synchronization signal HSYNC output from the synchronization separation circuit 1 and has a sampling clock CLOC synchronized with the horizontal synchronization signal HSYNC.
Generate K.

The A / D converter 3 samples the component video signals Y, U and V using a sampling clock CLOCK. Here, for convenience of explanation, only the Y signal is shown.

The digital data obtained by the A / D converter 3 is sent to the ternary synchronizing signal detecting circuit 4 and the data service signal detecting circuit 5.

The three-valued sync signal detection circuit 4 comprises a slice circuit 41, a three-valued sync signal detection section 42 and a three-valued sync positive period end detection section 43. The ternary sync signal detection circuit 4 includes a horizontal sync signal HSYNC and a vertical sync signal VSYNC.
The sampling clock CLOCK is also input.

The slice circuit 41 has a horizontal synchronizing signal HSYNC.
Is input, the positive period of the ternary synchronization signal is sliced using the first threshold value set by the microcomputer control unit 6. As the first threshold value, a level capable of slicing the ternary sync signal is set.

The ternary sync signal detector 42 determines whether the sync signal is a ternary sync signal based on the output of the slice circuit 41. If the sync signal is a ternary sync signal, Set the TRISYNC_DETECT signal to High.

Tri-level synchronization positive period end detection section 43
When the ternary sync signal detection unit 42 determines that the sync signal is a ternary sync signal, TRIS detects the end point of the ternary sync signal based on the output of the slice circuit 41.
Outputs YNC_END pulse.

The data / service signal detecting circuit 5 includes a slice circuit 51, an HSYNC end detecting circuit 52, a Ref signal width detecting circuit 53, a bit0 detecting circuit 54, and bit1 to 20 detecting circuits 5.
5, a CRC check circuit 56 and a data service signal result output circuit 57 are provided.

The slice circuit 51 has a horizontal synchronizing signal HSYNC.
Is input, the data service signal is sliced using the second threshold value set by the microcomputer controller 6. As the second threshold value, a level at which the data service signal can be sliced is set. Normally, the second threshold value is set to a value larger than the first threshold value.

The HSYNC end detection circuit 52 outputs a horizontal sync signal.
Detects the end point of HSYNC and outputs HSYNC_END pulse. The Ref signal width detection circuit 53 measures the Ref signal width of the data service signal based on the output of the slice circuit 51.

The Ref signal width detection circuit 53 starts the Ref signal width measurement based on the output of the slice circuit 51 after the HSYNC_END pulse from the HSYNC end detection circuit 52 is input. If the sync signal is determined to be a ternary sync signal by, the measurement result until the TRISYNC_END pulse is input from the ternary sync positive period end detection unit 43 is canceled (invalid), and TRISYNC_END After the pulse is input, the Ref signal width measurement based on the output of the slice circuit 51 is started.

Therefore, when the sync signal is a binary sync signal, the Ref signal width detection circuit 53 is based on the output of the slice circuit 51 from the time when the HSYNC_END pulse is input, as shown in FIG. Ref Signal width measurement starts. In other words, when the sync signal is a binary sync signal, the detection of the data service signal is started at the end of the horizontal sync signal HSYNC.

If the sync signal is a ternary sync signal,
The Ref signal width detection circuit 53, as shown in FIG.
Slice circuit 5 from when the C_END pulse is input
A Ref signal width measurement based on an output of 1 will essentially start. In other words, when the sync signal is a ternary sync signal, the detection of the data service signal is started from the start start point of the positive period of the ternary sync signal. Therefore, it is possible to prevent the positive period of the ternary synchronization signal from being erroneously detected as the data service signal.

When the Ref signal width detection circuit 53 detects the Ref signal width, the bit0 detection circuit 54 uses the interval of the Ref signal width based on the output of the slice circuit 51 to detect the bit0 of the data service signal. Data (low) is detected.
Further, the bit1 to 20 detection circuit 55 detects the data of bit1 to bit20 of the data service signal based on the output of the slice circuit 51 using the intervals of the Ref signal width.

Bit 0 to bit of the data service signal detected by the bit 0 detection circuit 54 and the bits 1 to 20 detection circuit 55
The data of bit20 is sent to the CRC check circuit 56.
The CRC check circuit 56 performs a CRC check based on the detected data of bit0 to bit20, and if there is no bit error, transfers the data of bit0 to bit20 to the data service signal result output circuit 57. The data service signal result output circuit 57 outputs the data of bit0 to bit20 transferred from the CRC check circuit 56 as a data service signal.

When the CRC check circuit 56 detects a bit error, the CRC check circuit 56 does not adopt the data and holds the previous data service signal.

[0030]

According to the present invention, it is possible to prevent the positive period of the ternary sync signal from being erroneously detected as a data service signal, and the data service signal can always be detected stably. become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data service signal detection device.

FIG. 2 is a time chart showing a data service signal inserted in a vertical blanking period of a Y signal when a horizontal synchronizing signal is a binary synchronizing signal.

FIG. 3 is a time chart showing a data service signal inserted in a vertical blanking period of a Y signal when a horizontal synchronizing signal is a ternary synchronizing signal.

[Explanation of symbols]

1 Sync separation circuit 2 PLL clock generator 3 A / D converter 4 Tri-level sync signal detection circuit 5 Data service signal detection circuit

Claims (2)

[Claims] 1. A sync separating circuit for separating a horizontal synchronizing signal and a vertical synchronizing signal from an input video signal, a clock generating circuit for generating a sampling clock synchronized with the horizontal synchronizing signal obtained by the sync separating circuit, and an input video signal. From the A / D conversion circuit that samples based on the sampling clock obtained by the clock generation circuit, the horizontal sync signal end position detection circuit that detects the end position of the horizontal sync signal obtained by the sync separation circuit, and the A / D conversion circuit A first slice circuit for slicing output image data with a threshold value for detecting a three-valued synchronization signal; a three-valued synchronization signal detection circuit for detecting the presence or absence of a three-valued synchronization signal based on the output of the first slice circuit; End of ternary sync signal for detecting end position of positive period of ternary sync signal based on output of first slice circuit Image data output from the position detection circuit and A / D conversion circuit
Based on the output of the second slice circuit and the second slice circuit that slices with the service signal detection threshold value,
The data service signal detection circuit for detecting the data service signal is provided, and the data service signal detection circuit detects the data service signal from when the horizontal synchronization signal end position is detected by the horizontal synchronization signal end position detection circuit. Start detection, but 3
When the three-valued sync signal is detected by the value-sync signal detection circuit, the detection result of the data service signal obtained from the horizontal sync signal end position up to that point is invalidated, and the three-value sync signal end position detection circuit detects the three-value. A data service signal detecting device, wherein detection of a data service signal is started from a time point when an end position of a positive period of a synchronization signal is detected. 2. The data service signal detection circuit is a circuit for measuring the width of the reference signal of the data service signal, a circuit for detecting that bit0 of the data service signal is low, and bits 1 to 1 of the data service signal. The circuit that detects the data of bit20 and the CRC check for the detected data service signal, update the data service signal detection result only when no error is detected, and when the error is detected The data service signal detection device according to claim 1, further comprising: a circuit that holds a previous data service signal detection result.