JP2003017620A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when a semiconductor device is constituted of a semiconductor chip size, it is feared of a damage of an element in the case of rewiring on an element region of the chip. SOLUTION: The semiconductor device comprises a conductor wiring layer 12 having grooves 10 arriving at electrode pads 8 on a front surface at a rear surface of the semiconductor chip 9 and forming a conductor wiring layer 12 electrically connected via the grooves 10, and a wiring pattern having no influence to an element region of the chip 9 provided on the rear surface side by rewiring on the chip rear surface side. Thus, in the case of mounting the semiconductor device on a mounting substrate, it is not feared to damage the element region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-like semiconductor device which can be mounted on a wiring board with high efficiency, enables high-density mounting, and realizes highly reliable board mounting, and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device which can be manufactured at a semiconductor wafer level and can realize a highly reliable semiconductor device structure, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, as the weight and size of portable devices have increased and the density thereof has increased, the density of semiconductor packages having lead terminals as external terminals has increased. A technique for mounting a semiconductor device on a wiring board or the like of an electronic device has been developed.

A conventional semiconductor device will be described below with reference to the drawings.

FIG. 6 is a diagram showing a conventional semiconductor device.
6A is a configuration perspective view, and FIG. 6B is FIG.
It is sectional drawing of AA1 place of (a).

As shown in FIG. 6, the conventional semiconductor device has a semiconductor chip 2 having a plurality of electrode pads 1 connected to internal semiconductor integrated circuit elements in a peripheral region on one main surface, and each electrode pad 1. An insulating layer 3 made of an insulating low-elasticity resin formed on the main surface region of the semiconductor chip 2 other than the above, and each electrode pad 1 on the formed insulating layer 3 in the main surface of the semiconductor chip 2. A plurality of contact pads 5 two-dimensionally arranged by rewiring by the wiring layer 4 made of the connected metal conductors, and the semiconductor chip 2 excluding the contact pads 5
And an insulating resin layer 6 such as a solder resist that protects the electrode pad 1 and the wiring layer 4 and a protruding electrode 7 such as a solder ball provided on each contact pad 5. .

[0006]

However, in the conventional semiconductor device described above, although the semiconductor device can be formed in the size of the semiconductor chip, the contact pad is formed by rewiring on the element region of the semiconductor chip, that is, the active region. However, damage to the element region has been a concern.

Further, when mounting the semiconductor device on the mounting substrate, there has been a fear of damage to the element region.

Further, in the conventional semiconductor device structure, since the electrode (projection electrode) surface is mounted downward when mounting on a substrate, the electrode surface of the semiconductor device is hidden after mounting, and the semiconductor device is directly electrically connected to the semiconductor device. There was also a problem that it was not possible to carry out a physical examination.

The present invention is to solve the above-mentioned conventional problems, and it is possible to manufacture a semiconductor device at a semiconductor wafer level,
Moreover, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof, which can realize a semiconductor device having a semiconductor chip size with high reliability.

[0010]

In order to solve the above conventional problems, a semiconductor device of the present invention comprises a semiconductor chip having a plurality of semiconductor elements and a plurality of electrode pads on its surface,
A conductor that is provided from the back surface side of the semiconductor chip, reaches the bottom of each electrode pad of the semiconductor chip and is continuous with each electrode pad, and is provided in the groove and electrically connected to the bottom of the electrode pad. A layer, an insulating resin that exposes one end of the conductor layer and fills the groove, and a conductor wiring layer that is electrically connected to the conductor layer and is formed in the back surface region of the semiconductor chip via an insulating layer. The semiconductor device is composed of

More specifically, in the semiconductor device, the front surface side of the semiconductor chip is covered with an insulating resin.

Further, the semiconductor device is a semiconductor device in which the back surface side is covered with an insulating resin except for a part of the conductor wiring layer.

Further, the conductor wiring layer is a semiconductor device having a terminal pad for an external terminal, which is patterned on the back surface region of the semiconductor chip.

The terminal pads are semiconductor devices arranged in an area array.

The electrode pad is a semiconductor device provided in the center of the semiconductor chip.

Furthermore, the conductor layer provided in the groove and electrically connected to the bottom of the electrode pad is a semiconductor device in which a conductive material is plated on the inner wall of the groove to form a conductor layer.

According to the method of manufacturing a semiconductor device of the present invention, a semiconductor wafer having a plurality of semiconductor chips having a plurality of semiconductor elements and electrode pads on the surface is formed on the surface of the semiconductor wafer. From the step of forming a continuous groove portion in each electrode pad by cutting so as to reach the bottom portion of each electrode pad, and for the groove portion of each semiconductor chip of the semiconductor wafer, a conductor electrically connected to the bottom portion of the electrode pad Forming a layer and connecting to the conductor layer,
A step of forming a conductor wiring layer on the back surface of each semiconductor chip of the semiconductor wafer, a step of exposing one end of the conductor layer, filling and sealing the groove portion with an insulating resin, and each semiconductor chip unit of the semiconductor wafer It is a method of manufacturing a semiconductor device, which comprises a step of dividing.

Specifically, in the step of forming a conductor layer electrically connected to the bottom of the electrode pad in the groove of each semiconductor chip of the semiconductor wafer, a semiconductor in which a conductive material is plated on the inner wall of the groove It is a method of manufacturing a device.

Further, in the step of forming the groove portion so as to reach the bottom portion of each electrode pad from the back surface side of the semiconductor chip, it is a method of manufacturing a semiconductor device in which the groove portion is formed by cutting the semiconductor chip base material by dicing.

In the step of connecting to the conductor layer and forming the conductor wiring layer on the back surface of each semiconductor chip of the semiconductor wafer, a pattern is formed on the back surface region of the semiconductor chip by the conductor wiring layer, and terminals for external terminals are formed. It is a method of manufacturing a semiconductor device in which a pad is formed.

Further, it is a method of manufacturing a semiconductor device, which comprises a step of coating the surface of the semiconductor wafer with an insulating resin before the step of dividing the semiconductor wafer into individual semiconductor chips.

Further, it is a method of manufacturing a semiconductor device, which comprises a step of coating the back surface of the semiconductor wafer with an insulating resin before the step of dividing the semiconductor wafer into individual semiconductor chips.

Further, in the step of connecting to the conductor layer and forming the conductor wiring layer on the back surface of each semiconductor chip of the semiconductor wafer, after forming the insulating layer on the back surface of the semiconductor wafer, the conductor wiring layer is formed on the insulating layer. It is a method of manufacturing a semiconductor device to be formed.

As described above, the semiconductor device of the present invention is
The semiconductor chip element has a continuous groove on the back side of the semiconductor chip that exposes the bottom surface of the electrode pad on the front side, and a conductive layer for electrical connection is formed in the groove and rewiring is performed on the back side of the chip. A wiring pattern that does not affect the area is provided on the back surface side of the chip. Therefore, when the semiconductor device of the present invention is mounted on the mounting substrate, there is no fear of damage to the element region.

Further, in the method of manufacturing a semiconductor device of the present invention, since the pattern is formed by rewiring on the back surface side of each semiconductor chip in a semiconductor wafer state, damage to the element region during pattern formation can be prevented. Moreover, since the groove reaching the bottom surface of the electrode pad of each semiconductor chip is formed by dicing used in the wafer process,
It is an efficient manufacturing method.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First, the semiconductor device of this embodiment will be described.

FIG. 1 is a diagram showing a semiconductor device of this embodiment. In FIG. 1, FIG. 1A is a plan view.
1B is a bottom view, and FIG. 1C is B-B1 in FIG. 1B.
It is sectional drawing of a location.

As shown in FIG. 1, the semiconductor device of this embodiment includes a real chip size package (RCS).
P), a semiconductor chip 9 having a plurality of semiconductor elements (active areas) and electrode pads 8 on the surface, and formed on the back surface side of the semiconductor chip 9 and reaching the bottom of the electrode pad 8 of the semiconductor chip. A groove portion 10 which does not penetrate, a conductor layer 11 provided in the groove portion 10 and electrically connected to the bottom portion of the electrode pad 8 of the chip, and an insulating layer electrically connected to the conductor layer 11 and formed on the back surface region of the semiconductor chip 9. The semiconductor device includes a conductor wiring layer 12 formed via (not shown). The conductor wiring layer 12 is patterned on the back surface region of the semiconductor chip and has terminal pads 13 for external terminals. The groove 10 is filled with an insulating resin 14 to fix, protect and insulate the semiconductor chip 9, and prevent the chip itself from becoming weakened due to the formation of the groove 10 in the chip. It is a thing.

The conductor layer 11 provided in the groove 10 is
An inner wall of the groove 10 corresponding to each electrode pad is plated with a conductive material to form a conductor layer 11. The groove 10 is a series of grooves 10 continuously formed on each electrode pad 8 and is formed by cutting.

In the semiconductor device of this embodiment, since the conductor wiring layer 12 on the back surface of the semiconductor chip 9 is formed via the insulating layer, a short circuit between the conductor wiring layers 12 connected to the respective electrode pads 8 is prevented. In addition, the short circuit due to the solder cream at the time of mounting on the board is prevented.

Further, in the semiconductor device of this embodiment, the terminal pads 13 are arranged in an area array as shown in the drawing, and the electrode pads 8 on the front surface are routed to the back surface through the grooves 10 and re-wired. There is something.

In the present embodiment, the semiconductor device is constructed by using a memory type semiconductor chip in which the electrode pads 8 on the surface are formed in a row in the central region of the chip, but the electrode pads are the peripheral portion of the semiconductor chip. It may be a logic chip provided in.

Next, FIG. 2 is a diagram of a semiconductor device showing a structure in which protective packaging means is applied to the semiconductor device of this embodiment. In FIG. 2, FIG. 2A is a bottom view,
2B is a cross-sectional view taken along the line C-C1 in FIG. 2A, and the basic configuration is the same as that shown in FIG. In FIG. 2, a part of the configuration shown by a broken line is a transparent view of the internal configuration.

The semiconductor device shown in FIG. 2 is such that an insulating resin 15 is formed so as to cover the electrode pads 8 on the surface of the semiconductor chip 9 in the semiconductor device configuration of FIG. Further, the back surface side of the semiconductor chip 9 is also covered with the insulating resin 15 except for a part of the conductor wiring layer 12, that is, the terminal pad 13. In addition, a ball electrode 16 such as a solder ball is formed on the terminal pad 13 for mounting on a substrate. When the surface side of the semiconductor chip 9 is covered with the insulating resin 15, the electrode pad 8 may be opened to cover only the chip surface for electrical inspection after mounting.

The semiconductor device shown in FIG. 2 has a structure suitable for mounting on a substrate, which prevents an impact applied from the outside during mounting on the substrate.

As described above, in the semiconductor device of this embodiment, the groove portion 10 reaching the bottom surface of the electrode pad 8 on the front surface is provided on the back surface side of the semiconductor chip 9, and the conductor wiring layer 12 for electrical connection is formed in the groove portion 10. A wiring pattern that does not affect the element region of the semiconductor chip 9 is provided on the chip rear surface side by forming and rewiring on the chip rear surface side. When mounting the semiconductor device on the mounting substrate, the element region is not formed. No more worrying about damage to. Further, in the semiconductor device of this embodiment, the electrode pads 8 on the front surface side are exposed even after mounting on the substrate, so that after mounting on the substrate, the probe is brought into direct contact with the semiconductor device to cause electrical conduction. Inspection is possible.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to the drawings. 3 and 4 are cross-sectional views of main steps showing the method for manufacturing a semiconductor device of this embodiment.

First, as shown in FIG. 3A, a semiconductor wafer 17 having a plurality of semiconductor chips 9 having a plurality of semiconductor elements (not shown) and electrode pads 8 formed on the surface thereof is formed. prepare.

Then, as shown in FIG. 3B, a continuous groove 10 is formed on the semiconductor wafer 17 from the back surface of each semiconductor chip 9 to the bottom of each electrode pad 8 by a dicing blade. To cut and form.
In this step, the front surface side of the semiconductor wafer 17 is masked with a protective member 18 such as a dicing sheet, and the cutting by dicing is adjusted appropriately by setting the blade width and the cutting depth to properly set the bottom surface of the electrode pad 8 to the groove portion 10. Can be exposed inside. In the formation of the groove portion 10, cutting is performed so as not to penetrate. Semiconductor wafer 17
The recognition of the electrode pad 8 from the back surface side of is possible by infrared recognition.

Next, as shown in FIG. 3C, the protective member 1
With the surface side of the semiconductor wafer 17 masked at 8, the conductor layer 11 electrically connected to the bottom of the electrode pad 8 is formed in the groove 10 of each semiconductor chip 9. In this embodiment, the conductor layer 11 is formed by plating the inner wall surface of the groove 10 with a conductive material such as gold (Au), copper (Cu), or nickel (Ni). Then, the conductor wiring layer 12 is connected to the conductor layer 11 of the groove portion 10, the conductor wiring layer 12 is patterned on the back surface of each semiconductor chip 9 in the chip back surface region, and the terminal pad 13 is formed on the end portion of the conductor wiring layer 12. In addition, in this step, before forming the conductive wiring layer on the back surface of the semiconductor chip 9, the semiconductor wafer 1 is formed.
(6) An insulating layer is formed on the back surface, and the conductor wiring layer 12 is formed on the formed insulating layer. As a result, an independent pattern of the conductor wiring layers 12 can be formed and a short circuit can be prevented.

Next, as shown in FIG. 3D, the insulating resin 14 is filled and sealed in the groove portion 10 formed in the semiconductor wafer 17 in which the wiring pattern is re-routed on the back surface of the chip by the conductor wiring layer. By filling the insulating resin 14, each semiconductor chip 9 is fixed, protected, and insulated, and the weakening of the chip itself caused by the formation of the groove 10 in the chip is prevented.

Then, as shown in FIG. 4, by dividing each semiconductor chip by dicing, the groove portion 1 connected to the front surface electrode pad 8 on the rear surface side of the semiconductor chip 9 is divided.
0, the conductor wiring layer 1 for electrical connection in the groove portion 10
2 is formed, and an individual piece of the semiconductor device having a wiring pattern re-routed on the back surface side of the chip is obtained. In addition,
Before this chip dividing step, a step of covering necessary regions on the front surface and the back surface of the semiconductor wafer with an insulating resin may be provided for packaging. Further, when dividing into chips, it may be on the front surface side or the back surface side of the semiconductor wafer.

Next, a mounting mode of the semiconductor device of this embodiment will be described. FIG. 5 is a sectional view showing substrate mounting of the semiconductor device of this embodiment.

As shown in FIG. 5, the semiconductor device of this embodiment has the same structure as that of the semiconductor device shown in FIGS. 1 and 2, but the ball electrode 16 on the back surface side of the semiconductor chip 9 is connected to the wiring of the mounting substrate 19. It is in a state of being bonded onto the electrode 20. Since the surface side of the semiconductor chip 9 is located on the upper side and the electrode pad 8 on the surface is not covered with the insulating resin 15, the probe 21 is attached to the electrode pad 8 even after mounting. The semiconductor device can be brought into contact with and directly and electrically inspected.

As described above, the semiconductor device of this embodiment has a continuous groove portion reaching the electrode pad on the front surface on the back surface side of the semiconductor chip, and a conductive wiring layer for electrical connection is formed in the groove portion, and the back surface of the chip is formed. A wiring pattern that does not affect the element area of the semiconductor chip is provided on the back surface side of the chip by rewiring on the side, and there is no concern about damage to the element area when mounting the semiconductor device on the mounting substrate. It is a device.

[0047]

The semiconductor device of the present invention has a groove portion on the back surface side of the semiconductor chip connected to the electrode pad on the front surface, and a conductive layer for electrical connection is formed in the groove portion, and rewiring is performed on the back surface side of the chip. By doing so, a wiring pattern that does not affect the element region of the semiconductor chip is provided on the back surface side of the chip.
Therefore, when the semiconductor device of the present invention is mounted on the mounting substrate, the element region can be prevented from being damaged and mounted.

Further, in the method of manufacturing a semiconductor device of the present invention, since the pattern is formed by rewiring on the back surface side of each semiconductor chip in a semiconductor wafer state, damage to the element region during pattern formation can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a mounted state of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

1 electrode pad 2 semiconductor chips 3 insulating layers 4 wiring layers 5 contact pads 6 Insulating resin layer 7 protruding electrode 8 electrode pads 9 Semiconductor chips 10 groove 11 Conductor layer 12 conductor wiring layer 13 terminal pads 14 Insulating resin 15 Insulating resin 16 ball electrode 17 Semiconductor wafer 18 Protective material 19 Mounting board 20 wiring electrodes 21 probe

Claims (14)

[Claims] 1. A semiconductor chip having a plurality of semiconductor elements and a plurality of electrode pads on its surface, and a semiconductor chip provided from the back surface side of the semiconductor chip, reaching the bottom of each electrode pad of the semiconductor chip, and each electrode. A groove portion continuous to the pad, a conductor layer provided in the groove portion and electrically connected to the bottom portion of the electrode pad, one end of the conductor layer is exposed, and an insulating resin filling the groove portion, and the conductor layer, A semiconductor device comprising: a conductor wiring layer which is electrically connected and is formed in the back surface region of the semiconductor chip via an insulating layer. 2. The semiconductor device according to claim 1, wherein the surface side of the semiconductor chip is covered with an insulating resin. 3. The semiconductor device according to claim 1, wherein the back surface side of the semiconductor chip is covered with an insulating resin except for a part of the conductor wiring layer. 4. The semiconductor device according to claim 1, wherein the conductor wiring layer is patterned on the back surface region of the semiconductor chip and has terminal pads for external terminals. 5. The semiconductor device according to claim 4, wherein the terminal pads are arranged in an area array. 6. The semiconductor device according to claim 1, wherein the electrode pad is provided in a central portion of the semiconductor chip. 7. The conductor layer provided in the groove portion and electrically connected to the bottom portion of the electrode pad forms a conductor layer by plating a conductive material on the inner wall of the groove portion. The semiconductor device according to claim 1. 8. A semiconductor wafer having a plurality of semiconductor elements and electrode pads formed on the surface thereof, wherein a plurality of semiconductor chips are formed on the surface of the semiconductor wafer, reaching the bottom of each electrode pad from the back surface side of each semiconductor chip. To form a continuous groove portion in each electrode pad by cutting so as to, for the groove portion of each semiconductor chip of the semiconductor wafer,
Forming a conductor layer electrically connected to the bottom of the electrode pad; connecting to the conductor layer and forming a conductor wiring layer on the back surface of each semiconductor chip of the semiconductor wafer; and one end of the conductor layer And a step of filling and sealing the groove portion with an insulating resin, and a step of dividing the semiconductor wafer into individual semiconductor chips. 9. A step of forming a conductor layer electrically connected to a bottom portion of an electrode pad in a groove portion of each semiconductor chip of a semiconductor wafer, wherein an inner wall of the groove portion is plated with a conductive material. The method of manufacturing a semiconductor device according to claim 8. 10. The groove portion is formed by cutting the semiconductor chip base material by dicing in the step of forming the groove portion so as to reach the bottom portion of each electrode pad from the back surface side of the semiconductor chip. A method of manufacturing a semiconductor device according to item 1. 11. In the step of connecting to a conductor layer and forming a conductor wiring layer on the back surface of each semiconductor chip of a semiconductor wafer, a pattern is formed on the back surface region of the semiconductor chip by the conductor wiring layer, and a terminal for an external terminal is formed. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a pad is formed. 12. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of coating the surface of the semiconductor wafer with an insulating resin before the step of dividing the semiconductor wafer into individual semiconductor chips. Method. 13. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of coating the back surface of the semiconductor wafer with an insulating resin before the step of dividing the semiconductor wafer into individual semiconductor chips. Method. 14. In the step of connecting to a conductor layer and forming a conductor wiring layer on the back surface of each semiconductor chip of a semiconductor wafer, after forming an insulation layer on the back surface of the semiconductor wafer, the conductor wiring layer is formed on the insulation layer. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed.