JP2003007852A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device for which the timing control can be facilitated and a layout size is reduced by arranging a word line drivers at one side of a memory cell array. SOLUTION: In this semiconductor memory device, a first word line driver region WD1 at one side, and a second word line driver region WD2 at the other side are arranged sandwiching an address signal line region RA. On the opposite side of the address signal line region RA of the first word line driver region WD1, a memory cell array CA is arranged. Output signal lines of word line drivers in the second word line driver region WD2 are electrically connected to word lines WL on the memory cell array CA through third metal wirings M3 formed so as to cross the address signal line region RA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a word line driver is arranged on one side of a memory cell array, and more particularly to a semiconductor memory device for embedded logic.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access M)
In a high-density semiconductor memory device such as an emory), the width and interval of the memory cell selection line (hereinafter, word line) are processed to have the minimum width and interval according to the technique at that time.
For example, a DRAM memory cell is composed of one MOS transistor and one capacitor. The word line is a gate wiring of a MOS transistor which constitutes a memory cell. In the case of DRAM, it is necessary to make the memory cells alternately line-symmetrical, but even between the word lines with the minimum line width and spacing, it is easy to connect the word lines simply by arranging the memory cells in a grid pattern. You can

However, it is not easy to connect the word lines formed with the minimum line width and spacing and the word line driver for driving them in the most suitable arrangement. In recent years, CMOS circuits have been used as word line drivers, and one N
It is a CMOS inverter composed of a MOS transistor and one PMOS transistor. The row decoder is a NAND circuit that receives three address signals including a precharge signal as inputs. Therefore, the word line driver and row decoder connected to one word line are composed of two PMOS transistors and four NMOS transistors. It is difficult to fit these elements in a region matching the minimum line width and spacing of word lines.

FIG. 15 shows an example of a layout diagram of a conventional word line driver. Two CMOS inverters (word line drivers) are shown in the word line driver region WD of FIG. Each MOS transistor is composed of a source region connected to the power supply, a drain region connected to the word line at the output terminal of the CMOS inverter, and a gate region between them. SAC (Se
If you apply lf Aligned Contact) technology to this part,
It is possible to draw the pitch of the source region and the drain region with the sum of the minimum line width and the interval. However, since the same number of power supply wirings is required in addition to the word line wirings, two wiring areas are required for one word line driver.
That is, in reality, only two word lines WL can be wired in a region where four word lines WL can be wired, and only two word line drivers corresponding to two word lines can be arranged in this region.

Therefore, some ideas have been considered for connecting word line drivers to all the word lines WL.

First, there is a method of arranging word line drivers on both sides of the memory cell array, connecting the word line drivers to all the word lines, and mutually driving the word lines.
FIG. 16 is an example of a detailed layout diagram of the word line driver of the semiconductor memory device in the first conventional technique. In FIG. 16, two word line drivers are arranged on one side of the memory cell array CA for the four word lines WL0 to WL3. By arranging in this way, the word line driver can be arranged in the minimum area and can be connected to all the word lines WL.

The second method is to control the source terminal of the word line driver by the power supply decoder. FIG. 17 is a circuit diagram of a word line driver of a semiconductor memory device in the second related art, and FIG. 18 is an example of a detailed layout diagram of a word line driver of the semiconductor memory device in the second related art. In FIG. 17, a word line driver is arranged on one side of the memory cell array CA, and the output of one row decoder is input to the two word line drivers. Then, instead of connecting the power source wiring to the source terminal of the word line driver, the output wiring of the power source decoder (selected power source line S
V) is connected.

As shown in FIG. 17, the word line driver in the second conventional technique is composed of one PMOS transistor and two NMOS transistors. Figure 1
As shown in FIG. 8, the selected power supply line SV that replaces the power supply line connected to the source terminal of the PMOS transistor is the word line W.
Since it is wired at a position orthogonal to L, if the SAC technique is applied to this portion, it is possible to draw the pitch of the source region and the drain region by the sum of the minimum line width and the interval. Therefore, even if the word line driver is arranged only on one side of the memory cell array CA, the word line driver can be connected to all the word lines WL.

[0009]

However, when the selected word line WL operates, due to the inter-line parasitic capacitance,
The phenomenon that the potential of the non-selected word line WL floats occurs. When the potential of the non-selected word line WL rises, the off-current to the MOS transistor of the memory cell increases, and the charge stored in the capacitor escapes to the bit line. Since the DRAM holds data by storing charges in a minute capacitor, the unselected word line W
The floating phenomenon of the L potential hinders information retention.

Particularly, when the word line drivers are arranged on both sides of the memory cell array CA which is the first conventional technique, the floating amount of the potential of the non-selected word line becomes larger than when the word line drivers are arranged on one side. FIG. 19 shows a circuit model in the case of word line drivers arranged on both sides.
FIG. 19B shows the analysis result of this circuit model by the circuit analysis simulator in FIG. Further, FIG. 20 shows a circuit model in the case of the one-sided word line driver.
FIG. 20 (b) shows the analysis result of this circuit model by the circuit analysis simulator in FIG. 20 (b). 19B and 20B, the horizontal axis represents time and the vertical axis represents potential. From the figure, it can be seen that when the word line drivers are arranged on both sides, the floating amount of the potential of the non-selected word line due to the parasitic resistance and the parasitic capacitance of the word line is larger. Therefore, when the word line drivers are arranged on both sides, the information holding characteristic is deteriorated.

Further, when the word line drivers are arranged on both sides of the memory cell array CA, the routing of the address signal lines and the timing signal lines becomes complicated, and the operation speed is lowered and the power consumption is increased. In many semiconductor memory devices such as DRAMs, delicate timing control is required between the operation of the word line WL and the sense operation of the bit line during the write / read operation to the memory cell. The size of the memory cell array CA is
It is as large as several mm, which is a concern about the influence of wiring delay. This makes it difficult to match the operation timings of the word line drivers arranged on both sides of the memory cell array CA, and if the timing control is incorrect, not only the write / read operation will be delayed, but also the information will be destroyed. Will occur. Therefore, it is necessary to devise the routing of the signal line that controls the operation of the word line driver, and to allow a margin in the operation timing so that the delay does not cause a defective phenomenon. Then, the operation speed of the entire semiconductor memory device becomes slow.

Further, in a large-capacity semiconductor memory device, a plurality of memory cell arrays are present in a chip, which makes the routing of timing signal lines and address signal lines more complicated, which makes it difficult to control and operates. There is a problem that the current increases and the chip area increases.

When the power supply decoder of the second conventional technique is used, the operating current increases and the speed of word line operation decreases. Actually, the number of word line drivers and row decoders connected to one memory cell array is enormous, and for example, it is composed of 1024 word line drivers and 512 row decoders. Therefore, the current required to raise or lower the potential of the selected power source of the word line driver is one word line because many MOS transistors (MOS transistors forming the word line driver) are connected to the selected power source line. It becomes 4 to 10 times the charge / discharge current with respect to WL. In other words, the power-decoding word line driver requires only 4
It consumes 10 times as much current.

Further, in order to drive a wiring having a heavy capacity at a high speed, a large transistor is required. If the drivability of the transistor is not sufficient, the transition time of the word line WL is extended and the operation speed is reduced. However, the power supply decoder cannot be provided with sufficient drive capability because it must be accommodated in a fixed area (for example, an area sandwiched between the memory cell array and the word line driver). Therefore, in the power supply decoding method which is the second conventional technique, the operation speed of the entire semiconductor memory device becomes slow.

The present invention has been made to solve the above problems, and an object of the present invention is to arrange a word line driver on one side of a memory cell array for facilitating timing control and layout size. It is to provide a semiconductor memory device that reduces

[0016]

In a semiconductor memory device according to the present invention, an address signal line region in which an address signal line is wired and at least one row decoder are arranged on one side of the address signal line region. A first row decoder region, a second row decoder region in which at least one row decoder is arranged on the other side of the address signal line region, and the address signal sandwiching the first row decoder region. At least one first word line driver region in which at least one word line driver is arranged on one side of the line region and at least one on the other side of the address signal line region sandwiching the second row decoder region. A second word line driver area in which one word line driver is arranged,
A first memory cell array in which at least two word lines are wired on one side of the address signal line region sandwiching the first row decoder region and the first word line driver region. The output signal line of the word line driver arranged in the second word line driver area is
Wiring is performed on the first memory cell array across the address signal line region. Further, at least two word lines are arranged on the other side of the address signal line region sandwiching the second row decoder region and the second word line driver region.
The output signal line of the word line driver disposed in the first word line driver region is wired on the second memory cell array across the address signal line region. It has a feature.

Further, in the semiconductor memory device according to the present invention, the address signal line region in which the address signal line is wired, and the first row decoder in which at least one row decoder is arranged on one side of the address signal line region. A decoder region and a second row decoder region in which at least one row decoder is arranged on the other side of the address signal line region,
A first word line driver region in which at least one word line driver is arranged is sandwiched between one side of the address signal line region sandwiching the first row decoder region and the second row decoder region. On the other side of the address signal line region, a second word line driver region in which at least one word line driver is arranged, the first row decoder region and the first word line driver region are sandwiched. A first memory cell array in which at least two word lines are wired is provided on one side of the address signal line region to form a word line driver arranged in the second word line driver region. The first metal wiring layer electrically connected to the drain region of each MOS transistor is located on the second word line driver region and is located on the first word line driver region.
Second metal extending over the first memory cell array across the address signal line region via a first connection hole formed in an interlayer insulating film formed on the metal wiring layer of Via a second connection hole formed in the interlayer insulating film electrically connected to the wiring layer and electrically connected to the second metal wiring layer on the first memory cell array. , And is electrically connected to the word line wired in the first memory cell array.

Further, the semiconductor memory device according to the present invention includes an address signal line region in which address signal lines are wired, and a row decoder region in which at least one row decoder is arranged on one side of the address signal line region. , A first word line driver region in which at least two word line drivers are arranged on one side of the address signal line region sandwiching the row decoder region, and at least on the other side of the address signal line region. A second word line driver area in which two word line drivers are arranged and a power supply decoder for controlling the word line driver in the first word line driver area are provided on one side of the address signal line area. The first power supply decoder region arranged and the second word line driver region on the other side of the address signal line region A second power supply decoder region in which a power supply decoder for controlling the selected word line driver is arranged, and at least 4 on one side of the address signal line region sandwiching the row decoder region and the first word line driver region. A first memory cell array having a plurality of word lines wired therein, and an output signal line of the word line driver arranged in the second word line driver region extends across the address signal line region. Is wired in the memory cell array.

Further, the semiconductor memory device according to the present invention includes an address signal line region in which address signal lines are wired, and a row decoder region in which at least one row decoder is arranged on one side of the address signal line region. , A first word line driver region in which at least two word line drivers are arranged on one side of the address signal line region sandwiching the row decoder region, and at least on the other side of the address signal line region. A second word line driver area in which two word line drivers are arranged and a power supply decoder for controlling the word line driver in the first word line driver area are provided on one side of the address signal line area. The first power supply decoder region arranged and the second word line driver region on the other side of the address signal line region A second power supply decoder region in which a power supply decoder for controlling the selected word line driver is arranged, and at least 4 on one side of the address signal line region sandwiching the row decoder region and the first word line driver region. A first memory cell array having a plurality of word lines wired therein, and a first memory cell array electrically connected to a drain region of each MOS transistor forming a word line driver arranged in the second word line driver region. A first metal wiring layer is formed on the second word line driver region,
Second metal extending over the first memory cell array across the address signal line region via a first connection hole formed in an interlayer insulating film formed on the metal wiring layer of Via a second connection hole formed in the interlayer insulating film electrically connected to the wiring layer and electrically connected to the second metal wiring layer on the first memory cell array. , And is electrically connected to the word line wired in the first memory cell array.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor memory device of the present invention effectively utilizes a thin film wiring layer which allows high-density processing, and selects signal lines (hereinafter, word lines) arranged with a minimum line width and interval.
The above-mentioned driver is arranged on one side of the memory cell array to improve the problems in the conventional semiconductor memory device.
In particular, it is effective for a logic embedded memory in which a large number of wiring layers are prepared, and it is effective in reducing the mounting area, operating power consumption, and operating speed.

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram of a semiconductor memory device according to the first embodiment. In the semiconductor memory device of the present embodiment, the first row decoder region RD1 is arranged on one side and the second row decoder region RD2 is arranged on the other side with the address signal line region RA interposed therebetween. Also,
The first word line driver area WD is provided on the right side of the first row decoder area RD1 (on the side opposite to the address signal line area RA).
The first word line driver region WD2 is arranged on the left side of the second row decoder region RD2 (on the side opposite to the address signal line region RA). Then, on the right side of the first word line driver area WD1 (first row decoder area RD
A memory cell array CA is arranged on the side opposite to 1).

Further, in FIG. 1, four word lines WL0 to WL0 are provided.
WL3, four CMOS inverters (word line drivers), and four NAND circuits (row decoders) are shown. Two CMOSs in each word line driver area
Inverters are arranged, and two are provided in each row decoder area.
Each NAND circuit is arranged.

The address signal line is an address signal line region R.
The first row decoder region RD1 and the second row decoder region RD2 are arranged in A and are laid in the vertical direction of the drawing.

Each row decoder is a precharge NAND circuit composed of one PMOS transistor and three NMOS transistors. The precharge signal and the decoded row address signal are supplied from the address signal line to the input terminal of each NAND circuit. The combination of address signal lines connected to each row decoder is different, and a unique row decoder is selected according to the input row address.

Each word line driver has one NM.
It is a CMOS inverter composed of an OS transistor and one PMOS transistor. The input signal of each word line driver is the output signal of the corresponding row decoder. Therefore, the output of the word line driver receiving the output signal from the uniquely selected row decoder is activated and the unique word line WL is selected.

Although not shown, each memory cell is, for example, a DRAM memory cell composed of one MOS transistor and one capacitor. The gate terminal of the MOS transistor of each memory cell is electrically connected to the word line WL and is supplied with the output signal of the word line driver.

In FIG. 1, even-numbered word lines WL0, W
The output signal line of the CMOS inverter arranged in the first word line driver region WD1 is connected to L2, and the odd-numbered word lines WL1 and WL3 are connected to the CMOS inverter arranged in the second word line driver region WD2. The output signal line is connected. That is, the output signal line of the CMOS inverter in the second word line driver region WD2 is electrically connected to the gate wiring (word line) of the memory cell in the memory cell array CA across the address signal line region RA.

Next, FIGS. 2 to 5 are detailed layout diagrams of the word line driver region of the semiconductor memory device according to the first embodiment. FIGS. 2 to 5 show layouts of two word line drivers (CMOS inverters) arranged in each word line driver region, arranged at the pitch of the minimum processing dimension. Here, what is characteristic is that the upper metal wiring layer (third metal wiring layer) is used for the connection between the word line WL and the word line driver. Incidentally, FIG.
5 indicates the gate polysilicon (gate region), the hatched portion in FIG. 3 indicates the first metal wiring layer M1, the hatched portion in FIG. 4 indicates the second metal wiring layer M2, and the hatched portion in FIG. 3 shows a metal wiring layer M3. 6 is a sectional view taken along the line AA ′ shown in FIG. 2, and FIG. 7 is a sectional view taken along the line BB ′ shown in FIG.

As shown in FIGS. 2 to 7, in the NMOS transistor, a source / drain region formed by an n ⁻ type diffusion layer and a gate insulating film between these source / drain regions are formed on the p-well region. It is composed of a gate electrode (gate wiring) formed through the above. In addition, the PMOS transistor is on the n-well region,
It is composed of a source / drain region composed of ap ⁺ type diffusion layer and a gate electrode (gate wiring) formed between the source / drain region via a gate insulating film. And one PMOS transistor and one
One NMOS transistor forms a CMOS inverter.

Then, the first metal wiring layer M1 electrically connected to the source / drain regions is formed via the contact formed in the interlayer insulating film formed above the gate wiring layer. (Fig. 3). Further, a second metal wiring layer M2 electrically connected to the drain region is formed via the first via V1 formed in the interlayer insulating film formed on the upper layer (FIG. 4). . The second metal wiring forms the output signal line of the CMOS inverter and is electrically connected to the word line WL which is the gate wiring of the memory cell.

The specific resistance value of the gate wiring is several Ω / □ to several hundreds Ω / □, which is one to four orders of magnitude higher than the specific resistance value of the metal wiring. Therefore, on the memory cell array CA, wirings having the same pitch are laid using the second metal wiring layer M2 for each word line WL, and the gate wiring and the second metal wiring layer M2 are connected in places. Is desirable.

The output signal line of the CMOS inverter in the first word line driver region WD1 is formed by the second metal wiring layer M2, and the memory cell array CA is formed.
It is wired above and is electrically connected to the word line WL.

On the other hand, the second word line driver area WD2
The output signal line of the CMOS inverter in is formed by the second metal wiring layer M2. Then, the second via V2 formed in the interlayer insulating film formed in the upper layer
It is electrically connected to the third metal wiring layer M3 formed in the upper layer via a (FIG. 5). Further, it is electrically connected to the second metal wiring layer M2 via the second via V2b formed on the memory cell array CA. That is, the output signal line of the CMOS inverter in the second word line driver region WD2 is formed as a third metal wiring M3 formed so as to straddle the address signal line region RA.
Is electrically connected to the word line WL on the memory cell array CA via.

The first metal wiring layer M1 is also used as a bit line on the memory cell array CA, and the second metal wiring layer M2 is also used as an address signal line on the address signal line area RA. To be Although not shown, the global wiring and the power supply wiring are laid in a layer above the third metal wiring layer M3.

As described above, by dividing and arranging the word line driver into the two regions WD1 and WD2 with the address signal line region RA sandwiched therebetween, each element can be arranged with the minimum line width and interval, and mounting is performed. The area can be reduced. Further, since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained. Further, as compared with the case of arranging the word line drivers on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased. (Second Embodiment) In the semiconductor memory device according to the second embodiment, a memory cell array is further arranged on one side of the second word line driver area.

FIG. 8 is a circuit diagram of a semiconductor memory device according to the second embodiment. In the semiconductor memory device of the present embodiment, the first row decoder region RD1 is arranged on one side and the second row decoder region RD2 is arranged on the other side with the address signal line region RA interposed therebetween. The right side of the first low decoder area RD1 (address signal line area RA
The first word line driver area WD1 is on the opposite side), and the second word line driver area WD2 is on the left side of the second row decoder area RD2 (on the opposite side of the address signal line area RA).
Are arranged. Then, the first memory cell array CA1 is provided on the right side of the first word line driver area WD1 (on the side opposite to the first row decoder area RD1) and the left side of the second word line driver area WD2 (second row decoder area). The second memory cell array CA2 is arranged on the side opposite to RD2).

FIG. 8 shows eight word lines WL10-WL.
13, WL20 to WL23, four CMOS inverters (word line drivers), and four NAND circuits (row decoders) are shown. Two CMOS inverters are arranged in each word line driver area, two NAND circuits are arranged in each row decoder area, and
Four word lines WL are provided in each memory cell array.

The address signal line is an address signal line region R.
The first row decoder region RD1 and the second row decoder region RD2 are arranged in A and are laid in the vertical direction of the drawing.

Each row decoder is a precharge type NAND circuit composed of one PMOS transistor and three NMOS transistors. The precharge signal and the decoded row address signal are supplied from the address signal line to the input terminal of each NAND circuit. The combination of address signal lines connected to each row decoder is different, and a unique row decoder is selected according to the input row address.

Each word line driver has one NM.
It is a CMOS inverter composed of an OS transistor and one PMOS transistor. The input signal of each word line driver is the output signal of the corresponding row decoder. Therefore, the output of the word line driver receiving the output signal from the row decoder uniquely selected is activated, and the unique word line WL of each memory cell array is selected.

Although not shown, each memory cell is, for example, a DRAM memory cell composed of one MOS transistor and one capacitor. The gate terminals of the MOS transistors of the memory cells in the first and second memory cell arrays CA1 and CA2 are connected to the word line WL which is the gate wiring of the memory cells,
Output signals are supplied from the word line drivers arranged in the second word line driver areas WD1 and WD2.

In FIG. 8, word lines WL10, WL12,
The output signal lines of the CMOS inverters arranged in the first word line driver region WD1 are connected to WL20 and WL22, and the word lines WL11, WL13, WL21, W are connected.
The output signal line of the CMOS inverter arranged in the second word line driver region WD2 is connected to L23.

That is, the first word line driver area W
The output signal line of the CMOS inverter in D1 is the first
Of the memory cells in the memory cell array CA1 (word lines WL10, WL12), and further, the gate lines of the memory cells in the second memory cell array CA2 (word lines WL20) across the address signal line region RA. , WL22). The output signal line of the CMOS inverter in the second word line driver region WD2 is electrically connected to the gate wiring (word lines WL21, WL23) of the memory cell in the second memory cell array CA2, and further, the address signal line. It is electrically connected to the gate wiring (word lines WL11, WL13) of the memory cell in the first memory cell array CA1 across the region RA.

Next, FIG. 9 shows a detailed layout diagram of the word line driver region of the semiconductor memory device in the second embodiment. The structure up to the second metal wiring layer M2 is the same as that of the first embodiment, and the description thereof is omitted. Here, further layers will be described.

The output signal line of the CMOS inverter in the first word line driver region WD1 is formed by the second metal wiring layer M2, and is wired on the first memory cell array CA1 and electrically connected to the word line WL. It is connected to the. Further, it is electrically connected to the third metal wiring layer M3 formed in the upper layer through the second via V21a formed in the interlayer insulating film formed in the upper layer of the second metal wiring layer M2. Has been done. Then, it is electrically connected to the second metal wiring layer M2 via the second via V22b formed on the second memory cell array CA2.

On the other hand, the second word line driver area WD2
The output signal line of the CMOS inverter in is formed by the second metal wiring layer M2, is wired on the second memory cell array CA2, and is electrically connected to the word line WL. In addition, the second via V22 formed in the interlayer insulating film formed in the upper layer of the second metal wiring layer M2.
It is electrically connected to the third metal wiring layer M3 formed in the upper layer via a. Then, it is electrically connected to the second metal wiring layer M2 via the second via V21b formed on the first memory cell array CA1.

That is, the first word line driver area W
The output signal line of the CMOS inverter in D1 is the second
In the metal wiring layer M2 of the first memory cell array CA
One word line WL and the word line WL of the second memory cell array CA2 are electrically connected to each other via the third metal wiring layer M3 formed so as to straddle the address signal line region RA. The output signal line of the CMOS inverter in the second word line driver region WD2 is the second memory cell array C in the second metal wiring layer M2.
A2 word line WL and address signal line area RA
It is electrically connected to the word line WL of the first memory cell array CA1 via the third metal wiring layer M3 formed so as to straddle the line.

As described above, by dividing and arranging the word line driver into the two regions WD1 and WD2 with the address signal line region RA sandwiched therebetween, each element can be arranged with the minimum line width and interval, and mounting is performed. The area can be reduced. Further, since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained. Further, as compared with the case where the word line drivers are arranged on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased.

In addition, the second word line driver area WD2
By arranging the memory cell array on one side as well, it is possible to configure a memory macro having a capacity twice that of the first embodiment. (Third Embodiment) In the semiconductor memory device according to the third embodiment, the power supply control of the word line driver is performed by the power supply decoder, and the power supply decoder area is divided and arranged on both sides of the address signal line area. It is a thing.

FIG. 10 is a circuit diagram of a semiconductor memory device according to the third embodiment. The semiconductor memory device of this embodiment is similar to the first embodiment in that the first and second row decoder regions R are sandwiched by the address signal line region RA.
D1 and RD2 are arranged, and the first and second word line driver regions WD1 and WD2 are arranged on one side of these. The memory cell array CA is arranged on one side of the first word line driver area WD1.

Further, in the third embodiment, the first power supply decoder region SD1 is arranged on one side and the second power supply decoder region SD2 is arranged on the other side across the address signal line region RA. ing.

FIG. 10 shows four word lines WL0-WL0.
3 and 4 word line drivers, 2 row decoders and 4 power supply decoders are shown. Two word line drivers are arranged in each word line driver area,
One row decoder is arranged in each row decoder region, and two power decoders are arranged in each power decoder region.

The address signal line is an address signal line region R.
The first row decoder region RD1 and the second row decoder region RD2 and the first power decoder region SD1 and the second power decoder region SD2 are arranged in the vertical direction on the paper surface. Has been done.

Each row decoder is a modified NAND circuit composed of one PMOS transistor and two NMOS transistors. The precharge signal and the decoded row address signal are supplied from the address signal line to the input terminal of each NAND circuit. The combination of address signal lines connected to each row decoder is different, and a unique row decoder is selected according to the input row address.

Each word line driver has two NMs.
This is a modified NAND circuit including OS transistors N1 and N2 and one PMOS transistor P1. P
The source terminal of the MOS transistor P1 is the selected power supply line S
Connected to V. The NMOS transistor N1 has a source terminal connected to GND and a drain terminal PMOS
It is connected to the drain terminal of the transistor P1. The output signals of the corresponding row decoders are both supplied to the gate terminals. Also, the NMOS transistor N
2, the source terminal is connected to GND and the gate terminal is P
An inverted signal of the signal on the selected power supply line SV connected to the MOS transistor P1 is supplied. This NMOS
The transistor N2 functions to suppress the word line WL in the non-selected state to the low potential state. Further, the drain terminal of the MOS transistor forming the word line driver is connected to the word line WL.

The word line driver has such a circuit configuration that the row decoder at the preceding stage is shared by the two word line drivers. Since the row decoder is shared, the two word line drivers connected to the uniquely selected row decoder are simultaneously selected. Then, one of the two word line drivers uniquely selected is selected based on the signal from the selected power supply line SV supplied to the source terminal of the PMOS transistor.

Each power supply decoder selects the selected power supply line SV based on the 1-bit row address signal and the precharge signal.
Is a circuit for activating the. Depending on the state of the row address, either one of the two power supply decoders arranged in each power supply decoder area (selected power supply line SV) is activated.

The selected power supply line SV which is the output signal line of the power supply decoder is connected to the source terminal of the PMOS transistor of the word line driver. The selected power supply line SV via the inverter is connected to the gate terminal of one NMOS transistor of the word line driver. Finally, one word line driver is selected by the combination of the output of the row decoder and the decoded selected power supply line SV.

Although not shown, each memory cell is, for example, a DRAM memory cell composed of one MOS transistor and one capacitor. The gate terminal of the MOS transistor of each memory cell is connected to the word line WL and is supplied with the output signal of the word line driver.

Further, in FIG. 10, word lines WL0,
An output signal line of a word line driver arranged in the first word line driver area WD1 is connected to WL1, and a word line driver arranged in the second word line driver area WD2 is connected to word lines WL2 and WL3. The output signal line of is connected. That is, the output signal line of the word line driver in the second word line driver region WD2 is electrically connected to the gate line (word line WL) of the memory cell of the memory cell array CA across the address signal line region RA. .

FIG. 11 is a detailed layout diagram of the word line driver area of the semiconductor memory device according to the third embodiment. FIG. 11 shows a layout of two word line drivers (CMOS inverters) arranged in the pitch of the minimum processing size and two in each word line driver region. Here, what is characteristic is that the upper metal wiring layer (third metal wiring layer M3) is used for the connection between the word line WL and the word line driver. For the sake of explanation, FIG. 11 shows the layout below the second metal wiring layer M2 and the layout of the third metal wiring layer M3 separately. By overlapping the second via V2, the layout diagram in the third embodiment is obtained.

As shown in FIG. 11, the NMOS transistor is formed on the p-well region with a source / drain region formed of an n ⁻ type diffusion layer and a gate insulating film between these source / drain regions. The gate electrode (gate wiring) is formed. Also PM
The OS transistor is composed of a source / drain region formed of ap ⁺ type diffusion layer on the n-well region and a gate electrode (gate wiring) formed between these source / drain regions via a gate insulating film. Has been done. And one PMOS transistor and two NM
A word line driver is formed by the OS transistor.

Then, the first metal wiring layer M1 electrically connected to the source / drain regions is formed through the contact formed in the interlayer insulating film formed above the gate wiring layer. There is. Further, via the first via V1 formed in the interlayer insulating film formed on the upper layer,
Second metal wiring layer M electrically connected to the drain region
2 is formed. The second metal wiring layer M2 forms an output signal line of the word line driver and is electrically connected to the word line WL which is the gate wiring of the memory cell.

The output signal line of the word line driver in the first word line driver region WD1 is formed by the second metal wiring layer M2, is wired on the memory cell array CA, and is electrically connected to the word line WL. Has been done.

On the other hand, the second word line driver area WD2
The output signal line of the word line driver in is the second via V2a formed in the interlayer insulating film formed in the upper layer.
Third metal wiring layer M formed further above through
3 is electrically connected. Then, it is electrically connected to the word line WL (second metal wiring) via the second via V2b formed on the memory cell array CA. That is, the output signal line of the word line driver in the second word line driver region WD2 is on the word line WL on the memory cell array CA via the third metal wiring M3 formed so as to straddle the address signal line region RA. Is electrically connected to.

The first metal wiring layer M1 is also used as a bit line on the memory cell array CA, and the second metal wiring layer M2 is also used as an address signal line on the address signal line area RA. To be Although not shown, the global wiring and the power supply wiring are laid in a layer above the third metal wiring layer M3.

Thus, even when the word line driver is controlled by the decoded selected power supply line SV, the power supply decoder area is divided with the address signal line area RA interposed therebetween.
By arranging them, the word line driver can be arranged on one side of the memory cell array.

Therefore, by dividing and arranging the word line driver in the two regions WD1 and WD2 with the address signal line region RA interposed therebetween, each element can be arranged with the minimum line width and interval, and the mounting area can be reduced. Can be reduced. Further, since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained. Further, as compared with the case of arranging the word line drivers on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased. (Fourth Embodiment) In addition to the configuration of the third embodiment, the semiconductor memory device of the fourth embodiment has a memory cell array arranged also on one side of the second word line driver area. is there.

FIG. 12 is a circuit diagram of a semiconductor memory device according to the fourth embodiment. The semiconductor memory device of the present embodiment is similar to the third embodiment in that the first and second row decoder regions R are sandwiched by the address signal line region RA.
D1 and RD2, and first and second power supply decoder areas SD1 and SD2 are arranged, and the first or second word line driver area WD1 is provided on one side of each row decoder area.
WD2 is arranged. The first memory cell array CA1 is arranged on one side of the word line driver area WD1 and the second memory cell array CA2 is arranged on one side of the word line driver area WD2.

FIG. 12 shows eight word lines WL10-W.
L13, WL20 to WL23, four word line drivers, two row decoders, and four power supply decoders are shown. Two word line drivers are arranged in each word line driver area, one row decoder is arranged in each row decoder area, and two row decoders are arranged in each power decoder area.
Each power supply decoder is arranged, and each memory cell array is provided with four word lines WL.

Incidentally, the circuit configuration arranged in each region is the same as that of the third embodiment, and therefore its explanation is omitted.

In FIG. 12, the output signal line (selected power supply line SV) of the power supply decoder arranged in the first power supply decoder area SD1 is a PMOS transistor of the word line driver arranged in the first word line driver area WD1. Is connected to the source terminal of. Further, the output signal line (selected power supply line SV) of the power supply decoder arranged in the second power supply decoder area SD2 has the second word line driver area WD2.
Is connected to the source terminal of the PMOS transistor of the word line driver arranged at.

In addition, word lines WL10 and WL11 wired in the first memory cell array CA1 and WL20 and WL21 wired in the second memory cell array CA2 are
The output signal lines of the word line drivers arranged in the first word line driver area WD1 are connected. Then, the word line WL wired in the first memory cell array CA1
The output signal line of the word line driver arranged in the second word line driver region WD2 is connected to the WL22 and WL23 wired to the WL12 and WL13 and the second memory cell array CA2.

That is, the first word line driver area W
The output signal line of the word line driver in D1 is electrically connected to the gate wiring (word lines WL10, WL11) of the memory cell in the first memory cell array CA1, and further, the second signal across the address signal line region RA. It is electrically connected to the gate wiring (word lines WL20, WL21) of the memory cell in the memory cell array CA2. The output signal line of the word line driver in the second word line driver region WD2 is electrically connected to the gate wiring (word lines WL22, WL23) of the memory cell in the second memory cell array CA2, and further,
The gate wiring (word line W of the memory cell in the first memory cell array CA1 is straddled across the address signal line area RA.
L12, WL13) are electrically connected.

Regarding the layout of the word line driver area of the semiconductor memory device in the fourth embodiment,
Since the configuration is similar to that of the second and third embodiments,
The description is omitted.

As described above, by dividing and arranging the word line driver into the two regions WD1 and WD2 with the address signal line region RA interposed therebetween, each element can be arranged with the minimum line width and interval, and mounting is performed. The area can be reduced. Further, since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained. Further, as compared with the case of arranging the word line drivers on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased.

In addition, the second word line driver area WD2
By arranging the memory cell array on one side as well, it is possible to configure a memory macro having a capacity twice that of the third embodiment. (Fifth Embodiment) A semiconductor memory device according to the fifth embodiment has a power supply decoder for controlling the power supply of a word line driver, and is arranged in a row decoder region arranged on one side of an address signal line region. The output signal of one row decoder is shared by the four word line drivers.

FIG. 13 is a circuit diagram of a semiconductor memory device according to the fifth embodiment. In the semiconductor memory device of the present embodiment, the row decoder region RD is arranged on one side and the second word line driver region WD2 is arranged on the other side with the address signal line region RA interposed therebetween. The first word line driver area WD1 is arranged on the right side of the decoder area RD (on the side opposite to the address signal line area RA). A first power supply decoder SD1 is arranged on one side and a second power supply decoder SD2 is arranged on the other side of the address signal line area RA. Then, on the right side of the first word line driver area WD1 (the row decoder area R
The memory cell array CA is arranged on the side opposite to D).

In FIG. 13, four word lines WL0 to WL
Three, four word line drivers, one row decoder and four power supply decoders are shown. Two word line drivers are arranged in each word line driver area,
Two power supply decoders are arranged in each power supply decoder area.

The address signal line is the address signal line region R.
The first power supply decoder region S, which is disposed between the row decoder region RD and the second word line driver region.
It is laid in the vertical direction on the paper surface between D1 and the second power supply decoder area SD2.

Each row decoder is a modified NAND circuit composed of one PMOS transistor and two NMOS transistors. The precharge signal and the decoded row address signal are supplied from the address signal line to the input terminal of each NAND circuit. The combination of address signal lines connected to each row decoder is different, and a unique row decoder is selected according to the input row address.

Each word line driver has two NMs.
It is a modified NAND circuit composed of an OS transistor and one PMOS transistor. This configuration is the third
This is similar to the word line driver in the above embodiment.

Each power supply decoder receives the selected power supply line SV based on the 1-bit row address signal and the precharge signal.
Is a circuit for activating the. The power supply decoder according to the present embodiment has different input signals, and among the four power supply decoders, depending on the input row address state,
Either output (selected power supply line SV) is activated.

The selected power supply line SV which is the output signal line of the power supply decoder is connected to the source terminal of the PMOS transistor of the word line driver. Different selection power supply lines SV are connected to the word line drivers sharing the row decoder. In addition, the selected power supply line SV via the inverter
Is connected to the gate terminal of the NMOS transistor of the word line driver. Finally, one word line driver is selected by the combination of the output of the row decoder and the decoded selected power supply line.

Although not shown, each memory cell is, for example, a DRAM memory cell composed of one MOS transistor and one capacitor. The gate terminal of the MOS transistor of each memory cell is connected to the word line WL and is supplied with the output signal of the word line driver.

In FIG. 13, the first power supply decoder area SD
The output signal line (selected power supply line SV) of the power supply decoder arranged in No. 1 is connected to the source terminal of the PMOS transistor of the word line driver arranged in the first word line driver region WD1. Further, the output signal line (selected power supply line SV) of the power supply decoder arranged in the second power supply decoder area SD2 is connected to the source terminal of the PMOS transistor of the word line driver arranged in the second word line driver area WD2. Has been done.

The word lines WL0 and WL1 have the first
Output signal lines of the word line drivers arranged in the word line driver area WD1 of
An output signal line of the word line driver arranged in the second word line driver region WD2 is connected to 3. That is, the output signal line of the word line driver in the second word line driver region WD2 is the address signal line region R.
It is electrically connected to the gate wiring (word line WL) of the memory cell of the memory cell array CA across A.

Then, the second word line driver area WD
The output signal line of the word line driver in FIG.
Through the third metal wiring layer M3 as in the fourth embodiment.
Through the word line WL which is the gate wiring of the memory cell
Electrically connected to.

Thus, even when the word line driver is controlled by the decoded selected power supply line SV, the power supply decoder area is divided with the address signal line area RA interposed therebetween.
By arranging them, the word line driver can be arranged on one side of the memory cell array. Further, the number of row decoders can be reduced by connecting different address signal lines to the respective power supply decoders to which the output of the common row decoder is supplied. Therefore, since the row decoder area can be reduced, the row decoder can be arranged only on one side of the address signal line area RA.

Therefore, by dividing and arranging the word line driver in the two regions WD1 and WD2 with the address signal line region RA interposed therebetween, each element can be arranged with the minimum line width and interval, and the mounting area can be reduced. Can be reduced. Further, since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained. Further, as compared with the case of arranging the word line drivers on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased.

In the present embodiment, the output signal line of the row decoder arranged in the row decoder region RD also crosses the address signal line region RA, and the word line arranged in the second word line driver region WD2. It is connected to the driver. The output signal line of the row decoder may be electrically connected to the gate wiring of the element forming the word line driver via the first metal wiring layer M1, or via the third metal wiring layer M3. May be electrically connected. Alternatively, they may be electrically connected via a metal wiring layer that is an upper layer than the third metal wiring layer M3. (Sixth Embodiment) In the semiconductor memory device according to the sixth embodiment, in addition to the fifth embodiment, a memory cell array is arranged also on one side of the second word line driver region WD2. .

FIG. 14 is a circuit diagram of a semiconductor memory device according to the sixth embodiment. In the semiconductor memory device of the present embodiment, the row decoder region RD is arranged on one side of the address signal line region RA, and the first or second word line is sandwiched between the address signal line region RA and the row decoder region RD. Driver areas WD1 and WD2 are arranged. In addition, the first or second address signal line region RA is sandwiched therebetween.
Power supply decoder areas SD1 and SD2 are arranged.
Then, the first memory cell array CA1 is arranged on one side of the first word line driver area WD1 and the second memory cell array CA2 is arranged on one side of the second word line driver area WD2.

FIG. 14 shows eight word lines WL10-W.
L13, WL20 to WL23, four word line drivers, one row decoder, and four power supply decoders are shown. Two word line drivers are arranged in each word line driver area, two power source decoders are arranged in each power source decoder area, and four word line drivers are arranged in each memory cell array.
Word lines WL for each book are wired.

Note that the circuit configuration arranged in each region is the same as that of the fifth embodiment, and therefore its explanation is omitted.

In FIG. 14, the word lines WL10, WL11 and the second line connected to the first memory cell array CA1 are arranged.
Word line WL2 wired to the memory cell array CA2 of
0 and WL21 have the first word line driver area WD1.
The output signal line of the word line driver arranged at is connected. Then, the word lines WL12, WL13 wired in the first memory cell array CA1 and the word lines WL22, WL23 wired in the second memory cell array CA2.
Is connected to the output signal line of the word line driver arranged in the second word line driver region WD2.

That is, the first word line driver area W
The output signal line of the word line driver in D1 is electrically connected to the gate wiring (word lines WL10, WL11) of the memory cell in the first memory cell array CA1, and further, the second signal across the address signal line region RA. It is electrically connected to the gate wiring (word lines WL20, WL21) of the memory cell in the memory cell array CA2. The output signal line of the word line driver in the second word line driver region WD2 is electrically connected to the gate wiring (word lines WL22, WL23) of the memory cell in the second memory cell array CA2, and further,
The gate wiring (word line W of the memory cell in the first memory cell array CA1 is straddled across the address signal line area RA.
L12, WL13) are electrically connected.

Then, as in the second and fourth embodiments, the first and second word line driver regions WD are formed.
1, the output signal line of the word line driver in WD2 is
Word line WL wired to the first or second memory cell array CA1 or CA2 via the third metal wiring layer M3
Electrically connected to.

As described above, by dividing and arranging the word line driver into the two regions WD1 and WD2 with the address signal line region RA interposed therebetween, each element can be arranged with the minimum line width and interval, and mounting The area can be reduced. Further, since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained. Further, as compared with the case of arranging the word line drivers on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased.

In addition, the second word line driver area WD2
By arranging the memory cell array on one side as well, it is possible to configure a memory macro having a capacity twice as large as that of the fifth embodiment.

Although not shown in the drawings of the first to sixth embodiments, in order to operate stably as a memory macro, a sense amplifier for amplifying a potential and a data input for controlling input / output of data are input. Output buffer and control circuit,
There is a power supply circuit that generates an internal power supply.

By the way, in ISSCC99, a semiconductor memory device as shown in FIG. 21 is reported. The semiconductor memory device of FIG. 21 is provided with two modules including a memory cell array and a word line driver, and these modules are arranged back to back with an address signal line interposed therebetween. On the other hand, in the semiconductor memory device of the sixth embodiment, one word line driver is shared by two memory cell arrays, and the output signal line of the word line driver is wired across the address signal area. Although the sixth embodiment requires a larger number of wiring layers, the number of elements connected to the memory cell can be significantly reduced and the mounting area can be reduced. The configuration and effect of the semiconductor memory device in FIG. 21 and the sixth embodiment are different.

The semiconductor memory device of the present invention is particularly suitable for a memory-embedded logic LSI capable of multilayer wiring. The memory-embedded logic LSI includes, for example, 16 1 Mbit DRAM memory cell arrays mounted thereon, and includes a memory macro that operates as a 16 Mbit DRAM macro as a whole and a logic unit. In the logic section of the memory-embedded logic LSI, the wiring layers are being multi-layered in order to increase the efficiency of use of the elements. For example, the third metal wiring layer is formed to have almost the same film thickness, and the upper metal wiring layer is formed to be thicker than the lower metal wiring layer in consideration of use as a power supply wiring.

Therefore, in the semiconductor memory device according to the first to sixth embodiments, even if the word line driver is divided and arranged on one side with the address signal line region RA interposed therebetween, the semiconductor memory device according to the third embodiment can be used.
Can be electrically connected to the gate wiring layer of the memory cell via the metal wiring layer M3.

By thus configuring the memory section, the mounting area of the entire LSI can be reduced. Further, as compared with the case where the word line drivers are arranged on both sides of the memory cell array, it is not necessary to lay out the wiring such as the address signal line to the row decoder corresponding to the word line driver. Power consumption in the operation of the logic LSI can be reduced. Further, since it is not necessary to consider the merge of the operation timing due to the wiring length, the operation speed of the entire memory-embedded logic LSI can be increased.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0106]

According to the present invention, by dividing and arranging the word line driver into two regions with the address signal line region interposed therebetween, it is possible to arrange each element with the minimum line width and interval. The area can be reduced. Also,
Since the word line driver is arranged on one side of the memory cell array, the floating of the potential of the non-selected word line due to the influence of the coupling capacitance between the word lines can be suppressed and the data retention characteristic can be maintained.

Further, as compared with the case where the word line drivers are arranged on both sides of the memory cell array, it is not necessary to route the wiring such as the address signal line to the row decoder corresponding to the word line driver, so that the load due to the wiring length can be reduced. The power consumption during operation can be reduced. Further, since it is not necessary to consider the merge of the operation timing depending on the wiring length, the operation speed can be increased.

By arranging the memory cell array also on one side of the second word line driver area, a memory macro having a double capacity can be constructed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment.

FIG. 2 is a detailed layout diagram of a word line driver region of the semiconductor memory device according to the first embodiment.

FIG. 3 is a detailed layout diagram of a word line driver area of the semiconductor memory device according to the first embodiment.

FIG. 4 is a detailed layout diagram of a word line driver area of the semiconductor memory device according to the first embodiment.

FIG. 5 is a detailed layout diagram of a word line driver area of the semiconductor memory device according to the first embodiment.

FIG. 6 is a cross-sectional view of the semiconductor memory device according to the first embodiment.

FIG. 7 is a cross-sectional view of the semiconductor memory device according to the first embodiment.

FIG. 8 is a circuit diagram of a semiconductor memory device according to a second embodiment.

FIG. 9 is a detailed layout diagram of a word line driver area of the semiconductor memory device according to the second embodiment.

FIG. 10 is a circuit diagram of a semiconductor memory device according to a third embodiment.

FIG. 11 is a detailed layout diagram of a word line driver area of the semiconductor memory device according to the third embodiment.

FIG. 12 is a circuit diagram of a semiconductor memory device according to a fourth embodiment.

FIG. 13 is a circuit diagram of a semiconductor memory device according to a fifth embodiment.

FIG. 14 is a circuit diagram of a semiconductor memory device according to a sixth embodiment.

FIG. 15 is a detailed layout diagram of a word line driver of a conventional semiconductor memory device.

FIG. 16 is a detailed layout diagram of a word line driver of the semiconductor memory device in the first conventional technique.

FIG. 17 is a circuit diagram of a semiconductor memory device according to a second conventional technique.

FIG. 18 is a detailed layout diagram of a word line driver of a semiconductor memory device according to a second conventional technique.

FIG. 19A is a circuit model in which word line drivers are arranged on both sides of a memory cell array. (B) Results of analysis by the circuit analysis simulator in the circuit models arranged on both sides.

FIG. 20A is a circuit model in which a word line driver is arranged on one side of a memory cell array. (B) Results of analysis by a circuit analysis simulator in a circuit model with one-sided layout.

FIG. 21 is a circuit diagram of a semiconductor memory device in ISSCC99.

[Explanation of symbols]

RA ... Address signal line areas WD, WD1, WD2 ... Word line driver areas RD, RD1, RD2 ... Row decoder areas CA, CA1, CA2 ... Memory cell arrays SD, SD1, SD2 ... Power supply decoder areas WL0-WL3, WL10-WL13, WL20 ~ WL
23 ... Word line SV ... Selected power supply line M1 ... First metal wiring layer M2 ... Second metal wiring layer M3 ... Third metal wiring layer V1 ... First vias V2a, V2b, V21a, V21b, V22a, V2
2b ... second via

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 AD00 GA02 GA03 GA09 KA01                       LA05 LA11 LA16 LA21 MA06                       MA16                 5M024 AA50 AA62 BB07 BB08 BB30                       BB40 CC22 CC50 DD33 LL02                       LL11

Claims (17)

[Claims] 1. An address signal line region in which an address signal line is wired, a first row decoder region in which at least one row decoder is arranged on one side of the address signal line region, and the address signal line. A second row decoder region in which at least one row decoder is arranged on the other side of the region, and at least one word on one side of the address signal line region sandwiching the first row decoder region. A first word line driver area in which a line driver is arranged, and a second word in which at least one word line driver is arranged on the other side of the address signal line area sandwiching the second row decoder area. A line driver region and one side of the address signal line region sandwiching the first low decoder region and the first word line driver region are provided on a small side, and And a first memory cell array in which two word lines are wired, and the output signal line of the word line driver arranged in the second word line driver region extends across the address signal line region. A semiconductor memory device characterized in that wiring is provided on a first memory cell array. 2. A second line in which at least two word lines are arranged on the other side of the address signal line region sandwiching the second row decoder region and the second word line driver region. An output signal line of a word line driver provided in the first word line driver region is provided on the second memory cell array across the address signal line region. The semiconductor memory device according to claim 1. 3. An address signal line region in which an address signal line is wired, a first row decoder region in which at least one row decoder is arranged on one side of the address signal line region, and the address signal line. A second row decoder region in which at least one row decoder is arranged on the other side of the region, and at least one word on one side of the address signal line region sandwiching the first row decoder region. A first word line driver area in which a line driver is arranged, and a second word in which at least one word line driver is arranged on the other side of the address signal line area sandwiching the second row decoder area. A line driver region and one side of the address signal line region sandwiching the first low decoder region and the first word line driver region are provided on a small side, and And a first memory cell array in which two word lines are wired, and is electrically connected to the drain region of each MOS transistor forming the word line driver arranged in the second word line driver region. The first metal wiring layer is formed on the second word line driver region through a first connection hole formed in an interlayer insulating film formed on the first metal wiring layer, and It is electrically connected to the second metal wiring layer extending over the first memory cell array across the address signal line region, and is electrically connected to the second metal wiring layer over the first memory cell array. Electrically connected to a word line wired in the first memory cell array through a second connection hole formed in the interlayer insulating film that is electrically connected Storage device. 4. A second line in which at least two word lines are arranged on the other side of the address signal line region sandwiching the second row decoder region and the second word line driver region. The first metal wiring layer, which comprises a memory cell array and is electrically connected to the drain regions of the respective MOS transistors forming the word line driver arranged in the first word line driver region, comprises: The second memory cell array is formed on the word line driver region and across the address signal line region through a third connection hole formed in an interlayer insulating film formed on the first metal wiring layer. In the interlayer insulating film electrically connected to the second metal wiring layer extending above, and electrically connected to the second metal wiring layer on the second memory cell array. Formation 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is electrically connected to a word line wired in the second memory cell array through the formed fourth connection hole. 5. A row decoder arranged in the first and second row decoder regions is a NAND which receives a precharge signal and an address signal as inputs.
5. The semiconductor memory device according to claim 1, which is a circuit. 6. A word line driver arranged in the first and second word line driver areas is an inverter circuit which receives an output of a row decoder arranged in the first or second row decoder area. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is present. 7. A first power supply decoder in which at least two power supply decoders for controlling word line drivers arranged in the first word line driver area are arranged on one side of the address signal line area. A region, and a second power supply decoder region in which at least two power supply decoders controlling the word line drivers arranged in the second word line driver region are arranged on the other side of the address signal line region. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 8. The output of the row decoder arranged in the first row decoder region is supplied to at least two word line drivers arranged in the first word line driver region, and the second row decoder is provided. 8. The semiconductor memory device according to claim 7, wherein the output of the low decoder arranged in the area is supplied to at least two word line drivers arranged in the second word line driver area. 9. A word line driver arranged in the second word line driver area is supplied with an output of a power supply decoder arranged in the second power supply decoder area at a source terminal thereof and the gate terminal of the second power supply decoder.
A PMOS transistor to which the output of the row decoder arranged in the row decoder region is supplied, a first NMOS transistor to which the ground potential is supplied to the source terminal and the output of the row decoder is supplied to the gate terminal, and a source terminal A second NMO in which the ground potential is supplied to the gate and the inverted signal of the output of the power supply decoder is supplied to the gate terminal.
9. An S-transistor, wherein the drain terminals of the PMOS transistor and the first and second NMOS transistors are connected to a word line of the first memory cell array. Semiconductor memory device. 10. The semiconductor memory device according to claim 9, wherein drain terminals of the PMOS transistor and the first and second NMOS transistors are connected to a word line of the second memory cell array. . 11. An address signal line region in which an address signal line is wired, a row decoder region in which at least one row decoder is arranged on one side of the address signal line region, and the row decoder region is sandwiched between the row decoder region and the row decoder region. A first word line driver area in which at least two word line drivers are arranged on one side of the address signal line area, and at least two word line drivers in the other side of the address signal line area. A second word line driver area, and a first power supply decoder having a power supply decoder for controlling the word line driver arranged in the first word line driver area arranged on one side of the address signal line area. A region and a word line driver arranged in the second word line driver region on the other side of the address signal line region. At least four word lines are wired on one side of the second power supply decoder region in which the power supply decoder is arranged and the address signal line region sandwiching the row decoder region and the first word line driver region. A first memory cell array, and an output signal line of the word line driver arranged in the second word line driver region is wired to the first memory cell array across the address signal line region. A semiconductor memory device characterized by the above. 12. A second memory cell array in which at least four word lines are wired on the other side of the address signal line region that sandwiches the second word line driver region, The semiconductor device according to claim 11, wherein an output signal line of the word line driver arranged in the first word line driver area is wired to the second memory cell array across the address signal line area. Storage device. 13. An address signal line region in which an address signal line is wired, a row decoder region in which at least one row decoder is arranged on one side of the address signal line region, and the row decoder region is sandwiched between the row and decoder regions. A first word line driver area in which at least two word line drivers are arranged on one side of the address signal line area, and at least two word line drivers in the other side of the address signal line area. A second word line driver area, and a first power supply decoder having a power supply decoder for controlling the word line driver arranged in the first word line driver area arranged on one side of the address signal line area. A region and a word line driver arranged in the second word line driver region on the other side of the address signal line region. At least four word lines are wired on one side of the second power supply decoder region in which the power supply decoder is arranged and the address signal line region sandwiching the row decoder region and the first word line driver region. A first memory cell array, the first metal wiring layer electrically connected to the drain region of each MOS transistor forming the word line driver arranged in the second word line driver region, On the second word line driver region, the first signal hole is formed across the address signal line region via the first connection hole formed in the interlayer insulating film formed on the first metal wiring layer. Layer electrically connected to a second metal wiring layer extending over the memory cell array, and electrically connected to the second metal wiring layer over the first memory cell array. Through the second contact hole formed in the insulating film, a semiconductor memory device, characterized in that it is wired word line electrically connected to said first memory cell array. 14. A second memory cell array in which at least four word lines are wired on the other side of the address signal line region sandwiching the second word line driver region, The first metal wiring layer electrically connected to the drain region of each MOS transistor forming the word line driver arranged in one word line driver region is formed on the first word line driver region, The third memory cell array is formed on the first metal wiring layer, and the third connection hole is formed in the interlayer insulating film. A fourth connection hole electrically connected to the second metal wiring layer and formed in the interlayer insulating film on the second memory cell array and electrically connected to the second metal wiring layer. Through 14. The semiconductor memory device according to claim 13, wherein the semiconductor memory device is electrically connected to a word line wired in the second memory cell array. 15. The output of the row decoder arranged in the row decoder area is supplied to at least two word line drivers arranged in the first and second word line driver areas, respectively. 15. The semiconductor memory device according to claim 11, wherein: 16. The word line driver arranged in the second word line driver area is supplied with an output of a power supply decoder arranged in the second power supply decoder area at a source terminal and the row decoder at a gate terminal. A PMOS transistor to which the output of the row decoder arranged in the region is supplied, a first NMOS transistor to which the source terminal is supplied with the ground potential and the gate terminal is supplied with the output of the row decoder, and a source terminal which is connected to the ground potential And a second NMO whose gate terminal is supplied with an inverted signal of the output of the power supply decoder.
16. An S transistor, and the drain terminals of the PMOS transistor and the first and second NMOS transistors are connected to a word line of the first memory cell array. Semiconductor memory device. 17. The semiconductor memory device according to claim 16, wherein drain terminals of the PMOS transistor and the first and second NMOS transistors are connected to a word line of the second memory cell array. .