JP2003006143A - System, device and method of sharing bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device which reduces the number of terminals of a device, having a PCI I/F and a ROM I/F and dispenses with an external circuit or the like. SOLUTION: A PCI device 22 and a ROM 21 are connected to a shared bus 2, a multiplexer 33 for selecting a connection path between either the ROM I/F 12 or the PCI I/F 13 and the shared bus 2, according to a mode set value is provided; and there is provided a mode controller 32 that makes an arbiter 14 in a ROM mode, use the shared bus for ROM access, waiting for the ROM access to be finished, in the case of stopping PCI clock supply and shifting to a PCI mode and start clock supply, and makes the arbiter 14, in the PCI mode, avoid contention between ROM access and PCI access on the shared bus and conduct control that stops clock supply, in the case of shifting to the ROM mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bus control technology, and more particularly to a bus sharing system, apparatus and method.

[0002]

2. Description of the Related Art A clock synchronous PCI (personal co
mponent interconnect) bus and asynchronous ROM
The buses to which (read-only memory) is connected are
Buses with different protocols. A conventional system using both types of devices is described below.

FIG. 7 shows a ROM interface (I / F).
12 is a diagram showing a configuration of a system using a conventional host device A24 having separate terminals for 12 and a PCI interface (I / F) 13 respectively.

The host bus 1 has ROM I / Fs 12, P
The CI I / F 13 and the CPU 11 are connected.

The ROM I / F 12 is a circuit that converts a read command or a write command sent from the CPU 11 through the host bus 1 into a ROM protocol.

The PCI I / F 13 is connected from the host bus 1 to P
This is a bridge circuit that performs protocol conversion to the CI bus (PCI dedicated bus) 5 and protocol conversion from the PCI bus 5 to the host bus 1.

The ROM 21 is a general-purpose ROM device such as a mask ROM or a flash ROM, and an address signal, a data signal, and a control signal (other than CS # 41) are connected to the ROM dedicated bus 4.

Control line CS # 41 (where "#" is Low
When the level is active, it means ROM
21 is a chip select signal for the ROM I / F
12 is used to control the active / inactive state of the ROM 21.

The PCI device A22 connected to the PCI dedicated bus 5 is a PCI device complying with the PCI local bus specifications, and is supplied with a PCI clock from the clock distributor 15.

A bus request signal (REQ_A # 42) to the PCI arbiter 14 and a permission signal GNT_A # 43 from the PCI arbiter 14 are connected to the PCI device A22.
The PCI device A22 can start the bus master operation only when the bus use permission is given down (when the permission signal GNT_A # 43 is asserted).

PCI address of PCI device A22 /
Data signal, bus request signal (REQ_A # 42), enable signal GNT_
Control signals other than A # 43 are connected to the PCI dedicated bus 5.

The PCI arbiter 14 is a circuit that arbitrates the PCI bus.

The ROM 21 is connected to the ROM dedicated bus 4 and is accessible from the ROM I / F 12.

The PCI device A22 is connected to the PCI dedicated bus 5 and is accessible from the PCI I / F 13.

In the configuration shown in FIG. 7, the conventional host device 24 includes a PCI I / F 13 and a ROM I / F 1.
Each has two separate terminals for the two.

For this reason, there are problems that the number of terminals of the host device 24 is large, and that the number of bus wires on the board is large.

FIG. 8 shows an example of the configuration of a system using a conventional host device B25 having only a PCI I / F function and a PCI device having a ROM I / F function (PCI-ROM I / F) 23. FIG. CPU11,
PCI I / F 13, clock distributor 15, ROM 21,
The PCI device A22 is the same as that shown in FIG.

The PCI-ROM I / F 23 is an external circuit for converting read / write commands in the PCI protocol into the ROM protocol, and is connected to the PCI dedicated bus 5.

The access from the CPU 11 to the ROM 21 is once converted into the PCI bus protocol and then
The protocol of the ROM 21 is converted by the PCI-ROM I / F 23.

In the configuration shown in FIG. 8, the host device B2
5 does not need to have a terminal for ROM I / F,
The number of terminals is reduced as compared with the configuration shown in FIG. However, since the ROM 21 does not have a function of directly responding to the PCI protocol, the ROM 21 and PCI
It is necessary to convert the protocol between
PCI device with F function (PCI-ROM I / F)
23 is required to be newly developed or procured, which increases the number of parts and increases the cost of the entire system.

Incidentally, for example, in Japanese Unexamined Patent Publication No. 7-160626, a PCI address / data bus and an RO are described as a system for connecting a short word length memory to a wide bus which operates in an address / data multiplexing mode.
A configuration in which an 8-bit data bus for M access and a 24-bit address bus are multiplexed is disclosed.

[0022]

Therefore, the problems to be solved by the present invention are PCI interface and RO.
An object of the present invention is to provide an apparatus, a system and a method which reduce the number of terminals of an apparatus having a plurality of interfaces such as M interface having different protocols and which do not require an external circuit for protocol conversion.

[0023]

According to one aspect of the present invention which provides means for solving the above-mentioned problems, a synchronous device connected to a clock synchronous bus and an asynchronous device are provided. Commonly connected to one shared bus, the synchronous device and the asynchronous device share an address line and a data line, and at least a part of a plurality of control lines in the shared bus. , A synchronous device interface for performing an interface between a higher-level device and the synchronous device and the shared bus are electrically connected depending on whether the access mode is the synchronous device access mode or the asynchronous device access mode. Or an asynchronous device interface that interfaces with the higher-level device and the asynchronous device. In the case of the asynchronous device access mode, a switching unit electrically connecting the shared bus to the shared bus and the asynchronous device access mode are set so that the asynchronous device interface and the asynchronous device can use the shared bus. In the case of the synchronous device access mode, the clock supply to the synchronous device is stopped, the clock is supplied to the synchronous device, and the use of the shared bus for accessing the asynchronous device is prohibited. , Means for controlling so as to avoid access conflict between the asynchronous device and the synchronous device on the shared bus.

The present invention is a synchronous type device driven by a clock, which inputs an address signal and inputs or outputs a data signal and a control signal, and an asynchronous type device which inputs an address signal and inputs or outputs a data signal and a control signal. The device is
They are commonly connected to one bus (shared bus), and the synchronous device and the asynchronous device are connected to the shared bus by address lines, data lines, and some control lines of a plurality of control lines. A synchronous device interface that is shared and that interfaces between the host device and the synchronous device; an asynchronous device interface that interfaces between the host device and the synchronous device;
Connected to the synchronous device interface, the asynchronous device interface, and the shared bus,
Depending on whether the access mode is the synchronous device access mode or the asynchronous device access mode, one of the synchronous device interface or the asynchronous device interface and the shared bus are electrically connected. Equipped with a multiplexer to
In the asynchronous device access mode, an arbiter circuit of the bus is set to set the asynchronous device interface and the asynchronous device so that the shared bus can be used, and a clock for the synchronous device is set. When supply is stopped and the asynchronous device access mode is changed to the synchronous device access mode, supply of a clock to the synchronous device is started, and in the synchronous device access mode, the arbiter circuit is operated. , Disallowing the use of the shared bus for accessing the asynchronous device,
When conflicting between the asynchronous device access and the synchronous device access on the bus is avoided, and when the synchronous device access mode is changed to the asynchronous device access mode, the supply of the clock to the synchronous device is stopped. It has a mode control circuit for performing control.

In another aspect, the invention is a PC
An I (Peripheral Component Interconnect) device, a ROM (Read Only Memory) device, and the P
A shared bus to which the CI device and the ROM device are commonly connected, and in the shared bus, an address line, a data line, and a plurality of control lines are provided between the PCI bus and the ROM access bus. Part of the control lines are shared and are connected to the ROM interface and the PCI interface, and the mode setting value is the ROM mode in which the ROM device can be accessed, or the PCI device in which the PCI device can be accessed. A multiplexer for selecting a connection path between the ROM interface and the shared bus or a connection path between the PCI interface and the shared bus, an arbiter circuit for the shared bus, and the PCI device, depending on the mode. And a clock distributor for distributing clocks to the ROM mode. The arbiter circuit causes the shared bus to be used for accessing the ROM device, and the clock distributor stops the supply of the PCI clock to shift from the ROM mode to the PCI mode. Waiting until the access of the ROM device is completed, the clock distributor is made to start the supply of the PCI clock, and in the PCI mode, the arbiter circuit is made to prohibit the access of the ROM device by the shared bus, A mode control circuit for avoiding the conflict between the access and the PCI access and controlling the clock distributor to stop the supply of the PCI clock at the time of shifting from the PCI mode to the ROM mode is provided. As will be apparent from the following description, the above problems can be solved in the same manner by the inventions of the claims of the present application.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described. The present invention is a PCI interface (I / F) and RO
A device having both an M interface (I / F) has the following features in terms of configuration.

The ROM interface is regarded as one PCI bus master, and the PCI arbiter is caused to perform bus arbitration.

By controlling ROM chip select and PCI clock, buses of different protocols PCI and ROM are shared without interfering with each other.

Not only address and data lines,
The signal line for control is also shared.

An embodiment of the present invention will be described. According to one embodiment of the present invention, a synchronous device (22 in FIG. 1) connected to a clock synchronous bus such as a PCI bus is connected to a bus of a protocol different from the clock synchronous bus. The asynchronous device (21 in FIG. 1) is commonly connected to one shared bus (2 in FIG. 1), and the synchronous device (22 in FIG. 1) and the asynchronous device (21 in FIG. 1) are connected to each other. In the shared bus (2 in FIG. 1), the address line and the data line and at least a part of the plurality of control lines are shared, and the access mode is the synchronous device access mode, or the asynchronous device Depending on whether it is in the access mode, the host device (1 in FIG.
1) Synchronous device interface (13 in FIG. 1) for interfacing with the synchronous device (22 in FIG. 1)
Or the shared bus (2 in FIG. 1) is electrically connected, or the host device (11 in FIG. 1) and the asynchronous device (21 in FIG. 1)
A switching means (33 in FIG. 1) for electrically connecting the asynchronous device interface (12 in FIG. 1) for interfacing with the shared bus (2 in FIG. 1); and an asynchronous device access mode In this case, the asynchronous device interface (12 in FIG. 1) and the asynchronous device (21 in FIG. 1) are set to use the shared bus (2 in FIG. 1), and the asynchronous device interface (22 in FIG. 1) is set. In the synchronous device access mode, the clock is supplied to the synchronous device (22 in FIG. 1) and the shared bus for accessing the asynchronous device (21 in FIG. 1) is supplied. The use of 1) 2) is prohibited,
Means (32, 14, 15 in FIG. 1) for controlling so as to avoid contention between the asynchronous device access and the synchronous device access on the shared bus (2 in FIG. 1).

The present invention is based on the PCI interface and ROM.
In one embodiment applied to an interface, FIG.
2, the PCI device (22) connected to the clock synchronous PCI bus and the asynchronous device R connected to the bus of a protocol different from the PCI bus.
The OM device (21) is connected to the shared bus (2). In the shared bus (2), the PCI bus and the RO are connected.
Address and data lines to and from the M access bus,
Some control lines of the plurality of control lines are shared.

The shared bus host device (20) is provided with a mode controller (32) and a multiplexer (33) forming a bus switching circuit as a configuration for realizing the sharing of the bus between the PCI device and the ROM device. .

The multiplexer (33) is connected to the ROM interface (12) and the PCI interface (13), and the mode setting value is the ROM mode in which the ROM device can be accessed or the PCI device in which the PCI device can be accessed. A path for electrically connecting the ROM interface (12) and the shared bus (2) or a path for electrically connecting the PCI interface (13) and the shared bus (2) is selected depending on the mode. .

In the ROM mode, the shared bus arbiter circuit (14) is used to use the shared bus (2) for accessing the ROM device (21), and the clock distributor (15) is used for the PCI clock. Supply of
When changing from ROM mode to PCI mode, RO
Waiting for the end of the access of M, the clock distributor (15) is started to start the supply of the PCI clock. In the PCI mode, the arbiter circuit (14) is used to access the ROM device by the shared bus (2). As a non-permission, a mode controller (32) is provided for avoiding the conflict between the ROM access and the PCI access, and controlling the clock distributor to stop the supply of the PCI clock when shifting from the PCI mode to the ROM mode. There is.

The mode setting register (31) includes a ROM
Either the mode or the PCI mode is set as a value, and the mode controller (32) controls the selection of the multiplexer (33) according to the set value of the mode setting register (31). In the ROM mode, the multiplexer (33) selects a route from the ROM I / F (12) to the shared bus (2) and the CPU (11) to the ROM.
It becomes possible to access (21).

In the PCI mode, the multiplexer (3
3) selects a path from the PCI I / F (13) to the shared bus (2), accesses the CPU (11) to the PCI device A (22), and connects the PCI device A (22) to the host bus (1). ) You will be able to access the above devices.

During the ROM mode, the mode controller (32) continues to hold the bus use right through the PCI arbiter (14), and the ROM I / F (12) occupies the shared bus (2) for ROM access. I am able to do it.

During the PCI mode, the mode controller (32) releases the right to use the bus to other PCI devices, and the PCI I / F (13) and PCI device A (2).
As a master, 2) enables PCI access.

The shared bus (2) can be used for both PCI access and ROM access simply by setting a value in the mode setting register (31).

As the ROM device and PCI device to be connected, conventional products are used as they are, and it is not necessary to prepare a dedicated ROM / PCI device for bus sharing.

When designing the host device, the PC
The I / F (13) can use the existing host bus-PCI bus bridge circuit, and therefore, no modification is required for bus sharing.

The ROM I / F (12) can be reused with the existing configuration with only a slight modification such as adding an output signal that shows the access state.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the embodiment of the present invention described above in more detail, an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. ROM I / F (interface) 1
2, a shared bus type host device 20 having a PCI I / F 13, a CPU 11 and a ROM on the system board
21 and a PCI device A22. A ROM 21 and a PCI device A22 are connected to the shared bus 2, and PCI access and ROM access from the shared bus type host device 20 are possible through the shared bus 2.

The host bus 1 has ROM I / Fs 12, P
The CI I / F 13 and the CPU 11 are connected.

The ROM I / F 12 reads the read / write command sent from the CPU 11 through the host bus 1 into the R / F.
This is a circuit for converting to the OM protocol.

The PCI I / F 13 is from the host bus 1 to P.
It is a bridge circuit that performs protocol conversion to the CI bus and protocol conversion from the PCI bus to the host bus 1.

The ROM 21 is a general-purpose ROM device such as a mask ROM or a flash ROM, and has address signals, data signals, control signals (chip select signal CS # 41).
Other than) are connected to the shared bus 2.

The control line CS # 41 is a chip select signal for the ROM 21, and the ROM I / F 12 makes the ROM 2
Used to control active / inactive of 1.

The PCI device A22 is a PCI device complying with the PCI local bus specification, and receives the PCI clock 48 from the clock distributor 15.

A bus request signal REQ_A # 42 for the PCI arbiter 14 and a permission signal GNT_A # 43 from the PCI arbiter 14 are connected to the PCI device A22.
The CI device A22 can start the bus master operation only when the bus use permission is given.

PCI address of PCI device A22 /
Data signal, bus request signal REQ_A # 42, permission signal GNT_A #
Control signals other than 43 are connected to the shared bus 2.

The multiplexer 33 includes the shared bus 2 and R
Select a route connecting either OM I / F 12 or PCI I / F 13.

The mode setting register 31 is a register in which a value indicating either the PCI mode or the ROM mode is set by the access from the CPU 11 and holds the set value.

The mode controller 32 switches between the ROM mode and the PCI mode according to the set value of the mode setting register 31, supplies a route selection signal to the multiplexer 33, and controls the route selection of the multiplexer 33. The circuit 30 including the mode setting register 31, the mode controller 32, and the multiplexer 33 is newly introduced in the present invention.

The signal ROM_BUSY 40 passed from the ROM I / F 12 to the mode controller 32 is a signal indicating the ROM access state.

The PCI arbiter 14 is an arbitration circuit for the PCI bus, and includes a mode controller 32 and a PCI I / F1.
3. Accept the PCI bus use request from the PCI device A22 and give the bus use permission to one of them.

REQ_PCIIF # 44 and GNT_PCIIF # 45 are a bus request signal and a permission signal from the PCI I / F 13, respectively. REQ_CONT # 46 and GNT_CONT # 47 are a bus request signal and a permission signal from the mode controller 32, respectively.

The clock distributor 15 is for each block, PC
It is a circuit for distributing a PCI clock to the I device, and stops / starts the PCI clock 48 by a clock control signal 49 from the mode controller 32.

The operation of the embodiment of the present invention will be described with reference to the state transition diagram of the control state of the mode controller shown in FIG.

In the initial state, the mode controller 32
In the "ROM mode A1", the ROM I / F 12 can access the ROM 21 through the shared bus 2.

In this state, the mode controller 32
Holds the right to use the shared bus 2 for ROM access.

The PCI arbiter 14 is in a state where the bus permission is given to the mode controller 32, and GNT_CONT #
Continue to assert 47.

GNT_PCIIF # 45 and GNT_A # 43 are deasserted to prevent the PCI I / F 13 and PCI device A22 from acquiring the bus use right and starting the master operation.

The clock distributor 15 uses the PCI clock 4
8 is stopped to prevent the PCI device A22 from malfunctioning in response to the ROM access signal on the shared bus.

When the PCI mode is set in the mode setting register 31, the mode controller 32 causes the "ROM
Transition to the access end waiting state A2 ”.

In the "ROM access end wait state A2", if the ROM I / F 12 is in the middle of access, it waits until the access ends, and immediately after the access ends, it immediately transits to the "PCI mode transition state A3".

In the "PCI mode transition state A3", the mode controller 32 sends the clock P to the clock distributor 15.
The start signal of the CI clock 48 is sent, and the multiplexer 33 is controlled to select the path on the PCI I / F 13 side.

When the PCI clock 48 is started, "P
CI mode state A4 ".

When the "PCI mode state A4" is entered, the mode controller 32 asserts REQ--
CONT # 46 is deasserted to release the shared bus 2 reserved for ROM access.

Then, the PCI I / F 13 and the PCI device A22 can start the master operation, and the shared bus 2 is used as a PCI bus. In addition,
In this state, the ROM I / F 12 controls the control signal CS # 41.
Is deasserted, and R is set for PCI access on the shared bus 2.
It prevents the OM 21 from responding and malfunctioning.

When the ROM mode is set in the mode setting register 31, the state transits to "PCI bus request state A5".

In the "PCI bus request state A5", the mode controller 32 asserts REQ_CONT # 46 to set P
Request the PCI bus usage right from the CI arbiter 14.

In response to this request, the PCI arbiter 14 makes the GN
When T_CONT # 47 is deasserted and the PCI bus becomes idle, the mode controller 32 determines that the shared bus can be secured for ROM access, and the "ROM
Transition to the mode transition state A6 ”.

In the "ROM mode transition state A6", the mode controller 32 outputs P to the clock distributor 15.
Sends CI clock stop signal, and also multiplexer 3
3 selects the path on the ROM I / F 12 side. When the stop of the PCI clock is completed, "ROM mode status A1"
Return to.

As described above, according to the state of the mode controller 32 from A1 to A6, the shared bus 2 is PCI
Used as a bus or ROM bus.

5 and 6 are diagrams showing an example of the timing operation of the embodiment of the present invention. In FIG. 5, the states of the mode controller 32 are changed from “ROM mode A1” to “PC.
I mode A4 ”is shown. Figure 5
Then, while the ROM I / F 12 is reading the data rDAT0 from the address rADR0 of the ROM 21, the mode setting value is set from the ROM mode to the PCI mode.
The fact that the ROM is being accessed is indicated by the assertion of the ROM_BUSY signal, and is the period from time T01 to time T03.

At time T02, the state of the mode controller 32 transitions from "ROM mode A1" to "ROM access end wait A2" triggered by the change of the mode set value to the PCI mode.

After that, at time T03, when the read access of the ROM I / F 12 is finished and the ROM_BUSY 40 is deasserted, the transition to "PCI mode shift A3" is made.

Furthermore, at the timing of time T04, the PCI
When the supply of the clock 48 is started, "PCI mode A
4 ”, and the mode controller 32 displays REQ_CONT #
Deassert 46 to release the PCI bus.

In this example, at time T06, GNT_PCIIF # 45
Is asserted, and after T07, the PCIII / F13 starts the master operation.

The timing chart of FIG. 6 shows how the state of the mode controller 32 transits from "PCI mode A4" to "ROM mode A1".

In FIG. 6, while the PCI I / F 13 is reading the data rDAT0 from the address pADR0 of the PCI device A22, the mode setting value changes from PCI mode to ROM.
The mode is set. When the mode setting value is changed, the fact that the PCI access is being performed is indicated by FRAME # (cycle frame) or IDRY # (initiator ready) indicating assertion (at the low level).

In FIG. 6, after REQ_PCIIF # is asserted at time T12 and FRAME # is asserted at time T14,
At time T17, FRAME # and IRDY are both deasserted, and at time T18, until the PCI bus becomes idle,
It is the CI access period, which is between T12 and T18.

The state of the mode controller 32 is changed from "PCI mode A4" to "PCI bus request A5" triggered by the change of the mode set value to the ROM mode.
To the bus request REQ_CONT # at the timing of time T15.
Assert.

Thereafter, at the timing of time T18, the PCI
When the assertion of GNT_CONT # from the arbiter 14 and the idle state of the PCI bus are confirmed, "PCI mode transition A
6 ”.

Finally, at time T20, after waiting for the PCI clock to stop, the operation transits to "ROM mode A1".

FIG. 4 shows an RO suitable for sharing a bus.
It is a figure which shows the example of a combination of the terminal function of M and PCI.
ROM 21 data bus D [7: 0], address bus A [23: 0]
Is assigned a PCI tri-state bus AD [31: 0]. The PCI bus has 32 lines AD [31: 0] that are multiplexed by address and data transfer.

The WE # (write enable), OE # (output enable), and RDY # (ready) of the ROM control signal are respectively PCI sustain sustain lines.
Tobas, IRDY # (initiator ready), TRDY #
Assign (Target Ready) and STOP # (Stop). The ROM device 21 having WE # (write enable) as a control signal is a flash EEPROM.
Etc., and rewritable memory.

Since the pull-up resistor is connected to the power supply side to the sustain tri-state bus, it is deasserted even if all devices are in the non-drive state, and the ROM
The control line to 21 is prevented from being in an intermediate potential state for a long time.

In this way, the ROM I / F 12 and PCI
ROM on the host device that has both I / F13
By switching the multiplexer 33 according to the mode / PCI mode, the ROM access terminal and PCI
Since the terminals for access can be shared and used, the number of external terminals of the host device can be reduced.

Address bus 24bits, data bus 8bits,
And ROM bus with WE #, OE #, RDY # control lines,
When the PCI bus is shared, 35 terminals can be reduced.

Further, in the present embodiment, the mode controller 32 on the host device 20 and the PCI arbiter 14 cooperate to avoid contention on the bus, so that the external ROM, P
No change of CI device or new external circuit is required.

As an embodiment of the present invention, the basic structure is as described above, but even if the structure is partially replaced,
The same effect can be achieved. FIG. 3 is a diagram showing the configuration of the second exemplary embodiment of the present invention.

In the embodiment shown in FIG. 1, the writing of the PCI / ROM mode to the mode setting register 31 is performed by the CPU 11, but writing from other than the CPU 11 may be possible. For example, it is possible to set the mode by writing from a block having a bus master function on the host bus, or to set the mode directly by a signal without passing through the bus.

In this embodiment, the mode setting register 31
The ROM I / F 12 performs mode writing to the memory. The mode controller 32 is normally in the PCI mode state and switches to the ROM mode only when there is a request from the ROM I / F 12. With this configuration, unlike the above-described embodiment, it is not necessary to set the mode by software using the CPU 11, and it becomes possible to automatically switch the mode by using the ROM access as a trigger.

In the example shown in FIG. 3, the host bus 1 is not provided. In the present invention, the applicable device is not limited to the host device 20 shown in FIG. 1, but as shown in FIG. 3, ROM I / F12 and PCI I / F1
It could also be a normal device 26 with 3. In the configuration shown in FIG. 3, the clock distributor (15 in FIG. 1).
Are not shown.

In FIG. 3, the CPU and host bus shown in FIG. 1 are not provided, and the ROM of the shared bus type device 26 is provided.
A circuit A51 that requires access to the ROM 21 is directly connected to the I / F 12, and a PCI A / F 13 is connected to the PCI A13.
A circuit B52 that requires access to the device is connected. The number of terminals required for these two circuits 51 and 52 is reduced by sharing the bus.

In the present invention, as shown in FIG.
Instead of providing the PCI arbiter 14 in the host device 20, an external PCI arbiter may be used. In the embodiment shown in FIG. 3, the shared bus type device 26 does not perform arbitration of the entire PCI, operates as one of the PCI agents, outputs the bus request signal REQ_C # 62 to the external PCI arbiter 14, and Acquisition signal GNT_C # 6
Enter 3.

Internal P provided in the shared bus type device 26
The CI arbiter 53 includes a mode controller 32 and a PCI.
It arbitrates bus requests from only two I / Fs 13.

In the embodiment shown in FIG. 1, the external RO
The number of M and PCI connections is one each, but increase the number of ROM and PCI devices connected to shared bus 2 unless the load on the output buffer that drives the bus in each device becomes too large. Is possible. In the example shown in FIG. 3, the PCI device B5 is used as the PCI device.
4 have been added.

As described above, the present invention can be applied not only to the host device but also to general devices having PCI I / F and ROM I / F, such as the number of PCI / ROM devices, PCI arbiter, and mode setting. Register, PCI
There is flexibility regarding the configuration such as clock control. Although the present invention has been described above with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and a shared bus for commonly connecting a synchronous device and an asynchronous device is provided. It is needless to say that it is applicable and includes various variations and modifications that can be made by those skilled in the art within the scope of the invention of each claim.

[0102]

As described above, according to the present invention,
On a device that has both a PCI interface and a ROM interface, by switching the multiplexer according to the ROM mode / PCI mode, the ROM access pin and the PCI access pin can be used in common, so that the host device The number of external terminals can be reduced.

Further, according to the present invention, since the mode controller and the PCI arbiter cooperate with each other to avoid the conflict on the bus, there is no need to change the external ROM or PCI device or a new external circuit, and The number of points and the increase in cost are suppressed and reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram for explaining a state transition according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a PCI bus and ROM according to an embodiment of the present invention.
It is a figure which shows the signal line shared with a bus.

FIG. 5 is a timing diagram for explaining the operation of the embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 7 is a diagram showing a conventional system configuration.

FIG. 8 is a diagram showing a conventional system configuration.

[Explanation of symbols]

1 host bus 2 shared buses 4 ROM dedicated bus 5 PCI dedicated bus 11 CPU 12 ROM interface 13 PCI interface 14 PCI arbiter 15 clock distributor 20 Shared Bus Host Device 21 ROM 22 PCI device A 23 PCI-ROM interface 24 Conventional Host Device A 25 Conventional Host Device B 26 Shared Bus Device 31 Mode setting register 32 mode controller 33 multiplexer 40 ROM_BUSY 41 CS # (Chip Select) 42 REQ_A # 43 GNT_A # 44 REQ_PCIIF # 45 GNT_PCIIF # 46 REQ_CONT # 47 GNT_CONT # 48 PCI clock 49 PCI clock control signal 51 Circuit A 52 Circuit B 53 Internal PCI arbiter 54 PCI device B 60 REQ_B # 61 GNT_B # 62 REQ_C # 63 GNT_C #

Claims (19)

[Claims] 1. A synchronous type device connected to a clock synchronous type bus and an asynchronous type device connected to a bus having a protocol specification different from that of the clock synchronous type bus are commonly connected to one shared bus. The synchronous device and the asynchronous device share an address line, a data line, and at least a part of a plurality of control lines in the shared bus, and an access mode is a synchronous device access. Depending on the mode or the asynchronous device access mode, a synchronous device interface for interfacing the host device with the synchronous device is electrically connected to the shared bus, or the host device is connected. And an asynchronous device interface for interfacing with the asynchronous device and the shared bus. Switching means for electrically connecting, and in the case of the asynchronous device access mode, setting so that the asynchronous device interface and the asynchronous device can use the shared bus, and supply of a clock to the synchronous device In the case of the synchronous device access mode, supplying a clock to the synchronous device, disabling the use of the shared bus for accessing the asynchronous device,
A bus sharing apparatus comprising: a means for controlling so as to avoid access conflict between the asynchronous device and the synchronous device on the shared bus. 2. A synchronous device driven by a clock, which inputs an address signal and inputs or outputs a data signal and a control signal, and an asynchronous device which inputs an address signal and inputs or outputs a data signal and a control signal. Are commonly connected to one shared bus, and the synchronous device and the asynchronous device have at least a part of control lines of an address line and a data line and a plurality of control lines in the shared bus. A synchronous device interface that is shared and that interfaces between the host device and the synchronous device; an asynchronous device interface that interfaces between the host device and the synchronous device; the synchronous device interface; and the asynchronous device interface. Connected to the device interface and the shared bus,
Depending on whether the access mode is the synchronous device access mode or the asynchronous device access mode, one of the synchronous device interface or the asynchronous device interface and the shared bus are electrically connected. In the asynchronous device access mode, the multiplexer is provided with an arbiter circuit for the shared bus, and the asynchronous device interface and the asynchronous device are set to use the shared bus. When the supply of the clock to the synchronous device is stopped, and when the asynchronous device access mode shifts to the synchronous device access mode, the supply of the clock to the synchronous device is started, and the synchronous device access mode In the above An arbiter circuit for disabling use of the shared bus for accessing the asynchronous device, avoiding contention between the asynchronous device and the synchronous device on the shared bus, A bus sharing apparatus, comprising a mode control circuit for controlling to stop supply of a clock to the synchronous device when shifting from the access mode to the asynchronous device access mode. 3. The synchronous device is a PCI (Peripheral)
3. A bus sharing apparatus according to claim 1, wherein the bus sharing apparatus is a component interconnect) device, and the asynchronous device is an asynchronous memory device. 4. A PCI (Peripheral Component Interco)
nnect) device, an asynchronous memory device, and a shared bus to which the PCI device and the memory device are commonly connected, and in the shared bus, a PCI bus and a memory device access bus are provided. And address line and data line,
A part of a plurality of control lines is shared and is connected to a memory interface and a PCI interface, and the mode setting value is a memory mode in which the memory device can be accessed, or the PCI A multiplexer for selecting a connection path between the memory interface and the shared bus or a connection path between the PCI interface and the shared bus depending on whether the device is in a PCI mode in which the device is accessible, and an arbiter for the shared bus. A circuit and a clock distributor that distributes a clock to the PCI device. In a memory mode, the arbiter circuit is caused to use the shared bus for accessing the memory device, and the clock distribution is performed. Control, stop the clock supply, and switch to memory mode. When shifting to the PCI mode, after the access of the memory device is completed, the clock distributor is made to start the supply of the clock, and in the PCI mode, the arbiter circuit is made to operate the memory device of the shared bus. A mode control circuit is provided for avoiding contention between access and access of the PCI device, and controlling the clock distributor to stop the clock supply when shifting from the PCI mode to the memory mode. , A bus sharing system characterized by the following. 5. PCI (Peripheral Component Interco)
nnect) device, a ROM (Read Only Memory) device, and a shared bus to which the PCI device and the ROM device are commonly connected. In the shared bus, a PCI bus and a ROM access bus are provided. The address line, the data line, and a part of the plurality of control lines are shared, and the mode interface is connected to the ROM interface and the PCI interface and the mode setting value is accessible to the ROM device. A connection path between the ROM interface and the shared bus or a connection path between the PCI interface and the shared bus is selected depending on the mode or the PCI mode in which the PCI device is accessible. To the multiplexer, the arbiter circuit of the shared bus, and the PCI device In a ROM mode, the arbiter circuit is used to access the ROM device, and the clock distributor is used to supply a PCI clock. When the ROM mode is shifted to the PCI mode, the ROM device access is waited for, the clock distributor is caused to start the supply of the PCI clock, and in the PCI mode, the arbiter circuit is activated. By disabling access to the ROM device by the shared bus to avoid contention between ROM access and PCI access, and when shifting from PCI mode to ROM mode, the clock distributor is used to stop the supply of PCI clock. It is equipped with a mode control circuit that controls Bus sharing system that. 6. A mode setting register for setting one of a PCI mode and a ROM mode, wherein the mode control circuit switches between the ROM mode and the PCI mode according to a set value of the mode setting register. The bus sharing system according to claim 5, wherein the bus sharing system is a system. 7. The mode control circuit requests a bus use right from the arbiter circuit when the mode is changed from the PCI mode to the ROM mode, and occupies the shared bus for ROM access. The bus sharing system according to claim 5. 8. A ROM device address signal and data signal, a write enable signal, an output enable signal, a ready signal, a PCI bus address / data signal, an initiator ready signal, and a target ready signal, respectively. 6. The bus sharing system according to claim 5, wherein the bus sharing system is also used as a stop signal. 9. The ROM interface is the ROM
The bus sharing system according to claim 5, wherein the chip select signal for the device is supplied from a dedicated signal line. 10. The bus sharing system according to claim 5, wherein the writing of the mode setting value to the mode setting register is performed by a command from a host device. 11. The bus sharing system according to claim 5, wherein access to the ROM interface and the PCI interface is used as a trigger to write a mode setting value to the mode setting register. 12. In the ROM mode, the mode control circuit holds a right to use the shared bus for ROM access, and the arbiter circuit gives the mode control circuit permission to use the shared bus. The PCI interface and the PCI device do not start the master operation by acquiring the bus use right, the clock distributor stops the supply of the PCI clock, and the mode setting register When the PCI mode is set, the mode control circuit shifts to a ROM access end wait state, waits until the access end if the ROM interface is in the middle of access, and immediately after the access ends, shifts to the PCI mode. In the PCI mode transition state, the mode control Sends a PCI clock start signal to the clock distributor, controls the multiplexer to select a path on the PCI interface side, and when the PCI clock is started, transits to a PCI mode state, In the mode state, the mode control circuit releases the shared bus reserved for ROM access, the shared bus is used as a PCI bus, and the ROM interface outputs the chip select signal of the ROM device. 6. The bus sharing system according to claim 5, wherein deassertion is performed. 13. When the ROM mode is set in the mode setting register in the PCI mode, the PCI is set.
In the PCI bus request state, the mode control circuit requests the PCI bus use right from the arbiter circuit, receives the request, and the arbiter circuit deserts the PCI bus grant signal. When the PCI bus becomes idle, the mode control circuit is
In the ROM mode transition state, the mode control circuit sends a PCI clock stop signal to the clock distributor, and the multiplexer selects a path on the ROM interface side to stop the PCI clock. 13. The bus sharing system according to claim 12, wherein when the process is completed, the mode returns to the ROM mode. 14. A shared bus type device connected to a shared bus to which a PCI device and an asynchronous memory device are commonly connected, wherein the shared bus includes a PCI bus and a memory access bus. Address line and data line, and a part of control lines of the plurality of control lines are shared, and a memory mode accessible to the memory device and a PCI mode accessible to the PCI device are set. A mode setting register for storing the mode setting value, a memory interface, a PCI interface, and a mode for outputting a route selection signal depending on whether the mode setting value of the mode setting register is the memory mode or the PCI mode. A control circuit, and the memory based on the value of the path selection signal from the mode control circuit. Interface to the shared bus, a multiplexer for selecting one of the connection paths to the PCI interface and the shared bus, an arbiter circuit for the shared bus, and a clock distribution to the PCI device. In the memory mode, the mode control circuit causes the arbiter circuit to permit the shared bus to be used for accessing the memory device, and causes the clock distributor to perform PCI communication. When the clock supply is stopped and the memory mode is changed to the PCI mode, the clock distributor is made to start the supply of the PCI clock after the completion of the access of the memory device. In the PCI mode, the arbiter is Circuit to enable the memory device to operate on the shared bus. Access is prohibited, contention between memory access and PCI access is avoided, and when the PCI mode is changed to the memory mode, the clock distributor is controlled to stop the supply of the PCI clock. Shared bus control unit. 15. In the memory mode, the mode control circuit holds a shared bus use right for memory access, and the arbiter circuit gives the mode control circuit a bus use permission of the shared bus. It is in the state, and the P
When the CI interface and the PCI device do not start the master operation by acquiring the bus use right, the clock distributor stops the supply of the PCI clock and the PCI mode is set in the mode setting register. , The mode control circuit transits to an access end wait state of the memory device, waits until the access end if the memory interface is in the middle of access, and transits to the PCI mode transition state after the access ends, In the transition state, the mode control circuit sends a PCI clock start signal to the clock distributor, controls the multiplexer to select a path on the PCI interface side, and when the PCI clock is started, the PCI clock is started. Transition to mode state and enter PCI mode state The mode control circuit opens the said shared bus which has been reserved for memory access,
15. The shared bus control device according to claim 14, wherein the shared bus is used as a PCI bus, and the memory interface deasserts a chip select signal. 16. In a PCI mode state, when the memory mode is set in the mode setting register, P
Transition to the CI bus request state, and in the PCI bus request state,
The mode control circuit is connected to the arbiter circuit by a P
In response to this request, the arbiter circuit deserts the PCI bus grant signal, and when the PCI bus enters the idle state, the mode control circuit reserves the shared bus for memory access. When it is judged that it has been completed, the mode transitions to the memory mode transition state. In the memory mode transition state, the mode control circuit sends a PCI clock stop signal to the clock distributor, and the multiplexer routes the path on the memory interface side. 16. The shared bus control device according to claim 15, wherein when the PCI clock is completely stopped, the memory mode is returned to. 17. An external arbiter circuit provided outside the shared bus control device is used as the arbiter circuit of the shared bus, and the mode control circuit and the PCI interface are provided inside the shared bus control device. An internal arbiter circuit for arbitrating the use of the shared bus with a circuit is provided, wherein the internal arbiter circuit sends a bus use request to the external arbiter circuit and sends a permission signal from the external arbiter circuit. 15. The shared bus controller of claim 14, wherein the shared bus controller receives. 18. The shared bus control apparatus according to claim 14, wherein the memory device is a non-volatile memory or a rewritable non-volatile memory. 19. A synchronous device connected to a clock synchronous bus, and an asynchronous device connected to a bus having a protocol specification different from that of the clock synchronous bus,
The common type bus is commonly connected to one shared bus, and the synchronous type device and the asynchronous type device share an address line and a data line and at least a part of control lines of a plurality of control lines in the shared bus. Depending on whether the mode is the synchronous device access mode or the asynchronous device access mode, the synchronous device interface for interfacing between the host device and the synchronous device is electrically connected to the shared bus. Or performing switching control for electrically connecting an asynchronous device interface for interfacing the higher-level device with the asynchronous device and the shared bus; and in the asynchronous device access mode, the bus. The arbiter circuit of the Enabling the ephemeral device to use the shared bus and stopping the supply of the clock to the synchronous device; and when the asynchronous device access mode shifts to the synchronous device access mode, the asynchronous device The access to the asynchronous device is controlled, the step of controlling the supply of the clock to the synchronous device is started, and in the synchronous device access mode, the arbiter circuit is used to access the asynchronous device. Disabling the use of the shared bus and avoiding access conflict between the asynchronous device and the synchronous device on the shared bus; and when shifting from the synchronous device access mode to the asynchronous device access mode Is a clock to the synchronous device. Including a step of performing control to stop the supply of the bus sharing wherein the.