JP2003098238A - Method and circuit for checking pattern data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To check whether a test pattern is transferred normally or not, when a pattern data written in a device program is transferred to a pattern memory. SOLUTION: This pattern data checking circuit for checking whether the pattern data is transferred normally or not, when the pattern data used by execution of the device program is transferred to the pattern memory 14 stored with the pattern data, and when a parity pattern data provided by conducting preliminarily a parity operation to a value of the pattern data is transferred to a parity pattern memory 17 to which the pattern data is stored, by a CPU 12 respectively, has a parity computing circuit 31 for conducting the parity operation for the pattern data transferred to the pattern memory 14 by the CPU 12, and an inconsistency detecting circuit 32 for detecting inconsistency between a parity computation result by the parity computing circuit 31 and the transmitted parity pattern data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for testing a semiconductor integrated device (hereinafter referred to as an IC tester), and more specifically, it is installed inside an IC tester and checks pattern data when transferring test pattern data. The present invention relates to a pattern data check circuit and a pattern data check method.

[0002]

2. Description of the Related Art In recent years, ICs (Integrated Circuits) for circuits used in various electric devices have been rapidly developed. IC, LSI (Large Scale Integrated Circuit)
Etc., each element such as a resistor, a capacitor, a transistor, etc. is realized by a circuit formed by a method such as printing or fusing, but there is some variation in characteristics between mass-produced products. For this reason, it is performed to test whether the characteristics of the IC or the LSI satisfy the standard by using the IC tester.

A pattern data transfer circuit used in a conventional IC tester will be described below with reference to FIG. FIG. 3 shows a conventional pattern data transfer circuit 11
3 is a block diagram showing the configuration of each circuit connected to the pattern data transfer circuit 11. FIG. In FIG. 3, the pattern data transfer circuit 11 is a CPU (Central Processing Uni
t) 12, a plurality of pattern memories 14 provided for each tester channel, a plurality of parity pattern memories 17 provided for each group of tester channels, and one or more provided for a plurality of tester channels. The address control circuit 18 is provided.

Further, the pattern data transfer circuit 11 includes an address generation circuit 13 for executing a test pattern, a plurality of pattern generation circuits 15 provided for each tester channel,
A plurality of parity pattern generation circuits 16 provided for each group of tester channels, and a plurality of parity check circuits 1 provided for each group of tester channels
9, the plurality of waveform shaping circuits 20 provided for each tester channel, and the pin electronics 21 are connected to test the operation of the DUT 22. DUT (Device U
nder Test) 22 is a device under test such as IC, LSI, etc., each input / output pin of the DUT 22 is connected to each pin electronics 21 corresponding to each channel of the IC tester having the pattern generation circuit 15, Operation check is performed by the IC tester.

The CPU 12 loads a device program corresponding to a designated DUT from among various device programs corresponding to various DUTs stored in a storage medium in the storage device (not shown) in the RAM (not shown) in the storage device 23. It is stored in a memory area in (Random AccessMemory) and controls each hardware of the IC tester according to the device program.

FIG. 4 is a diagram showing an example of pattern data and parity pattern data. The pattern data is DUT22.
This is data programmed in the device program executed at the time of the test, and is given to each tester channel. With this data, D of each tester channel
Output of Hi / Lo driver waveform input to UT22, capture of waveform output from DUT22, Hi / Lo
Lo determination is controlled.

In the example shown in FIG. 4, the pattern data is set to "Hi
/ Lo, "I / O", and "strobe mask" are represented by a 3-bit structure, and "1" of "Hi / Lo" data is "Hi".
gh ”,“ 0 ”is“ Low ”,“ 1 ”of“ I / O ”data is“ input ”,“ 0 ”is“ output ”,
"1" of "strobe mask" data is "no judgment",
“0” means “determined”. As a result, for example, in the "Tester Channel""1","0output","1output","Lexpectation", ...
., "H expectations" ... and the following data are not shown,
Various pattern data are given. In addition, other "T
Similarly, pattern data is also given for "ester Channel".

As the parity pattern data, several tester channels are grouped into a group of tester channels, and the result of performing a parity operation on the pattern data included in the tester channel group is given. In the example shown in FIG. 4, the tester channels 1 to 8 are set as one group, and “Hi / Lo”, “I / O”,
Parity pattern data for address 0 of the "strobe mask" are given as "0", "0", and "0", respectively.

One address generating circuit 13 is provided for a plurality of tester channels of the IC tester, or a plurality of address generating circuits 13 are provided corresponding to the tester channels. The test pattern of each tester channel is addressed by the device program corresponding to the DUT 22. The address generation circuit 13 outputs the pattern address to the pattern generation circuit 15 and the parity pattern generation circuit 16 according to the above device program.

A plurality of pattern memories 14 are provided corresponding to each tester channel of the IC tester. The above pattern data is stored in the pattern memory 14 corresponding to each tester channel. The pattern generation circuit 15
Multiple corresponding to each tester channel of the IC tester,
It is provided. The pattern generation circuit corresponding to each tester channel is controlled by the corresponding pattern address, and outputs the pattern data from the pattern memory 14 to the waveform shaping circuit 20 and the parity check circuit 19.

A plurality of parity pattern memories 17 are provided corresponding to each tester channel group of the IC tester.
It is provided. The parity pattern memory 17 corresponding to each tester channel group stores the parity pattern data. Parity pattern generation circuit 16
As shown in FIG. 3, a plurality of are provided corresponding to each tester channel group of the IC tester. The parity pattern generation circuit 16 corresponding to each tester channel group is controlled by the corresponding pattern address, and outputs the parity pattern data from the parity pattern memory 17 to the parity check circuit 19.

One address control circuit 18 is provided for a plurality of tester channels of the IC tester, or a plurality of address control circuits 18 are provided corresponding to the tester channels. The address control circuit 18 outputs addresses to the pattern memory 14 and the parity pattern memory 17 when writing and reading data in the pattern memory and the parity pattern memory. A plurality of parity check circuits 19 are provided corresponding to each tester channel group of the IC tester.

The parity check circuit 19 corresponding to each tester channel group performs a parity operation on the basis of the pattern data from the pattern generating circuit 15 for each pattern address when executing the test pattern, and the operation result and the parity pattern generating circuit 16 are executed. Detect the mismatch with the parity pattern data from. The detected non-coincidence signal is output to the address generation circuit 13 and the CPU 12. In the address generation circuit 13, the test pattern execution can be forcibly stopped by this signal. With this signal, the CPU 12 can inform the user that the test pattern has not been normally executed.

As shown in FIG. 3, the waveform shaping circuit 20 includes
Multiple corresponding to each tester channel of the IC tester,
It is provided. The waveform shaping circuit 20 corresponding to each tester channel shapes the driver waveform required for the IC test based on the pattern data input from the pattern generation circuit 15, and outputs the driver waveform to the pin electronics 21.
The pin electronics 21 is used as an interface corresponding to each input / output pin of the DUT 22.
This is a circuit on the C tester side, and as shown in FIG.
A plurality of testers are provided corresponding to each tester channel.

The pin electronics 21 corresponding to each tester channel is connected to each input / output pin of the DUT 22 and receives the driver waveform input from the waveform shaping circuit 20 as D.
Output to each input pin of UT22, and DUT2
The waveform output from 2 is captured. Next, according to the flowchart shown in FIG. 5, as an example, the pattern data and the parity pattern data shown in FIG. 4 are written in the pattern memory 14 and the parity pattern memory 17, respectively.
The pattern data transfer operation of the pattern data transfer circuit 11 will be described.

First, the CPU 12 loads a device program corresponding to the DUT 22 stored in a storage medium (not shown) in the storage device (not shown) in the storage device 23.
The data is stored in a work area in the AM, and the pattern data and parity pattern data are temporarily stored in the RAM (not shown) in the storage device 23 according to the device program corresponding to the DUT 22. CPU12 is the above R
The Hi / Lo data of the pattern address "0" is selected by referring to the pattern address stored in the AM (step 200).

Next, the CPU 12 refers to the pattern data stored in the RA to refer to the pattern address "0", Hi /
Pattern data “0110100” for Lo data
1 "and parity pattern data" 0 "are read and transferred to the pattern memory 14 and the parity pattern memory 17 (step 201). The transferred pattern memory data is written in the pattern memory 14, and the transferred parity pattern data is written in the parity pattern memory 17. (Step 202, Step 203).

Next, the CPU 12 determines whether or not there is untransferred data (step 204).
Since the data after the address "1" remains, the process returns to step 200 and the same pattern data transfer operation is performed for the address "1". When the pattern data transfer is completed up to the final address, there is no next address in step 204, so that the series of pattern data transfer operations is completed. The I / O data and strobe mask data are also transferred in the same manner as the Hi / Lo data.

[0019]

However, in the conventional pattern data transfer circuit 11, as described above,
In steps 200 to 203 of FIG. 5, the test pattern may not be transferred correctly due to a software error in the CPU 12 or data corruption in the transfer path. At this time, if the test result is a normal test pattern, the device test execution result should be "pass", but the normal test pattern was not transferred, so the test result is "fail".
There is a risk of doing it. On the contrary, it is possible that the result of "fail" is "pass".

An object of the present invention is to provide a pattern data check circuit capable of checking whether or not a normal test pattern has been transferred when transferring pattern data described in a device program to a pattern memory. To do.

[0021]

In order to achieve the above object, the invention described in claim 1 is to execute a device program prepared corresponding to a device under test for performing a functional test of the device under test. The pattern data described in the device program to be used is stored in a pattern memory in which the pattern data is stored, and the pattern data is parity pattern data obtained by performing a parity operation on the value of the pattern data in advance. A pattern data check method for checking whether or not pattern data has been normally transferred to the stored parity pattern memory when the pattern memory is transferred from the arithmetic processing unit. The parity data of the pattern data transferred to the Detecting a mismatch between Ndeta, pattern data on the basis of the detection result and judging whether or not successfully transferred.

The invention described in claim 2 is the same as claim 1.
In the pattern data check method according to the item (1), each time the pattern memory and the parity pattern memory are transferred from the arithmetic processing unit to the pattern data and the parity pattern data, the parity arithmetic unit outputs the transferred pattern data. It is characterized in that the parity calculation is performed, and the mismatch detection unit detects a mismatch between the parity calculation result by the parity calculation unit and the parity pattern data.

The invention described in claim 3 is a pattern described in the device program, which is prepared corresponding to the device under test and is used by executing a device program for performing a functional test of the device under test. Data is processed in a pattern memory in which the pattern data is stored, and parity pattern data obtained by performing a parity calculation on the value of the pattern data in advance is processed in a parity pattern memory in which the pattern data is stored. A pattern data check circuit for checking whether or not the pattern data is normally transferred when the pattern data is transferred from the means, and a parity operation means for performing a parity operation on the pattern data transferred from the operation processing means to the pattern memory; A parity operation result by the parity operation means and the transferred parity pattern And having a mismatch detecting means for detecting a mismatch between data.

The invention according to claim 4 is the same as claim 3
In the pattern data check circuit described in (1), each time the pattern memory and the parity pattern memory are transferred from the arithmetic processing unit to the pattern memory and the parity pattern data, the parity arithmetic unit outputs the transferred pattern data. It is characterized in that the parity calculation is performed, and the mismatch detection unit detects a mismatch between the parity calculation result by the parity calculation unit and the parity pattern data.

The invention described in claim 5 is a pattern described in the device program, which is prepared for the device under test and is used by executing a device program for performing a functional test of the device under test. Data is processed in a pattern memory in which the pattern data is stored, and parity pattern data obtained by performing a parity calculation on the value of the pattern data in advance is processed in a parity pattern memory in which the pattern data is stored. A pattern data check circuit for checking whether or not the pattern data is normally transferred when the pattern data is transferred from the means, and a parity operation means for performing a parity operation on the pattern data transferred from the operation processing means to the pattern memory; A parity operation result by the parity operation means and the transferred parity pattern It has a disagreement detecting means for detecting a disagreement with the data, and a state holding means for holding a state signal output from the disagreement detecting means, and once the disagreement means detects the disagreement, the state holding means Is characterized by continuing to hold the disagreement state.

The invention described in claim 6 is a pattern described in the device program, which is prepared corresponding to the device under test and used by executing a device program for performing a functional test of the device under test. Data is processed in a pattern memory in which the pattern data is stored, and parity pattern data obtained by performing a parity calculation on the value of the pattern data in advance is processed in a parity pattern memory in which the pattern data is stored. A pattern data check circuit for checking whether or not the pattern data is normally transferred when the pattern data is transferred from the means, and a parity operation means for performing a parity operation on the pattern data transferred from the operation processing means to the pattern memory; A parity operation result by the parity operation means and the transferred parity pattern A mismatch detection means for detecting a mismatch with the data, and a transfer log memory in which the status signal output from the mismatch detection means is stored for each data transfer, the arithmetic processing means, after the pattern data transfer, It is characterized in that the location of the pattern data where the transfer error has occurred is specified by reading the log data in the transfer log memory.

According to the present invention, the pattern data described in the device program, which is prepared for the device under test and is used by executing the device program for performing the functional test of the device under test, is used as the pattern data. And the parity pattern data obtained by performing a parity operation on the value of the pattern data in advance to the parity pattern memory in which the pattern data is stored by the arithmetic processing means. Then, a parity operation is performed on the pattern data transferred to the pattern memory by the operation processing means, a mismatch between the parity operation result and the parity pattern data is detected, and the pattern data is normally transferred based on the detection result. Since it was decided whether or not the pattern described in the device program Normal test pattern in transferring the pattern memory can be checked whether it is transferred.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the configuration of the pattern data check circuit according to the embodiment of the present invention. A pattern data check circuit according to an embodiment of the present invention is a pattern described in a device program that is prepared for a device under test and is used by executing a device program for performing a functional test of the device under test. Data is processed in a pattern memory in which the pattern data is stored, and parity pattern data obtained by performing a parity calculation on the value of the pattern data in advance is processed in a parity pattern memory in which the pattern data is stored. A pattern data check method for checking whether or not the pattern data has been normally transferred when the pattern data is transferred from the means, and a parity operation is performed on the pattern data transferred from the operation processing means to the pattern memory when the pattern data is transferred. , A mismatch between the parity calculation result and the parity pattern data is detected. And a circuit for implementing the pattern data check method characterized by determining whether the pattern data on the basis of the detection result has been transferred successfully.

In FIG. 1, a pattern data check circuit 1 is a circuit for checking the pattern data at the time of transferring the pattern data among the circuits forming the IC tester.
U12, parity check circuit 2, pattern memory 1
4, a parity pattern memory 17, an address control circuit 18, and a transfer log memory 3. Further, although not shown, the pattern data check circuit 1 includes a pattern generation circuit, a waveform shaping circuit, a pin electronics, and an IC for each tester channel forming the IC tester.
It is connected to a parity pattern generation circuit and a parity check circuit for each tester channel group forming the tester, and pin electronics is further connected to the DUT.

Descriptions of the DUT, the pattern generation circuit, the waveform shaping circuit, the pin electronics, the parity pattern generation circuit, and the parity check circuit, which are not shown, are omitted because they are the same as those of FIG. Pattern data check circuit 1 of the form
The purpose is to check whether the pattern data for setting the test signal pattern for the UT has been normally transferred from the CPU 12 to the pattern memory 14.

In FIG. 1, the CPU 12 specifies a D specified from various device programs corresponding to various DUTs stored in a storage medium (not shown).
A device program corresponding to the UT is stored in a work area of a RAM (not shown) in the storage device 23, and the hardware of the IC tester is controlled according to the device program. Further, the CPU 12 temporarily stores the pattern data having a configuration as shown in FIG. 4 input from the storage medium in the storage device in a RAM (not shown) in the storage device 23, and stores it in the pattern memory 14 and the parity check circuit 2. Output to. Similarly, the CPU 12 temporarily stores the parity pattern data having the configuration shown in FIG. 4 in the RAM (not shown) in the storage device 23, and the parity pattern memory 1
7, output to the parity check circuit 2.

A plurality of parity check circuits 2 (for example, four in 8-bit units) are provided corresponding to a group of tester channels of the IC tester (for example, 32-bit bus). The parity check circuit 2 corresponding to each tester channel group outputs the result of the parity check to the transfer log memory 3 and the CPU 12 for each transfer of the pattern data and the parity pattern data.

The parity check circuit 2 comprises a parity operation circuit 31, a mismatch detection circuit 32, and a state holding circuit 33. The parity arithmetic circuit 31 is a CPU
Parity calculation is performed on the pattern data transferred from 12, and the calculation result is output to the mismatch detection circuit 32. The mismatch detection circuit 32 detects a mismatch between the calculation result from the parity calculation circuit 31 and the parity pattern data transferred from the CPU 12, and outputs the detection result to the transfer log memory 3 and the state holding circuit 33.

Once the mismatch signal is detected by the mismatch detection circuit 32, the status holding circuit 33 continues to hold the status. That is, this state signal is a signal for detecting whether or not the pattern data is abnormally transferred. This status signal is output to the CPU 12. In addition, the pattern memory 14
Are provided corresponding to each tester channel of the IC tester. The pattern data transferred from the CPU 12 is stored in the pattern memory 14 corresponding to each tester channel.

A plurality of parity pattern memories 17 are provided corresponding to the tester channel groups of the IC tester. The result of the parity calculation of the pattern data read from the device program by the CPU 12 in advance is stored as an expected value in the parity pattern memory 17 corresponding to each tester channel group. One address control circuit 18 is provided for a plurality of tester channels of the IC tester, or a plurality of address control circuits 18 are provided corresponding to the tester channels.

The address control circuit 18 is used for the pattern memory 1
4, the parity pattern memory 17, the transfer log memory 3, when writing and reading data to the address, the pattern memory 14, the parity pattern memory 17, the transfer log memory 3
To the output. A plurality of transfer log memories 3 are provided corresponding to the tester channel groups of the IC tester. The transfer log memory 3 corresponding to each tester channel group stores the result of the parity check output from the parity check circuit 2.

Next, the operation of the pattern data check circuit according to this embodiment will be described with reference to the flowchart shown in FIG. In this embodiment, the address shown in FIG.
The pattern data check operation of the pattern data check circuit 1 will be described by taking as an example the case where the pattern data and the parity pattern data are written in the pattern memory 14 and the parity pattern memory 17 in the 0 "and Hi / Lo pattern data. Address, "I / O", "
The same operation is performed for the “strobe mask” data.

First, the CPU 12 stores the device program corresponding to the DUT stored in the storage medium in the storage device (not shown) in the work area in the RAM (not shown), and also according to the device program corresponding to the DUT. Data and pattern parity data are temporarily stored in a RAM (not shown). The CPU 12 refers to the pattern address and selects the Hi / Lo data of the pattern address "0" (step S100). Next, the CPU 12
Refers to the pattern data stored in the RAM, the pattern address "0", the pattern data "011101001" for the Hi / Lo data, the parity pattern data "
0 "is read and transferred to the pattern memory 14 and the parity pattern memory 17 (step 101).

The transferred pattern memory data is written in the pattern memory 14, and the transferred parity pattern data is written in the parity pattern memory 17. (Step 102, Step 104) The parity operation circuit 31 performs a parity operation on the pattern data “011101001” transferred from the CPU 12, and outputs the operation result “0” to the mismatch detection circuit 32. (Step 103)

The mismatch detection circuit 32 detects a mismatch between the parity calculation result “0” from the parity calculation circuit 31 and the parity pattern data “0” transferred from the CPU 12. In this case, since the patterns match, it means that the normal pattern data transfer is performed, and the mismatch detection circuit 32 outputs the mismatch detection data “0” to the transfer log memory 3 and the state holding circuit 33. (Step 105) In the transfer log memory 3, the mismatch detection data “0” input from the mismatch detection circuit 32 is stored as the transfer result of the Hi / Lo data of the pattern address “0” (step 106).

The state holding circuit 33 includes a mismatch detection circuit 32.
Since the mismatch detection data transferred from is 0, and the transfer result of the pattern data is normal, the data (status signal)
“0” is output to the CPU 12. (Step 107) The CPU 12 transfers the pattern data and the parity pattern data until there is no next pattern address. (Step 108) For example, at address "2", it is assumed that the pattern data "01101011" originally output from the CPU 12 is corrupted and the pattern data "00101011" is output.

It is assumed that "1" is normally output as the parity pattern data. In this case, the parity calculation circuit 31 outputs “0” as the parity calculation result. (Step 103) At this time, the mismatch detection circuit 32 has a mismatch, and the mismatch detection circuit 32 outputs a mismatch signal “1” to the transfer log memory 3 and the state holding circuit 33.
Is output to. (Step 105) The transfer log memory 3 sets the mismatch detection data “1” from the mismatch detection circuit 32 to Hi / Lo of the pattern address “2”.
Store as data transfer result. (Step 10
6)

The state holding circuit 33 includes a mismatch detection circuit 32.
The mismatch detection data transferred from is "1", and the data (status signal) "1" is output to the CPU 12 as a result of abnormal transfer of the pattern data. State holding circuit 33
Then, once an abnormal transfer of pattern data is detected,
Hold inconsistency. For example, even if a match is detected after the next address, the mismatch state “1” is held. (Step 109) Then, when the next pattern address is exhausted in the CPU 12, a series of pattern data transfer operation is ended. (Step 108)

The CPU 12 can detect that an error has occurred in the pattern data transfer by the non-coincidence signal (state signal) from the state holding circuit 33. Therefore, the user can be notified that the device test is invalid before the test is executed. This makes it possible to eliminate the pass device fail determination and the fail device pass determination by the invalid device test in advance. Further, when an error occurs in the pattern data transfer, the contents of the transfer log memory 3 are read, whereby the location of the pattern data where the error transfer has occurred can be specified.

As a result, if the pattern data is retransferred only at the error transfer location, it becomes possible to execute the device test as a complete program. By retransferring the pattern data only at the error transfer location in this manner, it is possible to correct the pattern data in a shorter time than when all the pattern data and the parity pattern data are retransferred.
As described above, in this embodiment, the parity check circuit and the transfer log memory are added in correspondence with the tester channel groups.

That is, the device test pattern data,
At the time of transferring the parity pattern data, the parity of the transferred pattern data can be calculated, and the calculation result can be detected as a mismatch with the transferred parity pattern data. In the present embodiment, a soft error or a data garble occurs when transferring the pattern data and the parity pattern data,
When the transfer of the pattern data is not normally performed, the abnormality can be detected and the abnormal portion of the transferred pattern data can be specified.

[0047]

According to the present invention, the pattern data described in the device program, which is prepared for the device under test and is used by executing the device program for performing the functional test of the device under test, is stored. Transferring the pattern data to the pattern memory, and the parity pattern data obtained by performing the parity operation on the value of the pattern data in advance to the parity pattern memory storing the pattern data from the arithmetic processing means. In doing so, a parity operation is performed on the pattern data transferred to the pattern memory from the operation processing means, a mismatch between the parity operation result and the parity pattern data is detected, and the pattern data is normally detected based on the detection result. Since it was decided whether or not it was transferred, the pattern described in the device program Successfully test pattern when transferring data to the pattern memory can be checked whether it is transferred.

That is, a parity check circuit and a transfer log memory are added to correspond to the tester channel groups, and when the pattern data and the parity pattern data are transferred, the parity operation data and the parity pattern of the transferred pattern data are transferred. By detecting the inconsistency with the data, it is possible to detect whether or not a state in which the pattern data is not normally transferred has occurred due to a software error or data corruption during the transfer of the pattern data.

Further, every time the pattern data is transferred, a status signal of the match / mismatch between the parity-operated data of the transferred pattern data and the parity pattern data is stored in the transfer log memory, whereby the abnormal transfer of the pattern data is carried out. If the location can be specified and only that location is retransmitted, the normal pattern data can be restored in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pattern data check circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a pattern data transfer operation of the pattern data check circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional pattern data transfer circuit and each circuit connected to the pattern data transfer circuit.

FIG. 4 is an explanatory diagram showing the relationship between pattern data and pattern addresses.

5 is a flowchart showing an example of a pattern data transfer operation of the pattern data transfer circuit shown in FIG.

[Explanation of symbols]

1 Pattern data check circuit 2 Parity check circuit 3 Transfer log memory 12 CPU (arithmetic processing means) 14 pattern memory 17 Parity pattern memory 18 Address control circuit 31 Parity calculation circuit (parity calculation means) 32 mismatch detection circuit (mismatch detection means) 33 State holding circuit (state holding means)

Claims (6)

[Claims] 1. Pattern data described in the device program, which is prepared corresponding to the device under test and is used by executing a device program for performing a functional test of the device under test, is stored in the pattern data. When the parity pattern data obtained by performing the parity operation on the value of the pattern data in advance is transferred to the parity pattern memory in which the pattern data is stored by the operation processing means, the pattern is normally processed. A pattern data check method for checking whether or not data has been transferred, wherein a parity operation is performed on the pattern data transferred to the pattern memory from the operation processing means during pattern data transfer, and the parity operation result and the parity pattern are sent. Detects inconsistency with the data, and based on the detection result, pattern data Pattern data checking method characterized by determining whether it is successfully transferred. 2. Each time the arithmetic processing means transfers the pattern data and the parity pattern data to the pattern memory and the parity pattern memory, respectively, the parity arithmetic means performs a parity operation on the transferred pattern data. The mismatch detection means detects a mismatch between the parity calculation result of the parity calculation means and the parity pattern data.
The pattern data check method described in. 3. The pattern data, which is prepared corresponding to the device under test and is used by executing a device program for performing a functional test of the device under test, is stored in the pattern data. When the parity pattern data obtained by performing the parity operation on the value of the pattern data in advance is transferred to the parity pattern memory in which the pattern data is stored by the operation processing means, the pattern is normally processed. A pattern data check circuit for checking whether or not data has been transferred, the parity operation unit performing a parity operation of the pattern data transferred from the operation processing unit to the pattern memory, and the parity operation result by the parity operation unit. And a mismatch between the transferred parity pattern data is detected. Pattern data check circuit comprising: the coincidence detection means. 4. The parity operation means performs a parity operation on the transferred pattern data every time the operation processing means transfers the pattern data and the parity pattern data to the pattern memory and the parity pattern memory, respectively. The mismatch detection means detects a mismatch between the parity calculation result of the parity calculation means and the parity pattern data.
The pattern data check circuit described in. 5. The pattern data, which is prepared corresponding to the device under test and is used by executing a device program for performing a functional test of the device under test, is stored in the pattern data. When the parity pattern data obtained by performing the parity operation on the value of the pattern data in advance is transferred to the parity pattern memory in which the pattern data is stored by the operation processing means, the pattern is normally processed. A pattern data check circuit for checking whether or not data has been transferred, the parity operation unit performing a parity operation of the pattern data transferred from the operation processing unit to the pattern memory, and the parity operation result by the parity operation unit. And a mismatch between the transferred parity pattern data is detected. It has a coincidence detecting means and a state holding means for holding a state signal output from the non-coincidence detecting means, and once the non-coincidence means detects the non-coincidence, the state holding means continues to hold the non-coincidence state. A pattern data check circuit characterized in that 6. The pattern data, which is prepared corresponding to the device under test and is used by executing a device program for performing a functional test of the device under test, is stored in the pattern data. When the parity pattern data obtained by performing the parity operation on the value of the pattern data in advance is transferred to the parity pattern memory in which the pattern data is stored by the operation processing means, the pattern is normally processed. A pattern data check circuit for checking whether or not data has been transferred, and parity operation means for performing a parity operation on the pattern data transferred from the operation processing means to the pattern memory,
A mismatch detection unit that detects a mismatch between the parity calculation result by the parity calculation unit and the transferred parity pattern data; and a transfer log memory in which the status signal output from the mismatch detection unit is stored for each data transfer. The pattern data check circuit is characterized in that the arithmetic processing means specifies a portion of the pattern data in which a transfer error has occurred by reading log data in the transfer log memory after the pattern data transfer is completed.