JP2003086508A - Compound semiconductor layer substrate, method of manufacturing the same, and device manufactured on the same substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a compound semiconductor layer substrate having the superior quality of inexpensive compound semiconductor layer manufactured thereon, and also a device manufactured on the substrate. SOLUTION: The substrate includes a GaAs substrate 101 having a porous region 102, pores 103 in the porous region, and a wall part 104 forming the pores 103. A layer of surface part 105 sealing the pores is formed on a surface of the porous GaAs layer. A III-V compound semiconductor layer 106 is formed on the surface part 105. At this time, the thickness of the formed compound semiconductor layer 106 is made much heavier than the thickness of the surface part 105. Thereby dislocation generated based on a lattice constant difference or thermal expansion coefficient difference can be prevented and thus the superior quality of inexpensive compound semiconductor substrate can be obtained. Further, the superior quality of crystal of another compound semiconductor not lattice-matched with the above substrate can be obtained. In addition, with use of this substrate, an inexpensive compound semiconductor device having proper characteristics can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor layer substrate, a method for producing the same, and a device produced on this substrate. More specifically, the present invention relates to a compound semiconductor layer substrate for manufacturing an electronic device or a light emitting device by laminating a compound semiconductor different from this semiconductor substrate on the compound semiconductor substrate, and a method for manufacturing the same, and a method for manufacturing the same. The device manufactured in.

[0002]

2. Description of the Related Art Conventionally, a compound semiconductor layer substrate, a method for producing the same, and devices produced on this substrate have been applied to, for example, light emitting diodes, semiconductor lasers, high-speed electronic devices, and the like.

In such a situation, ZnSSe system, CdMnT
Typical II-VI and III-V group compound semiconductors as Conventional Example 1 represented by e-type, InGaAs-type, InGaP-type and GaN-type are suitable for light emitting diodes, semiconductor lasers and high-speed electronic devices. Therefore, many devices using these materials have been manufactured conventionally.

However, with these material systems it is very difficult to obtain bulk large area crystals, or
Even if such a bulk crystal is obtained, it is very expensive. Therefore, as a substrate for growing these crystals, a substrate such as GaAs or InP that can be manufactured at a relatively low cost is mainly used. However, since these substrates generally have different material physical properties from the compound semiconductor crystal to be laminated thereon, it has been pointed out that there are problems in producing the following good quality crystals.

One of them is a problem caused by the fact that the compound semiconductor material to be laminated and the substrate generally do not have the same lattice constant. For this reason, for ternary compound semiconductors such as ZnSSe and quaternary compound semiconductors such as InGaAsP, only the material whose lattice constant is approximately the same as the compound substrate such as GaAs or InP to be used by adjusting this composition , Or a pseudo lattice-matching region (Pseudo-morphic region)
Is commonly used.

However, adjusting the composition so as to be lattice-matched or pseudo-lattice-matched has the disadvantage that the physical constants such as the band gap of the compound semiconductor cannot be freely selected. There is a drawback that only a part of the degree of freedom that the system has can be used.

In order to utilize the original degree of freedom of these compound semiconductors, it has been attempted to grow a crystal of a material having a lattice constant different from that of the substrate. However, this difference in lattice constant causes stress and lattice defects, and as a result, there is a drawback in that good light emission characteristics and electric conduction characteristics cannot be obtained when a device is manufactured on this substrate.

Another problem is a problem due to the difference in coefficient of thermal expansion between the compound semiconductor to be laminated and the substrate. This is because, when a compound semiconductor is formed on a substrate, crystal growth is generally performed at a temperature considerably higher than room temperature, that is, a temperature of several hundreds to one thousand and several hundreds of degrees. In such a case, if the difference in the coefficient of thermal expansion between the compound semiconductor to be laminated and the substrate is different, dislocations will occur due to the difference in the coefficient of thermal expansion in the process of returning it to room temperature, even if it is lattice-matched at the growth temperature. There is a problem that ends up.

Various methods have been tried so far in order to solve the problems caused by the difference in lattice constant and the difference in thermal expansion coefficient. Among them, a twist-bonded substrate has recently been proposed. (FEEjeckam et al, Applie
d Physics, vol.70, p, 1685 (1997)) As shown in Fig. 2, this is a thin film with the same plane orientation made of the same material as the base substrate of several nanometers to tens of nanometers. This is a method in which a substrate is prepared in which crystal axes are rotated in a plane and bonded to each other, and a semiconductor material which is not lattice-matched with the substrate material is epitaxially grown on the substrate.

By this method, InGa that does not lattice match with GaAs
It has been reported that crystals of P, InSb, InGaAs, etc. have been grown, and crystals with a very low dislocation density could be grown.

However, in this method, the twist
In order to fabricate a bonded substrate, prepare a substrate with a structure in which an etch stop layer is epitaxially grown and inserted in advance, and bond it to a base substrate, and then polish and selectively etch it. It requires a complicated process of performing. Therefore, it is considered that there is a drawback in that the substrate is expensive to manufacture and the substrate becomes very expensive.

On the other hand, as a method of Conventional Example 2 for forming a compound semiconductor on a silicon substrate, a silicon substrate having a porous silicon region in which the porous region on the surface is sealed is used and a single substrate is formed thereon. A method for laminating a crystalline compound semiconductor layer has been proposed (Japanese Patent Application No. 9-62856 and Yasuh).
ikoHayashi et al., Japanese Journal of Applied Phys
ics, vol., 37, pp. L1354-1357 (1988)). in this way,
A silicon substrate having a porous region is heat-treated in order to seal the pores on the surface of the porous region, and a compound semiconductor layer is laminated on the substrate.

When the compound semiconductor layer is produced in this manner, the lattice mismatch with the silicon substrate and the lattice defects and strains caused by the difference in the coefficient of thermal expansion when the temperature is lowered from the film forming temperature to room temperature are porous. It is introduced only into the ultrathin silicon layer that seals the silicon holes, and is rarely introduced into the compound semiconductor layer. This is because the ultrathin silicon layer formed on the brittle porous layer is much weaker than that of bulk silicon and the grown compound semiconductor layer.

In this way, since the defects are preferentially introduced into only the ultrathin silicon layer, not the grown compound semiconductor layer, a compound semiconductor layer with very few defects can be formed. Further, in the method of the conventional example 2, unlike the conventional example 1, a method such as the bonding of substrates and the selective etching, which requires a high production cost, is not used. Therefore, the compound semiconductor substrate can be manufactured at a lower cost than in Conventional Example 1.

[0015]

However, the method of Conventional Example 2 has been proposed as a method for forming a compound semiconductor on a silicon substrate. As a substrate for forming a compound semiconductor, a substrate made of the same compound semiconductor is used for the purpose of preventing generation of antiphase domains and improving wettability to facilitate two-dimensional growth, as compared with a silicon substrate. It is often better to use. Furthermore, in many compound semiconductors, GaAs, InP, and GaP are closer to the difference in lattice constant and the difference in thermal expansion coefficient than silicon, and thus are often suitable for growing a compound semiconductor.

In view of the above points, the present invention does not lattice match with the compound semiconductor on the compound semiconductor substrate.
Providing a new method for manufacturing different compound semiconductor layers,
It is an object of the present invention to provide a compound semiconductor layer substrate for producing a compound semiconductor layer which is cheaper and higher in quality than conventional methods, and a device produced on this substrate. Furthermore, it is an object of the present invention to provide a method for producing a compound semiconductor layer substrate which is lattice-matched and is capable of performing crystal growth of a compound semiconductor system that is inexpensive and has a relatively large area and does not have a suitable substrate.

[0017]

In order to achieve the above object, the compound semiconductor layer substrate of the invention according to claim 1 has a porous region and a surface portion in which the pores of this porous region are sealed. It is characterized by comprising a substrate of one compound semiconductor and a second compound semiconductor layer formed of a material different from the first compound semiconductor laminated on the substrate.

According to a second aspect of the present invention, in the compound semiconductor layer substrate according to the first aspect, the second compound semiconductor layer is made of a material different from the surface portion in which the pores of the porous region are sealed. Good.

In the invention according to claim 3, in the compound semiconductor layer substrate according to claim 1 or 2, the thickness of the surface portion is preferably thinner than the thickness of the second compound semiconductor layer.

According to a fourth aspect of the invention, in the compound semiconductor layer substrate according to the third aspect, the thickness of the surface portion is 1/5 or less of the thickness of the second compound semiconductor layer, and more preferably 10 It is good to be less than 1 /.

According to a fifth aspect of the invention, in the compound semiconductor layer substrate according to the fourth aspect, the thickness of the surface portion is 1 n.
It may be selected from the range of m to 100 nm in consideration of the layer pressure of the compound semiconductor layer.

According to a sixth aspect of the invention, the first to fifth aspects of the invention are provided.
In the compound semiconductor substrate according to any one of 1 to 3, the porous region and the surface portion may be made of a single crystal of the first compound semiconductor.

According to the invention of claim 7, claims 1 to 6
In the compound semiconductor substrate according to any one of 1 to 3, the first compound semiconductor may be any of GaAs, InP, and GaP.

A method of manufacturing a compound semiconductor layer substrate according to an eighth aspect of the present invention comprises a step of subjecting a first compound semiconductor substrate having a porous region to a heat treatment for sealing pores on a porous surface, And a step of epitaxially growing a second compound semiconductor layer on the porous region having pores sealed by heat treatment.

According to the ninth aspect of the invention, in the method for manufacturing the compound semiconductor substrate according to the eighth aspect, in order to seal the pores on the porous surface, the evaporation of the element in the compound semiconductor substrate is compensated. Therefore, heat treatment may be performed while irradiating the substrate with this element.

According to a tenth aspect of the invention, in the method of manufacturing a compound semiconductor device according to the ninth aspect, the heat treatment is
It is preferable to irradiate the substrate with an element slightly in excess of the amount of evaporation of the element.

A device produced on a compound semiconductor layer substrate according to the eleventh aspect of the present invention comprises a first compound semiconductor substrate having a porous region and a surface portion in which pores of the porous region are sealed, It is characterized in that it has a first compound semiconductor laminated on a substrate and a second compound semiconductor layer made of a material different from that of the first compound semiconductor, and that the thickness of the surface portion is thinner than the thickness of the second compound semiconductor layer. .

According to the twelfth aspect of the invention, in the device fabricated on the compound semiconductor layer substrate according to the eleventh aspect, the thickness of the surface portion is 5 times the film thickness of the second compound semiconductor layer.
It is good to be 1/10 or less, more preferably 1/10 or less.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a compound semiconductor layer substrate, a method for producing the same, and a device produced on the substrate according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIGS. 1 and 2, there is shown one embodiment of a compound semiconductor layer substrate of the present invention, a method for producing the same, and a device produced on this substrate.

FIG. 1 is a schematic sectional view showing a method for manufacturing a semiconductor substrate according to a preferred embodiment of the present invention.

In FIG. 1A, the compound semiconductor layer substrate of this embodiment is a GaAs substrate 1 having a porous region 102.
01, a porous region of a hole 103 and a wall portion 104 forming the hole 103. In order to manufacture such a substrate, an n-GaAs substrate is ultrasonically cleaned with isopropyl alcohol and methyl alcohol, and then an electrode that makes electrical contact with In is formed on the back surface of the substrate. After this, anodizing treatment is performed in HCl solution, and G
Porous regions can be formed on the surface of the aAs substrate.

Next, as shown in FIG. 1B, porous GaAs
A layer of the surface portion 105 in which this hole is sealed is formed on the surface of the layer. In order to form such a layer, the porous GaAs substrate 101 is loaded into a molecular beam epitaxy (MBE) apparatus and heated to a temperature of 600 ° C. or higher while irradiating an arsenic beam. To do. At this time, the natural oxide film formed on the GaAs surface is removed, and further, on the porous GaAs surface, migration of Ga atoms on the surface occurs to smooth the minute roughness and lower the surface energy, and the surface pores are sealed. A surface portion 105 that is stopped and has a significantly reduced hole density is formed. At this time, a small amount of Ga beam may be irradiated to further promote the sealing of the hole.

Next, as shown in FIG. 1C, a III-V group compound semiconductor layer 106 is continuously formed on the surface portion 105. At this time, the compound semiconductor layer 106 to be formed is formed sufficiently thicker than the surface portion 105.

As described above, the compound semiconductor 1
If 06 is formed, a lattice defect caused by a difference in lattice constant with GaAs and a difference in coefficient of thermal expansion is mainly introduced into the GaAs surface layer 105 formed on the fragile porous GaAs layer 102 and grown. Very little is introduced into layer 106. Therefore, the compound semiconductor single crystal layer 106 having very few defects can be obtained.

Each step adopted in the method for manufacturing a semiconductor substrate of the present invention will be described in more detail below.

[Porous Compound Semiconductor] Porous GaAs has recently been obtained by Schmuki et al. By anodizing an n-type (100) GaAs substrate in HCI (P. Schmuki et al, Journal.
of Electrochemical Society 143, p. 3316 (1996)), and Wada et al.
It has been reported that it is formed by anodizing in a 40% HF aqueous solution (1998 Spring Society of Applied Physics Proceedings 29a-PC-25). These studies are conducted mainly to see the light emission phenomenon from the similarity of porous silicon. However, the porous GaAs targeted by the present invention is essentially the same as the previously reported porous GaAs, and is not limited to the substrate position, impurities, and the manufacturing method.

On the other hand, porous InP and porous GaP are anodized in HCl by Ferreira et al. (NG Ferreira et al., Journal of Electrochemic).
alSociety, vol.142, p. 1348 (1995). ), By anodizing in a H ₂ SO ₄ by Erne etc. (BHErne eta
l., Adv. Mater.vol.7, p. 739 (1995)), respectively. Porous In targeted by the present invention
P and porous GaP are essentially the same as the previously reported porous InP and GaP, and are not limited to the plane orientation of the substrate, impurities, and the manufacturing method.

[Sealing of Holes] In order to seal the holes on the upper surface of the porous region 102 in the present invention, when a GaAs substrate is used, the substrate is heated in an arsenic atmosphere. In the present invention,
The GaAs substrate 101 on which the porous GaAs region 102 is formed is held in a molecular beam epitaxial device, and the substrate temperature is raised to 600 ° C. or higher while irradiating an As beam. At this time, migration of gallium atoms on the surface is promoted, and the effect of lowering the surface energy seals the pores on the surface of the porous region. GaAs required to seal surface holes
The thickness of the layer is extremely thin, and is approximately the same as or smaller than the diameter of the holes, specifically 100 nm or less, and more preferably 30 nm or less.

In some cases, in order to further promote the effect of sealing the hole, a small amount of gallium beam is irradiated to accelerate the crosslinking of GaAs formed on the upper part of the hole. This is to more effectively seal the holes by performing heat treatment while supplying gallium in an excessive amount.

In the present embodiment, it is desirable that the substrate temperature at this time is relatively high in order to particularly effectively migrate the gallium atoms on the surface. Further, it is more effective to promote the migration of group III atoms by using the method of migration enhanced epitaxy (MEE). This is because in the case of III-V group semiconductors such as GaAs, InP, and GaP, only group III (in some cases, a small amount of group V) is supplied in order to promote migration of group III atoms, and group III is It is a method of supplying group V atoms when it has settled down to an appropriate site.

Further, when the supply of gallium atoms is excessive, a gallium arsenide layer is further stacked on top of the sealed holes. In this case, depending on the film thickness of the compound semiconductor film formed on the upper portion, lattice defects caused by lattice mismatch or difference in coefficient of thermal expansion are also introduced into the compound semiconductor layer formed on the upper portion. In order to avoid such a situation, it is desirable that the film thickness of the surface portion 105 is sufficiently smaller than the critical film thickness of the compound semiconductor layer formed on the surface portion 105, and more specifically, it is in the range of 1 nm to 100 nm. It is recommended to select it considering the layer pressure.

Now, the lattice constant of the surface portion 105 is b, the elastic constant of biaxial deformation is K _b , the lattice constant of the semiconductor crystal formed on the upper portion of the surface portion 105 is a, and the elastic constant of biaxial deformation is K _a.
Then, depending on the balance of forces when the warp deformation of the substrate is ignored,

[0043]

[Equation 1] Becomes However, ε _a and ε _b are strains of the semiconductor crystal of a, respectively. Therefore, the elastic energy stored in this system is

[0044]

[Equation 2] Becomes Now, when the thin film substrate is not used, the elastic energy stored in the system is at the critical film thickness h _c ,

[0045]

[Equation 3] Becomes Here, the critical film thickness of the semiconductor crystal layer when a thin film substrate is used is E = Ec,

[0046]

[Equation 4] Becomes Therefore,

[0047]

[Equation 5] If the film thickness is set so that the critical film thickness disappears,
That is, the epitaxial growth layer can be stacked to have an arbitrary thickness without transition.

Now, InP is added to GaAs with the holes sealed.
When compound semiconductors such as GaP and GaP are stacked, K_a≒ K_b a≈b Therefore, h_b≤ h_cWhen epitaxy without metastasis
Local growth layers can be laminated.

That is, it is desirable to set the film thickness of the surface portion 105 to be smaller than the critical film thickness of the compound semiconductor layer formed above.

In the above description, the MBE apparatus is used to supply gallium and arsenic by a solid source. However, a chemical beam epitaxial (CBE) apparatus is used, and each source is an organic material such as trimethylgallium or arsine. A metal source may be used. Also, of course,
The MOCVD device may be used to seal the holes in the surface.

[Heteroepitaxial growth of compound semiconductor single crystal] Ga having a porous GaAs layer with pores on the surface sealed
The compound semiconductor 106 is formed on the As substrate by the MBE method, the CBE method, or the MOCVD method. As the crystal growth apparatus used here, the apparatus used for sealing the holes is used as it is,
It is desirable to continuously perform crystal growth without breaking the vacuum after sealing the holes.

The compound semiconductors to be stacked are:
III-V compounds (GaP, InP, InAs, GaN, InGaN etc.) and II-VI compounds (ZnSe, ZnS, CdTe, CdMnTe, HgTe, HgCdTe etc.) and IV-IV compounds (SiC, SiGe etc.) However, the present invention is not limited to this.

The thickness of the growing compound semiconductor is preferably 5 times or more, more preferably 10 times or more, the thickness of the surface portion 105, and more specifically, 5 nm to 5 nm.
It is desirable that the thickness is 00 nm or more.

[Production of Device] The compound semiconductor crystal substrate produced by the above method should be used as a substrate for producing a high-speed electronic device such as a light emitting element such as a light emitting diode or a semiconductor laser, a field effect transistor or the like. You can In this case, lattice defects caused by lattice mismatch or difference in coefficient of thermal expansion are hardly introduced into the growth layer. Therefore, when a light emitting diode or a semiconductor laser is formed on this substrate, the light emission efficiency of the device can be increased, and further the deterioration of the device due to lattice defects can be prevented.

When an electronic device is fabricated on this substrate, the mobility of the device can be improved, lower power consumption and high speed operation can be realized, and the device deterioration caused by lattice defects can be achieved. Can be suppressed.

EXAMPLES The present invention will be described in detail below with reference to examples.

(Example 1) n having a thickness of 450 μm
A 2-inch GaAs substrate having a (100) orientation of the mold was sequentially ultrasonically cleaned with isopropyl alcohol and methyl alcohol, and then In was attached to the back surface to make electrical contact.
Further, this substrate was subjected to anodization with an aqueous solution of HCl. At this time, the current was measured while gradually increasing the applied voltage. Finally, a current of 5 mA / cm ² was applied and anodization was performed for 10 minutes, and then the thickness of the porous layer was 10
The micron and porosity were 20%.

Next, this substrate was carried into an MBE apparatus, and while the arsenic beam was irradiated by a solid source, the temperature of the substrate was gradually raised, and finally raised to 600 ° C. and kept as it was for 20 minutes.

At this time, RHEED (Reflection High En
When observing the pattern of ergy ELectron Diffraction), it gradually changed from a halo pattern to a spot pattern and a streak pattern, and finally a 4x2 surface reconstruction was confirmed, and a layer that blocked the pores on the surface was formed. It was confirmed.

Continuing from this, the In _x Ga _1-x As layer 1
Epitaxial growth was performed to a thickness of μm. The growth conditions at this time were such that the substrate temperature was 600 ° C. and the V / III ratio was 300. The composition ratio x of In is 0.15, 0.2, 0.3, 0.
Six substrates were manufactured with the thickness changed to 4, 0.5, and 0.6.

When a cross section of this wafer was observed with a transmission electron microscope, almost no defects were introduced into the grown In _x Ga _1-x As layer, and In _x Ga _1-x having good crystallinity was observed. As
It was confirmed that a layer was formed.

[0062] The etch pit density of the wafer was measured by the defect manifestation etching, both 10 ⁴
It was confirmed to have a very low defect density of (1 / cm ² ) or less.

(Example 2) n having a thickness of 450 μm
A 2-inch GaAs substrate having a (100) orientation of the mold was sequentially ultrasonically cleaned with isopropyl alcohol and methyl alcohol, and then In was attached to the back surface to make electrical contact.
Further, this substrate was subjected to anodization with an aqueous solution of HCl. At this time, the current was measured while gradually increasing the applied voltage. Finally, a current of 5 mA / cm ² was applied and anodization was performed for 10 minutes, and then the thickness of the porous layer was 10
The micron and porosity were 20%.

Next, this mounting plate was carried into the MBE apparatus, the temperature of the substrate was gradually raised while irradiating the arsenic beam with the solid source, and finally raised to 600 ° C. and kept as it was for 20 minutes.

At this time, at the same time, RHEED (Reflection High En
When observing the pattern of `` Electron Electron Diffraction '', it gradually changed from a halo pattern to a spot pattern and a streak pattern, and finally a 4x2 surface reconstruction was confirmed, and a layer that blocked the pores on the surface was formed. It was confirmed.

Further to this, subsequently, an In _x Ga _1-x As layer was epitaxially grown to a thickness of 1 μm. The growth conditions at this time were such that the substrate temperature was 600 ° C. and the V / III ratio was 300. The composition ratio x of In is 0.15, 0.2, 0.3, and 0.
Six substrates were manufactured with the thickness changed to 4, 0.5, and 0.6.

When a cross section of this wafer was observed with a transmission electron microscope, few defects were introduced into the grown In _x Ga _1-x As layer, and In _x Ga _1-x having good crystallinity was observed. As
It was confirmed that a layer was formed.

[0068] The etch pit density of the wafer was measured by the defect manifestation etching, both 10 ⁴
It was confirmed to have a very low defect density of (1 / cm ² ) or less.

(Example 3) n having a thickness of 450 μm
A 2-inch GaAs substrate having a (100) orientation in a mold was sequentially ultrasonically cleaned with isopropyl alcohol and methyl alcohol, and then In was attached to the back surface to make electrical contact.
Further, this substrate was subjected to anodization with an aqueous solution of HCl. At this time, the current was measured while gradually increasing the applied voltage. Finally, a current of 5 mA / cm ² was applied and anodization was performed for 10 minutes, and then the thickness of the porous layer was 10
The micron and porosity were 20%.

Next, this substrate was carried into an MBE apparatus, the temperature of the substrate was gradually raised while irradiating an arsenic beam with a solid source, and finally raised to 600 ° C. and kept as such for 20 minutes.

At this time, at the same time, RHEED (Reflection High En
When observing the pattern of (ergy Electron Diffractjon), the pattern gradually changed from a halo pattern to a spot pattern and a streak pattern, and finally a 4x2 surface reconstruction was confirmed, and a layer that blocked the empty bill on the surface was formed. It was confirmed that

Continuing from this, ZnS by the MBE method
The Se layer was epitaxially grown to a thickness of 1 μm. The growth condition at this time is a substrate temperature of 500 ° C.

Cross-sectional observation of this wafer with a transmission electron microscope confirmed that defects were scarcely introduced into the grown ZnSSe layer and that a ZnSSe layer having good crystallinity was formed. .

When the etch pit density of this wafer was measured by defect revealing etching, it was 10 ⁴ (1 / cm
² ) It was confirmed that the defect density was very low as follows.

(Example 4) n having a thickness of 450 μm
A 2-inch InP substrate having a (100) orientation in a mold was sequentially ultrasonically cleaned with isopropyl alcohol and medel alcohol, and then In was attached to the back surface to make electrical contact.
Further, this substrate was subjected to anodization with an aqueous solution of HCl. At this time, the current was measured while gradually increasing the applied voltage. Finally, a current of 5 mA / cm ² was applied and anodization was performed for 10 minutes, and then the thickness of the porous layer was 10
The micron and porosity were 20%.

Next, this substrate was loaded into a CBE apparatus and PH ₃
While irradiating the gas source, the temperature of the substrate was gradually raised, and finally raised to 600 ° C. and kept as it was for 20 minutes.

At this time, at the same time, RHEED (Reflection High En
When observing the pattern of `` Electron Electron Diffraction '', it gradually changed from a halo pattern to a spot pattern and a streak pattern, and finally a 4x2 surface reconstruction was confirmed, and a layer that blocked the pores on the surface was formed. It was confirmed.

Further to this, subsequently, by the CBE method, I
An n _0.8 Ga _0.2 As layer was epitaxially grown to a thickness of 1 μm. The growth condition at this time is a substrate temperature of 500 ° C.

When the cross section of this wafer was observed with a transmission electron microscope, almost no defects were introduced into the grown In _0.8 Ga _0.2 As layer, and In _0.8 Ga having good crystallinity was obtained.
It was confirmed that a _0.2 As layer was formed.

The etch pit density of this wafer was measured by defect revealing etching, and it was 10 ⁴ (1 / c
It was confirmed that the defect density was very low at m ² ) or less.

(Embodiment 5) 450-μm thick p-type 2-inch GaAs substrate 301 having (111) orientation is sequentially ultrasonically cleaned with isopropyl alcohol and methyl alcohol, and then In is applied to the back surface. They made electrical contact. Further, this substrate was subjected to anodization with an aqueous HF solution. At this time, the current was measured while gradually increasing the applied voltage. Finally, a current of 5 mA / cm ² was applied and anodization was performed for 10 minutes, and then the thickness of the porous layer was 10
The micron and porosity were 20%.

Next, this substrate was carried into an MBE apparatus, the temperature of the substrate was gradually raised while irradiating an arsenic beam with a solid source, and finally raised to 600 ° C. and kept as it was for 20 minutes.

At this time, RHEED (Reflection High En
Observation of the pattern of ergy ELectron Diffaction) confirmed that a halo pattern was gradually changed to a spot pattern and a streak pattern, and a layer blocking the surface pores was formed. And after this,
The GaN layer was epitaxially grown to a thickness of 1 μm by the MBE method.

At this time, the Ga beam was supplied by a solid source, and the N beam was supplied by cracking nitrogen gas with an RF plasma cell. The nitrogen gas is 3
The film was formed at a sccm of 400 W, an electric power of 400 W, and a substrate temperature of 800 ° C.

Cross-sectional observation of this wafer with a transmission electron microscope confirmed that defects were scarcely introduced into the grown GaN layer and that a GaN layer having good crystallinity was formed. .

The dislocation density of this wafer was measured by a transmission electron microscope, and it was confirmed that it had a very low defect density of 10 ⁶ (1 / cm ² ) or less.

Subsequently, the p-GaN layer 304 and p-Al _0.15 G were formed on the substrate not subjected to the above-mentioned measurement by the MOCVD method.
a _0.85 N layer 305, In _0.05 Ga _0.95 N layer 306, n-Al _0.15 Ga
_{The 0.85} N layer 307 and the n-GaN layer 308 were sequentially stacked. For the p type, Mg was used as a dopant, and for the n type, silicon was used as a dopant.

Next, a Ti / Al electrode 30 is formed on the upper portion of this wafer.
9 was vapor-deposited with an Al electrode 310 on the bottom thereof and heat-treated to make ohmic contact with each other, to fabricate a light emitting diode as shown in FIG. When the light emitting characteristics of this light emitting diode were examined, a high light emitting efficiency with an external quantum efficiency of about 10% was confirmed.

(Example 6) n having a thickness of 450 μm
A 2-inch GaAs substrate 401 having a (100) orientation in a mold is sequentially coated with isopropyl alcohol and medel alcohol,
After ultrasonic cleaning, In was attached to the back surface to make electrical contact. Further, this substrate was subjected to anodization with an aqueous HF solution. At this time, the current was measured while gradually increasing the applied voltage. The thickness of the porous layer 402 after finally anodizing by applying a current of 5 mA / cm ² for 10 minutes was 10 μm and the porosity was 20%.

Next, this substrate was carried into an MBE apparatus, the temperature of the substrate was gradually raised while irradiating the arsenic beam with a solid source, and finally raised to 600 ° C. and kept for 20 minutes.

At this time, RHEED (Reflection High En
When observing the pattern of ergy ELecton Diffraction), it gradually changed from a halo pattern to a spot pattern and streak pattern, and finally a 4x2 surface reconstruction was confirmed, forming a layer 403 that occludes empty bills on the surface. It was confirmed that it was done. Further to this, subsequently, the GaN layer 404 was epitaxially grown to a thickness of 1 μm by the MBE method.

At this time, the Ga beam was supplied by a solid source, and the N beam was supplied by cracking nitrogen gas with an RF plasma cell. The nitrogen gas is 3
The film was formed at a sccm of 400 W, an electric power of 400 W, and a substrate temperature of 800 ° C.

Cross-sectional observation of this wafer with a transmission electron microscope confirmed that defects were scarcely introduced into the grown GaN layer and that a GaN layer having good crystallinity was formed. .

The dislocation density of this wafer was measured by a transmission electron microscope, and it was confirmed that it had a very low defect density of 10 ⁶ (1 / cm ² ) or less.

Continuing further, with the same MBE device, In _0.05 Ga
_0.95 N layer 405, n-Al _0.15 Ga _0.85 N layer 406, GaN layer 40
7 were sequentially laminated, a source electrode and a drain electrode portion were patterned, and then a Ti / Au electrode was vapor-deposited. After forming the electrode portion by a lift-off method, heat treatment was performed to form a source electrode 408 and a drain electrode 409. Further, after that, a gate electrode 410 was formed by a lift-off method to manufacture a GaN-based high electron mobility transistor shown in FIG.

When the transconductance of this transistor was measured, it showed a transconductance equivalent to that of a transistor manufactured with the same structure on a sapphire substrate.

[0097]

As is apparent from the above description, the compound semiconductor layer substrate of the present invention has a surface portion in which the pores of the porous region are sealed in the substrate of the first compound semiconductor, and And a second compound semiconductor layer made of a material different from the first compound semiconductor laminated on the first compound semiconductor layer. Therefore, it is possible to prevent dislocations that occur due to the difference in lattice constant and the difference in coefficient of thermal expansion, and to manufacture a good quality and inexpensive compound semiconductor substrate. Further, it is possible to obtain a high quality crystal of another compound semiconductor which is not lattice-matched with this substrate. Furthermore, by using this substrate, an inexpensive compound semiconductor device having excellent characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a manufacturing process showing an embodiment of a compound semiconductor layer substrate and a manufacturing method thereof according to the present invention.

FIG. 2 is a schematic configuration diagram showing a conventional manufacturing process of a compound semiconductor.

FIG. 3 is a schematic configuration diagram showing a fifth embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing a sixth embodiment of the present invention.

[Explanation of symbols]

101 (first) compound semiconductor substrate, 102 porous compound semiconductor, 103 pores in the porous region, 104 wall of porous region, 105 a surface layer with pores sealed in the porous region, 106 (second) compound semiconductor.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F041 AA03 CA34 CA40 CA46 CA65                       CA66 CA77                 5F045 AA05 AB14 AB17 AB22 AF04                       BB08 BB12 BB16 DA52 DA67                       DA69 DA70                 5F052 JA07 JA10 KA01

Claims (12)

[Claims] 1. A substrate of a first compound semiconductor having a porous region and a surface portion in which pores of the porous region are sealed, and a material different from the first compound semiconductor laminated on the substrate. A second compound semiconductor layer, and a compound semiconductor layer substrate. 2. The compound semiconductor layer substrate according to claim 1, wherein the second compound semiconductor layer is made of a material different from the surface portion in which the pores of the porous region are sealed. Compound semiconductor substrate. 3. The compound semiconductor layer substrate according to claim 1, wherein the thickness of the surface portion is smaller than the thickness of the second compound semiconductor layer. 4. The compound semiconductor layer substrate according to claim 3, wherein the thickness of the surface portion is 1/5 or less, more preferably 1/10 or less of the film thickness of the second compound semiconductor layer. And a compound semiconductor substrate. 5. The compound semiconductor layer substrate according to claim 4, wherein the thickness of the surface portion is selected from the range of 1 nm to 100 nm in consideration of the layer pressure of the compound semiconductor layer. . 6. The compound semiconductor substrate according to claim 1, wherein the porous region and the surface portion are made of a single crystal of the first compound semiconductor. . 7. The compound semiconductor substrate according to claim 1, wherein the first compound semiconductor is GaA.
A compound semiconductor substrate, which is one of s, InP, and GaP. 8. A step of subjecting a substrate of a first compound semiconductor having a porous region to a heat treatment to seal the pores on the surface of the porous surface, and a porous material having the pores sealed by the heat treatment. And a step of epitaxially growing a second compound semiconductor layer on the region, a method of manufacturing a compound semiconductor substrate, comprising: 9. The method of manufacturing a compound semiconductor substrate according to claim 8, wherein the element in the compound semiconductor substrate is evaporated in order to seal the pores on the porous surface. A method of manufacturing a semiconductor substrate, characterized in that heat treatment is performed while irradiating the substrate with. 10. The method for producing a compound semiconductor device according to claim 9, wherein the heat treatment is performed while irradiating the substrate with an element slightly in excess of the amount of evaporation of the element. Manufacturing method. 11. A substrate of a first compound semiconductor having a porous region and a surface portion in which pores of the porous region are sealed, and a material different from the first compound semiconductor laminated on the substrate. And a second compound semiconductor layer, wherein the thickness of the surface portion is smaller than the thickness of the second compound semiconductor layer. A device manufactured on a compound semiconductor layer substrate. 12. The device manufactured on the compound semiconductor layer substrate according to claim 11, wherein the thickness of the surface portion is 1/5 or less of the film thickness of the second compound semiconductor layer,
More preferably, it is 1/10 or less, and a device manufactured on a compound semiconductor substrate.