JP2003067442A - Verification device for asynchronous circuit timing and method for verification of timing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for verifying timing of asynchronous circuit when a synchronous circuit and an asynchronous circuit are intermingled in a semiconductor integrated circuit. SOLUTION: When verifying timing of an asynchronous circuit, the present invention reads RTL description from a circuit inputting part 1 in the timing verifying device 14, extracts instances to which restriction is added at a circuit analyzing part 2 and makes the timing restriction and the path restriction described in the instances extracted at the circuit analyzing part 2 into commands at a path and restriction extracting part 3. The timing verifying device reads a clock restriction at a clock condition inputting part 4 and performs timing verification at a restriction information creating part 5 according to the restriction commands and clock restriction information created at the path and restriction extracting part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous circuit timing verification device and a timing verification method thereof, and more particularly to an asynchronous circuit timing verification device and a timing verification method thereof when a synchronous circuit and an asynchronous circuit are mixed.

[0002]

2. Description of the Related Art When a synchronous circuit and an asynchronous circuit of a semiconductor integrated circuit coexist, there is a dynamic simulation for simulating the timing of the asynchronous circuit by using an actual delay value.

Also, due to the recent increase in the scale of integration, the simulation time has become enormous.

Therefore, it is well known that the asynchronous circuit is also shifting to the static timing verification in order to reduce the number of design steps.

Such a conventional simulation technique is disclosed, for example, in Japanese Unexamined Patent Publication No. 10-198723 (referred to as cited document 1). The processing flow of this conventional simulation technique is shown in FIG.

Referring to FIG. 9, in the conventional simulation technique described in the cited document 1, in the method of verifying the timing of a circuit in which a synchronous circuit and an asynchronous circuit are mixed (step S17), first, the synchronous circuit is To process. That is, based on the circuit connection information (15) and the timing designation and clock designation information (16), static timing verification of the synchronous circuit portion (step S19) is executed, and if OK, timing verification of the asynchronous circuit portion ( Step S20) is executed.

In the timing verification of the asynchronous circuit part (step S20), if the extracted path delay data is available in the static timing verification phase of the synchronous circuit part, this is used to Designation
By inputting the route relationship designation as the constraint file (18), the route delay of the route is specified from the delay data extracted for each route with respect to the route designated for the asynchronous circuit part described above. It is to verify whether or not it is satisfied.

[0008]

However, this conventional technique has two major problems.

First, in order to perform static verification in an asynchronous circuit, the circuit is not clock-synchronized, so the delay value between registers must be specified for each path.

The constraint file specifies the route and the delay value. At present, the timing verification device takes time because it is necessary to create a constraint file for each device because the route and the delay value are formatted differently for each manufacturer.

Secondly, the work is separated due to the increase in the circuit scale, and the RTL designer and the timing verifier may be different. In this case, the RTL designer creates the constraint file, but it may be erroneous because a human needs to search and specify the instance name of the register from the RTL when the route is specified.

Since the verifier works with the constraint file containing such a mistake, it is necessary to debug the constraint file before the timing verification. The contents of the constraint file are
Since only the RTL designer knows, every time an error occurs, it is necessary to confirm with the designer that the correct instance name is corrected, which increases the work time.

Therefore, it is an object of the present invention to provide a timing verification device for an asynchronous circuit and a timing verification method for the case where a synchronous circuit and an asynchronous circuit are mixed, which solves the above problem.

[0014]

A timing verification device for an asynchronous circuit according to the present invention is a circuit for reading an RTL in which timing constraint information and route / constraint information are added as parameters to an instance name based on a predetermined naming rule. Circuit analysis for extracting a register group to which timing constraint information and a route constraint are added based on the timing constraint name and the route designation name in the constraint information table from the description contents of the RTL read by the input unit and the circuit input unit Section and the register group, the constraint and path described from the constraint instance extracted by the circuit analysis section are stored in the storage section.
A constraint / route information extraction unit for comparing the constraint and route added in the instance into a command and storing them in the constraint / route information storage unit; a clock condition input unit 4 for inputting a clock condition file; A constraint information generation unit for reading a clock constraint from a clock condition input unit; a timing verification unit for performing timing verification for performing timing verification based on the constraint command and clock constraint information created by the constraint / path information extraction unit; And a storage unit that stores information necessary for the timing verification.

Furthermore, the timing verification method of the present invention is
A timing verification method applied to a timing verification device for an asynchronous circuit, wherein when performing timing verification for an asynchronous circuit, RT is input from a circuit input unit in the timing verification device.
The first step of reading the L description, the second step of extracting the instance to which the constraint is added by the circuit analysis unit, and the command of the timing constraint and the route constraint described in the instance extracted by the circuit analysis unit 3rd to turn
And a fourth step of reading the clock condition from the clock constraint file, and the circuit analysis unit uses the read content of the RTL to read the timing constraint name and the routing name in the constraint information table based on the timing constraint name. A fifth step of extracting the register group to which the information and the route constraint are added and supplying the register group to the route / constraint extracting unit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail below with reference to the drawings. The features of the present invention will be described with reference to FIG.

First, the feature of the present invention is that, when performing timing verification of an asynchronous circuit, the RTL description is read from the circuit input unit 1 in the timing verification device 14, and the circuit analysis unit 2 extracts an instance to which a constraint is added. The route / constraint extraction unit 3 converts the timing constraint and the route constraint described in the instance extracted by the circuit analysis unit 2 into commands.

Further, the clock constraint is read from the clock condition input unit 4, and the constraint information generation unit 5 performs timing verification based on the constraint command and the clock constraint information created by the constraint / path information extraction unit 3. A timing verification method and device.

Here, RTL is an abbreviation for register transfer level and represents a description level expressing a register, a counter, etc., including a clock concept which is a structural element of a circuit, and in the present invention, RTL ( register·
The instance name in the (transfer level) has timing constraint information and routing information added as parameters in advance.

The instance means an individual name added to the called module described in the RTL description.

Next, a first embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 1, a data processing device 13 in a timing verification device 14 for an asynchronous circuit according to a first embodiment of the present invention includes a circuit input section 1 for reading an RTL and an RT.
A circuit analysis unit 2 for extracting an instance name from L,
A route constraint extraction unit 3 that extracts a route / constraint from an instance name and turns it into a command, a clock condition input unit 4 that inputs a clock constraint, and a constraint information generation that matches a clock constraint when extracted from the route / constraint extraction unit 3 as a command Part 5 and
It has a timing verification unit 6 for performing timing verification, and a storage unit 12 for storing information necessary for timing verification.

The storage unit 12 stores the constraint / route information table 7
And a constraint / path information storage unit 8, a clock condition table 9, a clock information storage unit 10, and a timing verification creation command 11.

MULTn, FALSE, Max_del
The constraint information table 7 in which constraints such as ay are written is RT
Includes a list of timing constraint names that extract instance names from L.

Similarly, the clock condition table 9 includes a constraint / path storage unit 8 that includes designations regarding clock waveforms.
Stores the command created by the circuit analysis unit 3, the clock information storage unit 10 stores the clock constraints input from the clock condition input unit 4, and the timing verification creation command storage unit 11 creates the constraint information. The command created by the unit 5 is stored.

Next, the operation of the timing verification device 14 for the asynchronous circuit according to the first embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 2, the circuit input unit 1 of the timing verification apparatus for an asynchronous circuit according to the first embodiment of the present invention.
Reads the RTL in which the timing constraint information and the route / constraint information are added as parameters to the instance name based on a predetermined naming rule, and supplies the RTL to the circuit analysis unit 2. (Steps S1 to S3 in FIG. 2).

Based on the timing constraint name and the route designation name in the constraint information table 7 from the read RTL description contents, the circuit analysis unit 2 adds the timing constraint information and the route constraint to the register (flip-flop, (Elements such as latches) are extracted and the registers are supplied to the route / constraint extraction unit 3 (step S5).

The clock condition file input from the clock condition input unit 4 is input (step S4), and the path
The constraint extraction unit 3 compares the constraints and routes described by the constraint instance extracted by the circuit analysis unit 2 with the constraint / route information table 7 in the storage unit 12, and commands the constraints and routes added in the instance. It is stored in the constraint / route information storage unit 8 (step S6).

The commanded clock condition file or clock constraint information input in step S4 is
In comparison with the clock condition table 9 stored in the storage unit 12,
The clock constraint given from the clock condition input unit 4 is converted into a command, and the information is stored in the clock information storage unit 10 (step S7).

A method and apparatus for extracting a constraint from an instance, outputting a commandized file, storing it in the timing verification creation command description section 11, reading it as a timing verification command in the timing verification phase, and performing timing verification. .

Next, the operation of the present invention will be described in more detail with reference to actual examples. Regarding a circuit in which a part of the verification target has the maximum delay constraint, the flip-flop FF0 to the flip-flop FF have the register configuration of the RTL diagram shown in FIG.
The maximum delay value limit is 1 to 10 ns, the maximum delay value limit is 15 ns from flip-flop FF0 to flip-flop FF2, and the maximum delay value limit is 20 n from flip-flop FFx to flip-flop FF1.
If s, the timing verification command is set (see FIG. 4).

In the prior art, the constraint file had to create each constraint command one by one according to the format required by each timing verification and verification device.

When performing the timing verification in the form of FIG. 1 in the embodiment of the present invention, a parameter added with a constraint condition is added to the RTL (register transfer level).

The parameter to which the constraint condition is added indicates a parameter in which the verification path / constraint condition is added in advance to the instance name of the register described in the RTL.

The parameter to which the verification route / constraint is added in advance will be described with reference to the example of the maximum delay described below. Information such as “condition: maximum delay” and “constrained route: FF0 to FF1” is used as an instance. It is to add.

An example of naming an instance name is to add and set an example of “unique name” _ “constraint name” _ “path designation” based on the following naming rule. << Example of parameter naming rule name >><Uniquename>: Unique name for selecting elements <Constraint name>: MULTn (n is the number of cycles): Multi-cycle
Path: FALSE: False path: Max_delayyn (n is a delay value): Maximum delay <Path designation>: FR "Target instance name" Path from the target instance name to the cell named with this naming rule: _TO "Target Instance name "Path from cell with this naming instance name to target instance name: _FROM" Target instance name "All paths to cell with instance name according to this naming rule: _TOALL" Target instance name "This naming rule All paths from the cell with the instance name added from the above rule, "Maximum delay 1 from FF0 to FF1
When specifying an instance of "0 ns", the instance name is unique name: FF0, constraint name: Max_del.
ayn (delay value is set to 10 ns and n = 10), path (route): FF1 (from current FF0 to FF1), instance name is FF0_Max_delay1
0_TOFF1 ”.

This RTL having the above constraint parameters
Is shown in FIG.

The RTL shown in FIG. 5 is used as the circuit input unit 1 of FIG.
Further, the circuit / analysis unit 2 extracts the register using the route / constraint condition parameter described in the RTL, and the route / constraint extraction unit 3 extracts the route / constraint from the route / constraint condition parameter to determine the constraint / route. Store in the information storage unit.

Further, the clock condition input section 4 is made to read a command in which clock constraints are described.

The clock constraint specifies the names of clock pins and clock cycle names of rising and falling clock pins.

The specification format is "set clockpin clock pin name rise Rise_Min Rise_Max FALL_Min FALL_Maxperiod
Clock cycle value ".

In the constraint information generation unit 5, the constraint / route extraction unit 3 creates the constraint route information storage unit 8 shown in FIG.
The command F2 described in 1 and the command stored in the clock information storage unit 10, that is, the clock designation and the route / path relation command F3 are output as a single command file F4 by pattern conversion (command shown in FIG. 6). Will be). This process is shown in FIG.

As described above, for the purpose of performing timing verification, the circuit designer creates a register or the like by assigning an instance name based on a naming rule in advance from the RTL (register transfer level) creation stage, and then performs the timing verification. Is to extract the instance name from the RTL and automatically create and verify the constraint file according to the naming rule. Therefore, the constraint condition and the routed constraint file required in the timing verification processing flow in the related art shown in FIG. 18 is not needed.

Next, a second embodiment of the present invention will be described.

In the verification method of the timing verification device for an asynchronous circuit according to the first embodiment of the present invention, the case where the RTL designer and the timing verifier are the same has been described, but in the second embodiment of the present invention. , RTL designer and timing verifier will be described with reference to FIG.

Referring to FIG. 8, in the verification method of the timing verification device for an asynchronous circuit according to the second embodiment of the present invention, the first embodiment of the present invention is performed from the addition of the RTL constraint to the timing verification command generation. Since it is the same as the verification method of the timing verification device for an asynchronous circuit of this form, description thereof will be omitted.

The command created by the constraint information generating unit 5 shown in FIG. 1 can be used as a timing verification command for the timing verification apparatus. Therefore, the timing apparatus can use this command as a medium or network. Above, the timing can be verified by passing it over.

In the description of the operation of the verification method of the timing verification device for an asynchronous circuit according to the first embodiment of the present invention, the maximum delay has been shown as an example, but by changing the constraint, multi
It can also be applied to cycle passes and false passes.

Next, a third embodiment of the present invention will be described.

In the verification method of the timing verification device for an asynchronous circuit according to the first embodiment of the present invention, the example of a single element is used. However, the timing verification of the asynchronous circuit according to the third embodiment of the present invention is performed. In the method of verifying the device, it is possible to measure paths between multiple elements by increasing the constraint parameters.

In the verification method of the timing verification device for an asynchronous circuit according to the third embodiment of the present invention, in FIG. 5, when the maximum delay from flip-flop FF0 to flip-flop FF1 is 10 ns, the constraint parameter is "FF0_Ma".
x_delay10_TOFF1 ", but flip-flops FF0 to FF between multiple elements
1. When designating a route to the flip-flop FF2, the constraint parameter is “FF0_Max_delay10_TO
Verification can be performed by setting "FF1_FF2".

[0053]

As described above, the first effect of the present invention is that the time for creating the constraint file used during the timing verification is reduced.

That is, conventionally, in order to perform static verification in an asynchronous circuit, the circuit is not clock-synchronized, so that a delay value between registers must be specified for each path.

Further, conventionally, since the timing verification device has different formats of the route and the delay value for each manufacturer, it is necessary to set all the constraints to be verified by the command for each device, and the time for creating the constraint file is required. It was hanging.

However, in the present invention, the circuit designer uses the RTL.
Since the timing constraint information and the routing information are added as parameters to the instance name of (register transfer level), it becomes possible to extract the added parameters and create constraint information from the pattern conversion when the timing device performs verification. There is no need to create a constraint file, which saves time in creating a constraint file.

The second effect is that the verification time can be reduced due to a mistake in the constraint command or a miss path. The reason is that in the conventional timing verification, if the RTL designer and the timing verifier are different, the RTL designer creates a constraint file to reflect the RTL designer's intention as it is. Since it is necessary for a person to search and specify from the RTL, there is a case where the user makes a mistake.

Since the verifier performs the work with the constraint file including such a mistake, the constraint file needs to be debugged before the timing verification, and the content of the constraint file is RT.
Since only the L designer can understand, errors such as incorrect element designations, incorrect element names, and mis-paths with the constraint command
The work required to confirm with the designer every time the instance name was corrected was increased, increasing the work time.

However, in the present invention, the circuit designer adds the timing constraint information and the routing information to the instance to be verified beforehand in the circuit to be verified. This means that the constraint conditions are added as they are.Therefore, between the circuit designer and the timing verifier, which had been happening in the past, errors such as incorrect designation of elements, incorrect element names, mispasses, etc. Since the work of confirming the above is eliminated, the verification time can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a timing verification system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow of timing verification in the first embodiment of the present invention.

FIG. 3 is an example at maximum delay.

FIG. 4 is an example of a constraint file.

FIG. 5 is a description example of RTL.

FIG. 6 is an example of a timing verification creation command.

FIG. 7 is a command process diagram.

FIG. 8 is a diagram showing a processing flow of timing verification when the RTL designer and the timing verifier are different in the second embodiment of the present invention.

FIG. 9 is a diagram showing a processing flow of timing verification of a conventional technique.

[Explanation of symbols]

1 Circuit Input Unit 2 Circuit Analysis Unit 3 Path / Constraint Extraction Example 4 Clock Condition Input Input Unit 5 Constraint Information Creation Unit 6 Timing Verification Unit 7 Constraint / Route Information Table 8 Constraint / Route Information Storage Unit 9 Clock Condition Table 10 Clock Information Storage Part 11 Timing verification creation command storage part 12 Storage part 13 Data processing device 14 Verification device 15 Circuit connection information to be verified 16 Input / output signal timing designation and clock designation information 18 Relationship between route designation and route measurement by asynchronous circuit Information F1 RTL example F2 Constraint / route command example F3 Clock command example F4 Creation command example S1 RTL creation step S2 RTL constraint addition step S3 RTL reading step S4 Clock condition reading step S5 Constraint instance name extraction step S6 Instance name Ri constraint path extracting step S7 a clock constraint extraction step S8 timing functions for command generation step S17 static timing verification phase static timing verification phase S20 asynchronous circuit of a conventional static timing verification method S19 synchronizing circuit of the

Claims (15)

[Claims] 1. A register transfer, in which timing constraint information and route / constraint information are added as parameters to an instance name based on a predetermined naming rule.
A circuit input unit that reads a level (hereinafter, abbreviated as RTL), and timing constraint information and a routing name based on the timing constraint name and the routing name in the constraint information table based on the description content of the RTL read by the circuit input unit. A circuit analysis unit that extracts a register group to which a route constraint is added; a constraint / route information table that stores the constraint and route described by the constraint instance extracted by the circuit analysis unit in the storage unit; The constraint / route information extraction unit that compares the constraints and routes added to the instance into commands and stores them in the constraint / route information storage unit, the clock condition input unit that inputs the clock condition file, and the clock condition input unit A constraint information generation unit for reading clock constraints, and a constraint command and clock constraint information created by the constraint / path information extraction unit. And timing verification unit which performs timing verification to perform timing verification on the basis of the timing verification apparatus of the asynchronous circuit characterized in that it comprises a storage unit for storing information necessary for the timing verification. 2. The timing verification device for an asynchronous circuit according to claim 1, wherein the register group is composed of flip-flops. 3. The timing verification device for an asynchronous circuit according to claim 1, wherein the register group is composed of a latch. 4. The storage unit includes a constraint / route information table, a constraint / route information storage unit, a clock condition table, a clock information storage unit, and a timing verification creation command. 3. A timing verification device for an asynchronous circuit according to 3. 5. The timing verification device for an asynchronous circuit according to claim 4, wherein the constraint information table includes a list of timing constraint names for extracting an instance name from the RTL in which the constraints are written. 6. The constraint is MULTn.
A timing verification device for the asynchronous circuit described. 7. The constraint is FALSE.
A timing verification device for the asynchronous circuit described. 8. The timing verification device for an asynchronous circuit according to claim 5, wherein the constraint is Max_delay. 9. The constraint / route storage unit stores the command created by the circuit analysis unit.
Alternatively, the timing verification device for an asynchronous circuit according to item 8. 10. The clock condition table includes designations regarding a waveform of an input clock.
Alternatively, the timing verification device for an asynchronous circuit according to Item 9. 11. The timing verification device for an asynchronous circuit according to claim 5, wherein the clock information storage unit stores the clock constraint input from the clock condition input unit. 12. The timing verification of an asynchronous circuit according to claim 5, wherein the timing verification creation command storage unit stores a command created by the constraint information generation unit. apparatus. 13. The timing verification method applied to the timing verification device for an asynchronous circuit according to claim 1, wherein when performing timing verification for the asynchronous circuit, an RTL description is read from a circuit input unit in the timing verification device. First
And a second step of extracting an instance to which a constraint is added by the circuit analysis unit, and a third step of converting the timing constraint and the route constraint described in the instance extracted by the circuit analysis unit into a command. And read the clock conditions from the clock constraint file 4th
And the circuit analysis unit extracts the register group to which the timing constraint information and the route constraint are added based on the timing constraint name and the route designation name in the constraint information table from the description content of the read RTL. A fifth step of supplying the register group to the path / constraint extraction unit. 14. The command-converted clock condition file or clock constraint information input in the fourth step is compared with a clock condition table in the storage unit to compare the clock constraint given from the clock condition input unit. 14. The timing verification method according to claim 13, further comprising a seventh step of converting into a command and storing the information in the clock information storage unit. 15. The eighth step of extracting a constraint from an instance, outputting a commandized file, storing the file in a timing verification creation command description section, and reading it as a timing verification command in a timing verification phase. Timing verification method described.