JP2003066903A - Display panel drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce variation of current which occurs at a current mirror, and to eliminate variation in reference current between a plurality of IC chips. SOLUTION: Switching circuits SW1 and SW2 are switched over for time- division control. Thus, the variation quantity between a current source Iorg which realizes original current of current mirror and currents Iref1 and Iref2 decreases, while the current Iref1 and the current Iref2 supplied to a plurality of IC chips are equal to each other. By switching over the relationship between a plurality of IC chips and a plurality of drive current sources at a prescribed cycle, the current variation occurring at the current mirror is reduced. Since the variation in reference current between a plurality of IC chips is eliminated, a regular emission luminosity is provided on a display panel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel drive circuit, and more particularly to a drive circuit for a display device using a display panel composed of a self-luminous element such as an organic electroluminescence element.

[0002]

2. Description of the Related Art An organic electroluminescence (hereinafter referred to as EL) element is known as a self-luminous element for realizing a thin and low power consumption display device. FIG. 5 is a diagram showing a schematic configuration of such an EL element. As shown in the figure, the EL element has a transparent substrate 100 made of a glass plate or the like on which a transparent electrode 101 is formed.
At least one organic functional layer 102 including an electron transport layer, a light emitting layer, a hole transport layer, and the like, and a metal electrode 103 are laminated on top.

FIG. 6 is an equivalent circuit that electrically shows the characteristics of such an EL element. As shown in the figure, the EL element can be replaced by a capacitance component C and a diode characteristic component E coupled in parallel with the capacitance component.
Here, the positive electrode of the transparent electrode 101, the metal electrode 10
When a negative voltage is applied to the cathode of No. 3 and a direct current is applied between the transparent electrode and the metal electrode, electric charge is accumulated in the capacitance component C. At this time, when the barrier voltage or the emission threshold voltage peculiar to the EL element is exceeded, a current starts to flow from the electrode (the anode side of the diode component E) to the organic functional layer serving as the light emitting layer, and the organic functional layer has an intensity proportional to the current. The layer 102 emits light.

FIG. 7 is a diagram showing a schematic configuration of an EL display device for displaying an image using an EL display panel in which a plurality of EL elements are arranged in a matrix. In FIG. 1, an ELDP 10 serving as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n that carry the first display line to the nth display line, and an array that intersects with the cathode lines B _{1 to} B _n. is the m anode lines (transparent electrodes) a ₁ to a _m are formed. These cathode lines B ₁ ~
EL elements E _{11 to} E _nm having the above-described structure are formed at the respective intersections of B _n and the anode lines A 1 to Am. Incidentally, these EL elements E ₁₁ to E _nm each, ELDP1
It is responsible for one pixel as 0.

The light-emission control circuit 1 outputs the input image data for one screen (n rows, m columns) to a pixel data group D corresponding to each pixel of the ELDP 10, that is, each of the EL elements E _{11 to} E _{nm. It} is converted into _{11 to} D _nm , and these are sequentially supplied to the anode line drive circuit 2 for each row as shown in FIG. For example, the pixel data D _{11 to} D _nm is E
EL elements E _{11 to} E belonging to the first display line of the LDP 10
There are m data bits that specify whether or not to perform light emission for each _{nm. When} the logic level is "1", "light emission" is performed, and when the logic level is "0", "non-light emission" is performed. "Emission".

Further, the emission control circuit 1 sequentially scans each of the first display line to the nth display line of the ELDP 10 in synchronization with the pixel data supply timing for each row as shown in FIG. The scanning line selection control signal to be supplied is supplied to the cathode line scanning circuit 3. First, the anode line drive circuit 2
From the m data bits in the pixel data group, all the data bits at the logic level "1" designating "light emission" are extracted. Next, the anode line belonging to "columns" corresponding to the data bits each and the extracted selected all from among the anode lines A ₁ to A _m, connects the constant current source only to the selected anode line, predetermined The pixel drive current i is supplied.

The cathode ray scanning circuit 3 includes the cathode rays B _{1 to} B _n.
Of the above, the cathode line corresponding to the display line indicated by the scanning line selection control signal is selectively selected to set this cathode line to the ground potential, and a predetermined high potential Vcc is applied to each of the other cathode lines. Apply. The high potential V
cc is set to be approximately the same value as the voltage across the EL element (voltage determined based on the amount of charge in the parasitic capacitance C) when the EL element is emitting light with a desired luminance.

At this time, a light emission drive current is provided between the "column" to which the constant current source is connected by the anode line drive circuit 2 and the display line set to the ground potential by the cathode line scanning circuit 3. The EL elements formed by flowing and crossing the display lines and the "columns" emit light according to the light emission drive current. On the other hand, since no current flows between the display line set to the high potential Vcc by the cathode line scanning circuit 3 and the "column" to which the constant current source is connected, the display line and the "column" are crossed. The EL element thus formed remains non-luminous.

[0009] The above described operation is pixel data groups D ₁₁ ~
_{D 1m, D 21 ~D 2m,} ..., D n1 when to D _{n m} is performed on the basis of each, on the screen of ELDP10, 1 field of emission pattern corresponding to the input image data, i.e. image Is displayed.

[0010]

Here, in recent years, in order to increase the screen size of a display panel, the number of display lines, that is, the number of the cathode lines B is increased, and the number of the anode lines A is increased to increase the screen size. The need for higher definition has arisen. Therefore, as the number of each of the anode lines A and the cathode lines B increases, the circuit scale of each of the anode line drive circuit 2 and the cathode line scanning circuit 3 also increases. Therefore, when both are integrated into an IC, the yield accompanying the increase in chip area increases. There is concern about deterioration. Therefore, it has been considered to construct each of the anode line drive circuit 2 and the cathode line scanning circuit 3 with a plurality of IC chips.

However, when the anode line drive circuit 2 is constructed by a plurality of IC chips, due to manufacturing variations and the like,
The amount of light emission drive current to be supplied to the anode line may differ between the IC chips. Therefore, there is a problem that regions having different brightness are formed on the screen of the ELDP 10 due to the difference in the light emission drive current. A technique for solving this is disclosed in Japanese Patent Laid-Open No. 2001-42.
No. 827.

FIG. 9 is a diagram showing a schematic configuration of the EL display device described in the publication. In FIG. 1, an ELDP 10 ′ as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n that carry the first display line to the nth display line and the cathode lines B _{1 to} B _n, respectively. Arranged 2m anode wires (transparent electrodes) A ₁ ~
A _2m is formed. EL elements E _{1,1 to} En _{, 2m} having a structure as shown in FIG. 5 are formed at the intersections of the cathode lines B _{1 to} B _n and the anode lines A _{1 to} A _2m . Each of the EL elements E _{1,1 to} En _{, 2m} is an ELD.
It is responsible for one pixel as P10 '.

The light emission control circuit 1'is, as shown in FIG. 10, the first display line to the nth display line of the ELDP 10 '.
A scanning line selection control signal for sequentially scanning each display line is supplied to the cathode line scanning circuit 30. Cathode ray scanning circuit 30
Means to selectively select a cathode line corresponding to the display line indicated by the scanning line selection control signal from the cathode lines B _{1 to} B _n of the ELDP 10 ′ and ground it to the ground potential, and the other cathode lines. A predetermined high potential Vcc is applied to each of them.

Further, the light emission control circuit 1'is
Image data for screen (n rows, 2m columns) is ELDP10 '
Of each of the pixels, that is _, the pixel data D _{1,1 to} D _{n, 2m} corresponding to each of the EL elements E _{1,1 to} En _{, 2m} , and the pixel data D _{1, 1 to} D _{n, 2m} belonging to the first to m-th columns, It is divided into those belonging to the (m + 1) th column to the 2m-th column. At this time, the pixel data belonging to the first column to the m-th column is grouped for each display line to form pixel data D _{1,1 to} D _{1 , m} , D _{2,1 to} D _{2, m} , D _3,1. ~
D _{3, m,} ..., and D _{n, 1} to D n, the _m each, as shown in Figure 10, the first drive data GA _1-m, sequentially,
It is supplied to the first anode line drive circuit 21. At the same time, the light emission control circuit 1 ′ groups the pixel data belonging to _{the m + 1th column to the 2mth} column into display pixel groups D _{1, m + 1 to} D _1,2m , D _{2, m. +1} ~ D _2,2m , D _{3, m + 1
-D3,2m} , ..., and Dn _{, m + 1 to} Dn _{, 2m are} respectively set as the second drive data GB1 _-m as shown in FIG.
The power is sequentially supplied to the second anode line drive circuit 22.

Each of the first drive data GA _1-m and the second drive data GB _1-m is sequentially synchronized with the scanning line selection control signal as shown in FIG. It is supplied to each of the first anode line drive circuit 21 and the second anode line drive circuit 22. At this time, the first drive data group GA _1-m is the first of the display lines of the ELDP 10 ′.
These are m data bits that specify whether or not to emit light for each of the m EL elements belonging to each of the column to the m-th column. The second drive data group GB _1-m means the (m + 1) th column to the 2nd column of each display line of the ELDP 10 ′.
These are m data bits that specify whether or not to emit light for each of the m EL elements belonging to each of the m columns. For example, when the data bit is at the logic level "1", the light emission is performed, while when the data bit is "0", the light emission is not performed.

FIG. 11 is a diagram showing the internal structure of each of the first anode line drive circuit 21 and the second anode line drive circuit 22 as a drive circuit. The first anode line drive circuit 21 and the second anode line drive circuit 22 are respectively built in two different IC chips. In the figure, the first anode line drive circuit 21 includes a reference current control circuit RC, a control current output circuit CO, a switch block SB, and transistors Q _{1 to} Q _m and resistors R ₁ to as _m current drive sources. It consists of R _m .

Transistor in the reference current control circuit RC
Q_bResistor R for the emitter of₀Through the predetermined voltage V_BEContact
The bases and collectors are
Q _aThe collector of is connected. For operational amplifier OP
Is a predetermined reference potential V_REFAnd transistor Q_aThe emitter of
The potential is input, and the output potential is the transistor
Q_aEntered in the base of. Transistor Q_aThe emitter of
Is the resistance R_pGrounded to the ground potential. Since
With the above configuration, the transistor Q_aCollector of
Reference current I between the mitters_REF(= V_REF/ R_p) Flows
It will be.

The pixel drive potential V _BE is applied to the emitters of the transistors Q _{1 to} Q _m via the resistors R _{1 to} R _m , and the bases of the transistors Q _b are connected to the respective bases. ing. At this time, the resistances of the resistors R _r and R _{1 to} R _m are the same, and further,
Each of the transistors Q _{1 to} Q _m , Q _a and Q _b has the same characteristics. Therefore, the reference current control circuit RC and the transistors Q _{1 to} Q _{m form} a current mirror circuit (hereinafter, referred to as a current mirror), and the emitter-collector of each of the transistors Q _{1 to} Q _m. , The light emission drive current i having the same current value as the reference current I _REF flows and is output.

The switch block SB has the above-mentioned transitions.
Star Q₁~ Q_mThe light emission drive current i output from each
Output end X₁~ X_mM switchons leading to each
Element S₁~ S_mIs provided. At this time, the first anode wire
In the switch block SB of the drive circuit 21,
First drive data GA supplied from the light control circuit 1 '₁~
GA_mDepending on the logic level of each, the switching element
Child S₁~ S_mEach is independently turned on / off. example
For example, the first drive data GA₁Is at logic level "0"
Is the switching element S₁Turns off while the heels
First drive data GA₁Is at logic level "1"
Is turned on and supplied from the transistor Q1
The light emission drive current i is led to the output terminal X1. Also, the first drive
Motion data GA _mIs a logic level "0", the switch
Holding element S_mTurns off while the logic level
If it is "1", the transistor Q is turned on.
_mThe light emission drive current i supplied from the output terminal X_mDerive to
It Thus, the transistor Q₁~ Q_mFrom each of
The emitted light emission drive current i is output X₁~ X_mEach of
Through the ELDP 10 ', as shown in FIG.
Anode wire A₁~ A_mSupplied to each of the.

The emitter of the transistor Q ₀ in the control current output circuit CO is connected to the pixel drive potential V _BE via the resistor R _0.
There are applied, the base of the transistor Q _b in the reference current control circuit RC is connected to its base. At this time, the resistance value of the resistor R ₀ is the same as the resistance R _r of the reference current control circuit RC, and the transistor Q ₀ has the same characteristics as the transistors Qa and Qb of the reference current control circuit RC. Is.
Therefore, the transistor Q in the control current output circuit CO
₀ and the reference current control circuit RC form a current mirror, and a current having the same amount as the reference current I _REF flows between the emitter and collector of the transistor Q ₀ . The control current output circuit CO uses the current as a control current ic, and supplies this to the input end I _in of the second anode line drive circuit 22 via the output end I _out . That is, anode lines A ₁ to A respective same current and the light emission drive current i supplied to the _m of the first anode line drive circuit 21 is ELDP10 'is second anode lines as the control current ic drive circuit 2
2 is supplied.

The second anode line drive circuit 22 includes a drive current control circuit CC, a switch block SB, and transistors Q _{1 to} Q _m and resistors R ₁ as m current drive sources.
It consists of ~R _m. The collector and base of the transistor Qc in the drive current control circuit CC are connected to the input terminal I _in , and the emitter thereof is grounded to the ground potential via the resistor R _Q1 . Therefore, the control current ic output from the first anode line drive circuit 21 flows between the collector and the emitter of the transistor Q _c via the input terminal I _in thereof.

Further, the pixel drive potential V _BE is applied to the emitter of the transistor Q _e in the drive current control circuit CC via the resistor R _S , and the collector of the transistor Q _d is connected to the base and collector thereof. There is. The base of the transistor Q _d is connected to the collector and the base of the transistor Q _c , respectively, and the emitter thereof is grounded to the ground potential via the resistor R _Q2 . At this time, the transistor Q _{0 of} the first anode line drive circuit 21
And the transistors Q _c , Q _d , and Q _e have the same characteristics, and the resistance R ₀ and the resistance R _S in the first anode line drive circuit 21 have the same resistance value. Therefore, the same current as the control current ic supplied from the first anode line drive circuit 21 flows between the collector and the emitter of the transistor Q _d .

A resistor R ₁ is provided at the emitter of each of the transistors Q _{1 to} Q _m in the second anode line drive circuit 22.
Pixel drive potential V _BE is applied via each of R _m to R _m, and the bases of the transistors Q _e are connected to the respective bases. At this time, the resistors R _S and R ₁
To R _m, respectively of the resistance value is the same, further, the transistor Q ₁ to Q _m, each of Qd and Qe are those having the same characteristics. Therefore, the drive current control circuit C
C and the transistors Q _{1 to} Q _m form a current mirror, and the control current ic supplied from the first anode line drive circuit 21 is provided between the emitter and collector of each of the transistors Q _{1 to} Q _m. A light emission drive current i having the same amount of current as the above flows and is output respectively. That is,
By the driving current control circuit CC, the light emission drive current i output from the transistor Q ₁ to Q _m, respectively of the second anode line drive circuit 22, light emission driving current and the same current first anode line drive circuit 21 has output It is adjusted to be the quantity.

In the switch block SB, m switching elements S _{1 to} S _m for deriving the light emission drive currents i output from the transistors Q _{1 to} Q _m to the output terminals X _{1 to} X _m , respectively. Is provided. At this time, in the switch block SB of the second anode line drive circuit 22, the second drive data GB1 to GB1 supplied from the light emission control circuit 1 '
The switching elements SI to Sm are independently turned on / off according to the logic level of each GBm.

For example, when the second drive data GB ₁ is at the logic level "0", the switching element S ₁ is in the off state, while when the second drive data GB ₁ is at the logic level "1", it is in the on state. Turned transistor Q ₁
The light emission drive current i supplied from is output to the output terminal X ₁ . Further, when the second drive data GB _m is the logic level “0”, the switching element S _m is in the off state, and when the second drive data GB _m is the logic level “1”, it is in the on state and supplied from the transistor Q _m . The light emission drive current i is led to the output terminal X _m . As described above, the light emission drive current i output from each of the transistors Q _{1 to} Q _m of the second anode line drive circuit 22 is output through each of the output terminals X _{1 to} X _m as shown in FIG. And the anode wire A _{m + 1 of} ELDP 10 ′
It is supplied to each A _2m .

As described above, in the drive circuit described in the above publication, in addition to the current sources (transistors Q _{1 to} Q _m ) for generating the light emission drive current, the light emission is performed in the anode line drive circuit. A drive current control circuit CC that maintains the drive current at a current amount according to the input control current, and a control current output circuit CO that outputs the light emission drive current itself as a control current are provided. Here, when the anode lines of the display panel are shared by the plurality of anode line drive circuits constructed in the individual IC chips and are driven, the first anode line drive circuit is the second anode line drive circuit. Based on the light emission drive current actually output by
The amount of light emission drive current to be output is controlled. Therefore, even if there are variations in characteristics among the IC chips (as anode line drive circuits), the amount of light emission drive current output from each is substantially the same, so that uniform light emission brightness is displayed on the display panel. Will be obtained.

In the technique described in the above-mentioned publication, the reference current is passed from the first anode line drive circuit 21 formed of an IC chip to the second anode line drive circuit 22 formed of another IC chip. At that time, a current mirror is used. For this reason, if a current variation occurs in the current mirror, the output current varies among a plurality of IC chips. Then, there is a drawback that uniform emission brightness cannot be obtained on the display panel.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and the object thereof is to reduce the current variation generated in the current mirror and to reduce the reference current between a plurality of IC chips. It is an object of the present invention to provide a display panel drive circuit which can eliminate the variation of

[0029]

A display panel drive circuit according to claim 1 of the present invention supplies a current to a plurality of IC chips, and the plurality of ICs are supplied by the supplied current.
A display panel drive circuit for driving a display panel by a drive output output from a C chip, wherein the drive current supply means is provided corresponding to each of the plurality of IC chips and outputs a drive current to the corresponding IC chip. It is characterized by including a switching means for switching the correspondence between the IC chip and the drive current supply means at a predetermined cycle.

A display panel drive circuit according to a second aspect of the present invention is the display circuit drive circuit according to the first aspect, further including a reference current source provided in common to the drive current supply means, the reference current source and the drive current supply means. It is characterized in that a current mirror circuit is configured by. The display panel drive circuit according to claim 3 of the present invention is the display panel drive circuit according to claim 1 or 2, wherein the plurality of IC chips include three or more IC chips, and the correspondence relationship between the drive current supply source and the IC chip is a predetermined cycle. It is characterized by being rotated by and switching.

A display panel driving circuit according to a fourth aspect of the present invention is the display panel driving circuit according to any one of the first to third aspects, in which the display panel is driven by a plurality of electromotive outputs output from the IC chips. It is characterized by being constituted by a luminescence element. In short, by switching the correspondence relationship (electrical connection relationship) between the plurality of IC chips and the plurality of driving current supply sources in a predetermined cycle, it is possible to reduce the current variation generated in the current mirror. Further, since it is possible to eliminate variations in the reference current among a plurality of IC chips, it is possible to obtain uniform light emission brightness on the display panel.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. In each of the drawings referred to in the following description, the same parts as those in the other drawings are designated by the same reference numerals. FIG. 1 is a diagram showing a configuration of a main part in an embodiment of a display panel drive circuit according to the present invention. A reference current generation circuit is shown in FIG. In this example, the case where the number of IC chips to which the reference current is supplied is two is shown.

[0033] As shown in the figure, the reference current generating circuit 20 includes a current source I _org, a transistor Q ₂₀ constituting the reference current source with the current source I _org, current source I _org
And a transistor Q ₂₀ as a common reference current source, and transistors Q ₂₁ and Q ₂₂ that form a current mirror together with the reference current source are included. Currents I _cm1 and I _cm respectively derived from the transistors Q ₂₁ and Q _22
cm2 is given to the drive circuits 21 and 22 (not shown) which are IC chips.

Further, the reference current generating circuit 20 includes a transistor.
Register Q_{twenty one}, Q_{twenty two}Current derived from
I_cm1, I_cm2And drive circuits 21 and 22 not shown
Switching circuit SW that switches the correspondence relationship at a predetermined cycle
1, SW2 are provided. Ie transistor
Q_{twenty one}, Q_{twenty two}Current I derived from_cm1, I
_cm2By the switching circuits SW1 and SW2
Switched, output current I_ref1, I _ref2Not shown as
It is given to the drive circuits 21 and 22.

Switching the switching circuits SW1 and SW2
By performing time-sharing control,
Current source I that realizes current_orgAnd current I_ref1, I_ref2With
The amount of variation is reduced and the current I_ref1And current I_ref2
And are equal. Specifically, the original current of the current mirror
I_orgAnd the current I generated by the current mirror_cm1And the current
The amount of fluctuation is ΔI₁, The original current I of the current mirror_orgAnd boyfriend
Current I generated by the mirror_cm2And the amount of current variation with
ΔI₂Then, the output current I of the switching circuit _ref1,
I_ref2The current variation is also time-shared, so
The average is as follows.

Average of variation = 1/2 × √ (ΔI ₁ ² + ΔI ₂ ² ) Here, if ΔI ₁ and ΔI ₂ = ΔI, then the average of variation = 1 / √2 × ΔI, which is generated by the current mirror. It becomes smaller than the amount of variation in the currents I _cm1 and I _cm2 .

Further, since the output currents I _ref1 and I _ref2 of the switching circuit are equal to each other, even when the display panel drive circuit is configured by using a plurality of IC chips, the variation in the output current between the IC chips is reduced. be able to. Here, switching of the switching circuit is performed at the switching timing of the cathode ray signal. Figure 2
(A) is a timing chart which shows the switching timing of a switching circuit. In the figure, the currents I _cm1 and I _cm2 generated by the current mirror are the switching circuit SW.
It is shown that the output current I _ref1 or I _ref2 is output by the switching operation of SW1 and SW2.

As shown in FIG.
By switching the switching circuits at the timing when the switches 2, 3, ... Are turned off, noise accompanying switching between the current I _ref1 and the current I _ref2 can be reduced. As a result, adverse effects such as flickering of the display screen can be avoided, and good image display can be realized. FIG. 3 shows the connection relationship between the reference current generation circuit 20 and the first anode line drive circuit 21 and the second anode line drive circuit 22. Referring to the figure, the above-mentioned switching circuits SW1 and SW
The output current I _ref1 output by the switching operation of 2 is input to the first anode line drive circuit 21 as the reference current of the current mirror, and the output current I _ref2 is input to the second anode line drive circuit 22 of the current mirror reference current. Has been entered as.

Since the output current I _ref1 and the output current I _ref2 of the switching circuit of the reference current generating circuit 20 described above are equal to each other, the first ICs composed of different IC chips respectively.
It is possible to reduce variations in the currents supplied to the anode line drive circuit 21 and the second anode line drive circuit 22, respectively. The switching circuits SW1 and SW are shown in FIG.
2 is shown. In the figure, switching circuits SW1 and SW2 are both MOS (Metal o
xide Semiconductor) transistor or the like.

Switching circuit SW shown in FIG.
1 and SW2 are two analog switches 41 and 42 to which the current output from the channel number N of the corresponding IC chip is input, and analog switches 43 and 4, respectively.
4 is included. Analog switch 41,
42, 43, and 44 are each composed of an N-type MOS transistor and a P-type MOS transistor having a common source and drain. And these N type M
The gates of the OS transistor and the P-type MOS transistor serve as a switching control terminal, and ON / OFF is controlled by mutually inverted signals.

Further, in the figure, it is configured to include an inverter INV which inverts and supplies the pulse 201 to the gate which is the switching control terminal. The inverter INV is, for example, a well-known CMOS (Compl).
elementary Metal Oxide Semi
It is composed of an inverter circuit. While the pulse 201 is directly input to the N-type MOS transistor of the analog switch 41, the P-type MOS transistor of the analog switch 42, the P-type MOS transistor of the analog switch 43, and the N-type MOS transistor of the analog switch 44, the analog switch 41 P
Type MOS transistor, N type M of analog switch 42
N-type MOS of OS transistor and analog switch 43
The output pulse 201 is logically inverted and input to the transistor and the P-type MOS transistor of the analog switch 44 by the inverter INV. Therefore, pulse 2
When 01 is high level, analog switches 41 and 44
Is on, the analog switches 42 and 43 are off. On the other hand, when the pulse 201 is at the low level, the analog switches 41 and 44 are off, and the analog switches 42 and 43 are on.

Within the former period, the current I_cm1Out
Force current I_ref1And the current I_cm2Output
Current I_ref2Is derived as On the other hand, within the latter period
The current I_cm1Is the output current I_ref2Is derived as
And the current I_cm2Is the output current I _ref1Is derived as
By configuring the switching circuit as described above,
Display panel drive circuit using a plurality of IC chips
Even when configured, the output current between IC chips
The variation can be reduced.

In this embodiment, the reference current generating circuit 20
Although the example in which the IC is provided outside the IC chip 1 and the IC chip 2 is shown, the reference current generation circuit 20 is provided inside the IC chip 1 to supply the output current I _ref1 to the IC chip 1 and to output the output current I _ref2. May be supplied to the IC chip 2.
In this case, the IC chip 1 is the master IC and the IC chip 2 is
Can be configured with only two chips as a slave IC.

Although the case where two IC chips are used has been described above, the correspondence relationship between the IC chips and the driving current supply source (electrically connected state) is likewise obtained when more IC chips are used. It is possible to reduce the variation in the output current between the IC chips by switching the output voltage in a predetermined cycle. For example, for multiple IC chips,
When a plurality of drive current sources are prepared and the connection between the IC chip and the drive current source is switched while rotating in sequence at a predetermined cycle, the drive currents to the plurality of IC chips are averaged,
It can be about the same level. FIG. 2B is a timing chart showing the timing at which three drive current sources are prepared for three IC chips and switched while rotating.

[0045]

As described above, according to the present invention, a plurality of I
By switching the correspondence between the C chip and the plurality of drive current supply sources in a predetermined cycle, it is possible to reduce the current variation generated in the current mirror. Further, since it is possible to eliminate variations in the reference current among a plurality of IC chips, there is an effect that uniform emission brightness can be obtained on the display panel.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of a display panel drive circuit according to the present invention.

FIG. 2 is a timing chart showing switching timing of a switching circuit in the display panel driving circuit of FIG.

FIG. 3 is a diagram showing a connection relationship between a reference current generation circuit and an anode line drive circuit.

FIG. 4 is a diagram illustrating a configuration example of a switching circuit.

FIG. 5 is a diagram showing a schematic configuration of an EL element.

FIG. 6 is a diagram showing an equivalent circuit that electrically shows the characteristics of EL elements.

FIG. 7 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of EL elements are arranged in a matrix.

FIG. 8 is a diagram showing a supply timing of pixel data and a scanning line selection signal.

FIG. 9 is a diagram showing a case where an anode line drive circuit is constructed by two IC chips.

FIG. 10 is a diagram showing the supply timing of pixel data and a scanning line selection control signal by the light emission control circuit.

FIG. 11 is a diagram showing an example of the internal configuration of an anode line drive circuit.

[Explanation of symbols]

1 Light emission control circuit 2 Anode line drive circuit 3 Cathode line scanning circuit 10 ELDP 20 Reference current generation circuits 21, 22 Anode line drive circuit 30 Cathode line scanning circuit 100 Transparent substrate 101 Transparent electrode 102 Organic functional layer 103 Metal electrode CC Driving current control circuit CO Control current output circuit I _org Current source Q ₂₀ , Q ₂₁ , Q ₂₂ Transistor SW1, SW2 Switching circuit

Continued front page    F-term (reference) 3K007 AB02 AB17 BA06 DA01 DB03                       EB00 GA04                 5C080 AA06 BB05 DD03 EE28 JJ02                       JJ03

Claims (4)

[Claims] 1. A display panel drive circuit for supplying a current to a plurality of IC chips, and driving a display panel by a drive output output from the plurality of IC chips by the supplied current.
It is characterized by including drive current supply means provided corresponding to each of the chips and outputting a drive current to the corresponding IC chip, and switching means for switching the correspondence relationship between the IC chip and the drive current supply means in a predetermined cycle. Display panel drive circuit. 2. A current mirror circuit is further comprised of a reference current source provided in common to the drive current supply means, and a current mirror circuit is constituted by the reference current source and the drive current supply means. The display panel drive circuit described. 3. The IC chip according to claim 1, wherein the plurality of IC chips include three or more IC chips, and the correspondence relationship between the drive current supply source and the IC chip is rotated and switched in a predetermined cycle. The display panel drive circuit described. 4. The display panel is configured by a plurality of electroluminescent elements that are driven by drive outputs output from the IC chip, respectively.
A display panel drive circuit according to item.