JP2002313865A - Semiconductor device and its pattern inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having TEGs for detecting pattern thickening, pattern thinning, and displacement by defect inspection, and to provide a method for inspecting the pattern. SOLUTION: First and second TEGs 1 and 2 are alternately arranged at the same position in adjacent chips in a wafer. In the first TEG 1, a dot pattern 6 and wiring patterns 4 and 5 are formed in first and second layers 10a, and 11a, respectively. In the second TEG 2, a dot pattern 9 and wiring patterns 7 and 8 are formed in a second layer 11b. As a result, a pair of TEGs for pattern inspection is composed, and allows abnormality in the patterns to be detected by the defect inspection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with an inspection pattern which can be easily inspected, and a method for inspecting the pattern.

[0002]

2. Description of the Related Art In a wafer manufacturing process, a TEG (test element group) is provided in a wafer or in each chip in the wafer, and various inspections are performed using an inspection pattern formed in the TEG. Is done.

[0003] Regarding pattern thinning, pattern thickening, and misalignment, since there is no TEG that can inspect these pattern abnormalities using a conventional defect inspection device with a bright field pattern, after performing a defect inspection, a length measurement SEM (scanning) is performed. At present, pattern abnormalities are inspected using a scanning electron microscope) and misalignment inspection equipment.

Accordingly, inspection patterns for detecting these pattern abnormalities have been used on the premise of visual inspection and in a form suitable for the inspection.

[0005]

However, it is difficult to expect a high throughput in the wafer inspection process when the defect is inspected and the defect is classified by a visual or misalignment inspection apparatus to detect a pattern abnormality. For this reason, it is desirable that the process up to the detection of a pattern abnormality can be performed consistently in the defect inspection process. In general, as a method for efficiently and automatically inspecting a circuit pattern in which the same type of pattern is repeatedly used, an inspection is performed by comparing the same type of circuit pattern with each other. This method is used not only for semiconductor chips but also for inspection of LCD patterns, for example. In Japanese Patent Laid-Open No. 6-202129 (Prior art 1), a pattern is arranged symmetrically with respect to a left-right symmetric position at the center of an LCD pattern, and the LC
An inspection method is described in which a comparative inspection system for performing a defect inspection of the D pattern is formed so as to be symmetrically movable about the left-right symmetric position of the LCD pattern. The effect that the automatic inspection can be performed by the comparison method is emphasized. However, in any case, the pattern thickening, the pattern thinning, and the misalignment are defects that occur in common throughout, and thus cannot be detected by a simple comparison judgment. An object of the present invention is to apply a conventional defect detection method to a pattern thickening, pattern thinning, and misalignment, which was difficult in principle with a conventional defect detection method using a bright-field pattern-based defect inspection device based on comparison judgment. It is an object of the present invention to provide a semiconductor device having a TEG that can be detected by using the semiconductor device and a method for inspecting a pattern abnormality thereof.

[0006]

In order to achieve the above object, in a semiconductor device according to the present invention, first TEGs and second TEGs are alternately arranged at the same position in adjacent chips in a semiconductor wafer. When the pattern thickening, pattern thinning, or misalignment occurs, the first TEG and the second
The first TEG and the second TEG are formed so as to cause a difference that can be compared and detected in the TEG planar image.

Further, first TEGs and second TEGs are alternately arranged at the same position in adjacent chips in a semiconductor wafer, and the first TEG has a plurality of element patterns constituting a pattern inspection pattern. Are formed in a plurality of layers, and a part of the plurality of element patterns is formed in a layer different from the layer formed by the first TEG in the second TEG, and the pattern inspection pattern is formed. Is formed.

[0008] Further, the first TEG and the second TEG are alternately arranged at the same position in adjacent chips in the semiconductor wafer, and a part of the plurality of element patterns is provided in the first TEG. The other element pattern is formed in the second layer in the second layer, and all of the plurality of element patterns are formed in the second layer in the second TEG.

Further, an oxide film is formed on the first TEG after forming a dot pattern on the first layer, and two oxide layers are formed on the second layer at equal distances with the dot pattern interposed therebetween. A wiring pattern is formed in parallel, only an oxide film is laminated on a first layer on the second TEG, and two wiring patterns and a dot pattern are formed on the second TEG in the first TEG.
It is formed with the same shape and positional relationship as in the case of EG.

Further, in the pattern inspection method according to the present invention, an oxide film is formed on the first TEG after forming a dot pattern on the first layer, and the dot pattern is sandwiched on the second layer. , Two wiring patterns are formed in parallel at the same distance from each other, and only the oxide film is laminated on the first layer on the second TEG, and the two wiring patterns and the dot pattern are formed on the second layer. Are formed in the same shape and positional relationship as in the case of the first TEG, and the first and second TEGs are compared and a plane image observed by combining the first and second layers is inspected. Things.

The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the distance between the second TEG and the dot pattern is c. Where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern, a = b, d = e, c = When the condition of f is satisfied, it is determined that there is no abnormality in the pattern.

The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the second TEG is Where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern. When this holds, it is determined that the pattern is abnormal due to misalignment.

The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the distance between the second TEG and the dot pattern is c. Where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern, a> d and b> e, c < When one or both of the conditions of f are satisfied, it is determined that the pattern is abnormal due to the pattern thickening.

The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the second TEG is A <d and b <e, c>, where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern. When the condition of f is satisfied, it is determined that the pattern is abnormal due to pattern thinning.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a plan view of the wafer W. FIG.
, A chip region 3 is formed in the wafer W,
In the chip area 3, equivalent chips T, T,... Are arranged adjacent to each other. FIG. 1 shows an example in which the chip area 3 in the wafer W includes 26 chips. In the semiconductor device according to the present invention, the first TEG1 is located at the same position in adjacent chips T, T,.
And the second TEG2 are alternately arranged.
The first TEG1 and the second TEG2 are formed so as to cause a detectable difference between the plane images of the G1 and the second TEG2.

Hereinafter, a specific method of pattern inspection will be described using the lowermost four chips T1, T2, T3, and T4 arranged in the horizontal direction as an example. The bottom four chips T1 and T
2, a first TEG1 or a second TEG formed of a pattern for pattern inspection at the same position in each chip of T3 and T4.
An area for G2 is secured, and the first and second Ts are set for chips T1, T2, T3, and T4 adjacent to each other in the horizontal direction.
EG1 and TEG2 are arranged alternately.

The detailed configuration of TEG1 and TEG2 will be described with reference to FIGS. 2 and 3 when there is no pattern abnormality in T1, T2, T3 and T4. FIG. 2A shows TEG1.
2 (b) is a sectional view of TEG2, and FIG. 3 (a)
Is a plan view of TEG1, and FIG. 3B is a plan view of TEG2. In the present invention, the first TEG1 is formed by dispersing a plurality of element patterns constituting a pattern inspection pattern in a plurality of layers, and the second TEG2 is configured to include a part of the plurality of element patterns. The pattern inspection pattern is formed on a layer different from the layer formed by the first TEG.

That is, in FIG. 2A, a rectangular dot pattern 6 is formed on the first layer 10a of the first TEG 1, and an oxide film is laminated thereon. Also, TEG1
In the second layer 11a, a first wiring pattern 4, which is two wiring patterns, and a second wiring pattern 5, are formed in parallel with each other.

On the other hand, in FIG. 2B, only an oxide film is laminated on the first layer 10b of TEG2. The second layer 11b of the second TEG2 is provided on the second layer 1b of the TEG1.
First and second wiring patterns 4 and 5 formed in 1a
The first and second wiring patterns 7 and 8 are formed in parallel with each other in the same shape and positional relationship with
A dot pattern 9 having the same size as the dot pattern 6 is also formed. Here, the dot pattern 6 is formed at a position at the same distance from the wiring patterns 4 and 5 (the center position between the wiring patterns 4 and 5), and the dot pattern 9 is formed at a position at the same distance from the wiring patterns 7 and 8 respectively. Formed.

In FIG. 3A, a is the distance between the wiring pattern 4 and the dot pattern 6 for the TEG 1;
“b” represents the distance between the wiring pattern 5 and the dot pattern 6, and “c” represents the width of the dot pattern 6. Similarly, FIG.
In (b), d and e represent the distance between the wiring patterns 7 and 8 and the dot pattern 9 for the TEG2, respectively, and f represents the width of the dot pattern 9.
In the present invention, the normality and abnormality of the formed pattern are determined by comparing the planar images observed by combining the first and second layers for the first and second TEGs. is there.

If there is no pattern abnormality, a = b, d
= E and c = f are satisfied, and therefore, when images of adjacent TEG1 and TEG2 are compared using a defect inspection device with a bright field pattern, no defect is recognized and it can be correctly determined that there is no pattern abnormality.

Next, a description will be given, with reference to FIG. 4 and FIG.

In FIG. 4A, the first layer 1 of the TEG 1
When a misalignment occurs between the first layer 0a and the second layer 11a, the first
The position of the dot pattern 6 formed on the layer 10a is the second position.
It deviates from the center of the wiring patterns 4 and 5 formed on the layer 11a, and in this example, the position is shifted toward the wiring pattern 5 side.

On the other hand, in TEG2, FIG.
As is clear from the cross-sectional view of TEG2, the dot pattern 9 and the wiring patterns 7 and 8 are all formed on the second layer 11b.
And correctly located in the center position.

Therefore, in the plan view of the TEG 1 shown in FIG. 5A, the distance a between the wiring pattern 4 and the dot pattern 6 and the distance b between the wiring pattern 5 and the dot pattern 6
The relationship of a> b is established between. On the other hand, FIG.
In the plan view of TEG2, the relationship of d = e is maintained without being affected by misalignment, so that TEG1 and TE
When the images of G2 are compared, they are recognized as defects, and a pattern abnormality due to misalignment can be determined.

Next, the case where the pattern is thickened will be described with reference to FIGS.

FIG. 6A shows a case where the pattern is thickened.
As shown in FIG. 5, wiring patterns 4 and 5 having thickened patterns are formed on the second layer 11a of the TEG1. On the other hand, T
As shown in FIG. 6B, the second layer 11b of EG2 has
Both the wiring patterns 7 and 8 and the dot pattern 9 are formed as a pattern with a thickened pattern.

Therefore, in FIG. 7A, the intervals a and b in the case of the TEG 1 are narrower than the normal case by the thickness of the wiring patterns 4 and 5. On the other hand, the intervals d and e in the case of TEG2 in FIG. 7B are further narrowed by adding the dot pattern 9 to the wiring patterns 7 and 8 and the pattern thickness.

As a result, a> d and b> e, and at the same time, c <
f. As a result, when the images of TEG1 and TEG2 are compared, one or both of these two conditions are detected and recognized as a defect, and the pattern abnormality due to the pattern thickening can be determined.

FIGS. 8 and 9 show the case where the pattern is thin.
This will be described below.

In the case where the pattern is thin, wiring patterns 4 and 5 having a thin pattern are formed on the second layer 11a of the TEG 1, as shown in FIG. Meanwhile, TEG
As shown in FIG. 8 (b), the wiring patterns 7, 8 and the dot pattern 9 are both formed on the second layer 11b as a thinned pattern.

Therefore, in FIG. 9A, the intervals a and b in the case of TEG1 are wider than in the normal case by the thinning of the wiring patterns 4 and 5. On the other hand, the intervals d and e in the case of TEG2 in FIG. 9B become wider due to the thinning of the dot patterns 9 added to the thinning of the wiring patterns 7 and 8.

As a result, a <d and b <e, and at the same time, due to the thinning of the dot pattern 9 itself, c> c
f. As a result, when comparing the images of TEG1 and TEG2, one or both of these two conditions are detected and recognized as a defect, and a pattern abnormality due to pattern thinning can be determined.

[0034]

As described above, by using the TEG for pattern inspection according to the present invention, misalignment and pattern in the wafer diffusion process can be performed by using the conventional defect inspection method using a defect inspection apparatus with a bright field pattern. Defect inspection for thick and thin patterns becomes possible.

If any of the pattern thickening, pattern thinning, and misalignment occurs, the chip is uniformly recognized as a defect in all the chips in the inspection target area. Defects can be clearly distinguished at the defect inspection stage.

As a result, it is not necessary to classify defects by visual inspection or misalignment inspection device after the defect inspection, and it is possible to consistently detect pattern abnormalities only by the defect inspection device, thereby realizing high inspection throughput.

[Brief description of the drawings]

FIG. 1 is a plan view of a wafer showing a chip arrangement in a wafer and an arrangement of TEG1 and TEG2 in a chip according to the present invention.

FIGS. 2A and 2B are cross-sectional views of TEG1 and TEG2 when there is no pattern abnormality, respectively.

FIGS. 3 (a) and 3 (b) are plan views of TEG1 and TEG2 when there is no pattern abnormality, respectively.

FIGS. 4A and 4B are cross-sectional views of TEG1 and TEG2 when misalignment occurs, respectively.

FIG. 5A and FIG. 5B are plan views of TEG1 and TEG2 when misalignment occurs, respectively.

FIGS. 6A and 6B are cross-sectional views of TEG1 and TEG2 when the pattern is thickened, respectively.

FIGS. 7A and 7B are plan views of TEG1 and TEG2 when the pattern is thickened, respectively.

FIGS. 8A and 8B are cross-sectional views of TEG1 and TEG2 when a pattern is thinned, respectively.

FIGS. 9A and 9B are plan views of TEG1 and TEG2 when the pattern is thinned, respectively.

[Explanation of symbols]

 1, 2, TEG 3 Chip area 4, 5, 7, 8 Wiring pattern 6, 9 Dot pattern 10a, 10b First layer 11a, 11b Second layer

 ──────────────────────────────────────────────────続 き Continued from the front page F term (reference) 2G011 AE03 2G132 AD15 AF11 AK03 AL09 4M106 AA01 AB20 BA02 BA04 BA10 DB21

Claims (9)

[Claims] A first TEG and a second TEG are alternately arranged at the same position in adjacent chips in a semiconductor wafer. The first TEG and the second TEG may be compared so as to cause a detectable difference between the planar images of the TEG and the second TEG.
And a TEG. 2. A first TEG and a plurality of elements forming a pattern inspection pattern are arranged alternately at the same position in adjacent chips in a semiconductor wafer. The pattern is formed by dispersing in multiple layers,
The second TEG includes a part of the plurality of element patterns,
A semiconductor device, wherein the pattern inspection pattern is formed on a layer different from the layer formed by the first TEG. 3. A first TEG and a second TEG are alternately arranged at the same position in adjacent chips in a semiconductor wafer, and a part of the plurality of element patterns is provided in the first TEG. 3. The method according to claim 2, wherein the first element layer is formed in one layer, the other element patterns are formed in a second layer, and the second TEG is formed with all of the plurality of element patterns in the second layer. 3. The semiconductor device according to claim 1. 4. The first TEG has a dot pattern formed in a first layer, an oxide film is laminated thereon, and two second layers are formed on a second layer at an equal distance from each other with the dot pattern interposed therebetween. Forming a wiring pattern in parallel with the second TE
G, only an oxide film is laminated on a first layer, and two wiring patterns and a dot pattern are formed on a second layer by the first TE.
4. The semiconductor device according to claim 3, wherein the semiconductor device is formed in the same shape and positional relationship as in the case of G. 5. The first TEG has a dot pattern formed on a first layer, an oxide film is laminated thereon, and two second layers are formed on a second layer at equal distances with the dot pattern interposed therebetween. Forming a wiring pattern in parallel with the second TE
G, only an oxide film is laminated on a first layer, and two wiring patterns and a dot pattern are formed on a second layer by the first TE.
G is formed with the same shape and positional relationship as in the case of G, and the first and second TEGs are combined and inspected by comparing plane images observed by combining the first and second layers. Item 4. The pattern inspection method for a semiconductor device according to Item 3. 6. The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the second TEG is Where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern, a = b, d = e, c = 6. The pattern inspection method for a semiconductor device according to claim 5, wherein when the condition of f is satisfied, it is determined that there is no abnormality in the pattern. 7. The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the second TEG is Where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern. 6. The pattern inspection method for a semiconductor device according to claim 5, wherein when the condition is satisfied, it is determined that the pattern is abnormal due to misalignment. 8. The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the second TEG is Where d is the distance between the first wiring pattern and the dot pattern, e is the distance between the second wiring pattern and the dot pattern, and f is the width of the dot pattern, a> d and b> e, c < 6. The pattern inspection method for a semiconductor device according to claim 5, wherein when one or both of the conditions of f are satisfied, it is determined that the pattern is abnormal due to the pattern thickening. 9. The distance between the first wiring pattern and the dot pattern for the first TEG is a, the distance between the second wiring pattern and the dot pattern is b, the width of the dot pattern is c, and the width of the second TEG is c. When the distance between the first wiring pattern and the dot pattern is represented by d, the distance between the second wiring pattern and the dot pattern is represented by e, and the width of the dot pattern is represented by f, a <d and b <e, c> f 6. The pattern inspection method for a semiconductor device according to claim 5, wherein when the condition is satisfied, it is determined that the pattern is abnormal due to pattern thinning.