JP2002313036A - Demodulation method, error correction method, and recording medium reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain code data of demodulated not-binary information. SOLUTION: A logarithmic likelihood ratio arithmetic circuit 11 calculates the logarithmic likelihood ratio L(a'i ) of inputted channel data a'i before demodulation, assuming a communication channel to be a white gauss communication channel. An arithmetic operation circuit 13 applies calculation to parallel data converted by shifting logarithmic likelihood ratio L(a'i ) in a p-stage shift register 12 by using a symbol correspondence rule of data before and after demodulation, and obtains the parallel data of the logarithmic likelihood ratio of m-bit code data after demodulation. A m-stage shift register 14 loads the parallel data after demodulation in parallel, shifts them, and outputs the logarithmic likelihood ratio L(c'i ) of the code data after demodulation. Thus, the code data after demodulation can be obtained with the logarithmic likelihood of a real numerical value, and the code data whose not-binary information is restored can be supplied to a post-stage turbo-decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing channel data by subjecting information data to error correction coding and modulation based on a symbol correspondence rule, recording the channel data on a recording medium, and reproducing from the recording medium. The present invention relates to a demodulation method and an error correction method for performing demodulation and error correction decoding on channel data based on a symbol correspondence rule to restore information data, and a recording medium reproducing apparatus.

[0002]

2. Description of the Related Art Among error correction systems, a turbo code system has a high performance close to a theoretical limit of a transmission rate at which transmission can be performed without errors (that is, a Shannon limit). It is getting attention.

Communication (or recording / reproduction) using turbo codes
The system will be briefly described. FIG. 11 is a schematic diagram of a recording / reproducing apparatus that performs an encoding process and a decoding process of a turbo code. Turbo encoder 1 outputs the code data c _i applies error correction coding to the information data u _i entered. The modulator 2 outputs the channel data a _i performs modulation on the inputted code data c _i. The output channel data a _i is transmitted (or recorded) to the communication channel 3. Here, the communication path 3 is a wireless communication path, a wired communication path, a recording medium, or the like.

The above-mentioned channel data a _i is provided with noise addition, fading, multi-path,
Subject to deformations such as band limiting, intersymbol interference, and crosstalk.
Therefore, an error is added to the channel data a ′ _i received (or reproduced) from the communication channel 3. Demodulator 4
Performs demodulation on the input data a ′ _i before demodulation and outputs restored code data c ′ _i . The turbo decoder 5
An error added to the input code data c ′ _i added in the communication path 3 is corrected, and the restored information data u ′ _i is output.

In general, in order for the turbo decoder 5 to perform an error correction process, the restored code data c ′ _i needs to be soft information. Therefore, the demodulator 4 needs to output the code data c ′ _i as soft information.

[0006]

However, the above-mentioned conventional recording / reproducing apparatus has the following problems. That is, when the communication path 3 is a recording medium, that is, in the case of a system that performs recording and reproduction on a medium such as magnetic recording, magneto-optical recording, and optical recording, the band limitation, the intersymbol interference, and the clock There are constraints such as synchronization. for that reason,
The modulation method of the modulator 2 includes a run length limit (Run Length).
h Limited: RLL) is generally used. RLL is generally denoted as RLL (d, k). Here, “d” and “k” represent the minimum and maximum run length of “0” in the channel data sequence based on the non-return-to-zero inversion (NRZI) rule.

Further, the RLL will be described in detail.
The polarity reversal interval of the recording waveform sequence is the minimum polarity reversal interval Tmin
And the maximum polarity inversion interval Tmax.
That is, each inversion interval T of the recording waveform sequence is Tmin ≦ T ≦
It is within the range of Tmax. Generally, the minimum polarity inversion interval Tmin is expressed as (d + 1) × Tw. The maximum polarity inversion interval Tmax is represented by (k + 1) × Tw. here,
"Tw" is the detection window width of the reproduced signal, and is equal to the greatest common divisor of each polarity inversion interval, and Tw = [eta] * Tb. Note that Tb is a data interval before modulation. Η is called a coding rate and is equal to m / n. That is, m bits before modulation are converted into n bits after modulation.

The RLL modulation and the RLL demodulation are generally performed by a logical operation circuit. Alternatively, the operation is performed by storing the result of the logical operation in a ROM (read only memory) in advance and referring to the ROM as a table. Therefore, the input data of the RLL demodulation is hard information, and the output data of the RLL demodulation is hard information.

FIG. 12 is a block diagram showing a configuration of a conventional RLL demodulator. The data a ′ _i before demodulation output from the communication path 3 shown in FIG.
The comparator 6 binarizes, that is, converts soft information into hard information. Each bit of the binarized data d ′ _i before demodulation is either “−1” or “+1”. The binary data d ′ _i before demodulation is input to the p-stage shift register 7. The number p of stages of this shift register is generally n or more. The p-stage shift register 7
The data is shifted by the interval Tw and the parallel data (d ′ ₁ ,
_{d '2, ..., d'} k, ..., and outputs the d _'p). Logical operation circuit 8
The parallel data _{(d '1, d' 2} , ..., d 'k, ..., d' p) to input by performing a logic operation mentioned above, the parallel data after demodulation (c _'1, c' ₂ , ..., c ' _j , ..., c' _m ). The m-stage shift register 9 with a parallel load function loads the demodulated parallel data (c ′ ₁ , c ′ ₂ ,..., C ′ _j ,..., C ′ _m ) in parallel,
The data is shifted at intervals of Tb, and the demodulated serial data c ′ _i is output. The logical operation and the parallel load are performed in synchronization at intervals (m × Tb).

As described above, when the communication path 3 is a recording medium such as a magnetic recording, a magneto-optical recording, an optical recording, etc., the constraint conditions such as the band limitation, the intersymbol interference, the clock synchronization and the like of the communication path 3 are set. Therefore, an RLL modulator is used as the modulator 2.
Therefore, the demodulator 4 uses an RLL demodulator. However, as described above, the RLL demodulator outputs the restored code data c ′ _i as hard information. However, the decoded code data c ′ _{i is} stored in the turbo decoder 5.
Must be input as soft information.

Therefore, when constructing a recording / reproducing apparatus using the above communication path as a recording medium, a turbo decoder cannot be used due to the use of an RLL demodulator, and the error correction capability of a Viterbi decoder or the like cannot be used. A low error correction decoder must be used. Therefore, there is a problem that the recording density on the recording medium is reduced as compared with the case where a turbo decoder is used.

An object of the present invention is to provide a demodulation method capable of outputting demodulated code data as soft information, an error correction method using the demodulation method, and a recording medium reproducing apparatus using the error correction method. It is in.

[0013]

In order to achieve the above object, a first aspect of the present invention is to provide a demodulation operation means for demodulating a set of consecutive bits in digital data as a symbol based on a symbol correspondence rule of data before and after demodulation. In the demodulation method of calculating post-demodulation data from the previous data, the likelihood calculation means calculates the likelihood of each bit of the input data before demodulation, and the demodulation calculation means calculates the likelihood of each bit of the data before demodulation. The likelihood is calculated for each symbol of the demodulated data based on the symbol correspondence rule from the likelihood, and the likelihood for each bit of the demodulated data is calculated from the likelihood of each symbol of the demodulated data. It is characterized in that the likelihood of each bit of the demodulated data is obtained from the likelihood of each bit of the previous data.

According to the above configuration, the likelihood of each bit of the demodulated data can be obtained by the demodulation operation means. The likelihood of each bit of the demodulated data is a real number and is soft information. Thus, a demodulation method capable of outputting soft information is realized.

In the second invention, a group of consecutive bits in the digital data is used as a symbol, and the symbol before demodulation, the symbol in the current internal state of the demodulation operation means, the data after demodulation, and the next internal state in the demodulation operation means are used. In a demodulation method for calculating post-demodulation data from pre-demodulation data by the demodulation calculation means based on a rule corresponding to a symbol, the likelihood calculation means calculates the likelihood of each bit of the input pre-demodulation data by the likelihood calculation means. The demodulation calculation means calculates the likelihood of each symbol of the demodulated data and the likelihood of the next internal state based on the symbol correspondence rule from the likelihood of each bit of the data before demodulation and the likelihood of each bit of the current internal state. The likelihood of each symbol is calculated, the likelihood of each bit of the demodulated data is calculated from the likelihood of each symbol of the demodulated data, and the symbol of the next internal state is calculated. By calculating the likelihood of each bit from the likelihood of the next internal state of each is characterized by obtaining a likelihood of each bit of the data after the demodulation from likelihood of each bit of the demodulated data before.

According to the above configuration, the likelihood of each bit of the demodulated data can be obtained by the demodulation operation means. The likelihood of each bit of the demodulated data is a real number and is soft information. In this manner, a demodulation method for maintaining an internal state capable of outputting soft information is realized.

In one embodiment, in the demodulation method according to the first or second aspect, the symbol correspondence rule is a rule table.

According to this embodiment, the conversion from the bit-by-bit likelihood of the data before demodulation to the bit-by-bit likelihood of the data after demodulation by the demodulation operation means is performed by the arithmetic operation derived based on the rule table. It is realized by calculation.

In one embodiment, in the demodulation method according to the first or second aspect, the symbol correspondence rule is a logical expression.

According to this embodiment, the conversion from the bit-by-bit likelihood of the data before demodulation to the bit-by-bit likelihood of the data after demodulation by the demodulation operation means is performed by an arithmetic operation derived based on a logical expression. It is realized by calculation.

In one embodiment, the demodulation method according to the first or second aspect is characterized in that a log likelihood ratio is used as the likelihood for each bit.

According to this embodiment, the logarithmic likelihood ratio for each bit of the demodulated data is obtained by the demodulation operation means. Therefore, it is possible to use a turbo decoding method using the log likelihood ratio as an input as an error correction decoding method after demodulation.

In one embodiment, in the demodulation method according to the first or second aspect, the symbol correspondence rule is a symbol correspondence rule based on an RLL modulation method.

According to this embodiment, a demodulation method based on the RLL system is realized. Thus, the present invention can be applied to demodulation of a reproduction signal from a recording medium that requires the RLL modulation method.

The error correction method according to the third invention is characterized in that the likelihood of each bit of the demodulated data obtained from the data before demodulation by the demodulation method of the first or second invention is determined by an error. It is characterized in that the error is corrected by the correction means.

According to the above configuration, error correction is performed on the likelihood of each bit of the demodulated data obtained as soft information. Therefore, error correction by turbo decoding becomes possible, and the error correction capability is improved.

A recording medium reproducing apparatus according to a fourth aspect of the present invention comprises:
Reproducing means for reproducing channel data recorded on a recording medium; demodulating means for obtaining a likelihood for each bit of demodulated data from the reproduced channel data by the demodulating method of the first or second invention; An error correction decoding means for correcting the likelihood error of each bit of the demodulated data and restoring the demodulated data into information data is provided.

According to the above arrangement, the RL is used as the demodulation means.
By using the demodulation means by the L modulation method and using the turbo decoding means as the error correction decoding means,
The error correction capability for the reproduction signal from the recording medium is improved. Therefore, the recording density of the recording medium is increased.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. <First Embodiment> This embodiment relates to an RLL demodulation method for demodulating only p bits of received channel data by a likelihood conversion method.

Generally, RLL demodulation is performed by the following equations (1) and (1).
It can be considered as a function that performs (2) and (3).

[0031] Here, the vector a _'t represents channel data p bits at time t, the vector c' _t represents the sign data m bits restored at time t. Also,
a ′ _{k, t} is the k-th bit in the vector a ′ _t .
c ′ _{j, t} is the j-th bit in the vector c ′ _t .
Further, f ₁ is' from _t, the vector c of m bits of the code data "vector a channel data of p bits received a logical operation function for calculating the _t. Time t is
This represents a time series for calculating equation (1), and is calculated at intervals of m × Tb = n × Tw in the present RLL demodulation. Here, Tb is a data interval before modulation, and Tw is a detection window width. Further, a symbol with a dash “′” indicates that the data is restored after reproduction, and a symbol without a dash “′” indicates that the data is before recording.

Generally, the number p of channel data bits to be subjected to the logical operation at the same time is equal to or more than the number n of bits of the modulated channel data data. Then, m bits of code data before modulation are modulated to n bits of channel data. That is, before and after modulation, m bits of code data correspond to n bits of channel data. On the other hand, when demodulation is considered, when p is equal to n, the corresponding m bits after demodulation are calculated from the n bits of the channel data. If p is greater than n, p including bits before and after this n bits
From the bits, m bits after demodulation will be calculated.
Thus, by performing demodulation based on the equation (1) at each time point, all the code data c ′ _i can be obtained from all the channel data a ′ _i .

The number of combinations of the p bits of the channel data is finite, and there are at most 2 ^p combinations including combinations that do not satisfy the RLL. In practice, there are no combinations that do not satisfy the RLL, so the number of cases will be even less than 2 ^p . Let H be the number of this combination. Then, a combination of m bits of code data corresponding to each of the H combinations of p bits of channel data can be obtained in advance. Therefore, the correspondence of each of the H combinations is defined as ( _Ch , _Ah ). _Ch is the code data m
Represents the h-th combination of bits, and A _h represents the h-th combination of p bits of channel data. That is, as shown in equation (4), If the channel data belongs to the vector A _h is to demodulate the code data of the demodulated vector C _h.
A _{h, k} and _{Ch, j} are constants of either “+1” or “−1”. Also, h = 1, 2,..., H. Since p bits of the channel data before demodulation are handled as a group, a unit of p bits of the channel data before demodulation (that is, the vector a ′ _t ) is referred to as a symbol. Similarly, since m bits of demodulated code data are treated as a group, a unit of m bits of demodulated code data (that is, the vector c ′ _t ) is referred to as a symbol. When p is larger than n, the symbol before demodulation shares the same bit between adjacent symbols.

The correspondence of the H combinations (C _h , A _h )
Corresponds to the symbol correspondence rule of the data before and after demodulation shown in the table. The above equation (1) corresponds to a symbol correspondence rule of data before and after demodulation expressed by a logical equation. That is, the channel data a ′ _{k, t} before demodulation can be obtained by a logical operation circuit that operates the above logical expression, or by referring to a ROM in which the rule table is stored in advance as a table.
Thus, it is possible to calculate the demodulated code data c ′ _{j, t} .

[0035] Now, in the conventional RLL demodulator shown in FIG. 12, the equation (1) a in the _'k, that is serving as the hard information binarized to _t, in the present embodiment, a' _{k , t} are treated as soft information. That is, _{a'k, t} is a real number.

Hereinafter, the likelihood of the channel data a ′ _{k, t} is _expressed as P (a ′ _{k, t} | _{ak, t} = + 1) = 1−P (a ′ _{k, t} | _{ak, t} = −1) ) (5) A method of performing demodulation based on the soft information of a'k _{, t} will be described. Note that P (a ' _{k, t} | a _{k, t} =
+1) is the conditional probability that the reproduced channel data will be _{a'k, t} when the recorded channel data is " _{ak, t} = + 1".

The likelihood of a ′ _t and c ′ _t is given by the following equation (6).
Can be calculated by In the formula (6), P (c ' t | c t = C h) , when the code data c _t is C _h, recovered code data c' is the conditional probability that a _t. Equation (6) represents the likelihood for each combination of all data strings before and after demodulation, that is, the likelihood for each symbol before and after demodulation.

Further, the j th code data c _j in the code data c _t, the likelihood of _t is Becomes Here, the numerator in the formula (7) is H _Ch
Represents the sum of P (c ' _t | c _t = C _h ) only for code data _{Ch, j} equal to “+1”. Also,
The denominator represents the sum of H ways of P ( _c't | _ct = _Ch ). still,
In general, the denominator of Expression (7) does not become “1”. This is because the denominator does not include a combination of channel data that does not satisfy RLL. Equation (7) represents conversion from the likelihood for each symbol after demodulation to the likelihood for each bit after demodulation.

From the above, it is possible to convert the likelihood of each bit before demodulation into the likelihood of each bit after demodulation by using the above equations (6) and (7). That is, first, the likelihood of each bit before demodulation is converted into the likelihood of each symbol after demodulation according to equation (6). Next, the conversion from the likelihood for each symbol after demodulation to the likelihood for each bit after demodulation is performed by equation (7).

In the turbo decoding, soft information of code data is generally represented as a log likelihood ratio. Therefore,
The conversion to the log likelihood ratio L (c ′ _i ) for each bit after demodulation will be described. For example, the log likelihood ratio L (c ′ of code data c _{j, t
j, t} ) Is defined as Here, ln represents a natural logarithmic function. _{Therefore, L (c 'j, t} ) and the code data c _t likelihood P (c' _t | c
_{If t} = C _h, it can be obtained as in the following equation (9) from the equations (7) and (8). Equation (9) is a conversion equation from the likelihood for each symbol after demodulation to the log likelihood ratio for each bit after demodulation. Furthermore, the above equation
Log likelihood ratio L (c in (9) _{'j, t)} and the channel data a _k, the likelihood P of the _{t (a' k, t |} a k, t = + 1) and P (a _{'k, t} | a _{k, t} = -1), the following equation (10) is obtained from the equation (6). Equation (10) is a conversion equation from the likelihood for each bit before demodulation to the log likelihood ratio for each bit after demodulation.

Here, the log likelihood ratio L (a ' _k ) of the channel data a _k is defined as shown in the following equation (11). Then, the following equation (12) is obtained from the equation (11). Here, B _{h, k} = (１) · (A _{h, k} +1) D _{h, k} = (１) · ( _{Ch, k} + 1)

That is, from A _{h, k} ∈ {± 1}, B _{h, k} ∈ {0,
1}. Correspondingly, D _{h, k} is defined similarly.
That is, _{C h, k ∈ {± 1} } than _{D h, k ∈ {0,1}} .
In this manner, B _{h, k} and D _{h, k} can be determined in advance so that A _{h, k} and Ch _{h, k} can be determined in advance.

Therefore, when the log likelihood ratio L (c ′ _{j, t} ) for each bit after demodulation is represented by the log likelihood ratio L (a ′ _{k, t} ) of the channel data a _{k, t} , the following equation is obtained. From (10) and equation (12), the equation
It can be expressed as (13). In equation (13), it is clear that the calculation amount using B _{h, k} is smaller than the calculation using A _{h, k} . This is because L ( _{a'k, t} ) may be summed up only for _{Bh, k} = 1. Therefore, in order to reduce the calculation amount and the calculation time at the time of the RLL demodulation, B _{h, k}
It is more preferable to use the calculation using.

As described above, when the above equation (13) is used, the log likelihood ratio L (c′t) of the demodulated code data is calculated from the log likelihood ratio L (a ′ _{k, t} ) of the channel data before demodulation. _{j, t} ) can be calculated.

From the above, all code data numbers j
If an arithmetic operation function for performing the calculation of the equation (13) and g ₁ for a demodulator according to the likelihood conversion method can be said to be a demodulator for performing an operation of following expression (14). _{(L (c '1, t} ), L (c' 2, t), ..., L (c 'j, t), ..., L (c' m, t)) = g 1 (L (a '1 _{, t), L (a '} 2, t), ..., L (a' k, t), ..., L (a 'p, t)) ... (14) where, g ₁ is reproduced channel It is an arithmetic operation function for calculating each log likelihood ratio of m bits of code data from each log likelihood ratio of p bits of data.

As described above, the serial sequence of the code data is represented by c _i, and the serial sequence of the corresponding channel data is represented by a _i
Then, the log likelihood ratio L (a ′ _i ) for each bit before demodulation is converted to the log likelihood ratio L (c ′ _i ) for each bit after demodulation using the symbol correspondence rules of the data before and after demodulation. You can do it. Hereinafter, the configuration of an RLL demodulator that performs demodulation by the above-described likelihood conversion method will be described with a specific example.

FIG. 1 is a block diagram showing a configuration of an RLL demodulator that performs demodulation by the above likelihood conversion method. The channel data a ′ _i before demodulation reproduced from the recording medium as a communication path is input to the log likelihood ratio calculation circuit 11 at intervals of Tw. Then, the log likelihood ratio calculation circuit 11 calculates the log likelihood ratio, and outputs the log likelihood ratio L (a ′ _i ) of the channel data before demodulation. The contents of the calculation performed by the log likelihood ratio calculation circuit 11 at this time will be described later.

Thus, the log likelihood ratio L (a ′ _i ) of the channel data output from the log likelihood ratio calculation circuit 11 is
The signal is input to the p-stage shift register 12. And the above p
The data is shifted by the stage shift register 12 at intervals of Tw, and the parallel data (L (a'1 _{, t} ), L (a'2 _{, t} ),
, L ( _{a'k, t} ), ..., L ( _{a'p, t} )) are output to the arithmetic operation circuit 13. Then, the arithmetic operation circuit 13 outputs the parallel data (L (a'1 _{, t} ), L (a'2 _{, t} ),..., L
(a ′ _{k, t} ),..., L (a ′ _{p, t} ))
An arithmetic operation is performed based on 4). Then, the parallel data (L (c ′) of the log likelihood ratio of the obtained demodulated code data is obtained.
_{1, t} ), L (c'2 _{, t} ), ..., L ( _{c'j, t} ), ..., L (c'm _{, t} )) are output to the m-stage shift register 14 with the parallel load function. I do.

The m-stage shift register 14 stores parallel data of the log likelihood ratio of the input demodulated code data.
(L (c ′ _{1, t} ), L (c ′ _{2, t} ),..., L (c ′ _{j, t} ),..., L (c ′ _{m, t} )) It shifts every Tb and outputs the log likelihood ratio L (c ′ _i ) of the demodulated code data.
At this time, the arithmetic operation by the arithmetic operation circuit 13 and the parallel load by the m-stage shift register 14 are separated by an interval (mx
The synchronization is performed every Tb). Since the log likelihood ratio is a real number, each of the p-stage shift register 12 and the m-stage shift register 14 holds a real number.

Next, the contents of the calculation by the log likelihood ratio calculation circuit 11 will be described in detail. Generally, this calculation is performed by considering the communication path as a simple noise addition source. That is, the channel data a ′ _i before demodulation is defined by Expression (15). a ′ _i = a _i + n _i (15) n _i : noise added to the channel data a _i Here, assuming that the communication path (recording medium) is a white Gaussian communication path, the log likelihood ratio calculation circuit 11 The log likelihood ratio L (a ′ _i ) of channel data output from
It is required as in (16). _{L (a 'i) = Lc} · a' i ... (16) Lc: CNR (Carrier to Noise Ratio) determined by the constant above the CNR ratio of the power spectral density No amplitude C and the noise n _i channel data C / If the channel is a white Gaussian channel, Lc = 2 × CNR. Therefore, the log likelihood ratio calculation circuit 11 multiplies the input channel data a ′ _i before demodulation by the constant Lc to obtain the log likelihood ratio L (a ′ _i ) of the channel data.

As described above, the RLL in the present embodiment is
The demodulator has a log likelihood ratio calculation circuit 11 to which channel data a ′ _i before demodulation reproduced from the communication path (recording medium) is input at every interval Tw. Then, assuming that the communication channel is a white Gaussian communication channel, the log likelihood ratio L (a ′ _i ) of the channel data is calculated and output according to equation (16). Further, the real log likelihood ratio L (a ′ _i ) is shifted by the p-stage shift register 12 and converted into parallel data. Then, the arithmetic operation circuit 13 calculates the parallel data of the log likelihood ratio of the demodulated m-bit code data for the parallel data from the p-stage shift register 12 based on Expressions (13) and (14). . Finally, the m-stage shift register 14 with the parallel load function
The demodulated parallel data is loaded in parallel, shifted at intervals of Tb, and the log likelihood ratio L of the demodulated code data is calculated.
(c ' _i ) is output.

Therefore, the RLL in the present embodiment is
The demodulated code data output from the demodulator is a real value, and the decoded code data, which is soft information, can be output to the subsequent turbo decoder. in this way,
Turbo decoding becomes possible by using the RLL demodulator by the likelihood conversion method of converting the likelihood before and after demodulation, and the recording density on the recording medium is lower than when a Viterbi decoder having a low error correction capability is used. Can be increased.

Hereinafter, in the RLL demodulator for performing demodulation by the likelihood conversion method shown in FIG. 1, the specific operation of the arithmetic operation circuit 13 for performing the operation based on the above equations (13) and (14) will be described in detail. explain.

FIG. 2 is a diagram showing a "Standardizing Information and Communication System: Sta."
ndardizing Information and Communication Systems ''
7 is a demodulation table of RLL (1, 7) standardized by the standard ECMA-195. In this case, the number of bits of the code data after demodulation is m = 2, and the number of bits of the channel data before demodulation is n = 3. However, in the demodulation table shown in FIG. 2, "1" of the channel bit indicates the polarity inversion of the reproduced signal. Further, “0” of the channel bit indicates that the bit has the same polarity as the immediately preceding bit (that is, retains the previous polarity). Such a signal will be referred to as a signal based on the NRZI rule. Referring to this demodulation table, the arithmetic operation circuit 13 can calculate 2 bits (m = 2) of demodulated code data from 7 bits (p = 7) of channel bits based on the NRZI rule.

FIGS. 3 and 4 are demodulation tables based on the reproduced signal obtained by expanding X in FIG. 2 into 0 and 1. FIG. FIG. 2 shows N
Channel bit notation based on the RZI rule, and FIGS. 3 and 4 are channel bit notation based on a reproduced signal.
The expansion in that case may be performed in consideration of the fact that the channel bits XX based on the NRZI rule are three types of 00, 01, and 10 due to the run length limitation. Note that there are 68 combinations of 8 channel bits based on the reproduced signal (H =
68). FIG. 3 is a demodulation table of the first to 34th demodulation tables. FIG. 4 shows the 35th to 68th demodulation tables. Equation (14) may be calculated based on FIGS. 3 and 4. Further, in the demodulation table of the signal based on the NRZI rule in FIG.
However, as shown in FIGS. 3 and 4, p = 8 in the demodulation table based on the reproduced signal. That is, the tables shown in FIG. 3 and FIG. 4 are the rule tables representing the symbol correspondence rules of the data before and after the demodulation.

FIG. 5 shows a block diagram of an RLL demodulator based on a likelihood conversion method based on RLL (1, 7). As described above, the log likelihood ratio calculation circuit 21 calculates the log likelihood ratio L (a ′ _i ) according to the above equation (16) based on the reproduced signal a ′ _i input for each interval Tw. Output.

The L (a ′ _i ) output from the log likelihood ratio calculation circuit 21 is input to an eight-stage shift register 22.
Then, the data is shifted at intervals of Tw in the eight-stage shift register 22, and the parallel data (L (a'1 _{, t} ), L (a'2 _{, t} ),
, L ( _{a'k, t} ), ..., L (a'8 _{, t} )) are output. The arithmetic operation circuit 23 outputs the input parallel data (L
_{(a '1, t),} L (a' 2, t), ..., L (a 'k, t), ..., L (a' 8, t)) the expression for (13) and ( An arithmetic operation based on 14) is performed, and the parallel data of the log likelihood ratio of the demodulated code data is
(L (c ′ _{1, t} ), L (c ′ _{2, t} )). Note that this RLL
The contents of the arithmetic operation in the case of (1, 7) will be described later. Two-stage shift register 24 with parallel load function
Is the parallel data of the log likelihood ratio of the demodulated code data
(L (c ′ _{1, t} ), L (c ′ _{2, t} )) are parallel-loaded, the data is shifted at intervals of Tb, and the log likelihood ratio L (c ′ _i ) of the demodulated code data is calculated. Output. The arithmetic operation and the parallel loading are performed in synchronization at intervals (2 × Tb) = (3 × Tw).

Next, the arithmetic operation contents of the arithmetic operation circuit 23 will be described in detail. First, the above equation (13) is expressed by the following equation.
Rewrite as (17). Here, exp (N _h ) in Expression (17) corresponds to the h-th row in the demodulation tables shown in FIGS.
N _h is B in the demodulation tables shown in FIGS.
represents the sum of L (a ′ _{k, t} ) where _{h, k} = 1. For example, L (c '
_The case of calculating ( _{1, t} ) will be described. N ₁ corresponding to h = 1 in the demodulation _{table, N 1 = L (a '} 2, t) + L (a' 3, t) + L (a '4, t) + L (a' 5, t) + L ( a ′ _{6, t} ) + L (a ′ _{7, t} ) + L (a ′ _{8, t} ) (18) Since D _1,1 = 0 from the demodulation table (FIG. 3), exp (N ₁ ) is an element of the sum of the denominators in equation (17). Similarly, since D _2,1 ,..., D _30,1 , D _43,1 ,..., D _48,1 = 0, ex = h = 2,.
p (N _h ) is also an element of the sum of the denominators.

N ₃₁ corresponding to h = 31 in the demodulation table is as follows: N ₃₁ = L (a ′ _{5, t} ) + L (a ′ _{6, t} ) + L (a ′ _{7, t} ) + L (a ′) _{8, t} ) ... (19). Further, D _31,1 = 1 from the demodulation table (FIG. 3). Therefore, exp (N ₃₁ ) is an element of the sum of the numerator in equation (17). _{Similarly, D 32,1, ..., D 42,1} , D 49,1, ..., D
_{Since 68,1} = 1, h = 32, ..., 42 and h = 49,
.., 68 exp (N _h ) are also elements of the sum of the molecules.

Thus, 68 in the demodulation table is obtained.
Calculate the N _h of the street, to calculate the exp (N _h) based on the N _h then followed _{exp (N 1), ...,} exp (N 30), exp (N 43), ..., exp
Based on the (N ₄₈₎ to calculate the denominator sum of the above formula _{(17), exp (N 31} ), ..., exp (N 42), exp (N 49), ..., exp
The sum of the molecules is calculated based on (N ₆₈ ). Finally, L (c ′ _{1, t} ) is calculated by the above equation (17).

Similarly, L (c ' _{2, t} ) can be calculated, and the arithmetic operation contents of the arithmetic operation circuit 23 are determined. That is, the arithmetic operation circuit 23 calculates the above equation
By performing arithmetic operations based on (18), (19) and (17), parallel data (L (c ′ _{1, t} ), L (c ′ ₂ ) of the log likelihood ratio of the demodulated code data is obtained. _{, t} )).

Also, as described below, the arithmetic operation circuit 2
3 can be simplified. That is, the expression (17) can simplify the calculation content by approximation as in the expression (20). Here, the first term of the above equation (20) is N _h where D _{h, j} is 1.
Represents the maximum N _h among Similarly, the second term is D _{h, j}
There representing the maximum and becomes N _h in N _h is zero.

According to the above equation (20), the operations of the exponential function “exp” and the natural logarithmic function “ln” can be omitted, and the addition in calculating each of the above N _h and the calculation in calculating the maximum value can be omitted. Parallel data (L (c ′ _{1, t} ), L (c ′ _{2, t} )) of the log likelihood ratio of the code data after demodulation can be calculated only by comparison and final subtraction. Therefore, the arithmetic operation of the arithmetic operation circuit 23 can be greatly simplified.

In the above equation (20), approximation is performed by leaving only the maximum N _h . However, D _h, N _h and D _{h j} is _"1", even if the approximation by leaving a predetermined number of terms from a large section of the values in the N _{h j} is "0" in this order No problem. In that case, it is possible to perform more accurate calculation instead of slightly increasing the calculation amount as compared with the case of the above equation (20).

FIG. 6 is a block diagram different from FIG. 5 in the RLL demodulator based on the likelihood conversion method based on RLL (1, 7). As described above, the log likelihood ratio calculation circuit 31 calculates the likelihood ratio based on the reproduced signal a ′ _i
The log likelihood ratio L (a ′ _i ) is calculated and output according to the above equation (16).

The NRZI rule converter 32 receives the log likelihood ratio L (a ′ _i ) and converts the log likelihood ratio L (z ′ _i ) of the channel data z ′ _i based on the NRZI rule into an interval Tw. Calculate and output each time. At this time, the fact that the channel bit z _i based on the NRZI rule is “+1” indicates that the polarity of the reproduced signal is inverted. The fact that the channel bit z _i based on the NRZI rule is “−1” indicates that the polarity of the reproduced signal is the same as the preceding bit, that is, the pre-polarity is maintained.
FIG. 7 shows a conversion table of the NRZI rule converter 32. In FIG. 7, when the two adjacent bits “a _i−1 ” and “a _i ” have different signs, the polarity is inverted, so that the channel bit z _i based on the NRZI rule is “+1”. In the case of the same code, since the polarity is not inverted, the channel bit z _i based on the NRZI rule
Becomes "-1". Therefore, the log likelihood ratio of the channel bit z _i based on the NRZI rule can be calculated as follows. Here, for example, P (a ' _i-1 | a _i-1 = + 1) is a
_{When i-1} is "+1", it is the conditional probability that the reproduced channel data is a ' _i-1 .

The log likelihood ratio L (z ′ _i ) output from the NRZI rule converter 32 is input to a seven-stage shift register 33. The parallel data (L (z'1 _{, t} ), L (z'2 _{, t} ),
.., L (z ′ _{k, t} ),..., L (z ′ _{7, t} )) are output. The arithmetic operation circuit 34 receives the parallel data (L (z ′ _{1, t} ),
An arithmetic operation is performed on L (z ′ _{2, t} ),..., L (z ′ _{k, t} ),..., L (z ′ _{7, t} ), and the log likelihood ratio of the demodulated code data is calculated. (L (c'1 _{, t} ), L (c'2 _{, t} )). The contents of the arithmetic operation in the case of this RLL (1, 7) will be described later. Two-stage shift register 35 with parallel load function
Is the parallel data of the log likelihood ratio of the demodulated code data
(L (c ′ _{1, t} ), L (c ′ _{2, t} )) are loaded in parallel, the data is shifted at intervals of Tb, and the log likelihood ratio L (c ′ _i ) of the demodulated code data is shifted. Is output. The arithmetic operation and the parallel load are performed in synchronization at intervals (2 × Tb).

Next, the arithmetic operation contents of the arithmetic operation circuit 34 will be described in detail. FIG. 8 is a demodulation table for obtaining demodulated data from channel data based on the NRZI rule.
Shown in The demodulation table in FIG. 8 can be obtained by expanding X in FIG. 2 into 0 and 1. Note that there are 34 combinations (H = 34) as shown in FIG. Therefore, the arithmetic operation circuit 34 has only to calculate Expression (13) with reference to the demodulation table in FIG. In this case, the arithmetic operation of Expression (13) may be performed by replacing the symbol z ′ _i of the channel data based on the NRZI rule input to the arithmetic operation circuit 34 with a ′ _i . Expression (13)
Is rewritten using the channel data symbol z ′ _i based on the NRZI rule, as shown in the following equation (22).

In the case of the RLL demodulator using the NRZI law converter 32 shown in FIG. 6, there are 34 combinations of channel bits z ′ _i . Thus, the NRZI shown in FIG.
Since this is half of the 68 combinations in the case of the RLL demodulator that does not use the law converter, the calculation amount and the calculation time can be reduced.

Next, an error correction method using an RLL demodulator that performs demodulation by the above-mentioned likelihood conversion method (hereinafter, referred to as a likelihood conversion RLL demodulator) will be described. FIG. 9 is a schematic diagram showing a configuration of a recording / reproducing apparatus that realizes the above-described error correction method. The turbo encoder 41 receives the input information data u
It applies error correction coding to _i, and outputs the code data c _i. RLL modulator 42 performs RLL modulation on the inputted code data c _i, and outputs the channel data a _i.
The channel data a _i thus output is stored in the recording circuit 4
3 is recorded on the recording medium 44. Here, the recording circuit 43 performs the recording by magnetic recording, magneto-optical recording, optical recording, or the like.

The reproduction circuit 45 reproduces the channel data a _i recorded on the recording medium 44 and outputs the reproduced channel data a ′ _i . The channel data a ′ _i thus reproduced has undergone deformation such as noise addition, band limitation, intersymbol interference, and crosstalk according to the characteristics of the recording circuit 43, the recording medium 44, and the reproducing circuit 45. That is, in FIG. 9, the recording circuit 43, the recording medium 44
And the reproduction circuit 45 becomes a communication path. as a result,
An error is added to the channel data a ′ _i reproduced from the recording medium 44. The likelihood transforming RLL demodulator 46 performs RLL demodulation on the input channel data a ′ _i before demodulation by the above likelihood transforming method, and outputs a log likelihood ratio L (c ′ _i ) of the demodulated code data. I do. The turbo decoder 47 corrects an error in the input log likelihood ratio L (c ′ _i ) added by the communication path, and outputs restored information data u ′ _i .

In this case, as described above, the likelihood transform RLL demodulator 46 can output the log likelihood ratio L (c ′ _i ) of the coded data as soft information. Therefore, according to the recording / reproducing apparatus shown in FIG. 9, the turbo code method can be applied even when RLL modulation is used. Therefore, the recording density on the recording medium can be increased as compared with the case where the Viterbi encoding method having a low error correction capability is applied.

<Second Embodiment> By the way, as described above, the RLL demodulation in the first embodiment is an RLL demodulating only p bits of received channel data.
This is a demodulation method. However, the demodulation by the above likelihood conversion method can be applied to a demodulation method in which an internal state is held in a demodulator. This embodiment relates to an RLL demodulation method for maintaining an internal state in a demodulator.

The demodulation holding the internal state can be generally regarded as a function that performs the following equation. The vector s' _t represents the current internal state q bits as shown in equation (24). Note that f ₂ is the reproduced p-bit channel data a ′ _t
And a logical operation function for calculating m bits c ′ _t of restored code data from the current internal state s ′ _t of q bits.

The internal state is calculated by the following equation (25). The vector s ′ _{t + 1} has the following internal state q as shown in equation (26).
Represents a bit. Note that f ₃ is the received p-bit channel data a ′ _t
And a logical operation function for calculating the next internal state s ′ _{t + 1} from the current q-bit internal state s ′ _t .

A part or all of the bits of the next internal state s ′ _{t + 1} may be the same as a part or all of the bits of the restored code data c ′ _t . For example, if the internal state is 1 bit (q = 1) and the same as c ′ _{1, t} (s ′ _{t + 1} = c ′ _{1, t} ), Becomes This is in demodulating the channel data a _'t,
This means that the demodulated code data c ′ _{1, t−1} restored immediately before is also referred to.

As described above, in the demodulation method in which the internal state is held in the demodulator, demodulation is performed based on equations (23) and (25).

Now, with respect to the demodulation method based on the above equations (23) and (25), _{a'k, t} is input as soft information and c'k _{, t} is output as soft information as follows. be able to. Formally, the above equations (23) and (25) are now represented by the following equations (28) to (30). Here, c ″ _t represents c ′ _t and s ′ _{t + 1} and is (m + q) bits. Similarly, a '' _t is a 'represents a _t and s' _t, (p +
q) bits.

The above equation (28) is formally equivalent to the above equation (1), and demodulation by the likelihood conversion method is possible in the same manner as in the case of equation (1). That is, Here, B ″ _{h, k} = (１) · (A ″ _{h, k} +1) D ″ _{h, k} = (１) · (C ″ _{h, k} +1)

That is, from A ″ _{h, k}よ り {± 1}, B ″ _{h, k} ∈
{0,1}. Correspondingly, D ″ _{h, k} is defined similarly. _{That, C '' h, k ∈} {± 1} from _{D '' h, k ∈ {} 0,
1}. As described above, B ″ _{h, k} and D ″ _{h, k} can also be obtained in advance so that A ″ _{h, k} and C ″ _{h, k} can be obtained in advance. is there.

The log likelihood ratio can be defined as follows.

Here, the number of (p + q) -bit combinations of (c '' _t , a '' _t ) is H ''. Also, the correspondence of each of the H ″ combinations is (C ″ _h , A ″ _h ). That is, Here, h = 1, 2,..., H ''. The correspondence of the H ″ combinations (C ″ _h , A ″ _h ) is based on the correspondence rule between the data before demodulation and the symbol in the current internal state, and the data after demodulation and the symbol in the next internal state, as shown in the table. Is equivalent to The above equation (28) corresponds to the rule of correspondence between the data before demodulation and the symbol of the current internal state, and the data after demodulation and the symbol of the next internal state, which are expressed by a logical equation. By a logical operation circuit for calculating the above logical expression, or by referring to the ROM storing the rule table in advance as a table _, from the channel data a ′ _{k, t} before demodulation,
This makes it possible to calculate the demodulated code data c ′ _{j, t} .

Thus, by using the above equation (31), the log likelihood ratio L (c ′ _j ) of the demodulated code data is calculated from the log likelihood ratio L (a ′ _{k, t} ) of the channel data before demodulation. _{, t} ) can be calculated using the symbol correspondence rules between the data before and after demodulation, the current internal state, and the next internal state. Therefore, assuming that an arithmetic operation function for performing the operation of Expression (31) for all the code data numbers j is g ₂ , the demodulator based on the likelihood conversion method has the following expression:
It can be said that the demodulator performs (35). (L (c ' _{1, t} ), L (c' _{2, t} ), ..., L (c ' _{j, t} ), ..., L (c' _{m, t} ), L (s' _{1, t + 1 ), L (s '2,} t + 1), ..., L (s' l, t + 1), ..., L (s 'q, t + 1)) = g 2 (L (a' 1, t ), L (a'2 _{, t} ), ..., L ( _{a'k, t} ), ..., L ( _{a'p, t} ), L (s'1 _{, t} ), L (s'2 _{, t} ) ,..., L (s ′ _{l, t} ),..., L (s ′ _{q, t} )) (35) where g ₂ is each of p bits of the reproduced channel data and q bits of the current internal state. An arithmetic operation function for calculating each log likelihood ratio of m bits of code data and q bits of the next internal state from the log likelihood ratio.

[0084] Thus, even when the demodulation method to hold the internal state in the demodulator, the serial sequence of the code data and c _i, the serial sequence of the corresponding channel data if a _i, before demodulation Log likelihood ratio L (a ′ _i )
Can be converted into a log likelihood ratio L (c ′ _i ) for each bit after demodulation. Hereinafter, the operation of the RLL demodulator that performs demodulation by the likelihood conversion method that holds the internal state in the demodulator will be described with a specific example.

FIG. 10 is a block diagram showing the configuration of an RLL demodulator that performs demodulation by the likelihood conversion method that holds the internal state in the demodulator. The channel data a ′ _i before demodulation reproduced from the recording medium as a communication path is input to the log likelihood ratio calculation circuit 51 at each interval Tw. Then, the log likelihood ratio calculation circuit 51 calculates the log likelihood ratio and calculates the log likelihood ratio L of the channel data before demodulation.
(a ' _i ) is output.

Thus, the log likelihood ratio L (a ′ _i ) of the channel data output from the log likelihood ratio calculation circuit 51 is
The signal is input to the p-stage shift register 52. Then, the data is shifted at intervals Tw by the p-stage shift register 52, and the parallel data (L (a'1 _{, t} ), L (a'2 _{, t} ),..., L (a ')
_{k, t} ),..., L ( _{a'p, t} )) are output to the arithmetic operation circuit 53.
Then, the arithmetic operation circuit 53 outputs the input parallel data (L (a'1 _{, t} ), L (a'2 _{, t} ),..., L ( _{a'k, t} ),.
L (a ′ _{p, t} )) and q-bit log likelihood ratios (L (s ′ _{1, t} ), L (s ′ _{2, t} ),..., L (s) representing the current internal state described later. ' _{l, t} ),…,
L (s ′ _{q, t} )) and an arithmetic operation is performed based on Expressions (31) and (35). Then, the parallel data (L (c ′ _{1, t} ), L (c ′ _{2, t} ), of the log likelihood ratio of the code data after demodulation,
.., L (c ′ _{j, t} ),..., L (c ′ _{m, t} )) and q representing the next internal state
The log likelihood ratio of each bit (L (s'1 _{, t + 1} ), L (s'2 _{, t + 1} ), ...,
L (s ′ _{l, t + 1} ),..., L (s ′ _{q, t + 1} )).

The m-stage shift register 54 with the parallel load function stores parallel data (L (c ′ _{1, t} ), L) of the log likelihood ratio of the code data demodulated from the arithmetic operation circuit 53.
(c ′ _{2, t} ),..., L (c ′ _{j, t} ),..., L (c ′ _{m, t} )) are parallel loaded, the data is shifted at intervals of Tb, and The log likelihood ratio L (c ′ _i ) is output. The log likelihood ratio (L) representing the next internal state from the arithmetic operation circuit 53
(s'1 _{, t + 1} ), L (s'2 _{, t + 1} ), ..., L ( _{s'q, t + 1} )) are input to registers 55a, 55b, ..., 55d, respectively. The registers 55a, 55b,..., 55d correspond to the respective bits indicating the internal state. Therefore, the registers 55a, 55b,
The total number of registers of 55d is q. Register 5 above
5a is the first log likelihood ratio L (s'1 _{, t + 1} ) of the next internal state
Is loaded and held at intervals (mxTb). And
At the next time point, it outputs to the arithmetic operation circuit 53 as the _first log likelihood ratio L (s'1 _{, t} ) of the current internal state.
Similarly, the other registers 55b,..., 55d have the second,..., Q-th log likelihood ratios L (s ′) in the next internal state.
_{2, t + 1} ), ..., L ( _{s'q, t + 1} ) and the second, ..., qth log likelihood ratio L of the current internal state
(s ′ _{2, t} ),..., L (s ′ _{q, t} ). At this time, the arithmetic operation by the arithmetic operation circuit 53, the parallel load by the m-stage shift register 54, the registers 55a,.
The loading by 55d is performed synchronously at intervals (m × Tb).

As described above, the RLL in the present embodiment is
The demodulator shifts the log likelihood ratio L (a ′ _i ) of the channel data before demodulation input from the log likelihood ratio calculation circuit 51 by the p-stage shift register 52 and converts it into parallel data. Then, the arithmetic operation circuit 53 stores the parallel data from the p-stage shift register 52 and the registers 55a to 55d.
For each log likelihood ratio representing the current internal state from
By performing the arithmetic operations of 1) and (35), the parallel data of the log likelihood ratio of the demodulated code data and each log likelihood ratio representing the next internal state are calculated. Finally, the demodulated parallel data is parallel-loaded by the m-stage shift register 54 with a parallel load function, shifted at intervals of Tb, and the log likelihood ratio L (c ′ _i ) of the demodulated code data is calculated. Output.

The log likelihood ratios representing the next internal state from the arithmetic operation circuit 53 are stored in the registers 55a to 55d.
At each interval (m × Tb). Then, at the next time, the log likelihood ratio of the current internal state is output to the arithmetic operation circuit 53.

Therefore, the RLL in the present embodiment
The demodulated code data output from the demodulator is a real value, and the decoded code data as soft information can be output to the subsequent turbo decoder. Thus,
This makes it possible to use an error correction decoder or the like having a high error correction capability, and to increase the recording density on a recording medium.

Of course, also in the case of the present embodiment, the first
As in the case of the embodiment, the exponential function "e
It is possible to apply a simplification method that eliminates the operations of “xp” and the natural logarithmic function “ln”, and the arithmetic processing by the arithmetic operation circuit 53 can be simplified.

In each of the above embodiments, the log likelihood ratio is a real number.
52, m-stage shift register 14.54 and register 55
Each of the registers a to 55d holds a real number. This real number may be a number quantized with floating point precision or fixed point precision. Further, it may be an integer-precision number. In general, the arithmetic precision is lower in the order of floating point precision, fixed point precision, and integer precision.

In each of the above embodiments, turbo coding is used as error correction coding. However, the present invention is not limited to this, and any error correction method for soft information input may be used. In this case, the turbo encoder 41 in FIG. 9 may be an error correction encoder, and the turbo decoder 47 may be an error correction decoder.

The modulation system is not limited to the above run-length limited modulation. The present invention may be applied to any modulation scheme based on a symbol correspondence rule in data before and after demodulation, or a modulation scheme based on a correspondence rule between data before demodulation and a symbol in a current internal state and data after demodulation and a symbol in a next internal state. You can do it.

In each of the above embodiments, a time-invariant demodulation method is used, but the present invention is not limited to this. Here, the time-invariant demodulation method is expressed by Equation (1) or Equation (1).
This means that the function of (28) does not change with respect to the time point t. However, the present invention can be applied to a time-varying demodulation method. Here, the time-varying demodulation method means that the function of Expression (1) or Expression (28) changes with respect to the time point t. When a time-varying demodulation method is applied, a function for performing likelihood conversion may be changed in response to a change in the function of equation (1) or equation (28). That is, the function of Expression (14) or Expression (35) may be changed for each time point.

[0096]

As is clear from the above description, the demodulation method of the first invention calculates the likelihood of each bit of the data before demodulation by the likelihood calculation means, and the demodulation calculation means calculates the likelihood of the symbol before and after the demodulation data. Based on the rule, the likelihood of each bit of the demodulated data, which is a real number, is obtained from the likelihood of each bit of the pre-demodulation data, so that a demodulation method capable of outputting soft information can be realized.

In the demodulation method according to the second invention, the likelihood calculating means calculates the likelihood for each bit of the data before demodulation,
The demodulation operation means calculates the real number of the demodulated data, which is a real number, from the likelihood of each bit of the pre-demodulation data on the basis of the correspondence rules between the pre-demodulation data and the symbol in the current internal state, the demodulated data and the symbol in the next internal state. Since the likelihood for each bit is obtained, a demodulation method capable of outputting soft information can be realized.

Further, in the demodulation method of one embodiment, since the symbol correspondence rule is a rule table, the likelihood for each bit of the data after demodulation by the demodulation calculation means is calculated from the likelihood for each bit of the data after demodulation. Can be converted by an arithmetic operation derived based on the rule table.

In the demodulation method of one embodiment, since the symbol correspondence rule is a logical expression, the likelihood of each bit of the data after demodulation by the demodulation operation means is calculated from the likelihood of each bit of the data after demodulation. Can be converted by an arithmetic operation derived based on the above logical expression.

In the demodulation method of the first embodiment, since the log likelihood ratio is used as the likelihood for each bit, a turbo decoding method using the log likelihood ratio as an input is used as an error correction decoding method after demodulation. be able to.

In the demodulation method of one embodiment, since the symbol correspondence rule is a symbol correspondence rule based on the RLL modulation method, a demodulation method based on the RLL method can be realized. Therefore, the present invention can be applied to demodulation of a reproduction signal from a recording medium that requires the RLL modulation method.

An error correction method according to a third aspect of the present invention is an error correction method for the bit likelihood of each bit of the demodulated data obtained as soft information by the demodulation method of the first or second aspect. Therefore, error correction by turbo decoding can be applied, and the error correction capability can be improved.

The recording medium reproducing apparatus of the fourth invention is
The channel data recorded on the recording medium is reproduced by the reproducing means, and the likelihood for each bit of the demodulated data is obtained from the reproduced channel data by the demodulating means in accordance with the demodulating method of the first or second invention, Since the error of the likelihood of each bit of the demodulated data is corrected by the error correction decoding means, the RLL demodulation means can be used as the demodulation means, and the turbo decoding means can be used as the error correction decoding means. The error correction capability for the reproduced signal from the device can be improved. Therefore, the recording density of the recording medium can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an RLL demodulator that performs demodulation by a likelihood conversion method as a demodulation method according to the present invention.

FIG. 2 is a diagram showing a demodulation table of RLL (1, 7) standardized by standard ECMA-195.

FIG. 3 is a diagram showing a demodulation table based on a reproduced signal in which X of FIG. 2 is expanded into 0 and 1;

FIG. 4 is a diagram showing a demodulation table following FIG. 3;

FIG. 5 is a block diagram of an RLL demodulator based on RLL (1, 7).

FIG. 6 is different from FIG. 5 based on RLL (1, 7).
It is a block diagram of an L demodulator.

7 is a diagram showing a conversion table in the NRZI rule converter in FIG. 6;

FIG. 8 is a diagram showing a demodulation table for obtaining demodulated data from channel data based on the NRZI rule.

9 is a configuration diagram of a recording / reproducing apparatus using the RLL demodulator shown in FIG.

FIG. 10 is a block diagram of an RLL demodulator that performs demodulation by a likelihood conversion method that retains an internal state.

FIG. 11 is a configuration diagram of a recording / reproducing apparatus that performs an encoding process and a decoding process of a turbo code.

FIG. 12 is a block diagram of a conventional RLL demodulator.

[Explanation of symbols]

 11,21,31,51 ... log likelihood ratio operation circuit, 12,52 ... p-stage shift register, 13,23,34,53 ... arithmetic operation circuit, 14,54 ... m-stage shift register, 22 ... 8-stage shift Register: 24, 35: two-stage shift register, 32: NRZI law converter, 33: seven-stage shift register, 41: turbo encoder, 42: RLL modulator, 43: recording circuit, 44: recording medium, 45: Reproduction circuit, 46: likelihood conversion RLL demodulator, 47: turbo decoder, 55a to 55d: registers.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 7/14 H03M 7/14 A 13/45 13/45 F-term (Reference) 5B001 AA03 AB02 5D044 AB01 BC01 BC04 CC04 GL02 GL28 GL31 GL50 5J065 AC03 AD03 AF01 AG05 AH05 AH15 AH21

Claims (8)

[Claims] 1. A demodulation method for calculating post-demodulation data from data before demodulation by demodulation operation means based on a symbol correspondence rule of data before and after demodulation using a group of continuous bits in digital data as a symbol. The likelihood of each bit of the input data before demodulation is calculated by the demodulation calculation means, and the likelihood of each bit of the data before demodulation is calculated for each symbol of the data after demodulation based on the symbol correspondence rule. The likelihood is calculated, the likelihood of each bit of the demodulated data is calculated from the likelihood of each symbol of the demodulated data, and the likelihood of each bit of the demodulated data is calculated from the likelihood of each bit of the data before demodulation. A demodulation method characterized by obtaining likelihood. 2. A correspondence rule between data before demodulation, a symbol in the current internal state of the demodulation operation means, a data after demodulation, and a symbol in the next internal state of the demodulation operation means, using a group of continuous bits in the digital data as a symbol. A demodulation method for calculating post-demodulation data from pre-demodulation data by the demodulation calculation means based on the likelihood calculation means; calculating likelihood for each bit of the input data before demodulation by the likelihood calculation means; From the likelihood for each bit of the data before demodulation and the likelihood for each bit of the current internal state, the likelihood for each symbol of the demodulated data and the likelihood for each symbol of the next internal state based on the symbol correspondence rule. Is calculated, and the likelihood of each bit of the demodulated data is calculated from the likelihood of each symbol of the demodulated data, and the likelihood of each symbol in the next internal state is calculated. Luo by calculating the likelihood of each bit of the next internal state, the demodulation method characterized by obtaining a likelihood of each bit of the data after the demodulation from likelihood of each bit of the demodulated data before. 3. The demodulation method according to claim 1, wherein the symbol correspondence rule is a rule table. 4. The demodulation method according to claim 1, wherein the symbol correspondence rule is a logical expression. 5. The demodulation method according to claim 1, wherein a log likelihood ratio is used as the likelihood for each bit. 6. The demodulation method according to claim 1, wherein the symbol correspondence rule is a symbol correspondence rule based on a run-length limited modulation method. 7. An error correction means for error-by-bit likelihood of each bit of the demodulated data obtained from the data before demodulation by the demodulation method according to any one of claims 1 to 6. An error correction method characterized by correcting the error. 8. A demodulating means for reproducing channel data recorded on a recording medium, and demodulated data from the reproduced channel data by a demodulating method according to any one of claims 1 to 6. Demodulation means for obtaining the likelihood of each bit of the data, and correcting the error of the likelihood of each bit of the demodulated data,
A recording medium reproducing apparatus comprising an error correction decoding means for restoring information data.