JP2002359343A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily materialize hollow structure without necessity of performing capping or resin sealing for protection of the device of a bare chip, and besides is possible of multistage stacking in such a way that two circuits can be easily stacked vertically in two stages, etc. SOLUTION: A first dielectric substrate 13 is formed by laminating a first dielectric layer 9, and a second dielectric layer 10 in this order. The first dielectric layer 9 has a first metallized layer 3 on the lower surface, and a second metallized layer 4 on the upper surface. The second dielectric layer 10 has a third metallized layer 5 on the upper surface, and a part thereof is hollowed out. A second dielectric substrate 14 is also laminated in the same manner as the first dielectric substrate 13. These two substrates 13, 14 are overlapped to constitute a space surrounded by the hollow parts. In the space, a pallet 1 of a semiconductor device or a piezoelectric device and a chip 2 of capacitor, inductor, resistor or the like are mounted at a fifth metallized layer 7 on a fourth dielectric layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device mounted with a semiconductor device or a piezoelectric device and suitable for a high-frequency circuit.

[0002]

2. Description of the Related Art Conventionally, this type of semiconductor device has a structure in which pellets and chip parts are mounted on a dielectric substrate and a cap is hermetically sealed. When it is desired to make the component mounting portion 16 hollow, for example, in the prior art 1 (Japanese Patent Laid-Open No. Hei 7-93389) shown in FIG. The confidentiality is obtained by filling the space 14 with the resin 14 or the like.
On the other hand, in the case of a two-stage circuit, an idea has been proposed in which the wiring 5 is provided on the cap 6 and the component 8 is mounted as in the prior art 2 (Japanese Patent Laid-Open No. Hei 1-286353) shown in FIG. I have. In this case, the package has a structure in which the upper circuit and the lower circuit are not connected, but are connected on a mounting substrate by soldering when the package is mounted. FIG. 12 shows a conventional technique 3 (Japanese Patent Laid-Open No. 7-94).
No. 670), the component 35 is mounted on the cap 30, and the circuit on the cap 30 and the circuit on the lower dielectric substrate 10 are electrically connected to each other through the through hole 12. The circuit and the lower circuit are connected. In each of the prior arts 2 and 3, only the circuit on one plane is formed in the hollow portion. In the prior art 4 (actually disclosed in Japanese Unexamined Utility Model Publication No. 5-62056) shown in FIG. f, 15 to 17 are mounted to form a circuit, and are joined face-to-face with the support bases 11 and 12 having connectors attached therebetween, and the circuit is put in the cavity by using two planes to reduce the mounting density. I'm giving it.

Further, a semiconductor device using a stacked package and a method of manufacturing the semiconductor device, which is “thin and excellent in hermeticity and elasticity and can be easily formed with a simple manufacturing process”, is disclosed in JP-A-2001-68624. It is proposed by the gazette. FIG. 14 shows a semiconductor device using the stacked package. The semiconductor device shown in FIG. 14 includes a plurality of piers having connection electrodes formed under the lands 17, a plurality of wiring boards 30 including wirings 8 electrically connected to the connection electrodes, and a plurality of wiring boards 30 mounted on the wiring board 30. A semiconductor element 5 electrically connected to the wiring, and a chip capacity portion 12 larger than the volume of the semiconductor element when the semiconductor element 5 is mounted. And a plurality of conductive peer insulating substrates 20 each having a connection electrode formed thereon. Thus, the thickness of the semiconductor device is about 30 to 200 μm. By doing this,
A semiconductor device having a thin stacked package can be obtained. According to the semiconductor device obtained in this way, even if the semiconductor device is slightly extended by bending the semiconductor device, the space between the semiconductor device and the tip-capacity portion absorbs the extension of the semiconductor element. The prior art described in this publication also has the following disadvantages. . Since there are no patterns in the space and the thickness of the space is as thin as 30 to 200 μm, chip components (capacitors,
(E.g., inductance) cannot be mounted, and a module cannot be configured. . The PKG requires a large number of substrates to construct the PKG, and particularly requires upper and lower lid substrates. Therefore, the structure is complicated and assembly accuracy is required. . The electrical characteristics cannot be checked for each layer, and rework in the case of defective assembly sorting cannot be performed for each layer.

<Primary Defects of the Prior Art> The prior arts 1, 2 and 3 are disadvantageous in that the dielectric substrate and the cap are expensive because they are made of ceramic, and the structure in which the cap is merely placed on the substrate. Therefore, there is a disadvantage that the structure becomes complicated. This is accompanied by a decrease in package yield and an increase in the number of steps, and as a result, there is a disadvantage that the cost is increased including the above-mentioned disadvantage. The prior art 4 also has many drawbacks, such as a support base and a connector for connecting the boards, and has a drawback that the manufacturing is troublesome, resulting in a high cost.
In any of the prior arts, since the connection method of the upper circuit and the lower circuit or the substrate structure is complicated, it is not possible to further increase the number of circuits in structure.

<Reason for causing the above-mentioned drawback> The use of ceramics and the roles of the cap and the substrate are separately handled, so that the structures of the substrate and the cap are different, resulting in a complicated structure or connection of two circuits. The method was complicated. This is because there was no effective method for connecting the upper circuit and the lower circuit when the circuit was vertically stacked and the hollow portion was formed, because the mounting substrate was considered to serve as the mounting substrate.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and has as its object to solve the above drawbacks and to protect bare chip devices. Provided is a semiconductor device which does not need to be sealed with a cap or resin, can easily realize a hollow structure, and can easily stack two circuits in two stages, such as two stages. It is in.

<Characteristics of the Invention> By stacking a dielectric substrate having a multilayer structure partially dug into an intermediate layer, the dug portion becomes a hollow structure surrounded by the dielectric substrate.
A semiconductor device or a piezoelectric device is mounted on a hollow structure portion of a dielectric substrate having a multilayer structure having at least two layers. Further, a metallized layer is formed on a dielectric layer constituting a dielectric substrate having a multilayer structure, and the metallized layers are electrically connected.

A semiconductor device according to the present invention that achieves the above object has the following features. 1: a first dielectric layer having a metallized layer formed on both sides, and a third metallized layer 5 on one or both sides
Formed, a first dielectric substrate formed by laminating a part of the second dielectric layer, and a third dielectric layer having a metallized layer formed on one or both surfaces, A metallized layer is formed on one or both surfaces, a second dielectric substrate formed by laminating a fourth dielectric layer partially hollowed out, and the first dielectric substrate, A first through hole for electrically connecting each metallized layer of the dielectric substrate, and a second through hole for electrically connecting each metallized layer of the second dielectric substrate to the second dielectric substrate And a multilayer substrate formed by laminating the first and second dielectric substrates so as to form a mounting space for mounting circuit elements, and mounted on a metallization layer in the mounting space. And a circuit element. 2: The multi-layer substrate is a multi-layer substrate configured by laminating the partly hollowed-out second dielectric layer and the partly hollowed-out fourth dielectric layer so as to face each other. 2. The semiconductor device according to the above item 1, wherein 3: The semiconductor device according to 1 or 2, wherein a circuit element is mounted on a metallized layer formed on the first and third dielectric layers in the mounting space of the multilayer substrate. 4: The semiconductor device according to the above item 3, wherein the circuit element is flip-chip mounted on the substrate by bumps. 5: The metallized layers of the first and second dielectric substrates are connected by a conductive adhesive, and at the same time, the second dielectric layer and the fourth dielectric layer are bonded by the conductive adhesive. 5. The semiconductor device according to any one of 1 to 4, wherein a circuit element mounted in the mounting space is electrically connected. 6: The semiconductor device according to the item 3, wherein a circuit element is also mounted on a metallization layer formed on a surface of the third dielectric layer outside the mounting space. 7: The semiconductor device according to any one of 1 to 6, wherein at least two or more multilayer substrates of the semiconductor device according to claim 1 are stacked. 8: The semiconductor device according to any one of 1 to 7, wherein terminal electrodes for input / output and GND are provided on a metallized layer formed on a surface of the first dielectric layer outside the mounting space. 9: A first dielectric layer having a metallized layer formed on both surfaces thereof, and a second dielectric layer having a third metallized layer formed on one surface or both surfaces and partially hollowed out. A dielectric substrate, a third dielectric layer having a metallized layer formed on one or both surfaces, and a fourth dielectric layer having a metallized layer formed on one or both surfaces and partially cut away, A second dielectric substrate, a through-hole for electrically connecting each of the metallized layers of the first and second dielectric substrates, and a second dielectric layer partially hollowed out. And a third dielectric layer to form a mounting space for mounting circuit components thereon, a multi-layer substrate configured by laminating both, and a metallized layer of the first dielectric layer in the mounting space, And the second part in the part where the part is hollowed out. A semiconductor device comprising: the circuit element which is Tosai on the metallized layer of the dielectric layer, in that it consists of. 10: The semiconductor device according to the item 3, wherein the circuit element is flip-chip mounted on a substrate by bumps. 11: connecting the metallized layers of the first and second dielectric substrates with a conductive adhesive, and simultaneously bonding the second dielectric layer and the third dielectric layer with the conductive adhesive, 11. The semiconductor device according to the item 9 or 10, wherein a circuit element mounted in the mounting space is electrically connected. 12: The semiconductor device according to any one of 9 to 11, wherein terminal electrodes for input / output, GND, and the like are provided on a metallized layer formed on a surface of the first dielectric layer outside the mounting space. 13: A first dielectric layer having a metallized layer formed on both surfaces thereof, and a second dielectric layer having a third metallized layer 5 formed on one surface or both surfaces and partially hollowed out. One dielectric substrate, a metallized layer formed on one or both surfaces, a fourth dielectric layer partially hollowed out, and a third dielectric layer having a metallized layer formed on one or both surfaces, respectively. A second dielectric substrate configured by laminating the first dielectric substrate, a first through hole for electrically connecting each metallized layer of the first dielectric substrate, A second through hole that electrically connects each metallization layer of the second dielectric substrate to the second dielectric substrate, and the first dielectric substrate so as to form a mounting space for mounting a circuit element. And fourth dielectric layers of the body substrate Are formed on the metallized layer formed on the first dielectric layer in the mounting space and outside the mounting space of the metallized layer formed on the third dielectric layer in the mounting space. And a circuit element mounted on the metallized layer. 14: The semiconductor device according to the above 13, wherein the circuit component mounted in the mounting space is a circuit component requiring protection. 15: The semiconductor device according to 13 or 14, wherein a terminal electrode for input / output and GND is provided on a metallized layer formed on a surface of the first dielectric layer outside the mounting space. 16: a first dielectric layer having a metallized layer formed on both surfaces thereof, and a second dielectric layer having a third metallized layer formed on one or both surfaces and partially hollowed out, A dielectric substrate, a third dielectric layer having a metallized layer formed on one or both surfaces, and a fourth dielectric layer having a metallized layer formed on one or both surfaces and partially cut away are laminated. A second dielectric substrate configured as described above, a through hole for electrically connecting each of the metallized layers of the first and second dielectric substrates, and a second dielectric layer in which the part is cut out. A third dielectric layer and a multilayer substrate formed by laminating both, so as to form a mounting space for mounting circuit components, and a metallized layer of the first dielectric layer in the mounting space, and , Within the part where the part is hollowed out A circuit element mounted on a metallization layer of a dielectric layer, and a semiconductor device comprising a fifth dielectric layer having a metallization layer formed on one or both surfaces, and a metallization layer formed on both surfaces, and A third dielectric substrate formed by laminating an uncut sixth dielectric layer, and a through-hole for electrically connecting a metallized layer of the third dielectric substrate; A fifth dielectric layer and the fourth dielectric layer are laminated, and a circuit component is mounted on a metallized layer on the fifth dielectric layer in the hollowed portion of the sixth dielectric. A semiconductor device characterized by the above-mentioned. 17: The metallization layer of the second dielectric layer and the metallization layer of the third dielectric layer, and the metallization layer of the fourth dielectric layer and the metallization layer of the fifth dielectric layer are electrically conductive. At the same time as connecting with an adhesive, bonding the second dielectric layer and the third dielectric layer, and bonding the fourth dielectric layer and the fifth dielectric layer with the conductive adhesive, respectively. 17. The semiconductor device according to the item 16, wherein a circuit element mounted in the mounting space is electrically connected to the circuit element. (18) The semiconductor device according to (16) to (17), wherein a terminal electrode for input / output, GND, and the like is provided on a metallized layer formed on a surface of the first dielectric layer outside the mounting space.

Further, a semiconductor device according to the present invention has the following features. 19: Dielectric formed by laminating a first dielectric layer having a metallized layer formed on both surfaces thereof and a second dielectric layer having a third metallized layer formed on one surface and partially cut away A semiconductor device using a substrate for a semiconductor device, comprising: a substrate; and a through hole for electrically connecting each metallization layer of the dielectric substrate. 20: A first dielectric layer including a metallized layer formed on one surface in a peripheral portion and a metallized layer formed on the other surface, and a second dielectric formed with a third metallized layer formed on one surface and partially cut away A semiconductor using a semiconductor device substrate, comprising: a dielectric substrate formed by stacking layers; and a through hole that electrically connects each metallized layer of the dielectric substrate. apparatus.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

<Structure of the first embodiment of the present invention> FIG.
Is shown in FIG. 2, which will be described with reference to FIG. In the surface-mount type semiconductor device of the first embodiment, a terminal electrode 17 for inputting / outputting a signal and a G
A terminal electrode composed of the ND electrode 16 is provided. The first dielectric substrate 13 has a first dielectric layer 9 having a first metallized layer 3 formed on a lower surface (see the drawing) and a second metallized layer 4 formed on an upper surface (see the drawing). , And a second dielectric layer 10 having a third metallized layer 5 formed on an upper surface (see the drawing) in this order.
A part of the second dielectric layer 10 is hollowed out, and a chip 1 such as a semiconductor device or a piezoelectric device and a chip component 2 such as a capacitor, an inductor or a resistor are formed in the hollowed portion on the first dielectric layer 9. It is mounted on the second metallization layer 4. Similarly, the second dielectric substrate 14 includes a third dielectric layer 11 having a fourth metallized layer 6 formed on the upper surface (see the drawing) and a fifth metallized layer 7 formed on the lower surface, A fourth dielectric layer 12 having a sixth metallized layer 8 formed on its surface (see the drawing) is laminated in this order. A part of the fourth dielectric layer 12 is cut out in the same manner as the first dielectric substrate 13,
A pellet 1 which is a semiconductor device or a piezoelectric device and a chip component 2 such as a capacitor, an inductor or a resistor are mounted on the fifth metallized layer 7 on the fourth dielectric layer 12 in the hollow portion. The third metallized layer 5, the second metallized layer 4, and the first metallized layer 3 are electrically connected to each other by through holes 15 in the first dielectric substrate 13, and the fourth metallized layer 6 is formed in the second dielectric substrate 14. And the fifth metallized layer 7 and the sixth metallized layer 8 are electrically connected to each other by through holes. The third metallization layer 5 and the sixth metallization layer 8 are connected by a conductive adhesive 19 and simultaneously the second dielectric layer 1
The circuit element formed on the first dielectric substrate 13 and the circuit element formed on the second dielectric substrate 14 are formed by bonding the first and fourth dielectric layers 12 with the conductive adhesive 19. Are electrically connected. Therefore, the mounting portion of the pellet 1 and the component 2 has a hollow structure surrounded by the first dielectric substrate 13 and the second dielectric substrate 14.

<Operation of First Embodiment> In the surface mount type semiconductor device of the first embodiment, the circuit wiring of the circuit formed in the hollow portion surrounded by the multilayer substrate is formed by the through hole 15 of the multilayer substrate. Different metallization layers 3
8 are connected to the circuits configured as described above to form one circuit as a whole. Further, a part of the wiring is connected to a terminal electrode 17 on the first metallization layer 3 serving as a mounting surface through a through hole 15, and the input / output of a signal and the feed of a power supply are performed from the terminal electrode 17.

<Explanation of Effect> A hollow portion in which devices are mounted is formed by stacking substrates having the same structure with dug-out portions, and the entire structure is a multilayer substrate. That is,
Since the multilayer substrate itself also functions as a device container, there is no need to provide a cap or resin sealing for protecting the bare chip device, and a hollow structure can be easily realized. Further, since the upper and lower circuits are electrically connected to each other and can be stacked in two stages, two circuits can be easily stacked vertically in two stages. Further, since the upper and lower substrate structures around the hollow have the same outer structure, multi-stage stacking or the like is also possible.

<Other Embodiments of the Invention> In the first embodiment shown in FIG. 2, the pellets are connected to the metallization on the substrate by wire bonding, while the second embodiment shown in FIG. 3 is shown in FIG. As described above, the present invention can also be applied to a case where flip-chip mounting is performed using bumps. The following figures will be described with reference to a case where flip-chip mounting is performed.

FIG. 4 shows a third embodiment. In the third embodiment, when connecting the first dielectric substrate 13 and the second dielectric substrate 14, the second dielectric substrate 14 is dug. This is an example in which the fourth metallization layer 8 and the third metallization layer 5 are connected such that the surface into which the metallization is inserted is opposite to that in FIG.

FIG. 5 shows a fourth embodiment, in which a circuit is formed in the fourth metallization layer 6 in the second embodiment of FIG. FIG. 6 shows a fifth embodiment in which there is no circuit configured in the fifth metallization layer 7 in the fourth embodiment of FIG. 5, but in this configuration, protection is provided as in the sixth embodiment shown in FIG. It is conceivable that only the pellet 1 to be mounted is mounted in the hollow portion and the chip component is formed on the surface.

FIG. 8 shows a seventh embodiment. In contrast to the third embodiment shown in FIG. 4, a third dielectric substrate having the same structure as the first dielectric substrate 13 and the second dielectric substrate 14 is shown. 26 is an example in which 26 is further stacked. FIG. 9 shows a seventh embodiment, in which two second embodiments of FIG. 3 are stacked.

In the first to eighth embodiments shown in FIGS. 2 to 9, the circuits in each layer are shown with one pellet and one chip component. It is also conceivable that the quantity is one and plural respectively.

In the first embodiment shown in FIG. 2, the first dielectric substrate 13 and the second dielectric substrate 14 which are dug are each a two-layer substrate. Although the first dielectric substrate 13 and the second dielectric substrate 14 may be multilayer substrates each having two or more layers, the first dielectric substrate 13 and the second dielectric substrate The number of 14 layers may be different. This is the same for the second to eighth embodiments of FIGS. 3 to 9.

FIGS. 2 to 9 In the first to eighth embodiments, the GND electrode is connected to the metallization on the side surface of the substrate and is further connected to the uppermost metallization layer. The metallized layer is not necessarily the uppermost layer and can be connected to any metallized layer. Further, the metallization on the side surface may not be required, and the GND electrode may be connected to another metallization layer via a through hole. Further, the terminal electrode may be connected to another metallized layer via the metallized surface.

[0021]

According to the present invention, a cavity in which a device is mounted is formed by stacking substrates having the same external structure with a dug-out portion, and a multilayer substrate is formed as a whole. That is, since the multilayer substrate itself also serves as a device container, there is no need to perform capping or resin sealing for protecting the bare chip device, and a hollow structure can be easily realized. Further, since the upper and lower circuits are electrically connected to each other and can be stacked in two stages, two circuits can be easily stacked vertically in two stages. Further, since the substrate structure around the hollow is the same structure in the upper and lower parts, multi-stage stacking is also possible.

In particular, the present invention forms a metallized layer on each of the dielectric layers constituting the multilayer substrate and electrically connects the metallized layers to each other, as compared with the structure described in JP-A-2001-68624. are doing. Therefore, since patterning can be performed, wiring between components can be performed and a module can be obtained. Also, the thickness of the space is 3
The module can be thickened to about 0 μm to 2 mm, and can be a module on which various components can be mounted. Also, since there is no upper lid and lower lid, the number of parts can be reduced, the connection method of the upper circuit and the lower circuit or the substrate structure can be simplified, the assembling accuracy can be improved, the assembling process can be reduced, and the circuit can be multistage. . Further, according to the present invention, an electrical check can be performed for each layer, so that a defective assembly rate can be reduced.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of the present invention.

FIG. 2 shows a first embodiment of the present invention.

FIG. 3 shows a second embodiment of the present invention.

FIG. 4 shows a third embodiment of the present invention.

FIG. 5 is a fourth embodiment of the present invention.

FIG. 6 shows a fifth embodiment of the present invention.

FIG. 7 shows a sixth embodiment of the present invention.

FIG. 8 shows a seventh embodiment of the present invention.

FIG. 9 shows an eighth embodiment of the present invention.

FIG. 10 is a prior art 1

FIG. 11 is prior art 2

FIG. 12 is prior art 3

FIG. 13 is prior art 4

FIG. 14: Prior art 5

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Takashi Nakajima 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation

Claims (20)

[Claims] 1. A first dielectric layer having a metallized layer formed on both sides thereof, and a second dielectric layer having a third metallized layer 5 formed on one or both sides and partially hollowed out. A first dielectric substrate, a third dielectric layer having a metallized layer formed on one or both surfaces, respectively, and a fourth metallized layer formed on one or both surfaces and partially cut away. A second dielectric substrate formed by laminating a dielectric layer; and a first through hole electrically connecting each metallized layer of the first dielectric substrate to the first dielectric substrate. And a second through hole for electrically connecting each metallization layer of the second dielectric substrate to the second dielectric substrate, and a mounting space for mounting a circuit element,
A semiconductor device comprising: a multilayer substrate formed by laminating the first and second dielectric substrates; and a circuit element mounted on a metallized layer in the mounting space. 2. The multi-layer substrate according to claim 1, wherein the multi-layer substrate is formed by laminating the second dielectric layer partially hollowed and the fourth dielectric layer partially hollow. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 1, wherein circuit elements are mounted on metallized layers formed on the first and third dielectric layers in the mounting space of the multilayer substrate. 4. The circuit element according to claim 3, wherein the circuit element is flip-chip mounted on the substrate by bumps.
13. The semiconductor device according to claim 1. 5. The metallized layers of the first and second dielectric substrates are connected with a conductive adhesive, and at the same time, the second dielectric layer and the fourth dielectric layer are bonded with the conductive adhesive. 5. The semiconductor device according to claim 1, wherein a circuit element mounted in the mounting space is electrically connected. 6. The semiconductor device according to claim 3, wherein a circuit element is also mounted on a metallization layer formed on a surface of said third dielectric layer outside said mounting space. 7. The semiconductor device according to claim 1, wherein at least two or more multilayer substrates of the semiconductor device according to claim 1 are stacked. 8. A metallization layer formed on a surface of the first dielectric layer outside the mounting space, and a terminal electrode for input / output, GND and the like is provided. Semiconductor device. 9. A first dielectric layer having a metallized layer formed on both surfaces thereof, and a second dielectric layer having a third metallized layer formed on one surface or both surfaces and partly cut away, being laminated. A first dielectric substrate, a third dielectric layer having a metallized layer formed on one or both sides, and a fourth dielectric layer having a metallized layer formed on one or both sides and partially hollowed out. A second dielectric substrate formed by laminating the first and second dielectric substrates, a through-hole electrically connecting each metallized layer of the first and second dielectric substrates, and a second part of which is cut out. A multilayer substrate formed by laminating a dielectric layer and a third dielectric layer so as to form a mounting space for mounting circuit components, and a metallization of a first dielectric layer in the mounting space. On the layer and the part was hollowed out A circuit element mounted on the metallized layer of the third dielectric layer in the portion. 10. The semiconductor device according to claim 3, wherein said circuit element is flip-chip mounted on a substrate by bumps. 11. The metallized layers of the first and second dielectric substrates are connected with a conductive adhesive, and at the same time, the second dielectric layer and the third dielectric layer are bonded with the conductive adhesive. 11. The semiconductor device according to claim 9, wherein a circuit element mounted in the mounting space is electrically connected. 12. A metallized layer formed on a surface of the first dielectric layer outside the mounting space, and terminal electrodes for input / output, GND, etc. are provided.
13. The semiconductor device according to claim 1. 13. A first dielectric layer having a metallized layer formed on both sides thereof, and a second dielectric layer having a third metallized layer 5 formed on one or both sides thereof and partially cut away, respectively. A first dielectric substrate, a metallized layer formed on one or both surfaces, a fourth dielectric layer partially cut away, and a third dielectric material provided with a metallized layer formed on one or both surfaces, respectively. Body layers,
A second dielectric substrate formed by laminating the first dielectric substrate, a first through hole electrically connecting each metallization layer of the first dielectric substrate, A second through hole for electrically connecting each metallization layer of the second dielectric substrate to the second dielectric substrate, and a mounting space for mounting a circuit element thereon,
A multilayer substrate formed by bonding and laminating a second dielectric layer and a fourth dielectric layer of the first dielectric substrate; and a metallized layer formed on the first dielectric layer in the mounting space. And a circuit element mounted on the metallization layer formed outside the mounting space of the metallization layer formed on the third dielectric layer. 14. The semiconductor device according to claim 13, wherein said circuit component mounted in said mounting space is a circuit component requiring protection. 15. The metallization layer formed on a surface of the first dielectric layer outside the mounting space, and a terminal electrode for input / output, GND, and the like is provided. Semiconductor device. 16. A first dielectric layer having a metallized layer formed on both surfaces thereof, and a second dielectric layer having a third metallized layer formed on one surface or both surfaces and partly hollowed out. A first dielectric substrate, a third dielectric layer having a metallized layer formed on one or both sides, and a fourth dielectric layer having a metallized layer formed on one or both sides and partially hollowed out. A second dielectric substrate formed by laminating the first and second dielectric substrates, a through-hole for electrically connecting each metallized layer of the first and second dielectric substrates, and a second dielectric having a part thereof cut out. A multilayer substrate formed by laminating a body layer and a third dielectric layer so as to form a mounting space for mounting circuit components, and a metallized layer of a first dielectric layer in the mounting space The top and the part were hollowed out A circuit element mounted on the metallization layer of the third dielectric layer in the portion, a semiconductor device comprising: a fifth dielectric layer having a metallization layer formed on one or both surfaces; and a metallization layer on both surfaces. A third dielectric substrate formed and formed by laminating a sixth dielectric layer partially hollowed out, and a through hole for electrically connecting the metallized layer of the third dielectric substrate, Further comprising: laminating the fifth dielectric layer and the fourth dielectric layer,
A semiconductor device having a circuit component mounted on a metallized layer on the fifth dielectric layer in the hollowed portion of the sixth dielectric. 17. A metallized layer of the second dielectric layer and a metallized layer of the third dielectric layer, and a metallized layer of the fourth dielectric layer and a metallized layer of the fifth dielectric layer. At the same time each connected by a conductive adhesive, the second dielectric layer and the third dielectric layer, and,
The circuit element mounted in the mounting space is electrically joined by bonding the fourth dielectric layer and the fifth dielectric layer with the conductive adhesive, respectively. 17. The semiconductor device according to claim 16, wherein 18. A metallized layer formed on a surface of the first dielectric layer outside the mounting space, and terminal electrodes for input / output, GND, and the like are provided.
8. The semiconductor device according to 7. 19. A laminated structure comprising: a first dielectric layer having a metallized layer formed on both surfaces thereof; and a second dielectric layer having a third metallized layer formed on one surface and partially cut away. A semiconductor device using a substrate for a semiconductor device, comprising: a dielectric substrate; and a through hole for electrically connecting each metallization layer of the dielectric substrate. 20. A first dielectric layer having a metallized layer formed on one surface in a peripheral portion and a metallized layer formed on another surface, and a third metallized layer formed on one surface and partially cut away. A semiconductor device substrate, comprising: a dielectric substrate formed by laminating two dielectric layers; and a through hole that electrically connects each metallized layer of the dielectric substrate. Semiconductor device used.