JP2002358050A - Liquid crystal driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving device which properly generates common signals having a stable and low central voltage corresponding to low voltage liquid crystals and has a simple circuit constitution. SOLUTION: A common electrode driving signal generating circuit consists of an operational amplifier OP1 which outputs pulse signals Vac having a prescribed signal period and a prescribed voltage amplitude, a coupling capacitor C1 which is connected between the output terminal of the amplifier OP1 and a combined contact Nc , an operational amplifier OP2 which outputs a direct current signal Vh having a prescribed voltage (Vh), an analog switch SW1 which is connected between the output terminal of the amplifier OP2 and the combined contact Nc and switches and controls the supply condition of the signal Vh from the amplifier OP2 to the contact Nc on the basis of a timing control signal having a prescribed signal frequency, and an output terminal OUT which is connected to the contact Nc .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal driving device, and more particularly to a liquid crystal driving device for supplying a driving signal (common signal) having a predetermined voltage waveform to a common electrode (common electrode) of a liquid crystal display panel. .

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices (Liquid Crystal Displays; LCDs), which are characterized by being thin, lightweight, space-saving, and capable of driving with low power consumption, have been widely used. For example, imaging devices such as digital video cameras and digital still cameras, personal digital assistants (PDAs), and the like are often used as lightweight, compact, and low power consumption display means for displaying image information and the like. Instead of a conventional cathode ray tube (CRT), it is widely used as a monitor or a display of an information device such as a computer or a television, or a video device.

[0003] The configuration and drive control method of a general liquid crystal display device will be briefly described below. Here,
As an example of a liquid crystal display device, a main part configuration of an active matrix type liquid crystal display device will be described. As shown in FIG. 5, the main configuration of the liquid crystal display device is roughly divided into a liquid crystal display panel 110 in which a plurality of display pixels are arranged in a matrix, and a signal line (data line) Ld arranged in a column direction. , A source driver (signal driver) 120 for applying a predetermined signal voltage based on an image display signal to the display pixel, and a scanning signal sequentially output to a scanning line (gate line) Lg arranged in the row direction. A gate driver (scan driver) 130 for setting the display pixel to a selected state and writing the signal voltage applied to the signal line Ld to the display pixel.

The liquid crystal display panel 110 generally includes a plurality of pixel electrodes disposed in the vicinity of an intersection of a signal line Ld and a scanning line Lg arranged in a matrix between opposing transparent substrates (not shown), and A common electrode (common electrode) disposed opposite to each pixel electrode, a display pixel (liquid crystal capacitor Clc) made of liquid crystal filled and held between the pixel electrode and the common electrode, and the display pixel (liquid crystal capacitor Clc). ), A storage capacitor Cs for holding a signal voltage applied thereto, and a thin film transistor (hereinafter, referred to as a thin film transistor) having a gate connected to the scan line Lg, a source connected to the pixel electrode, and a drain connected to the signal line Ld. , "Pixel transistor") TFT.

The source driver 120 includes a sample and hold circuit (not shown) and a shift register. Control signals sequentially shifted and output by the shift register based on a horizontal control signal are sequentially applied to the sample and hold circuit. By doing, R (red), G (green), B
An image display signal (analog RGB signal) composed of each color signal of (blue) is input to and held in the sample and hold circuit, and is amplified to a predetermined signal voltage at a predetermined timing.
It is applied to each signal line Ld of the liquid crystal display panel 110.

On the other hand, the gate driver 130 includes a shift register and a buffer (not shown), and a control signal sequentially shifted and output in a predetermined direction by the shift register based on a vertical control signal is output to the buffer. Each pixel transistor TFT is selectively driven by being applied to each scanning line Lg of the liquid crystal display panel 110 as a gate signal (scanning signal) via the source driver 120.
As a result, the signal voltage applied to each signal line Ld is applied to each pixel electrode via the pixel transistor TFT. Thereby, the alignment state (alignment angle) of the liquid crystal is controlled, and predetermined image information is displayed according to a change in light transmittance due to the alignment state.

In FIG. 5, the configuration of the storage capacitor Cs is shown in which the other end of the storage capacitor Cs is connected to an independent dedicated wiring to supply a predetermined potential Vcs (storage capacitor system). The other end of the storage capacitor Cs is connected to an adjacent (previous) scan line Lg to supply a predetermined potential (gate signal voltage Vg) (Cs on-gate line structure or additional capacitance system). The configuration may be applied.

In a liquid crystal display device having such a configuration, an operation of writing an image display signal (signal voltage) to each display pixel of a liquid crystal display panel generally involves alternating current driving of the liquid crystal in order to prevent deterioration of the liquid crystal. There is a need. Therefore, as shown in FIG. 6, the signal voltage Vsig (pixel electrode voltage Vp) applied to the pixel electrode every one field period,
A driving method in which the polarity of the driving voltage (common voltage) Vcom applied to the common electrode is set so as to be inverted is adopted. Further, in order to reduce the occurrence of flicker, for example, one horizontal scan is performed. There is also known a driving method in which the voltage polarity of the pixel electrode voltage Vp and the voltage polarity of the common signal Vcom are inverted every period (1H). In FIG. 6, VcomC is the center voltage (average voltage) of the common signal Vcom, Vsigc is the center voltage (average voltage) of the signal voltage Vsig, and Vg is the gate signal voltage. Also, one field time is about 16.7 ms, and the total time of two fields, plus and minus, is called one frame and is about 33.3 ms.

FIG. 7 is a schematic circuit diagram showing an example of a configuration of a common signal generation circuit for generating a common signal applied to the common electrode of the liquid crystal display panel 110 in the configuration of the liquid crystal display device described above. FIG. 8 is a timing chart for generating a common signal generation operation in the common signal generation circuit shown in FIG. The common signal generation circuit receives, for example, a reference signal (pulse signal) having a predetermined signal cycle as shown in FIG. 7A, and outputs a pulse signal Vac having a predetermined signal cycle and a voltage amplitude. OP11, a coupling capacitor C11 connected between the output terminal of the operational amplifier OP11 and the composite contact Nc, and a DC signal Vdc having a predetermined voltage (Vdc).
Operational amplifier OP12 that outputs
Resistor R11 connected between the output terminal of the
And an output terminal OUT connected to the composite contact Nc.

In addition, for example, as shown in FIG. 7 (b), the common signal generation circuit has a resistor group connected in series instead of the operational amplifier OP12 and the resistor 11 in the circuit configuration shown in FIG. 7 (a). DC signal Vdc having Rs and a voltage (Vdc) obtained from the resistor group Rs by resistance division.
Is output to the composite contact Nc.

As shown in FIG. 8, the operation of generating a common signal in the common signal generation circuit having such a circuit configuration is performed as a pulse signal Vac output from the operational amplifier OP11 as a signal cycle and voltage of a desired common signal Vcom. A voltage waveform in a desired common signal Vcom is set so as to have a voltage component (voltage waveform) corresponding to the amplitude Vpp, and is output by the operational amplifier OP12 or as a DC signal Vdc obtained by resistance division of the resistance group Rs. Is set so as to have a voltage component corresponding to the center voltage (average voltage) VcomC, the voltage component from both is combined (superimposed) at the combining contact Nc (or the output terminal OUT), for example, for one field. A high level Vcom based on the center voltage VcomC (= Vdc) for each period
H (= Vdc + Vpp / 2) and low level VcomL (= Vd
A common signal Vcom having a voltage waveform (voltage amplitude Vpp) of (c−Vpp / 2) is generated. Here, as a specific example of the common signal Vcom generated by the common signal generation circuit, the voltage amplitude Vpp = 5.5 to 6.5 V and the center voltage Vcom
comC = 1.5-2.0 V, so that, for example, high level VcomH = 5.25 V and low level Vc
It is set to have a voltage waveform such that omL = −1.75V.

[0012]

By the way, in recent years, the center voltage VcomC of the common signal Vcom has tended to be reduced in accordance with a demand for reduction in power consumption. In a typical low-voltage driven liquid crystal display device, For example, the voltage amplitude Vpp = 5.
As in the case of 1 V and the center voltage VcomC = 0.5 V, the center voltage VcomC may be set near 0 V, or may be set to a negative voltage depending on the specification of the liquid crystal display device.

The center voltage Vc of such a common signal Vcom
In response to the lowering of the omC voltage, the common signal generation circuit shown in FIGS. 7A and 7B outputs the center voltage VcomC, that is, the output from the operational amplifier OP12 or the voltage division of the resistor group Rs. When the DC signal Vdc is set to a value close to 0 V or a negative voltage, the ground potential (V
gnd = 0V), the power supply voltage Vss
And the output DC signal Vdc becomes small, the operation becomes unstable or inoperable in the case of the operational amplifier OP12, and in the case of the resistor group Rs, the resistance Output by the voltage becomes impossible, and a desired center voltage Vcom near 0V or negative voltage
There was a problem that C could not be set.

In order to avoid such a problem, conventionally, as shown in FIGS. 9A and 10, a negative voltage (−) is used as a low-potential power supply supplied to the operational amplifier OP12 and the resistor group Rs. VGL) or as shown in FIG. 9B, a negative bias voltage (VGL) is supplied to the combined contact Nc via the resistor R12. Here, in a drive circuit of a normal liquid crystal display device,
The power supply to which the negative voltage is applied is a low-level signal voltage (VGL: −15 V) of the gate signal voltage Vg shown in FIG.
, Only the power supply for setting the power supply voltage is set, so that this power supply is applied as the low-potential power supply of the operational amplifier OP12 and the resistor group Rs or the negative bias voltage power supply.

However, applying the negative voltage (-15 V) lower than necessary as described above as a power source on the low potential side, and using the operational amplifier OP12, the resistor group Rs or the bias voltage, the center voltage VcomC (DC signal) of the common signal Vcom Vdc), the amount of drive current flowing to the low-potential-side power supply increases, causing a problem that wasteful power consumption increases not only for the common signal generation circuit but also for the entire liquid crystal display device. . Therefore, it is conceivable to provide a power supply unit for generating an appropriate negative voltage. However, in this case, it is not preferable because the circuit configuration of the common signal generation circuit becomes complicated and large.

In view of the above-mentioned problems, the present invention provides a liquid crystal driving device capable of satisfactorily generating a common signal having a low and stable center voltage corresponding to a low voltage liquid crystal with a simple circuit configuration. The purpose is to provide.

[0017]

According to the present invention, there is provided a liquid crystal driving apparatus comprising: a display panel in which a plurality of display pixels formed by filling liquid crystal between a plurality of pixel electrodes and a common electrode facing each other are arranged in a matrix; On the other hand, in a liquid crystal driving device including a common electrode drive signal generation unit that generates a predetermined common electrode drive signal and applies the common electrode drive signal to the common electrode, the common electrode drive signal generation unit sets a predetermined signal period and a predetermined voltage amplitude. First signal generation means for generating and outputting a first signal having
Second signal generation means for generating and outputting a second signal having a predetermined signal voltage; and a composite contact for receiving the first signal and the second signal to generate the common electrode drive signal And the signal period and the voltage amplitude of the common electrode drive signal are defined based on the first signal, and at a timing when the first signal is on the high potential side,
The second signal is supplied to the composite contact, and a signal voltage on the high potential side of the common electrode drive signal is defined as a signal voltage of the second signal. Here, the second signal generated by the second signal generation means is set to a positive signal voltage.

That is, in the common electrode drive signal generation means for supplying a common voltage to the common electrode of the liquid crystal display panel, the first signal generation circuit defines a signal period and a voltage amplitude of the common electrode drive signal in a pulse-like voltage component. Is generated, and the second signal generation circuit generates
A second signal including a DC component that defines the high level of the common electrode drive signal is generated, and the high level of the common electrode drive signal based on the signal voltage of the first signal is generated at a predetermined timing. By clamping by
The signal voltage of the second signal is set as the high level of the common electrode drive signal, and the signal voltage is obtained by lowering the signal voltage of the second signal by the voltage amplitude of the first signal as the low level of the common electrode drive signal. Set. In this case, the high level of the common electrode drive signal is set to be always a positive voltage, but the low level may be a negative voltage.

Thus, the second signal generating means can generate a common signal whose center voltage is set to near 0 V (= Vgnd) or a negative voltage without using a negative voltage driving power supply. The operation of the common signal generation circuit does not become unstable or the output becomes impossible, so that the common signal can be generated stably and the amount of drive current flowing to the low voltage side power supply is suppressed. Thus, power consumption can be reduced.

Further, in the liquid crystal driving device according to the present invention, in the liquid crystal driving device, the common electrode driving signal generating means includes a switching means between the second signal generating means and the composite contact; The switching means conducts at a timing when the first signal is on the high potential side, and supplies the second signal to the composite contact. That is, the first signal output from the first signal generation means
The switch means is controlled to be conductive only at the timing when the first signal is on the high potential side by the timing control signal synchronized with the signal cycle of the signal of the second signal, and the second signal is supplied to the composite contact. At the timing when the signal is on the low potential side, the switching means is controlled to be cut off, and the supply of the second signal is cut off.

Thus, the signal voltage on the high potential side of the common electrode drive signal based on the first signal is clamped by the signal voltage of the second signal, and the common electrode drive signal based on the first signal is low. Since the signal voltage on the potential side is set to a voltage obtained by lowering the signal voltage of the second signal by the voltage amplitude of the first signal, a common electrode drive signal having a predetermined voltage waveform is generated. In the second signal generation means, it is possible to stably generate a common signal without generating a signal near 0 V or a negative voltage by applying a negative voltage driving power supply, and to reduce power consumption. it can.

Further, in the liquid crystal driving device according to the present invention, in the liquid crystal driving device, the common electrode driving signal generating means includes a current limiting means between the second signal generating means and the composite contact, The current limiting means causes a current to flow from the combined contact side to the second signal generation means side at a timing when the first signal is on the high potential side,
The current flowing from the second signal generating means side to the composite contact side is restricted at the timing when the signal (b) is on the low potential side. Here, the current limiting unit includes a diode having an anode connected to the composite contact side and a cathode connected to the second signal generation unit.
And a resistance element connected in parallel to the diode.

That is, at the timing when the first signal is on the high potential side, the voltage on the combined contact side rises higher than the second signal generating means side, so that the voltage via the diode constituting the current limiting means is increased. At the timing when the current transiently flows from the combined contact side to the second signal generating means side, while the first signal is on the low potential side, the voltage of the combined contact side is changed from the second signal generating means side. Even if the current drops, the resistance element constituting the current limiting means prevents the current from flowing from the second signal generating means to the combined contact.

Thus, in the common electrode drive signal generating means provided with the switch means, even if the generated common electrode drive signal has a negative voltage, the current does not flow back to the switch means. In addition, in order to prevent the current from flowing backward, it is not necessary to apply a negative voltage as a drive power supply on the low voltage side, so that a common signal can be generated stably and power consumption can be reduced.
In the common electrode drive signal generating means having no switch means, the current flows through the diode constituting the current limiting means at the timing when the first signal is on the high potential side, and power is consumed. In addition, the circuit configuration corresponding to the switch means can be simplified, and the power consumption can be reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the liquid crystal driving device according to the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a schematic circuit diagram showing a first embodiment of a common signal generation circuit applied to a liquid crystal driving device according to the present invention.

As shown in FIG. 1, a common signal generation circuit (common electrode drive signal generation means) according to the present embodiment receives a reference signal (pulse signal; for example, a horizontal synchronization signal) having a predetermined signal period as an input. , An operational amplifier OP1 (first signal generating means) for outputting a pulse signal Vac (first signal) having a predetermined signal period and voltage amplitude, and an operational amplifier O
A coupling capacitor C1 connected between the output terminal of P1 and the composite contact Nc to extract a voltage component from the pulse signal Vac output from the operational amplifier OP1, and a predetermined reference voltage to a non-inverting (+) input; At the same time, the feedback voltage of the output signal is used as the input on the inverting side (-), and a predetermined voltage (V
h), which is connected between an output terminal of the operational amplifier OP2 and the combining contact Nc, and has a predetermined signal period. The operational amplifier OP2 outputs a DC signal Vh (second signal) having the signal h). An analog switch SW1 (switch means) for switching and controlling the supply state of the DC signal Vh from the operational amplifier OP2 to the combining contact Nc based on the timing control signal, and an output terminal O connected to the combining contact Nc.
And a UT.

Here, at least the operational amplifier OP2 includes:
A power supply voltage Vdd is supplied as a high-voltage drive power supply, and a non-negative power supply voltage Vss (for example, a ground potential Vgnd) is supplied as a low-voltage drive power supply. Generate a signal Vh.
The analog switch SW1 is supplied with a power supply voltage Vdd equivalent to that of the operational amplifier OP2 as a high-voltage drive power supply, and is supplied with a negative power supply voltage VGL (−15 V) as a low-voltage drive power supply. The conduction (ON) operation and the cutoff (OFF) operation are performed in synchronization with the switching timing of the signal level in the timing control signal synchronized with the signal cycle of the output pulse signal Vac (or the reference signal). The analog switch SW1
The low-voltage-side drive power supply (negative voltage) supplied to the gate signal voltage is, for example, a signal voltage (VGL: −15) on the low-level side of the gate signal voltage Vg, as described in the related art.
A power supply for setting V) is applied.

With such a configuration, as described later,
The operational amplifier OP1 generates a pulse signal having a voltage waveform (for example, a signal cycle of 1H and a voltage amplitude of 5.1 V) that defines the signal cycle and the voltage amplitude Vpp of the common signal Vcom, and outputs the voltage via the coupling capacitor C1. Only the component is output to the composite contact Nc, and the operational amplifier OP2 generates a DC signal Vh (for example, voltage: +3.0 V) that defines the high level (VcomH) of the common signal, and the analog switch SW1 is turned on. It is output to the composite contact Nc for a predetermined period (1H). At the combined contact Nc, the signal voltage on the high potential (Hi) side of the pulse signal Vac output from the operational amplifier OP1 during a predetermined period (1H) during which the analog switch SW1 is turned ON, the DC voltage output from the operational amplifier OP2. The signal is clamped by the voltage component of the signal Vh, and is output from the output terminal OUT as a high-level common signal VcomH (= Vh).

Next, the operation of generating a common signal in the common signal generation circuit having the above configuration will be described with reference to the drawings. FIG. 2 is a timing chart for explaining a common signal generation operation in the common signal generation circuit according to the present embodiment. Here, a description will be given with reference to the above-described circuit configuration (FIG. 1) and a timing chart (FIG. 6) showing the driving state of the liquid crystal display device in the related art as appropriate.

As shown in FIG. 6, a period in which the high-level common signal VcomH is supplied to the common electrode of the liquid crystal display panel (that is, the signal voltage Vsig based on the image display signal).
In a period during which the operational amplifier OP1 is at a low level), as shown in FIG.
The pulse signal Vac output from the analog switch SW becomes high level, and the analog switch SW
1 is turned ON, and the DC signal Vh output from the operational amplifier OP2 is supplied to the combining contact Nc.

As a result, the analog switch SW1 is
During the N-operation period, the high-level voltage component of the pulse signal Vac output from the operational amplifier OP1 is clamped to the voltage component of the DC signal Vh output from the operational amplifier OP2 and is fixedly set at the combined contact Nc. Therefore, the output signal having the voltage Vh is output as the high-level common signal VcomH at the output terminal OU.
It is applied to the common electrode of the liquid crystal display panel via T.

Further, a period during which the low-level common signal VcomL is supplied to the liquid crystal display panel (that is, a period during which the signal voltage Vsig based on the image display signal is at the high level).
In the above, based on the signal period of the reference signal, the pulse signal Vac output from the operational amplifier OP1 becomes low level, the analog switch SW1 is turned off by the timing control signal, and the DC signal Vh output from the operational amplifier OP2 is output. To the composite contact Nc is shut off.

As a result, the analog switch SW1 is
During the period in which the FF operation is performed, only the voltage component of the pulse signal Vac output from the operational amplifier OP1 is applied to the composite contact Nc.
So that the voltage of the composite contact Nc is
A voltage lower than the above-mentioned high-level common signal VcomH (= Vh) by the voltage amplitude Vpp of the pulse signal Vac is set, and an output signal having this voltage (Vh-Vpp) is set as a low-level common signal VcomL as an output terminal. It is applied to the common electrode of the liquid crystal display panel via OUT.

Here, in the above-described operation of generating the common signal, the voltage component of the DC signal Vh output from the operational amplifier OP2 is set to be smaller than 電 圧 of the voltage amplitude Vpp of the pulse signal Vac output from the operational amplifier OP1. By setting the voltage to a low value (Vh <Vpp / 2), the center voltage VcomC of the common signal Vcom generated by the common signal generation circuit can be set to a negative voltage.

That is, in the common signal generation circuit (FIG. 7) shown in the above-mentioned prior art, the center voltage VcomC
Is a common signal Vcom set to near 0V or negative voltage
In the case where the ground potential (Vgnd) is applied as the power supply voltage Vss on the low voltage side of the operational amplifier OP12 or the resistor group Rs, the common signal generation circuit (or
There is a problem that the operation of the operational amplifier OP12) is unstable or output becomes impossible, and the power supply voltage V
In the case where a negative voltage (VGL: -15 V) is applied as ss, there is a problem that wasteful power consumption increases. However, in the present embodiment, the operational amplifier OP2
The ground potential (Vgnd) as the power supply voltage Vss on the low voltage side of
Is applied, the DC signal Vh output from the operational amplifier OP2 causes the high-level common signal Vco
mH, the low-level common signal VcomL is defined by the voltage amplitude Vpp of the pulse signal Vac output from the operational amplifier OP1, and the predetermined center voltage Vc
A common signal Vcom having omC (near 0 V or including a negative voltage) is generated. Therefore, the operational amplifier OP
2, there is no need to generate a signal near 0 V or a negative voltage by applying a negative voltage driving power supply, so that the operation of the common signal generation circuit becomes unstable or the output becomes impossible, The problem that power consumption increases can be avoided well.

In the present embodiment, a configuration is shown in which a low-level signal voltage (VGL: -15 V) of the gate signal voltage is applied as a low-voltage drive power supply for the analog switch SW1, but this is not the case. To prevent the current from flowing backward due to a potential difference between the common signal Vcom and the combined contact Nc when the common signal Vcom becomes a negative voltage, and supply the current to the generated common signal Vcom. Not something. Therefore, generation of useless power consumption in the common signal generation circuit can be suppressed.

In this embodiment, as a timing control signal for setting and controlling the ON / OFF operation of the analog switch SW1, a signal synchronized with the operation of outputting a high-level pulse signal Vac in the operational amplifier OP1, for example, a horizontal signal. Since a synchronization signal or the like can be applied, compared to a conventional common signal generation circuit, the analog switch SW1 and its driving power supply and a signal line for supplying a timing control signal have a simple circuit configuration.
The above-described effects can be obtained.

<Second Embodiment> Next, a second embodiment of a common signal generation circuit applied to the liquid crystal driving device according to the present invention will be described with reference to the drawings. Here, for a configuration equivalent to the above-described first embodiment,
The description is simplified or omitted. FIG. 3 is a schematic circuit diagram showing a second embodiment of the common signal generation circuit applied to the liquid crystal driving device according to the present invention.

In the above-described first embodiment, the low-level negative voltage (VGL: -15) of the gate signal voltage is used as the low-voltage side drive power supply for the analog switch SW1.
V) is applied, but in the present embodiment, the center voltage VcomC is set to 0 without applying a negative voltage to the drive power supply on the low voltage side of the analog switch SW2.
It has a configuration for generating a common signal Vcom set near V or a negative voltage.

Specifically, as shown in FIG. 3, the common signal generation circuit according to the present embodiment includes an operational amplifier OP1, a coupling capacitor C1, and an operational amplifier OP2 equivalent to the circuit configuration shown in the first embodiment. In addition, operational amplifier O
An analog switch SW2 connected to the output terminal of P2,
A current limiting circuit (current limiting means) connected between the analog switch SW2 and the composite contact Nc. Here, the analog switch SW2 uses the power supply voltages Vdd and Vss (ground potential Vgnd) equivalent to those of the operational amplifier OP2 as the high-voltage side and low-voltage side drive power supplies, respectively. Further, the current limiting circuit has, for example, an anode on the composite contact Nc side,
The cathode includes a diode D1 connected to the analog switch SW2 side and a resistor R1 connected in parallel with the diode D1.

The common signal generating operation in the common signal generating circuit having such a configuration is similar to that of the first embodiment (see FIG. 2), in which the pulse signal Vac (voltage amplitude Vpp) output from the operational amplifier OP1 is used. Becomes high level, the analog switch SW2 is turned ON, and the DC signal Vh output from the operational amplifier OP2 is supplied to the composite contact Nc.

As a result, the analog switch SW2 is
During the N-operation period, the high-level voltage component of the pulse signal Vac output from the operational amplifier OP1 is clamped by the voltage component of the DC signal Vh output from the operational amplifier OP2 at the combined contact Nc, so that the voltage Vh Is generated at a high level. At this time, the high-level common signal VcomH (voltage of the composite contact Nc) output to the output terminal OUT is:
High level of pulse signal Vac and analog switch SW2
Since the forward current transiently flows through the diode D1 due to a potential difference between the output voltage (Vh) and the output voltage (Vh), the voltage instantaneously increases (Vh + Vdf: Vdf is the forward voltage of the diode D1), and then the voltage gradually increases. Vh.

At the timing when the pulse signal Vac (voltage amplitude Vpp) output from the operational amplifier OP1 becomes low level, the analog switch SW2 is turned off to the combined contact Nc of the DC signal Vh output from the operational amplifier OP2. Supply is shut off. As a result, during the period in which the analog switch SW2 is turned off, only the voltage component of the pulse signal Vac output from the operational amplifier OP1 is supplied to the composite contact Nc, so that the voltage of the composite contact Nc becomes a high-level common signal. VcomH (=
Vh) is set to a voltage lower than Vh) by the voltage amplitude Vpp of the pulse signal Vac, and a low-level common signal VcomL having the voltage (Vh-Vpp) is generated.

Here, when the low level of the common signal Vcom is a negative voltage, a current flows forward in an electrostatic protection diode (not shown) provided at the input / output terminal of the analog switch SW2. Accordingly, the voltage of the output signal of the analog switch SW2 becomes Vgnd−Vef
(Vef is the forward voltage of the electrostatic protection diode).
At this time, the voltage of the combined contact Nc is changed by the analog switch S
Since the voltage is lower than the voltage of the output signal of W2 and a reverse bias is applied to the diode D1, current flows through the resistor R1, but the resistance value of the resistor R1 must be set appropriately. Accordingly, the amount of current flowing down to the composite contact Nc can be suppressed.

This will be described with reference to specific numerical values. The low-level common signal VcomL generated by the common signal generation circuit having the above-described configuration is set to −3 V, and the output voltage Vsw of the analog switch SW2 is set to −0.6 V.
Coupling capacitor C having μF capacitance Ccp
Assuming that 3 is always charged with a voltage of 3 V, the coupling capacitor C1 has Q = Ccp × V = 10 × 3 =
This means that 30 μC of electric charge is accumulated. At this time, the resistance value of the resistor R1 constituting the voltage drop means is set to 20 k.
Ω, the amount of charge flowing through the resistor R1 during one horizontal scanning period (1H) is ((−3 − (− 0.6)) / 20000 ×
63.5 μs = 7.62 nC, which means that only a very small amount of charge (current) flows compared to the charge amount Q (= 30 μC) stored in the coupling capacitor C1 and is output from the output terminal OUT. It does not affect the voltage waveform of the common signal Vcom.

Therefore, in the present embodiment, a predetermined voltage is not used as a driving power supply for the operational amplifier OP2 and the analog switch SW2 on the low voltage side in the same manner as in the above-described first embodiment without using a circuit configuration to which a negative voltage is applied. Can generate the common signal Vcom having the center voltage VcomC (approximately 0 V or including a negative voltage), thereby omitting a circuit configuration relating to a low-voltage side driving power supply and reducing wasteful power consumption. It is possible to stably generate the common signal Vcom while reducing the number.

Third Embodiment Next, a third embodiment of the common signal generation circuit applied to the liquid crystal driving device according to the present invention will be described with reference to the drawings. Here, the description of the same configuration as the first or second embodiment will be simplified or omitted. FIG. 4 is a schematic circuit diagram showing a third embodiment of the common signal generation circuit applied to the liquid crystal driving device according to the present invention.

In the first and second embodiments described above, the analog switches SW1 and SW2 are provided as means for supplying the DC signal Vh output from the operational amplifier OP2 to the combining contact Nc at a predetermined timing. However, the present embodiment has a configuration in which the common signal Vcom in which the center voltage VcomC is set near 0 V or set to a negative voltage is provided without providing an analog switch. Specifically, as shown in FIG. 4, the common signal generation circuit according to the present embodiment includes an operational amplifier OP1, a coupling capacitor C1, and an operational amplifier OP2 equivalent to the circuit configuration shown in the first or second embodiment. In addition,
It has only a current limiting circuit connected between the output terminal of the operational amplifier OP2 and the composite contact Nc, and has a circuit configuration without an analog switch. Here, the current limiting circuit includes a diode D as in the second embodiment.
1 and a resistor R2 are connected in parallel.

In the common signal generation operation of the common signal generation circuit having such a configuration, the pulse signal Vac (signal amplitude: Vpp) output from the operational amplifier OP1 has a high level, as in the second embodiment. In the state,
By the potential difference generated between the high level of the pulse signal Vac and the output voltage (DC signal Vh) of the operational amplifier OP2,
After a forward current transiently flows through the diode D1 and the voltage instantaneously increases, the voltage gradually approaches the voltage Vh, and a high-level common signal VcomH having the voltage Vh is generated.

When the pulse signal Vac (voltage amplitude Vpp) output from the operational amplifier OP1 is at a low level, the voltage at the composite contact Nc (low level of the pulse signal Vac) is changed to the output voltage (DC signal Vh) of the operational amplifier OP2. )
As a result, the reverse bias is applied to the diode D1, so that the supply of the DC signal Vh output from the operational amplifier OP2 to the composite contact Nc is substantially cut off. As a result, only the voltage component of the pulse signal Vac output from the operational amplifier OP1 is supplied to the combining contact Nc, and the high-level common signal VcomH
(= Vh), a low-level common signal VcomL having a voltage (Vh-Vpp) lower by the voltage amplitude Vpp of the pulse signal Vac is generated. Here, when the low level of the common signal Vcom is a negative voltage, based on the potential difference between the output voltage of the operational amplifier OP2 (DC signal Vh) and the voltage of the composite contact Nc (low-level common signal VcomH). Since the current flows through the resistor R2, the current flowing into the composite contact Nc slightly increases, and the power consumption increases.

On the other hand, the present embodiment has a configuration in which the output terminal of the operational amplifier OP2 is directly connected to the composite contact Nc via a current limiting circuit (diode D1, resistor R2) without connecting an analog switch. Therefore, even when the low level of the common signal Vcom is a negative voltage, the current does not flow to the electrostatic protection diode peculiar to the analog switch as shown in the second embodiment. In other words, the ESD protection diode itself is originally intended to protect the circuit against abnormal current, so even a small amount of current flow may cause a malfunction or failure of the analog switch. It is preferable to have a circuit configuration for avoiding the flow of the current to the circuit itself.

Therefore, in the present embodiment, the low level of the common signal Vcom is negative by applying a configuration that does not use the analog switch and its peripheral circuits, as compared with the above-described first or second embodiment. Even in the case of a voltage, similarly to the first and second embodiments described above, it is possible to stably generate the common signal Vcom having a predetermined center voltage VcomC (near 0 V or including a negative voltage). And the power consumption of the circuit portion can be reduced. In addition, since the circuit configuration can be further simplified, the number of circuit elements can be greatly reduced, and the product cost can be further reduced.

In each of the above-described embodiments, the DC signal Vh output from the operational amplifier OP2 at least when the pulse signal Vac goes high with respect to the pulse signal Vac output from the operational amplifier OP1. To generate a common signal Vco
Although the configuration for clamping the high-level voltage of m has been described, the present invention is not limited to this configuration. For example, as a DC signal Vh for clamping the high-level voltage of the common signal Vcom, for example, Conventional technology (FIG. 7B)
(See Reference), a desired signal voltage (h) may be generated by resistance division by applying a resistance group as shown in FIG.

[0054]

According to the liquid crystal driving device of the present invention, the common electrode driving signal generating means for supplying the common electrode driving signal to the common electrode of the liquid crystal display panel has a pulse-like shape having a predetermined signal period and voltage amplitude. A first signal generation circuit that generates and outputs a first signal including a voltage component, a second signal generation circuit that generates and outputs a second signal including a DC component having a predetermined signal voltage, A signal period and a voltage amplitude of the common electrode drive signal are defined based on the first signal, and the high level of the common electrode drive signal based on the signal voltage of the first signal is changed to a second level at a predetermined timing. , The signal voltage of the second signal is set as the high level of the common electrode drive signal, and the second signal is set as the low level of the common electrode drive signal. The common electrode drive signal a first voltage signal voltage amplitude component is dropped signals from the signal voltage is set is generated.

As a result, the second signal generating means can generate a common electrode driving signal whose center voltage is set to around 0 V (= Vgnd) or a negative voltage without using a negative voltage driving power supply. This makes it possible to generate a common signal stably without causing the operation of the common signal generation circuit to become unstable or making output impossible, and to reduce the amount of drive current flowing to the low potential side power supply. The power consumption can be reduced to suppress the power consumption.

Also, based on a timing control signal synchronized with the signal period of the first signal output from the first signal generating means, the switch means is controlled to be conductive only at the timing when the first signal is on the high potential side. Then, the second signal is supplied to the composite contact, and at the timing when the first signal is on the low potential side, the switch means is controlled to be cut off, thereby cutting off the supply of the second signal. The signal voltage on the high potential side of the common electrode drive signal based on the first signal is clamped by the signal voltage of the second signal, and the signal voltage on the low potential side of the common electrode drive signal based on the first signal is Since the common electrode drive signal having a predetermined voltage waveform is generated by setting the signal voltage of the second signal to a voltage obtained by lowering the voltage amplitude of the first signal from the signal voltage of the second signal, the second signal generating means generates a negative signal. Apply voltage drive power Te, without generating a signal 0V neighbors negative voltage, stably it is possible to generate a common signal, it is possible to reduce the power consumption.

Further, by providing current limiting means comprising a diode and a resistance element connected in parallel between the second signal generating means and the composite contact, the timing at which the first signal is on the high potential side can be obtained. When the voltage on the combined contact side rises higher than that on the second signal generating means side, a current transiently flows from the combined contact side to the second signal generating means side via the diode constituting the current limiting means. ,on the other hand,
At the timing when the first signal is on the low potential side, even if the voltage on the combined contact side drops below the second signal generating means side, the second signal is generated by the resistance element constituting the current limiting means. By suppressing the current from flowing from the generating means side to the combined contact side, even if the generated common electrode drive signal becomes a negative voltage, the current does not flow back to the switch means, In order to prevent the backflow of the current, it is not necessary to apply a negative voltage as a driving power source on the low potential side. Therefore, a common signal can be stably generated without using a negative voltage power supply in the common signal generation circuit, and power consumption can be reduced. Also, when this configuration is applied to a common signal generation circuit having no switch means,
At the timing when the first signal is on the high potential side, a current flows through the diode constituting the current limiting means and power is consumed. However, the circuit configuration corresponding to the switch means can be simplified, and The power consumption can be reduced by that amount.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing a first embodiment of a common signal generation circuit applied to a liquid crystal driving device according to the present invention.

FIG. 2 is a timing chart illustrating an operation of generating a common signal in the common signal generation circuit according to the first embodiment.

FIG. 3 is a schematic circuit diagram showing a second embodiment of a common signal generation circuit applied to the liquid crystal driving device according to the present invention.

FIG. 4 is a schematic circuit diagram showing a third embodiment of a common signal generation circuit applied to the liquid crystal driving device according to the present invention.

FIG. 5 is a schematic configuration diagram showing a main configuration of an active matrix type liquid crystal display device.

FIG. 6 is a timing chart showing an operation of writing an image display signal (signal voltage) to each display pixel of the liquid crystal display panel.

FIG. 7 is a schematic circuit diagram illustrating a configuration example of a common signal generation circuit according to the related art.

8 is a timing chart for generating a common signal generation operation in the common signal generation circuit shown in FIG. 7;

9 is a schematic circuit diagram showing one configuration example for solving a problem in the common signal generation circuit shown in FIG. 7;

FIG. 10 is a schematic circuit diagram showing another configuration example for solving the problem in the common signal generation circuit shown in FIG. 7;

[Explanation of symbols]

 Reference Signs List 10 liquid crystal display panel 20 source driver 30 gate driver 40 LCD controller 50 chroma interface circuit 51 RGB decoder 52 inverting amplifier 60 bias setting circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA06 NA33 NA34 NC03 NC04 NC18 NC22 NC23 ND38 5C006 AC25 BB16 BF24 BF25 FA46 FA47 5C080 AA10 BB05 DD26 FF11 JJ02 JJ03 JJ04

Claims (5)

[Claims] A predetermined common electrode drive signal is generated for a display panel in which a plurality of display pixels configured by sealing liquid crystal between a plurality of pixel electrodes and a common electrode facing the plurality of pixel electrodes are arranged in a matrix. A liquid crystal driving device including a common electrode drive signal generating means for applying the common electrode to the common electrode, wherein the common electrode drive signal generating means generates and outputs a first signal having a predetermined signal period and a voltage amplitude. Signal generating means, a second signal generating means for generating and outputting a second signal having a predetermined signal voltage, and the common electrode drive signal supplied with the first signal and the second signal. Wherein the signal period and voltage amplitude of the common electrode drive signal are defined based on the first signal, and at the timing when the first signal is on the high potential side, The said The signal is supplied to the synthesis contact, a liquid crystal driving device which signal voltages on the high potential side of the common electrode driving signal, characterized in that it is defined in the signal voltage of the second signal. 2. The common electrode drive signal generating means includes a switch means between the second signal generating means and the composite contact, and the switch means causes the first signal to be on a high potential side. 2. The liquid crystal drive device according to claim 1, wherein the second signal is supplied to the composite contact by conducting at a timing. 3. The common electrode drive signal generating means includes a current limiting means between the second signal generating means and the composite contact, wherein the current limiting means determines that the first signal is on a high potential side. At this time, a current flows from the composite contact side to the second signal generating means side, and at a timing when the first signal becomes a low potential side, the current flows from the second signal generating means side to the composite contact side. 3. The liquid crystal driving device according to claim 1, wherein the current flowing to the side is restricted. 4. The current limiting means includes: a diode having an anode connected to the composite contact side and a cathode connected to the second signal generation means; a resistance element connected in parallel to the diode; The liquid crystal driving device according to claim 3, comprising: 5. The liquid crystal driving device according to claim 1, wherein the second signal generated by the second signal generation unit is set to a positive signal voltage. apparatus.