JP2002353223A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002353223A JP2002353223A JP2001162377A JP2001162377A JP2002353223A JP 2002353223 A JP2002353223 A JP 2002353223A JP 2001162377 A JP2001162377 A JP 2001162377A JP 2001162377 A JP2001162377 A JP 2001162377A JP 2002353223 A JP2002353223 A JP 2002353223A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric constant
- low dielectric
- barrier metal
- constant film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に関し、詳しくは、半導体基板に絶縁膜お
よびバリアメタルを介して銅配線層を形成した半導体装
置およびその製造方法に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a copper wiring layer is formed on a semiconductor substrate via an insulating film and a barrier metal, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】半導体装置の高集積化、小型に伴い、配
線の微細化、配線ピッチの縮小化および配線の多層化が
進んでおり、半導体装置の製造プロセスにおける多層配
線技術の重要性が増大している。従来、多層配線構造の
半導体装置の配線材料としてアルミニウムが多用されて
きたが、近年の0.25μmルール以下のデザインルー
ルにおいて、信号の伝搬遅延を抑制するために、配線材
料をアルミニウムから銅に代えた配線プロセスの開発が
行われるようになっている。銅を配線に使用すると、低
抵抗と高エレクトロマイグレーション耐性を両立できる
という利点がある。2. Description of the Related Art Along with the high integration and miniaturization of semiconductor devices, finer wiring, smaller wiring pitch, and more multilayer wiring have been promoted, and the importance of multilayer wiring technology in the semiconductor device manufacturing process has increased. are doing. Conventionally, aluminum has been frequently used as a wiring material for a semiconductor device having a multilayer wiring structure. However, in recent design rules under the 0.25 μm rule, in order to suppress signal propagation delay, the wiring material was changed from aluminum to copper. Developed wiring processes are being developed. When copper is used for wiring, there is an advantage that both low resistance and high electromigration resistance can be achieved.
【0003】この銅を使用する配線プロセスでは、予め
層間絶縁膜に形成した溝状の配線パターンに金属を埋め
込み、CMP(Chemicai Mechanica
lPolishing;化学機械研磨)法によって余分
な金属膜を除去して配線を形成する、ダマシン法と呼ば
れる配線プロセスが有力になっている。このダマシン法
は、配線のエッチングが不要であり、さらに、上層の層
間絶縁膜を自ずと平坦なものになるので、工程を簡略化
できる。さらに、層間絶縁膜に配線用溝だけでなく、コ
ンタクトホールも溝として開け、配線用溝とコンタクト
ホールを同時に金属で埋め込むデュアルダマシン(Du
aldamascene)法では、さらに大幅な配線工
程の削減が可能となる。In a wiring process using copper, a metal is buried in a groove-shaped wiring pattern formed in an interlayer insulating film in advance, and a CMP (Chemica Mechanical) is used.
A wiring process called a damascene method, in which an excess metal film is removed by an IPolishing (chemical mechanical polishing) method to form a wiring, has become effective. This damascene method does not require wiring etching, and furthermore, the upper interlayer insulating film becomes naturally flat, so that the process can be simplified. Further, a dual damascene (Du) in which not only a wiring groove but also a contact hole is formed as a groove in the interlayer insulating film and the wiring groove and the contact hole are simultaneously filled with metal.
According to the adamascene method, it is possible to further reduce the number of wiring steps.
【0004】図2は、従来のデュアルダマシン法による
銅配線形成のプロセスを示している。図2(a)に示す
ように、酸化シリコン(SiO2)等の半導体基板1上
に、低誘電率膜(Low−k)2を形成し、さらにその
上に酸化シリコンからなる絶縁膜3を形成する。そし
て、バリアメタル4を絶縁膜3の表面および半導体基板
1の不純物拡散領域に通じるコンタクトホール5に形成
する。このバリアメタル4としては、Ta,Ti,Ta
N,TiN等の金属材料を周知のスパッタ法により形成
する。このバリアメタル4の上に、配線用溝(コンタク
トホール)5を埋め込むように銅配線層6を形成する。FIG. 2 shows a process of forming a copper wiring by a conventional dual damascene method. As shown in FIG. 2A, a low dielectric constant film (Low-k) 2 is formed on a semiconductor substrate 1 such as silicon oxide (SiO 2 ), and an insulating film 3 made of silicon oxide is further formed thereon. Form. Then, a barrier metal 4 is formed in a contact hole 5 communicating with the surface of the insulating film 3 and the impurity diffusion region of the semiconductor substrate 1. As the barrier metal 4, Ta, Ti, Ta
A metal material such as N or TiN is formed by a known sputtering method. A copper wiring layer 6 is formed on the barrier metal 4 so as to fill a wiring groove (contact hole) 5.
【0005】次に、図2(b)に示すように、配線用溝
5内の部分を残してバリアメタル4上の銅配線層6を除
去する。次に、図2(c)に示すように、絶縁膜3上の
余分なバリアメタル4をCMP法によって除去し、平坦
化する。最後に、図2(d)に示すように、絶縁膜3上
に窒化シリコン(SiN)のキャップ膜7を形成する。Next, as shown in FIG. 2B, the copper wiring layer 6 on the barrier metal 4 is removed except for the portion inside the wiring groove 5. Next, as shown in FIG. 2C, the excess barrier metal 4 on the insulating film 3 is removed by a CMP method and flattened. Finally, as shown in FIG. 2D, a cap film 7 of silicon nitride (SiN) is formed on the insulating film 3.
【0006】上記のような、従来の半導体装置の製造方
法では、銅配線層6の層間絶縁膜として低誘電率膜2を
使用しているが、この低誘電率膜2がCMPに対して強
度が小さく、そのため低誘電率膜2に傷が入ったり剥が
れたりして、CMP面として使用できなくなることがあ
る。そのため、従来では低誘電率膜2の上にさらに酸化
シリコンからなる絶縁膜3を設け、2層の絶縁膜とする
ことにより、耐CMPを確保している。In the conventional method of manufacturing a semiconductor device as described above, the low dielectric constant film 2 is used as the interlayer insulating film of the copper wiring layer 6, but the low dielectric constant film 2 has strength against CMP. Is small, so that the low dielectric constant film 2 may be scratched or peeled off, so that it cannot be used as a CMP surface. Therefore, conventionally, the insulating film 3 made of silicon oxide is further provided on the low dielectric constant film 2 to provide two insulating films, thereby ensuring the CMP resistance.
【0007】ところが、低誘電率膜2および酸化シリコ
ン膜3は、熱処理によってストレスを受けて剥がれが発
生しやすい。また、酸化シリコン膜3の厚さの分、銅配
線層6による誘電率が高くなり、配線抵抗が大きくなる
という問題があった。さらにまた、半導体装置の全体の
膜層が多くなるため、構造が複雑になり、信頼性が低下
するという問題もあった。However, the low-dielectric-constant film 2 and the silicon oxide film 3 are liable to be peeled off by receiving a stress due to the heat treatment. In addition, the dielectric constant of the copper wiring layer 6 is increased by the thickness of the silicon oxide film 3, and the wiring resistance is increased. Furthermore, since the number of film layers in the whole semiconductor device is increased, the structure is complicated, and there is a problem that reliability is reduced.
【0008】本発明は、上記のような問題を解決するた
めになされたもので、絶縁膜を低誘電率膜の1層のみと
することにより、構造が簡単で信頼性の高い半導体装置
およびその製造方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. By using only one low-dielectric-constant insulating film, a highly reliable semiconductor device having a simple structure and a highly reliable semiconductor device are disclosed. It is intended to provide a manufacturing method.
【0009】[0009]
【課題を解決するための手段】前記の目的を達成するた
め、本発明に係る半導体装置は、半導体基板上の絶縁膜
に形成されたコンタクトホールにバリアメタルを介して
銅配線層が形成された半導体装置であって、前記絶縁膜
は1層の低誘電率膜で構成されていることを特徴とす
る。In order to achieve the above object, in a semiconductor device according to the present invention, a copper wiring layer is formed via a barrier metal in a contact hole formed in an insulating film on a semiconductor substrate. In a semiconductor device, the insulating film is formed of a single-layer low dielectric constant film.
【0010】本発明に係わる半導体装置の製造方法は、
半導体基板上に、低誘電率膜を形成し、この低誘電率膜
に配線用溝を形成する工程と、前記低誘電率膜の表面お
よび配線用溝にバリアメタルを形成する工程と、前記配
線用溝を埋め込むように銅配線層を形成する工程と、前
記配線用溝内の部分を残して前記バリアメタル上の銅配
線層を除去する工程と、前記低誘電率膜上の余分なバリ
アメタルを除去する工程とを具備することを特徴とす
る。[0010] A method of manufacturing a semiconductor device according to the present invention comprises:
Forming a low dielectric constant film on a semiconductor substrate, forming a wiring groove in the low dielectric constant film; forming a barrier metal on the surface of the low dielectric constant film and the wiring groove; Forming a copper wiring layer so as to fill the groove for wiring, removing the copper wiring layer on the barrier metal while leaving a portion in the wiring groove, and forming an extra barrier metal on the low dielectric constant film. And a step of removing
【0011】また、前記低誘電率膜上の余分なバリアメ
タルを除去する工程を流体研磨で行うことができる。ま
た、前記バリアメタル上の銅配線層を除去する工程をC
MPまたは流体研磨のいずれかで行うことができる。Further, the step of removing excess barrier metal on the low dielectric constant film can be performed by fluid polishing. Further, the step of removing the copper wiring layer on the barrier metal is performed by C
It can be done with either MP or fluid polishing.
【0012】[0012]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。なお、図1において、図2と同一
部材または同一機能のものは同一符号で示している。図
1(a)に示すように、酸化シリコン(SiO2)等の
半導体基板1上に、低誘電率膜(Low−k)2のみを
形成する。この低誘電率膜としては、例えば、SiF、
SiOCH、ポリアリールエーテル、ポーラスシリカ、
ポリイミド等がある。そして、バリアメタル4を低誘電
率膜2の表面および配線用溝(コンタクトホール)5の
内壁に形成する。バリアメタル4としては、Ta、T
i、TaN、TiN等の金属材料を周知のスパッタ法に
より形成する。このバリアメタル4の上に、配線用溝5
を埋め込むように銅配線層6を形成する。Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the same members or those having the same functions as those in FIG. 2 are denoted by the same reference numerals. As shown in FIG. 1A, only a low dielectric constant film (Low-k) 2 is formed on a semiconductor substrate 1 such as silicon oxide (SiO 2 ). As this low dielectric constant film, for example, SiF,
SiOCH, polyaryl ether, porous silica,
Examples include polyimide. Then, the barrier metal 4 is formed on the surface of the low dielectric constant film 2 and the inner wall of the wiring groove (contact hole) 5. As the barrier metal 4, Ta, T
A metal material such as i, TaN, or TiN is formed by a known sputtering method. On this barrier metal 4, a wiring groove 5 is formed.
Is formed to form a copper wiring layer 6.
【0013】次に、図1(b)に示すように、配線用溝
5内の部分を残してバリアメタル4上の銅配線層6を研
磨により除去する。次に、図1(c)に示すように、低
誘電率膜2上の余分なバリアメタル4を研磨により除去
する。この場合、低誘電率膜2が軟質であるため、CM
P法で研磨を行うと、バリアメタル4を除去して低誘電
率膜2を露出させるときに低誘電率膜2にスクラッチや
剥がれが発生しやすい。そこで、図1(c)の除去工程
は、圧力が小さく衝撃の少ない流体研磨により行う。Next, as shown in FIG. 1B, the copper wiring layer 6 on the barrier metal 4 is removed by polishing while leaving the portion in the wiring groove 5. Next, as shown in FIG. 1C, the excess barrier metal 4 on the low dielectric constant film 2 is removed by polishing. In this case, since the low dielectric constant film 2 is soft, CM
When the polishing is performed by the P method, when the barrier metal 4 is removed and the low dielectric constant film 2 is exposed, the low dielectric constant film 2 is easily scratched or peeled. Therefore, the removal step in FIG. 1C is performed by fluid polishing with a small pressure and a small impact.
【0014】流体研磨は、研磨工具の微細孔から微細砥
粒が混合されているスラリーを被研磨面に向けて噴出さ
せて被研磨物面から極微小の除去を行う方法である。こ
の流体研磨に使用するスラリーは、低誘電率膜2が浸食
されない液体であって、微細砥粒の粒径は100nm以
下が好ましく、また、pHが7〜14の中性またはアル
カリ性のものが好ましい。このような流体研磨を用いる
ことにより、低誘電率膜2のスクラッチや剥がれが発生
をなくすることができる。Fluid polishing is a method in which a slurry in which fine abrasive grains are mixed is spouted from a fine hole of a polishing tool toward a surface to be polished to remove an extremely minute amount from the surface of the object to be polished. The slurry used for the fluid polishing is a liquid in which the low dielectric constant film 2 is not eroded, and the particle diameter of the fine abrasive grains is preferably 100 nm or less, and a neutral or alkaline pH of 7 to 14 is preferable. . By using such fluid polishing, scratching and peeling of the low dielectric constant film 2 can be prevented.
【0015】なお、図1(b)の銅配線層6の除去はC
MP法でもよいが、必要に応じてこの工程も流体研磨を
用いることができる。最後に、図1(d)に示すよう
に、絶縁膜3上に窒化シリコン(SiN)のキャップ膜
7を形成する。多層構造の場合は、このキャップ膜7上
に同構造の半導体装置を形成する。The removal of the copper wiring layer 6 shown in FIG.
Although the MP method may be used, fluid polishing can be used in this step if necessary. Finally, a cap film 7 of silicon nitride (SiN) is formed on the insulating film 3 as shown in FIG. In the case of a multilayer structure, a semiconductor device having the same structure is formed on the cap film 7.
【0016】[0016]
【発明の効果】以上、詳述したように、本発明の半導体
装置によれば、絶縁膜を1層の低誘電率膜で構成したの
で、従来のような低誘電率膜と酸化シリコン膜との界面
での剥がれをなくすることができると共に、酸化シリコ
ン膜がないため、銅配線層の全体が低誘電率膜層に接触
する構造になり、したがって、銅配線層による誘電率が
低く、配線抵抗も小さくすることができ、さらにまた、
半導体装置の全体の膜層が少ないため、構造が簡単で、
信頼性が向上するという効果がある。また、本発明の半
導体装置の製造方法によれば、絶縁膜が低誘電率膜の1
層で済むため、製造プロセスが少なくなり、製造コスト
を低減できるという効果がある。As described above in detail, according to the semiconductor device of the present invention, the insulating film is formed of a single low dielectric constant film, so that the conventional low dielectric constant film and silicon oxide film can be used. Of the copper wiring layer is in contact with the low dielectric constant film layer because there is no silicon oxide film, and therefore the dielectric constant of the copper wiring layer is low, and The resistance can be reduced, and
The structure is simple because the whole film layer of the semiconductor device is small,
There is an effect that reliability is improved. Further, according to the method of manufacturing a semiconductor device of the present invention, the insulating film is a low dielectric constant film.
Since only layers are required, the number of manufacturing processes is reduced, and there is an effect that manufacturing cost can be reduced.
【図1】本発明の実施の形態を示す製造工程断面図であ
る。FIG. 1 is a sectional view showing a manufacturing process according to an embodiment of the present invention.
【図2】従来の半導体装置の製造方法を示す製造工程断
面図である。FIG. 2 is a cross-sectional view of a manufacturing process showing a conventional method for manufacturing a semiconductor device.
1‥‥半導体基板、2‥‥低誘電率膜、4‥‥バリアメ
タル、5‥‥配線用溝、6‥‥銅配線層1 semiconductor substrate, 2 low dielectric constant film, 4 barrier metal, 5 wiring groove, 6 copper wiring layer
Claims (5)
用溝にバリアメタルを介して銅配線層が形成された半導
体装置であって、 前記絶縁膜は1層の低誘電率膜で構成されていることを
特徴とする半導体装置。1. A semiconductor device in which a copper wiring layer is formed via a barrier metal in a wiring groove formed in an insulating film on a semiconductor substrate, wherein the insulating film is formed of a single low dielectric constant film. A semiconductor device characterized by being performed.
程と、 前記低誘電率膜に配線用溝を形成する工程と、 前記低誘電率膜の表面および配線用溝にバリアメタルを
形成する工程と、 前記配線用溝を埋め込むように銅配線層を形成する工程
と、 前記配線用溝内の部分を残して前記バリアメタル上の銅
配線層を除去する工程と、 前記低誘電率膜上の余分なバリアメタルを除去する工程
と、を具備することを特徴とする半導体装置の製造方
法。2. A step of forming a low dielectric constant film on a semiconductor substrate; a step of forming a wiring groove in the low dielectric constant film; and forming a barrier metal on the surface of the low dielectric constant film and the wiring groove. Forming a copper wiring layer so as to fill the wiring groove; removing the copper wiring layer on the barrier metal while leaving a portion in the wiring groove; and forming the low dielectric constant film. Removing the excess barrier metal on the semiconductor device.
を除去する工程を流体研磨で行うことを特徴とする請求
項2記載の半導体装置の製造方法。3. The method according to claim 2, wherein the step of removing excess barrier metal on the low dielectric constant film is performed by fluid polishing.
る工程をCMP法で行うことを特徴とする請求項2また
は3記載の半導体装置の製造方法。4. The method according to claim 2, wherein the step of removing the copper wiring layer on the barrier metal is performed by a CMP method.
る工程を流体研磨で行うことを特徴とする請求項2また
は3記載の半導体装置の製造方法。5. The method for manufacturing a semiconductor device according to claim 2, wherein the step of removing the copper wiring layer on the barrier metal is performed by fluid polishing.
Priority Applications (1)
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JP2001162377A JP4507457B2 (en) | 2001-05-30 | 2001-05-30 | Manufacturing method of semiconductor device |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001162377A JP4507457B2 (en) | 2001-05-30 | 2001-05-30 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
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JP2002353223A true JP2002353223A (en) | 2002-12-06 |
JP4507457B2 JP4507457B2 (en) | 2010-07-21 |
Family
ID=19005516
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JP2001162377A Expired - Fee Related JP4507457B2 (en) | 2001-05-30 | 2001-05-30 | Manufacturing method of semiconductor device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004095558A1 (en) * | 2003-04-23 | 2004-11-04 | Nikon Corporation | Cmp polishing method and method for manufacturing semiconductor device |
JP2004327561A (en) * | 2003-04-22 | 2004-11-18 | Ebara Corp | Substrate processing method and device thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61178177A (en) * | 1985-01-31 | 1986-08-09 | Nec Corp | Grinding device for back of wafer |
JPH04356956A (en) * | 1991-06-03 | 1992-12-10 | Sharp Corp | Semiconductor device and its manufacture |
JP2000332111A (en) * | 1999-05-25 | 2000-11-30 | Shinko Electric Ind Co Ltd | Method for forming wire, multi-layered wiring substrate, and substrate device |
-
2001
- 2001-05-30 JP JP2001162377A patent/JP4507457B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61178177A (en) * | 1985-01-31 | 1986-08-09 | Nec Corp | Grinding device for back of wafer |
JPH04356956A (en) * | 1991-06-03 | 1992-12-10 | Sharp Corp | Semiconductor device and its manufacture |
JP2000332111A (en) * | 1999-05-25 | 2000-11-30 | Shinko Electric Ind Co Ltd | Method for forming wire, multi-layered wiring substrate, and substrate device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004327561A (en) * | 2003-04-22 | 2004-11-18 | Ebara Corp | Substrate processing method and device thereof |
WO2004095558A1 (en) * | 2003-04-23 | 2004-11-04 | Nikon Corporation | Cmp polishing method and method for manufacturing semiconductor device |
CN100369212C (en) * | 2003-04-23 | 2008-02-13 | 株式会社尼康 | CMP polishing method and method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP4507457B2 (en) | 2010-07-21 |
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