JP2002351356A - Display device, liquid crystal display device and semiconductor device for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a matrix type display device. SOLUTION: In the display device, any wiring of electrode lines such as a scanning line 11 or a signal line 12 and a power source line and others is parted at the cross part of the wiring. A connection layer 70 is formed to connect the parted wiring through a gate insulating layer 30 or an inter-layer insulation layer 83 and other kinds of insulation layers. An organic insulating layer 91 or a low resistance metallic layer 92 and an organic insulating layer 91 are formed on the connection layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having an image display function, and more particularly to an active liquid crystal display device or an organic EL display device.

[0002]

2. Description of the Related Art Recent advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology have resulted in the provision of large quantities of television images and various image display devices on a commercial basis with 5 to 50 cm diagonal liquid crystal panels. ing. Further, color display is easily realized by forming an RGB colored layer on one of two glass substrates constituting a liquid crystal panel. In particular, in a so-called active type liquid crystal panel in which a switching element is incorporated for each picture element, an image having little crosstalk, high speed response and high contrast ratio is guaranteed.

[0003] These liquid crystal display devices (liquid crystal panels) generally have a matrix organization of about 200 to 1200 scanning lines and about 200 to 1600 signal lines, but have recently responded to an increase in display capacity. Larger screens and higher definition are proceeding at the same time.

FIG. 10 shows a state of mounting on a liquid crystal panel.
A semiconductor integrated circuit chip 3 for supplying a drive signal to one of the transparent insulating substrates constituting the liquid crystal panel 1, for example, a group of scanning line terminal electrodes 6 formed on a glass substrate 2, is connected using a conductive adhesive. COG (Chip-On-Glass) method or a T-type having a terminal (not shown) of gold or solder-plated copper foil based on, for example, a polyimide resin thin film
TCP (Tape-Car) for fixing the CP film 4 to the terminal electrodes 5 of the signal lines by pressing with a suitable adhesive containing a conductive medium.
An electric signal is supplied to the image display unit by a mounting means such as a carrier-package method. Here, for the sake of convenience, two mounting methods are shown simultaneously, but in practice, either method is appropriately selected.

[0005] Reference numerals 7 and 8 denote an image display portion located substantially at the center of the liquid crystal panel 1 and terminal electrodes 5 and 6 of signal lines and scanning lines.
Between the terminal electrode groups 5, 6
It is not necessary to be made of the same conductive material as that described above. Reference numeral 9 denotes another transparent insulating substrate or a color filter, which is another transparent insulating substrate having a transparent conductive counter electrode common to all liquid crystal cells on the opposing surface.

FIG. 11 is an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element, and 11 (8 in FIG. 10).
Is a scanning line, 12 (7 in FIG. 10) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is electrically treated as a capacitive element. The elements drawn by solid lines are formed on one glass substrate 2 constituting the liquid crystal panel, and the common electrodes 14 common to all the liquid crystal cells 13 drawn by dotted lines are formed on the other glass substrate 9. ing. When the OFF resistance of the insulated gate transistor 10 or the resistance of the liquid crystal cell 13 is low or when importance is placed on the gradation of a display image, an auxiliary storage capacitor 15 for increasing the time constant of the liquid crystal cell 13 as a load. Are added to the liquid crystal cell 13 in parallel. Reference numeral 16 denotes a common bus of the storage capacitor 15 (storage capacitance line or common capacitance line).

FIG. 12 is a sectional view of a main part of an image display section of a liquid crystal panel. Two glass substrates 2 and 9 constituting the liquid crystal panel 1 are made of a resin material such as fiber, beads or a columnar spacer. (Not shown) at a predetermined distance of about several μm, and the gap (gap) is sealed by a sealing material made of an organic resin and a sealing material (neither is shown) at the periphery of the glass substrate 9. The closed space is stopped, and the liquid crystal 17 is filled in the closed space.

In order to realize a color display, an organic thin film having a thickness of about 1 to 2 μm containing one or both of a dye and a pigment called a colored layer 18 is applied to the closed space side of the glass substrate 9. Since a color display function is provided, in this case, the glass substrate 9 is also called a color filter (Color
The Filter abbreviation is called CF). Then, depending on the properties of the liquid crystal material 17, a polarizing plate 19 is stuck on one or both of the upper surface of the glass substrate 9 and the lower surface of the glass substrate 2, and the liquid crystal panel 1 functions as an electro-optical element.
At present, most liquid crystal panels on the market use TN (twisted nematic) type liquid crystal materials.
Usually, two polarizing plates 19 are required. Although not shown, a rear light source is disposed as a light source in the transmission type liquid crystal panel, and white light is emitted from below.

The two glass substrates 2 and 9 are in contact with the liquid crystal 17.
The polyimide resin thin film 20 having a thickness of, for example, about 0.1 μm formed thereon is an alignment film for aligning liquid crystal molecules in a predetermined direction. 21 is an insulated gate transistor 1
0 is a drain electrode (wiring) for connecting the transparent conductive picture element electrode 22 to the signal line (source line) 12.
Often formed at the same time. The semiconductor layer 23 is located between the signal line 12 and the drain electrode 21 and will be described later in detail. Colored layers 1 adjacent on color filter 9
8, a Cr thin film layer 24 having a thickness of about 0.1 μm
Is a light shield for preventing external light from entering the semiconductor layer 23, the scanning lines 11 and the signal lines 12, and is a technology fixed as a so-called black matrix (abbreviated as BM).

Here, the structure and manufacturing method of an insulated gate transistor as a switching element will be described. Two types of insulated gate transistors are currently in heavy use, and one of them is introduced as a conventional example (called an etch stop type). FIG. 13 is a plan view of a unit picture element of an active substrate (semiconductor device for a display device) constituting a conventional liquid crystal panel. FIG. 14 is a cross-sectional view taken along line AA ′ of FIG. This will be briefly described below. Note that a region 51 (a hatched portion falling to the right) where the projection 50 formed on the scanning line 11 and the pixel electrode 22 overlap with the gate insulating layer interposed therebetween forms the storage capacitor 15. Detailed description is omitted.

First, as shown in FIG. 14 (a), an insulating substrate having high heat resistance, chemical resistance, and transparency has a thickness of 0.5 to 0.5 mm.
As a first metal layer having a film thickness of about 0.1 to 0.3 μm on a glass substrate 2 of about 1.1 mm, for example, a main surface of 1737 (trade name, manufactured by Corning Incorporated) using a vacuum film forming apparatus such as SPT (sputtering). By depositing Cr, Ta, Mo or the like, or an alloy or silicide thereof, the gate electrode 11 also serving as a scanning line is selectively formed by a fine processing technique. The material of the scanning line is preferably selected in consideration of heat resistance, chemical resistance, hydrofluoric acid resistance and conductivity.

In order to reduce the resistance of the scanning line in response to the increase in the screen size of the liquid crystal panel, it is reasonable to use AL (aluminum) as the material of the scanning line. However, AL alone has low heat resistance. Therefore, Cr, T
Lamination with a, Mo or their silicides, or addition of an oxide layer (AL2O3) by anodic oxidation on the surface of AL is currently a common technique. That is, the scanning line 11 is formed of one or more metal layers.

Next, as shown in FIG. 14B, a first SiNx (silicon nitride) layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 by using a PCVD (Plasma Thievey) apparatus, and impurities are almost completely removed. Not including first amorphous silicon (a-Si) to be the channel of the insulated gate transistor
A second SiNx layer serving as an insulating layer for protecting the layer and the channel and three types of thin film layers are sequentially deposited to a thickness of, for example, about 0.3-0.05-0.1 μm to form 30, 31, and 32.

Subsequently, the second amorphous SiNx layer on the gate 11 electrode is selectively made 32 'thinner than the gate electrode 11 by a fine processing technique to expose the first amorphous silicon layer 31 as 32'. Using an apparatus, an amorphous silicon layer 33 containing, for example, phosphorus as an impurity is formed as a second semiconductor layer serving as a source / drain of an insulated gate transistor, for example.
After deposition with a thickness of about 0.05 μm, the first amorphous silicon layer 31 and the second amorphous silicon layer 33 are formed only on the vicinity of the gate 11 electrode as shown in FIG. The island 3
The gate insulating layer 30 is exposed while leaving the gate insulating layers 1 'and 33'. Subsequently, as shown in FIG. 14 (d), for example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as SPT or the like, and is subjected to fine processing. The picture element electrode 22 is selectively formed on the gate insulating layer 30 by a technique.

Further, as shown in FIG. 14E, a selective opening 63 is formed in the gate insulating layer 30 on the scanning line 11 at the periphery of the image display portion necessary for electrical connection to the scanning line 11. After that, as shown in FIG. 14 (f), a heat-resistant metal thin film layer 34 of, for example, Ti, Cr, Mo, etc.
An AL thin film layer 35 having a thickness of about 0.3 μm is sequentially deposited as a low-resistance wiring layer, and is formed by laminating a heat-resistant metal layer 34 ′ and a low-resistance wiring layer 35 ′ by microfabrication technology and insulated including the pixel electrode 22. Gate type transistor drain wiring (electrode) 2
1 and a source wiring (electrode) 12 also serving as a signal line are selectively formed. Using the photosensitive resin pattern used for the selective pattern formation as a mask, the second amorphous silicon layer 33 ′ between the source and drain wirings (electrodes) is removed to expose the second SiNx layer 32 ′, In other regions, the first amorphous silicon layer 31 'is also removed to expose the gate insulating layer 30. This step is called an etch stop because the second SiNx layer 32 'which is a protective layer of the channel is present and the etching of the second amorphous silicon layer 33' is automatically completed. is there.

The source / drain wirings 12 and 21 are formed so as to partially overlap the gate 11 electrode (several μm) so that the insulated gate transistor does not have an offset structure. Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the photomask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about 2 μm. In addition, at the peripheral portion of the image display section, the terminal electrode 6 on the scanning line side or the wiring connecting the scanning line 11 and the terminal electrode 6 on the scanning line side simultaneously with the signal line 12 including the opening 63 on the scanning line 11. Forming the road 8 is also a general pattern design.

Finally, as a transparent insulating layer, a SiNx layer having a thickness of about 0.3 to 0.7 μm is deposited on the entire surface of the glass substrate 2 using a PCVD apparatus in the same manner as the gate insulating layer 30 to form a passivation insulating layer. 37, an opening 38 is formed on the pixel electrode 22 as shown in FIG.
Are exposed, and the manufacturing process of the active substrate ends. At this time, openings are also formed on the terminal electrodes 6 of the scanning lines and the terminal electrodes 5 of the signal lines, and most of the terminal electrodes are also exposed.

If the wiring resistance of the signal line 12 is not a problem, the low-resistance wiring layer 35 made of AL is not always necessary. In this case, if a heat-resistant metal material such as Cr, Ta, or Mo is selected, the source and the wiring can be used. The drain wirings 12 and 21 can be made into a single layer. The heat resistance of the insulated gate transistor is described in detail in Japanese Patent Laid-Open No. 7-74368, which is a prior example.

The passivation insulating layer 3 on the picture element electrode 22
The reason for removing 7 is, firstly, to prevent a decrease in the effective voltage applied to the liquid crystal cell, and secondly, because the film quality of the passivation insulating layer 37 is generally poor, This is for avoiding the accumulation of the electric charges and the burning of the displayed image. This is because the heat resistance of the insulated gate transistor is not so high, so that the film forming temperature of the passivation insulating layer 37 is inevitably lower than that of the gate insulating layer 30 by several tens of degrees Celsius and lower than 250 degrees Celsius. Because.

The above-described active substrate manufacturing process requires a photolithography process seven times, and is an almost standard manufacturing method called a seven-mask process. Reduction of the number of manufacturing processes is an important proposition for LCD panel manufacturers in order to realize lower prices for LCD panels and respond to further increases in demand, and a streamlined so-called five-mask process has recently become established. I've been.

FIG. 15 is a plan view of a unit picture element of the active substrate corresponding to the five masks. FIG. 16 is a cross-sectional view taken along the line AA 'of FIG. A brief description will be given below of a case where another conventional one (referred to as a channel etch type) is employed. Note that a region 52 (a hatched portion falling to the right) where the storage capacitance line (common capacitance line) 16 and the drain electrode 21 overlap with the gate insulating layer 30 interposed therebetween forms the storage capacitance 15. Detailed description is omitted.

First, similarly to the conventional example, as shown in FIG. 16A, a first film having a thickness of about 0.1 to 0.3 μm is formed on one main surface of a glass substrate 2 by using a vacuum film forming apparatus such as SPT. And a gate electrode 11 also serving as a scanning line and a storage capacitor line 16 are selectively formed by a fine processing technique.

Next, as shown in FIG. 16B, a SiNx layer serving as a gate insulating layer is formed on the entire surface of the glass substrate 2 using a PCVD apparatus, and a first channel serving as a channel of an insulated gate transistor containing almost no impurities. An amorphous silicon layer, a second amorphous silicon layer containing impurities and serving as a source / drain of an insulated gate transistor, and three types of thin film layers are sequentially formed in a thickness of, for example, about 0.3-0.2-0.05 μm. 30, 31, and 33 are attached.

Then, as shown in FIG. 16C, the gate insulating layer 3 is formed on the gate electrode 11 by leaving the semiconductor layers made of the first and second amorphous silicon layers in the form of islands 31 'and 33'.
Expose 0.

Subsequently, as shown in FIG.
Using a vacuum film forming apparatus such as PT, for example, a Ti thin film layer 34 as a heat-resistant metal layer having a thickness of about 0.1 μm, an AL thin film layer 35 having a thickness of about 0.3 μm as a low-resistance wiring layer, and a 0.1 μm thick For example, a Ti thin film layer 36 is sequentially deposited as an intermediate conductive layer, and the drain wiring 21 of the insulated gate transistor and the source wiring 12 also serving as a signal line are selectively formed by a fine processing technique. This selective patterning is
Using the photosensitive resin pattern used for forming the drain wiring as a mask, the Ti thin film layer 36, the AL thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33 ', and the first amorphous silicon layer 31' Are sequentially etched, and the first amorphous silicon layer 31 'is etched while leaving about 0.05 to 0.1 .mu.m, so that it is called a channel etch.

After removing the photosensitive resin pattern, as shown in FIG. 16E, a transparent insulating layer is formed on the entire surface of the glass substrate 2 by PCVD in the same manner as the gate insulating layer.
A passivation insulating layer 37 is formed by depositing a SiNx layer having a thickness of about 0.3 μm by using an apparatus, and an opening 63 is formed on the drain wiring 21 and an opening 63 is formed on a position where the terminal electrode 6 of the scanning line 11 is formed. To form the drain wiring 21 and the scanning line 1
Expose a portion of 1. Although not shown, an opening 64 is also formed at a position where the terminal electrode 5 of the signal line is formed, and a part of the signal line 12 is exposed.

Finally, as shown in FIG.
For example, ITO (Indium-Tin-Oxide) is applied as a transparent conductive layer having a film thickness of about 0.1 to 0.2 μm using a vacuum film forming apparatus such as Then, the picture element electrode 22 is selectively formed to complete the active substrate 2. A part of the exposed scanning line 11 in the opening 63 may be used as the terminal electrode 6, and the terminal electrode 6 ′ made of ITO is selectively formed on the passivation insulating layer 37 including the opening 63 as shown in the figure. It may be formed.

As described above, the five-mask process is performed once by the rationalization of the islanding process of the semiconductor layer, compared with the seven-mask process.
In addition, the step of forming an opening (contact) to a scanning line and the step of forming an opening to a pixel electrode and the step of forming a contact, which were required twice, have been streamlined once so that a total of two photo etching steps have been reduced. Can be. In addition, since the picture element electrode 22 is located on the uppermost layer of the active substrate 2, the passivation insulating layer 37 is formed by using a transparent resin thin film, for example, for 1.5 times.
If the pixel electrode 22 is formed thicker than μm, even if the pixel electrode 22 overlaps the scanning line 11 or the signal line 12, interference due to capacitance is small and deterioration of image quality can be avoided.
Can be formed to be large, and the aperture ratio can be improved.

[0029]

The power consumption of the above-mentioned transmission type liquid crystal panel includes the power consumption of the driving semiconductor integrated circuit on the scanning line side and the signal line side, the power consumption of the back light source, the scanning line side and the signal line. This is the sum of the power consumption of a control semiconductor integrated circuit (generally called a controller) that sends a control signal to the driving semiconductor integrated circuit on the side.

The power consumption of the driving semiconductor integrated circuits on the scanning line side and the signal line side is determined by the capacitance and the driving voltage of the scanning line and the signal line, which are loads, respectively, that is, the power accompanying the charging and discharging of the capacitance.
Although it largely depends on the screen size and definition of the liquid crystal panel, it is generally clear that the smaller the resistance value of the scanning line and the signal line and the smaller the capacitance component, the smaller the value.

As described above, the source / drain wirings 12 and 21 are formed so as to partially overlap the gate electrode 11 in a plane so that the insulated gate transistor does not have an offset structure. Since this overlap electrically acts as a parasitic capacitance, the smaller the better, the better. However, it is determined by the alignment accuracy of the exposure machine, the accuracy of the photomask, the expansion coefficient of the glass substrate, and the glass substrate temperature at the time of exposure. It is about 2 μm. Rather, from the viewpoint of manufacturing margin during mass production, 3μ
m is preferable, but at present, a self-aligned insulated gate transistor such as a single crystal silicon device has not been realized or established for various reasons. Further, no particular attention has been paid to an approach for reducing the parasitic capacitance caused by the plane crossing of the scanning line and the signal line.

The present invention has been made in view of the above-mentioned circumstances, and relates to a case where a parasitic capacitance formed between a scanning line or a signal line and a power supply line or other wiring intersecting with the scanning line or a signal line, and furthermore, the scanning line and the signal line intersect with each other. It is an object to reduce power consumption of a display device by reducing parasitic capacitance generated by the display device.

[0033]

According to the present invention, one of the wirings is provided at a crossing of two kinds of wirings such as a power supply line or other wiring intersecting a scanning line or a signal line, or an intersection of two kinds of wirings such as a scanning line and a signal line. Separate and add another insulating layer to a gate insulating layer or an interlayer insulating layer constituting an insulated gate transistor which is a switching element, and form a connection layer for connecting the divided wiring on the two or more types of insulating layers By doing so, the insulating layer at the intersection is formed thick. The passivation of the active substrate is secured by forming an organic insulating layer on the connection layer, and the resistance of the electrode wires due to the introduction of the connection layer is formed by forming a low-resistance metal layer and an organic insulating layer on the connection layer. This avoids an increase in the value.

According to a first aspect of the present invention, there is provided a display device having at least one switching insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the switching insulated gate transistor, and a signal line also serving as a source line. Insulation in which unit picture elements each having a storage capacitor connected to a drain wiring, a driving insulated gate transistor, and a display electrode connected to a drain wiring of the driving insulated gate transistor are arranged in a two-dimensional matrix. In a display device including a substrate and a display medium, a scanning line or a signal line is divided at an intersection of a scanning line and a signal line, and a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer are separated. And having an organic insulating layer on it by connecting any of the divided scanning lines or signal lines via Characterized in that the first connection layer is formed.

With this configuration, at the intersection of the scanning line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, so that the electrode layer is formed between the scanning line and the signal line. Parasitic capacitance is reduced. As a result, the power consumption of any of the driving circuits for driving the scanning lines and the signal lines is reduced. In addition, an active substrate insulated other than the display electrodes can be obtained.

According to a second aspect of the present invention, there is provided the display device, wherein either the scanning line or the signal line is divided at the intersection of the scanning line and the signal line, and the gate insulating layer or the interlayer insulating layer of the switching insulated gate transistor and the other. A first line having a low-resistance metal layer and an organic insulating layer on one of the above-mentioned divided scanning lines and signal lines connected thereto via a first insulating layer.
Is formed.

According to this configuration, the same effect as that of the display device according to the first aspect is obtained, and an increase in the resistance value of the scanning lines and the signal lines such as the signal lines due to the interposition of the first connection layer is avoided.
Even in a large screen and high definition display device, image quality does not deteriorate.

According to a third aspect of the present invention, there is provided the display device, wherein either the power supply line or the signal line is provided at the intersection of the power supply line and the signal line also serving as the source wiring of the driving insulated gate transistor substantially parallel to the scanning line. A second power supply line or a signal line which is separated via a gate insulating layer or an interlayer insulating layer of an insulated gate transistor for switching and another insulating layer and has an organic insulating layer thereon; A connection layer is formed.

With this configuration, at the intersection of the power supply line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the signal line decreases. As a result, the power consumption of the drive circuit driving the signal lines is also reduced. In addition, an active substrate insulated other than the display electrodes can be obtained.

According to a fourth aspect of the present invention, in the display device, one of the power supply line and the signal line is provided at the intersection of the power supply line and the signal line which also serves as the source wiring of the driving insulated gate transistor substantially parallel to the scanning line. The separated power supply line or signal line is connected via a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer, and a low-resistance metal layer and an organic insulating layer are formed thereon. And a second connection layer having:

According to this configuration, the same effect as that of the display device according to the third aspect is obtained, and an increase in the resistance value of the electrode wire due to the interposition of the second connection layer is avoided, so that the display device has a large screen and high definition. Is particularly effective in

According to a fifth aspect of the present invention, in the display device, one of the power supply line and the scanning line is provided at the intersection of the power supply line and the scanning line, which also serves as the source wiring of the driving insulated gate transistor substantially parallel to the signal line. A third power supply line or a scan line which is separated via a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer and has an organic insulating layer thereon; A connection layer is formed.

With this configuration, at the intersection of the power supply line and the scanning line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the scanning line decreases. As a result, the power consumption of the driving circuit for driving the scanning lines is also reduced. In addition, an active substrate insulated other than the display electrodes can be obtained.

According to a sixth aspect of the present invention, in the display device, either the power supply line or the scanning line is provided at the intersection of the power supply line and the scanning line, which also serves as the source wiring of the driving insulated gate transistor substantially parallel to the signal line. The divided power supply line or the scanning line is connected through a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer, and a low-resistance metal layer and an organic insulating layer are formed thereon. And a third connection layer having:

According to this structure, the same effect as that of the display device according to the fifth aspect is obtained, and an increase in the resistance value of the electrode wire due to the interposition of the third connection layer is avoided, so that the display device has a large screen and high definition. Is particularly effective in

The display device according to a seventh aspect is the display device according to the first or second aspect, which has a second or third connection layer in addition to the first connection layer.

With this configuration, the thickness of the insulating layer that insulates and separates these electrode lines at the intersection between the scanning line and the signal line and at the intersection between the power supply line and the scanning line or the signal line can be increased. As a result, the parasitic capacitance of the scanning line and the signal line is further reduced. As a result, the power consumption of the driving circuit for driving the scanning lines and the signal lines is further reduced.

The display device according to claim 8, wherein the low-resistance metal layer is made of any one of gold, silver and copper. is there.

With this configuration, an increase in the resistance value of the divided electrode lines is avoided, and the image quality is not deteriorated due to the introduction of the connection lines even in a large screen and high definition display device.

A display device according to a ninth aspect is characterized in that the switching insulated gate transistor and the driving insulated gate transistor are the same.

This configuration is applied to a display device that requires only a small amount of power to drive a display medium, and corresponds to, for example, a liquid crystal display device.

According to a tenth aspect of the present invention, there is provided a liquid crystal display device having at least one insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source line, and a drain line. A liquid crystal display in which liquid crystal is filled between an insulating substrate in which unit picture elements having connected pixel electrodes are arranged in a two-dimensional matrix, and a transparent insulating substrate or a color filter facing the insulating substrate. In the device, one of the scanning line and the signal line is divided at an intersection of the scanning line and the signal line, and the divided scanning is performed via a gate insulating layer or an interlayer insulating layer of an insulated gate transistor and another insulating layer. A first connection layer which connects either the line or the signal line and has an organic insulating layer thereon is formed.

With this configuration, at the intersection of the scanning line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and is formed between the scanning line and the signal line. Parasitic capacitance is reduced. As a result, the power consumption of any of the driving circuits for driving the scanning lines and the signal lines is reduced. Further, an insulated active substrate can be obtained except for the pixel electrodes.

In the liquid crystal display device according to the eleventh aspect, similarly, either the scanning line or the signal line is divided at the intersection of the scanning line and the signal line, and the gate insulating layer or the interlayer insulating layer of the insulated gate transistor and the other. And a first connection layer having a low-resistance metal layer and an organic insulating layer is formed thereon by connecting any of the divided scanning lines or signal lines via the insulating layer. And

According to this configuration, the same effect as that of the liquid crystal display device according to the tenth aspect is obtained, and an increase in the resistance value of the electrode wire due to the interposition of the first connection layer is avoided. It is particularly effective in devices.

According to a twelfth aspect of the present invention, in the liquid crystal display device, either the common capacitance line or the signal line is divided at the intersection of the common capacitance line and the signal line which are also substantially parallel to the scanning line, and the gate of the insulated gate transistor is separated. A second connection layer is formed, which connects any of the divided common capacitance lines or signal lines via an insulating layer or an interlayer insulating layer and another insulating layer, and has an organic insulating layer thereon. It is characterized by the following.

With this configuration, at the intersection of the common capacitance line and the signal line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the signal line decreases. As a result, the power consumption of the drive circuit driving the signal lines is also reduced. Further, an insulated active substrate can be obtained except for the pixel electrodes.

According to a thirteenth aspect of the present invention, in the liquid crystal display device, either the common capacitance line or the signal line is divided at the intersection of the common capacitance line and the signal line which are also substantially parallel to the scanning line, and the gate of the insulated gate transistor is formed. A second connection for connecting any of the divided common capacitance lines or signal lines via an insulating layer or an interlayer insulating layer and another insulating layer and having a low resistance metal layer and an organic insulating layer thereon; It is characterized in that a layer is formed.

According to this configuration, the same effect as that of the liquid crystal display device according to the twelfth aspect is obtained, and an increase in the resistance value of the electrode wire due to the interposition of the second connection layer is avoided, so that a large screen and high definition display is achieved. It is particularly effective in devices.

According to a fourteenth aspect of the present invention, there is provided the liquid crystal display device, wherein either the common capacitance line or the scanning line is divided at the intersection of the common capacitance line and the scanning line which are also substantially parallel to the signal line, and the gate of the insulated gate transistor is formed. A third connection layer is formed by connecting any of the divided common capacitance lines or scan lines via an insulating layer or an interlayer insulating layer and another insulating layer, and having an organic insulating layer thereon. It is characterized by the following.

With this configuration, at the intersection of the common capacitance line and the scanning line, the thickness of the insulating layer that insulates and separates these electrode lines can be increased, and the parasitic capacitance of the scanning line decreases. As a result, the power consumption of the driving circuit for driving the scanning lines is also reduced. Further, an insulated active substrate can be obtained except for the pixel electrodes.

According to a fifteenth aspect of the present invention, in the liquid crystal display device, either the common capacitance line or the scanning line is divided at the intersection of the common capacitance line and the scanning line which are also substantially parallel to the signal line, and the gate of the insulated gate transistor is separated. A third connection for connecting any of the divided common capacitance lines or scanning lines via an insulating layer or an interlayer insulating layer and another insulating layer and having a low resistance metal layer and an organic insulating layer thereon; It is characterized in that a layer is formed.

According to this structure, the same effect as that of the liquid crystal display device according to the fourteenth aspect is obtained, and an increase in the resistance value of the electrode wire due to the interposition of the third connection layer is avoided, so that a large screen and high definition display is achieved. It is particularly effective in devices.

In the liquid crystal display device according to the sixteenth aspect, the first
12. The liquid crystal display device according to claim 10, further comprising a second or third connection layer in addition to said connection layer.

With this configuration, the thickness of the insulating layer that insulates and separates these electrode lines at the intersection between the scanning line and the signal line and the intersection between the common capacitance line and the scanning line or the signal line can be increased. As a result, the parasitic capacitance of the scanning line and the signal line is further reduced. As a result, the power consumption of the driving circuit for driving the scanning lines and the signal lines is further reduced.

In the liquid crystal display device according to the seventeenth aspect, the low resistance metal layer is made of one of gold, silver and copper. It is.

With this configuration, an increase in the resistance value of the divided electrode lines is avoided, and the image quality is not deteriorated due to the introduction of the connection lines even in a large-screen and high-definition liquid crystal display device.

A semiconductor device for a display device according to claim 18, wherein a scanning line composed of at least one metal layer and also serving as a gate electrode of an insulated gate transistor is formed on one main surface of the insulating substrate, A first semiconductor layer containing no impurities is formed in an island shape through one or more gate insulating layers, and a second semiconductor layer formed on the first semiconductor layer so as to overlap with the gate and contain impurities is formed. A semiconductor layer serving as a source / drain; a drain wiring and a source wiring (signal line) separated from the second semiconductor layer except for a scanning line are formed of one or more metal layers; A passivation insulating layer having a pair of first openings and a second opening on the drain wiring is formed at both ends of the wiring (signal line), and a second opening is formed on the passivation insulating layer. Including picture element Wherein the connection layer and is formed with an organic insulating layer thereon with connecting electrode and the shed source wiring comprise a pair of first openings (signal lines).

According to this configuration, at the intersection of the scanning line and the signal line, any of the divided electrode lines is connected by a connection layer formed on a stack of a gate insulating layer and a passivation insulating layer, and is connected to the scanning line. It is possible to reduce the parasitic capacitance between the signal lines. In addition, an organic insulating layer is formed on the connection layer, and portions other than the pixel electrodes are insulated.

A semiconductor device for a display device according to claim 19, wherein a scanning line composed of at least one metal layer and also serving as a gate electrode of an insulated gate transistor is formed on one main surface of the insulating substrate, A first semiconductor layer containing no impurity is formed in an island shape through one or more gate insulating layers, and a second semiconductor layer is formed on the first semiconductor layer so as to overlap with the gate and contain an impurity. A semiconductor layer serving as a source / drain, a drain wiring and a source (signal line) wiring separated except for a scanning line are formed of one or more metal layers on the second semiconductor layer; A passivation insulating layer having a pair of first openings on both ends of the (signal line) wiring and a second opening on the drain wiring is formed, and a second opening is formed on the passivation insulating layer. Including picture element A connection layer having a low-resistance metal layer and an organic insulating layer formed thereon while connecting the separated source (signal line) wiring including a pole and a pair of first openings; Features.

According to this structure, the same effect as that of the liquid crystal display device according to the seventeenth aspect is obtained, and an increase in the resistance value due to the interposition of the connection layer is avoided, which is particularly effective in a large screen and high definition display device. .

According to a twentieth aspect of the present invention, in the semiconductor device for a display device, the picture element electrode and the connection layer are simultaneously formed of the same member. Device.

According to this configuration, the manufacturing process does not increase in forming any of the divided connection lines, so that a semiconductor device for a display device can be obtained without increasing the cost, and the power consumption of the display device is reduced.

In the semiconductor device for a display device according to the present invention, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate.
A gate electrode made of at least one metal layer also serving as a scanning line is formed on the semiconductor layer with a gate insulating layer interposed therebetween, and a semiconductor layer into which impurities are implanted except under the gate electrode is used as a source / drain. An interlayer insulating layer having an opening is formed on the source / drain, and a drain wiring and a source wiring (signal line) separated except on a scanning line are formed on the interlayer insulating layer including the opening, A passivation insulating layer having a pair of first openings and a second opening on the drain electrode is formed at both ends of the source wiring (signal line), and a second opening is formed on the passivation insulating layer. And a connection layer having an organic insulating layer formed thereon, connecting the divided source wiring (signal line) including the pixel electrode and the pair of first openings. Toss .

According to this configuration, any of the divided electrode lines at the intersection of the scanning line and the signal line is connected by a connection layer formed on a stack of an interlayer insulating layer and a passivation insulating layer, and is connected to the scanning line. It is possible to reduce the parasitic capacitance between the signal lines. In addition, an organic insulating layer is formed on the connection layer, and portions other than the pixel electrodes are insulated.

In the semiconductor device for a display device according to the present invention, an island-shaped semiconductor layer is formed on one main surface of the insulating substrate.
A gate electrode made of at least one metal layer also serving as a scanning line is formed on the semiconductor layer via a gate insulating layer, and a semiconductor layer into which impurities are implanted except under the gate electrode is used as a source / drain. An interlayer insulating layer having an opening is formed on the source / drain, and a drain wiring and a source (signal line) wiring separated except on a scanning line are formed on the interlayer insulating layer including the opening, A passivation insulating layer having a pair of first openings and a second opening on the drain electrode is formed at both ends of a source (signal line) wiring, and a second opening is formed on the passivation insulating layer. And a connection layer having a low resistance metal layer and an organic insulating layer is formed thereon while connecting the divided source (signal line) wiring including the pixel electrode and the pair of first openings. Have been It is characterized in.

According to this configuration, the same effect as that of the liquid crystal display device according to the twenty-first aspect is obtained, and an increase in resistance value due to the interposition of the connection layer is avoided, which is particularly effective in a large-screen and high-definition display device. .

According to a twenty-third aspect of the present invention, in the semiconductor device for a display device, the picture element electrode and the connection layer are simultaneously formed by the same member. Device.

According to this configuration, a semiconductor device for a display device can be obtained without increasing the cost because the number of manufacturing steps does not increase when any of the divided connection lines is formed, and the power consumption of the display device is reduced.

[0080]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 3 show equivalent circuit diagrams of display devices according to first to sixth embodiments of the present invention, and FIGS. 4 to 6 show liquid crystal display devices according to ninth to fourteenth embodiments of the present invention. 7 is a plan view of a semiconductor device for an image display device according to the sixteenth and seventeenth embodiments of the present invention. Similarly, the eighteenth and nineteenth embodiments respectively show a plan view of an active substrate (semiconductor device for a display device) and a cross-sectional view of a manufacturing process on line AA 'in FIG. 8 and FIG. Parts having the same functions as those of the conventional example are denoted by the same reference numerals, and detailed description thereof will be omitted.

(First and Second Embodiments) In the display devices according to the first and second embodiments of the present invention, ie, the first and second embodiments, as shown in the equivalent circuit diagram of FIG. The switching insulated gate transistor 10 is connected at each intersection of the scanning line 11 and the signal line 12, and the storage capacitor 15 and the gate electrode of the driving insulated gate transistor 40 are connected to the drain wiring of the transistor. The drain wiring of the insulated gate transistor 40 for
A display medium 41 composed of L light emitting elements is connected. The storage capacitor 15 is necessary to make the driving insulated gate transistor 40 ΔN during the holding period (Japanese Patent Laid-Open No. 6-3 / 1994).
No. 25869).

Reference numerals 42 and 43 denote power supply lines for supplying and recovering electric power for driving the display medium. A power supply line (+ potential) common to the source lines of all the driving insulated gate transistors 40 has a potential of 42. And a conductive path formed on the insulating substrate. On the other hand, a feedback line (ground line, earth line) 43 for a current flowing through the light emitting element 41, which is formed of a conductive thin film layer formed on the organic EL light emitting thin film and is common to all the light emitting elements 41, is shown in Japanese Patent Application Laid-Open No. H8 (1996) -8. -234683).

It is a known technique that the scanning line 11 and the signal line 12 are insulated and separated by at least one or more kinds of insulating layers, but the insulating layer forms an insulated gate transistor for switching or driving. In addition to the gate insulating layer, the interlayer insulating layer, and the passivation insulating layer, the insulating layer is appropriately selected from insulators forming a storage capacitor and used. Usually, one kind is selected from these insulating layers, and a gate insulating layer or an interlayer insulating layer of an insulated gate transistor is generally employed.

Therefore, at the intersection 71 between the scanning line 11 and the signal line 12, an insulating layer at the intersection 71 is added to the gate insulating or interlayer insulating layer, for example, a passivation insulating layer is laminated, One of the lines 12 is divided, an opening is formed in the laminated insulating layer, and the divided wiring is connected with another conductive thin film (first connection layer). As the other conductive thin film, for example, an electrode forming a storage capacitor or an electrode forming a display element can be selected. In the first embodiment, an organic insulating layer is formed on the first connection layer. In the second embodiment, a low-resistance metal layer and an organic insulating layer are formed on the first connection layer.

As a result, at the intersection 71 between the scanning line 11 and the signal line 12, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection of the scanning line 11 and the signal line 12 is reduced. The first connection layer is protected by the organic insulating layer exhibiting a passivation function. In the second embodiment, it is easy to lower the resistance value of the first connection layer, and when the number of the first connection layers is large or the first connection layer is elongated, that is, a display device with a large screen and high definition. Is particularly effective.

(Third and Fourth Embodiments) In the third and fourth embodiments of the present invention, that is, in the display device according to the third and fourth aspects, as shown in the equivalent circuit diagram of FIG. In addition, at the intersection 72 between the power supply line 42 also serving as the source wiring of the driving insulated gate transistor substantially parallel to the scanning line 11 and the signal line 12 of the switching insulated gate transistor, the insulating layer at the intersection 72 is replaced with the gate. In addition to laminating a passivation insulating layer, for example, in addition to the insulating or interlayer insulating layer, one of the signal line 12 and the power supply line 42 is separated,
An opening is formed in the laminated insulating layer, and any of the divided wirings is connected with another conductive thin film (second connection layer). In the third embodiment, an organic insulating layer is formed on the second connection layer. In the fourth embodiment, a low-resistance metal layer and an organic insulating layer are formed on the second connection layer.

As a result, at the intersection 72 between the signal line 12 and the power supply line 42, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection of the signal line 12 and the power supply line 42 is reduced. The second connection layer is protected by the organic insulating layer exhibiting a passivation function. In the fourth embodiment, it is easy to lower the resistance value of the second connection layer, and when the number of the second connection layers is large or the second connection layer is elongated, that is, a large screen and high definition display device. Is particularly effective.

As in the third and fourth embodiments, the power supply line 42 also serving as the source wiring of the driving insulated gate transistor
Is the scanning line 1 of the insulated gate transistor for switching
If the power supply line 42 is arranged in parallel with the power supply line 1 and the screen size of the display device is large, the potential drop of the power supply line 42 becomes large. Therefore, when the screen size is large, the power line 42 is connected to the signal line 12.
It is a general design matter to arrange them in parallel.

(Fifth and Sixth Embodiments) The display devices according to the fifth and sixth embodiments of the present invention, that is, the display devices according to the fifth and sixth aspects are shown in the equivalent circuit diagram of FIG. like,
An intersection 73 between the power supply line 42 also serving as the source wiring of the driving insulated gate transistor substantially parallel to the signal line 12 and the scanning line 11 of the switching insulated gate transistor.
In addition, the insulating layer at the intersection 73 is added to the gate insulating or interlayer insulating layer, for example, a passivation insulating layer is laminated, and one of the scanning line 11 and the power supply line 42 is separated, and an opening is formed in the laminated insulating layer. Is formed, and any of the divided wirings is connected by another conductive thin film (third connection layer). In the fifth embodiment, an organic insulating layer is formed on the third connection layer, and in the sixth embodiment, a low-resistance metal layer and an organic insulating layer are formed on the third connection layer.

As a result, at the intersection 73 between the scanning line 11 and the power supply line 42, the thickness of the insulating layer at the intersection is increased, so that the parasitic capacitance caused by the intersection between the scanning line 11 and the power supply line 42 is reduced. The third connection layer is protected by the organic insulating layer exhibiting a passivation function. In the sixth embodiment, it is easy to lower the resistance value of the third connection layer, and when the number of the third connection layers is large or the third connection layer is elongated, that is, a large screen and high definition display device. Is particularly effective.

(Seventh Embodiment) In a display device according to a seventh embodiment of the present invention, that is, a display device according to claim 7, although not shown, in addition to the above-described first connection layer, a second or third display layer is provided. The connection layer is added to minimize the load on the scanning lines and the signal lines, thereby suppressing power consumption.

In the second, fourth and sixth embodiments,
Specific examples of the low-resistance metal layer include gold, silver, and copper. Of course, even if these alloys are used, there is no problem. However, considering the utilization efficiency, etc., any one of them is preferable from the viewpoint of the manufacturing method, and it is preferable to form them by plating. Yield.

(Eighth Embodiment) In a display device according to an eighth embodiment of the present invention, that is, a ninth embodiment, a switching insulated gate transistor can also serve as a driving insulated gate transistor. The present invention is applied to a display device in which power for driving a display medium is small, and specifically, a liquid crystal display device using a liquid crystal as a display medium corresponds thereto.

(Ninth and Tenth Embodiments) The ninth and tenth embodiments of the present invention
And the tenth embodiment, that is, claims 10 and 11
As shown in the equivalent circuit diagram of FIG. 4 in the liquid crystal display device described in (1), in the active type liquid crystal display device in which the storage capacitor 15 is formed between the preceding scanning line 11 and the pixel electrode, the switching insulation At the intersection 71 between the scanning line 11 and the signal line 12 of the gate type transistor 10, an insulating layer at the intersection 71 is added to the gate insulation or interlayer insulation layer, for example, a passivation insulation layer is laminated, and the scanning line 11 and the signal Any one of the lines 12 is divided, an opening is formed in the laminated insulating layer, and any divided wiring is connected by another conductive thin film (first connection layer).
As the other conductive thin film, for example, a transparent conductive layer or the like can be selected as an electrode forming a storage capacitor or an electrode forming a display element. In the ninth embodiment, an organic insulating layer is formed on the first connection layer. In the tenth embodiment, a low-resistance metal layer and an organic insulating layer are formed on the first connection layer.

As a result, the thickness of the insulating layer at the intersection 71 between the scanning line 11 and the signal line 12 is increased, so that the parasitic capacitance caused by the intersection of the scanning line 11 and the signal line 12 is reduced. The first connection layer is protected by the organic insulating layer exhibiting a passivation function. In the tenth embodiment, it is easy to lower the resistance value of the first connection layer, and when the number of the first connection layers is large or the first connection layer is elongated, that is, a large screen / high definition display device Is particularly effective.

(Eleventh and Twelfth Embodiments) In the eleventh and twelfth embodiments of the present invention, that is, in the display device according to the twelfth and thirteenth aspects, as shown in the equivalent circuit diagram of FIG. In an active liquid crystal display device in which a storage capacitor 15 is formed between the storage capacitor line 16 and the pixel electrode, the storage capacitor line 16 and the signal line 12 substantially parallel to the scanning line 11 of the switching insulated gate transistor are used. At the intersection 72 with the gate insulation layer 4
Alternatively, for example, a passivation insulating layer is stacked in addition to the interlayer insulating layer, and any one of the signal line 12 and the storage capacitor line 16 is separated, and an opening is formed in the stacked insulating layer to form one of the separated insulating layers. The wiring is connected by another conductive thin film (second connection layer). In the eleventh embodiment, an organic insulating layer is formed on the second connection layer. In the twelfth embodiment, a low-resistance metal layer and an organic insulating layer are formed on the second connection layer.

As a result, the thickness of the insulating layer at the intersection 72 between the signal line 12 and the storage capacitor line 16 is increased, so that the parasitic capacitance caused by the intersection of the signal line 12 and the storage capacitor line 16 is reduced. I do. The second connection layer is protected by the organic insulating layer exhibiting a passivation function. In the twelfth embodiment, it is easy to lower the resistance value of the second connection layer, and when the number of the second connection layers is large or the second connection layer is elongated, that is, a large screen / high definition display device. Is particularly effective.

(Thirteenth and Fourteenth Embodiments) Embodiments of the thirteenth and fourteenth embodiments of the present invention, that is, claims 1
In the active liquid crystal display device having the storage capacitor 15 between the storage capacitor line 16 and the pixel electrode, as shown in the equivalent circuit diagram of FIG. A storage capacitor line 16 and a scanning line 11 substantially parallel to the signal line 12 of the switching insulated gate transistor
In addition to the gate insulating layer or the interlayer insulating layer, for example, a passivation insulating layer is laminated at the intersection 73 between the scanning line 11 and the storage capacitor line 1.
6, and an opening is formed in the laminated insulating layer, and any of the divided wirings is connected to another conductive thin film (third conductive film).
Connection layer). In the thirteenth embodiment, an organic insulating layer is formed on the third connection layer.
In the embodiment, a low resistance metal layer and an organic insulating layer are formed on the third connection layer.

As a result, at the intersection 73 between the scanning line 11 and the storage capacitance line 16, the insulating layer at the intersection is thickened, so that the parasitic capacitance caused by the intersection between the scanning line 11 and the storage capacitance line 16 is reduced. I do. The third connection layer is protected by the organic insulating layer exhibiting a passivation function. In the fourteenth embodiment, it is easy to lower the resistance value of the third connection layer, and when the number of the third connection layers is large or the third connection layer is elongated, that is, a large screen and high definition display device. Is particularly effective.

(Fifteenth Embodiment) In the fifteenth embodiment of the present invention, that is, in the liquid crystal display device according to the sixteenth aspect, although not shown, in addition to the above-described first connection layer, a second or a second connection layer is provided. The third connection layer is added to reduce the load on the scanning lines and the signal lines to the utmost so as to suppress the power consumption.

In the tenth, twelfth and fourteenth embodiments, the low-resistance metal layer specifically includes gold, silver or copper. Of course, even if these alloys are used, there is no problem. However, in consideration of the utilization efficiency and the like, any one of them is preferable from the viewpoint of the manufacturing method and is preferably formed by plating, but the detailed description is omitted.

(Sixteenth and Seventeenth Embodiments) FIGS. 16 and 17 are plan views of a unit pixel of a semiconductor device for a display device according to the sixteenth and seventeenth embodiments of the present invention. FIG. In manufacturing a transmissive liquid crystal display device by the streamlined five-mask process shown in FIG. 15, the signal line 12 is divided and formed at the intersection with the scanning line 11.
2 ′ and the signal line 1 separated from the drain wiring 21
A passivation insulating layer 37 having openings 62 and 61 at both ends of 2 'is formed, and the pixel electrode 22 including the opening 62 and the first connection layer 70 including the pair of openings 61 are transparent. It is formed using a conductive layer. In the sixteenth embodiment, the organic insulating layer 9 is formed on the first connection layer 70.
1 is formed. In the seventeenth embodiment, the low resistance metal layer 92 is formed on the first connection layer 70, and then the organic insulating layer 91 is formed on the low resistance metal layer 92.

In the seventeenth embodiment, the low-resistance metal layer 92 is formed on the first connection layer 70 by plating, but it is not necessary to form the low-resistance metal layer on the transparent conductive picture element electrode 22. It is necessary to perform plating in a dark place. In fact, the amount of plating formed on the pixel electrode 22 by the leakage current of the insulated gate transistor is insignificant. The thickness of the low-resistance metal layer 92 is determined by a required resistance value. For example, the low-resistance metal layer 92 having a thickness of about 0.2 μm is formed.

At least the first connection layer 7 in the image display section
In order to form the organic insulating layer 91 on the zero or low resistance metal layer 92, for example, a polyimide layer is formed to a thickness of about 0.2 μm by electrodeposition, but the organic insulating layer is formed on the pixel electrode 22. Since there is no necessity, it is necessary to perform electrodeposition in a dark place as in the above plating. The amount of electrodeposition formed on the pixel electrode 22 and the drain wiring 21 by the leak current of the insulated gate transistor is insignificant.

If a small amount of the low-resistance metal layer 92 and the organic insulating layer 91 are formed on the pixel electrode 22 with a slight leak current of the insulated gate transistor in the above-described manufacturing process, first, the organic insulating layer 91 is formed by oxygen plasma. Needless to say, it is only necessary to remove the low-resistance metal layer 92 using an appropriate chemical solution. Alternatively, they may be scattered and removed by reverse sputtering using Ar (argon) gas. In this case, there is the convenience that the low-resistance metal layer 92 and the organic insulating layer 91 can be removed at the same time.

The low resistance metal layer 92 on the first connection layer 70
When a mask material such as a photosensitive resin is used in combination for selective formation of the organic insulating layer 91 and the organic insulating layer 91, the number of manufacturing steps is increased. Therefore, basically, the inside of the substrate disclosed in Japanese Patent Application No. It is reasonable to employ a selective electrochemical treatment apparatus or the like to selectively form these thin films on the surface of the glass substrate 2.

The low resistance metal layer 92 on the first connection layer 70
It should be noted that when selectively forming the organic insulating layer 91, all the signal lines 12 need to be formed electrically in parallel or in series outside of the image display section. Needless to say, if this series-parallel operation is not released, not only the electrical inspection of the active substrate 2 but also the actual operation of the liquid crystal display device will be hindered. The technique of releasing the series-parallel connection by using means such as cutting or chamfering the glass substrate 2 or evaporation using a high-energy ray such as a laser is known and may be appropriately selected. Signal line 1
If the two are not connected in series or in parallel, a mechanism for bundling the terminal electrodes like an in-substrate selective electrochemical device, for example, pressing a metal electrode on a plurality of terminal electrodes via anisotropic conductive rubber Such a mechanism is required.

According to the above-described configuration, the scanning line 11 and the connection layer 70 which is a part of the signal line intersect with each other with the insulating layer formed by stacking the gate insulating layer 30 and the passivation insulating layer 37. Obviously, the parasitic capacitance decreases as the thickness of the layer increases. Select the etch stop type for the insulated gate type transistor and passivation insulating layer 3
When a flattening resin layer made of a highly transparent acrylic resin is adopted for 7, or when a flattening resin layer made of a highly transparent acrylic resin is further laminated in addition to the passivation insulating layer 37, the flattening resin usually becomes Since the film is formed with a thickness of 1.5 μm or more, the parasitic capacitance value is further reduced, and another parasitic capacitance, for example, the transparent conductive layer 14 on the color filter 9 facing the signal line 12 is interposed between the alignment film and the liquid crystal. It can be made as small as the same as the parasitic capacitance value configured by

As described in claim 20, the increase in the number of manufacturing steps is small, and the parasitic capacitance formed by the scanning lines 11 and the signal lines 12 can be significantly reduced only by changing the mask for manufacturing the active substrate 2. As a result, the effect of two birds per stone can be obtained for a liquid crystal panel for a mobile phone or the like, which has strict regulations on power consumption.

(Eighteenth and Nineteenth Embodiments) The eighteenth and nineteenth embodiments of the present invention, that is, plan views of a unit pixel of a semiconductor device for a display device according to claims 21 and 22 are shown. As shown in FIG. Unlike the sixteenth and seventeenth embodiments, an insulated gate transistor in which a so-called low-temperature polysilicon is selected for the semiconductor layer is used for switching, and the manufacturing on the line AA ′ in FIG. A process sectional view will be described.

First, although not shown, as described above, as an insulating transparent substrate 2 having excellent transparency, heat resistance, and chemical resistance, an alkali blocking layer having a thickness of 0.3 was formed on one main surface of a product name 1737 manufactured by Corning Incorporated. μm SiO2 or SiNx
To adhere. Then, using a PCVD device, the film thickness is 0.05μ.
After the amorphous silicon layer having a thickness of about m is deposited and heated to reduce the contained hydrogen, the amorphous silicon layer is crystallized by excimer laser irradiation. Then, the so-called low-temperature polysilicon which has been crystallized as shown in FIG. 9A is selectively removed to leave 80 on the glass substrate 2 in an island shape.

Next, the gate insulating layer 30 is entirely coated with SiO 2 having a thickness of about 0.1 μm at a substrate heating temperature of about 500 ° C. and a MoW alloy having a thickness of about 0.3 μm as a gate metal layer by CVD or TEOS-PCVD. After the contact, as shown in FIG. 9B, M is applied by a fine processing technique corresponding to the pattern of the gate 11 electrode (and the common capacitance line 16).
The low temperature polysilicon 80 is exposed by etching oW and SiO2. Then, although not shown, phosphorus is implanted into the low-temperature polysilicon 80 as an impurity by ion implantation or ion irradiation using the gate 11 electrode as a mask to form the source / drain 81, 82 of the insulated gate transistor. If necessary, a step of improving the electrical characteristics of the insulated gate transistor by providing a region with a reduced impurity concentration between the channel region below the gate 11 electrode and the source / drain 81, 82 may be provided. (Lightly-Doped-Drain
Configurations and abbreviations are LDD configurations).

Subsequently, as shown in FIG. 9C, for example, SiO 2 having a thickness of about 0.2 μm is applied as the interlayer insulating layer 83 by the above-mentioned manufacturing method, and is formed on the source / drain 81 and 82 by the fine processing technique. A pair of openings 84 and 85 are formed.

Subsequently, as shown in FIG. 9D, as the source / drain electrode material, for example, a film having a thickness of 0.1 / 0.3 / 0.1 μm is used.
After a stack of about m metal layers such as Ti / Al / Ti is deposited by using a film forming apparatus such as sputtering, a source (signal line) including a pair of openings 84 and 85 is formed by a fine processing technique. The drain wirings 12 'and 21 are formed. At this time, as shown in FIG. 8, the signal line 12 ′ is divided at the intersection with the scanning line 11.

Further, as shown in FIG. 9E, the passivation insulating layer 37 has a thickness of, for example, about 0.3 μm.
O2 is deposited by the above-described manufacturing method, and the opening 62 and the divided signal line 1 are formed on the drain electrode 21 by a fine processing technique.
A pair of openings 61 is formed on both ends of 2 ′.

Then, as shown in FIG.
After ITO, which is a transparent conductive layer having a thickness of about 0.2 μm, is deposited by using a film forming apparatus such as sputtering, the pixel electrode 22 and a pair of openings are formed on the passivation insulating layer 37 through the fine processing technique. In the eighteenth embodiment, an organic insulating layer 91 is formed on the first connection layer 70, as shown in FIG. 9 (g). In the nineteenth embodiment, as shown in FIG. 9H, a low resistance metal layer 92 is formed on the first connection layer 70, and then an organic insulating layer 91 is formed on the low resistance metal layer 92 for display. The device semiconductor device is completed. The semiconductor device for a display device and a color filter are attached to each other to form a liquid crystal panel to obtain a liquid crystal display device.

According to the above configuration, the scanning line 11 and the connection layer 70 which is a part of the signal line intersect with each other through the insulating layer formed by laminating the interlayer insulating layer 83 and the passivation insulating layer 37. It will be apparent that the increased parasitic thickness reduces the parasitic capacitance. Since the parasitic capacitance decreases as the passivation insulating layer 37 becomes thicker, a preferable result is obtained when a flattening resin layer made of highly transparent acrylic resin is used for the passivation insulating layer 37.

When the picture element electrode and the connection layer are simultaneously formed using the same member as described in the twenty-third aspect, the number of manufacturing steps is small, and the scanning line can be formed only by changing the mask for manufacturing the active substrate 2. It is possible to significantly reduce the parasitic capacitance formed by the signal line 11 and the signal line 12.

[0119]

As described above, according to the display device of the present invention, at the intersection between the scanning line or the signal line and another power supply line, or at the intersection between the scanning line and the signal line. ,
Any of the intersecting wirings is cut off, and a connection layer is formed to connect the separated wirings through another type of insulating layer such as a gate insulating layer or an interlayer insulating layer and a passivation insulating layer. Is reduced.
As a result, power consumption of a circuit for driving the scanning lines and the signal lines can be reduced, which is high in terms of energy saving. In particular, the effect is enhanced in a large screen and high definition display device.

The reduction in power consumption during driving also reduces the power consumption during standby.
This is an extremely useful technique for a battery-powered portable information terminal device such as A.

Further, since two types of insulating layers are laminated at the intersection, even if a pinhole or a defective portion occurs in any one of the insulating layers for some reason, the other insulating layer fills it. Therefore, the secondary effect of reducing the interlayer short-circuit at the intersection and improving the yield can be a notable feature from the viewpoint of production.

In the active matrix display device according to the present invention, as described above, the semiconductor material constituting the insulated gate transistor as the switching element is amorphous silicon, microcrystalline silicon, (low-temperature) polysilicon, or It is clear that there is no restriction on the material such as the mixed crystal. In addition, there is no problem in applying the FS (field sequential) type liquid crystal display device at all. Alternatively, the same applies to a reflection type liquid crystal display device in which a picture element electrode includes a reflection electrode, and a transflective liquid crystal display device in which a picture element electrode includes a transparent electrode and a reflection electrode. The effectiveness of the present invention does not change even in an active display device in which the display medium is an organic EL, one of the picture element electrodes is a transparent electrode or a reflective electrode, and the other common electrode is a reflective electrode or a transparent electrode. Which of the intersecting electrodes is divided is optional when the low-resistance metal layer and the organic insulating layer are formed on the connection line, and when only the organic insulating layer is formed on the connection line. Should select an electrode wire which does not disadvantageously increase the resistance value.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a display device according to first and second embodiments of the present invention.

FIG. 2 is an equivalent circuit diagram of a display device according to third and fourth embodiments of the present invention.

FIG. 3 is an equivalent circuit diagram of a display device according to fifth and sixth embodiments of the present invention.

FIG. 4 is an equivalent circuit diagram of a liquid crystal display device according to ninth and tenth embodiments of the present invention.

FIG. 5 is an equivalent circuit diagram of a liquid crystal display device according to eleventh and twelfth embodiments of the present invention.

FIG. 6 is an equivalent circuit diagram of a liquid crystal display device according to thirteenth and fourteenth embodiments of the present invention.

FIG. 7 is a plan view of a semiconductor device for a display device according to sixteenth and seventeenth embodiments of the present invention.

FIG. 8 is a plan view of a semiconductor device for a display device according to the eighteenth and nineteenth embodiments of the present invention.

FIG. 9 is a sectional view showing a manufacturing process of the semiconductor device for an image display device according to the eighteenth and nineteenth embodiments of the present invention.

FIG. 10 is a perspective view showing a mounted state of a liquid crystal panel.

FIG. 11 is an equivalent circuit diagram of a liquid crystal panel.

FIG. 12 is a sectional view of a main part of a liquid crystal panel.

FIG. 13 is a plan view of a conventional active substrate.

FIG. 14 is a sectional view showing a manufacturing process of a conventional active substrate.

FIG. 15 is a plan view of a streamlined active substrate.

FIG. 16 is a cross-sectional view of a manufacturing process of a rationalized active substrate.

[Explanation of symbols]

Reference Signs List 1 liquid crystal image display device (liquid crystal panel) 2 active substrate (insulating substrate, glass substrate) 3 semiconductor integrated circuit chip 4 TCP film 5, 6 terminal electrode 9 color filter (opposing glass substrate) 10 insulated gate transistor 11 scanning line ( (Gate electrode) 12 (12 ′) signal line (source electrode, source wiring) 14 counter electrode 16 storage capacitor line 17 liquid crystal 21 drain wiring (electrode) 22 (transparent conductive) picture element electrode 30 gate insulating layer (first 31) an amorphous silicon layer containing no impurity 32 (which is an insulating layer for protecting a channel) second Si
Nx layer 33 Amorphous silicon layer containing impurities 34 Refractory metal layer 35 Low resistance metal layer (AL) 36 Intermediate conductive layer 37 Passivation insulating layer 42, 43 Power supply line and recovery (feedback) line 61 for driving the display medium 61 Opening 62 (on the separated signal line 12 ′) 62 Opening (on the drain wiring) 70 Connection layer 71 (connecting the separated signal line 12 ′) 71 Intersection between the scanning line and the signal line 72 Signal line Intersection between scanning line and power supply line (storage capacitor line) 73 intersection between scanning line and power supply line (storage capacitor line) 83 interlayer insulating layer 91 organic insulating layer 92 low resistance metal layer

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G02F 1/1368 G02F 1/1368 G09F 9/35 G09F 9/35 H01L 29/786 H01L 29/78 612C 618A F term (reference) 2H092 GA24 HA06 HA28 JA24 JA34 JB22 JB31 JB57 KB04 NA26 5C094 AA04 AA05 AA13 AA22 AA42 AA43 BA03 BA27 BA43 CA19 CA24 DA15 DB01 DB04 DB10 EA04 EA05 DD06 FB03 DD02 FB02 EE45 FF02 FF29 FF30 GG02 GG13 GG14 GG15 GG25 GG45 HJ01 HJ12 HJ13 HL03 HL04 HL12 HL23 HM15 NN03 NN04 NN23 NN27 NN33 NN35 NN72 PP03 PP35 QQ11 QQ19

Claims (23)

[Claims] A storage capacitor connected to at least a switching insulated gate transistor, a scanning line also serving as a gate electrode of the switching insulated gate transistor and a source line, and a drain line on one main surface. And a display medium comprising a display medium and a unit picture element having a driving insulated gate transistor and a display electrode connected to a drain wiring of the driving insulated gate transistor arranged in a two-dimensional matrix. In the device, either the scanning line or the signal line is divided at the intersection of the scanning line and the signal line, and the division is performed via a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer. A first connection layer having an organic insulating layer formed thereon while connecting either the scanning line or the signal line; Display device according to claim Rukoto. 2. A storage capacitor connected to at least a switching insulated gate transistor on one principal surface, a scanning line also serving as a gate electrode of the switching insulated gate transistor, a signal line also serving as a source wiring, and a drain wiring. And a display medium comprising a display medium and a unit picture element having a driving insulated gate transistor and a display electrode connected to a drain wiring of the driving insulated gate transistor arranged in a two-dimensional matrix. In the device, either the scanning line or the signal line is divided at the intersection of the scanning line and the signal line, and the division is performed via a gate insulating layer or an interlayer insulating layer of a switching insulated gate transistor and another insulating layer. A first connection for connecting either the scanning line or the signal line and having a low resistance metal layer and an organic insulating layer thereon; Display device, wherein the layer is formed. 3. A storage capacitor connected to at least a switching insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the switching insulated gate transistor, a signal line also serving as a source line, and a drain line. And a display medium comprising a display medium and a unit picture element having a driving insulated gate transistor and a display electrode connected to a drain wiring of the driving insulated gate transistor arranged in a two-dimensional matrix. In the apparatus, either the power supply line or the signal line is divided at an intersection of a power supply line and a signal line which also serves as a source wiring of a driving insulated gate transistor substantially parallel to a scanning line, and a gate of the switching insulated gate transistor is provided. The separated power supply line or signal line is connected through an insulating layer or an interlayer insulating layer and another insulating layer. That the second connecting layer having an organic insulating layer is formed thereon with display device according to claim. 4. A storage capacitor connected to at least a switching insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the switching insulated gate transistor, a signal line also serving as a source line, and a drain line. And a display medium comprising a display medium and a unit picture element having a driving insulated gate transistor and a display electrode connected to a drain wiring of the driving insulated gate transistor arranged in a two-dimensional matrix. In the apparatus, either the power supply line or the signal line is divided at an intersection of a power supply line and a signal line which also serves as a source wiring of a driving insulated gate transistor substantially parallel to a scanning line, and a gate of the switching insulated gate transistor The separated power supply line or signal line is connected through an insulating layer or an interlayer insulating layer and another insulating layer. Display apparatus characterized by a second connecting layer having a low resistance metal layer and the organic insulating layer is formed thereon while. 5. A storage capacitor connected to at least a switching insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the switching insulated gate transistor, a signal line also serving as a source line, and a drain line. And a display medium including a display medium and a unit picture element having a driving insulated gate transistor and a display electrode connected to a drain wiring of the driving insulated gate transistor arranged in a two-dimensional matrix. In the device, either the power supply line or the scanning line is divided at an intersection of a power supply line also serving as a source wiring of the driving insulated gate transistor substantially parallel to the signal line and the scanning line, and a gate of the switching insulated gate transistor is provided. The separated power supply line or scanning line is connected through an insulating layer or an interlayer insulating layer and another insulating layer. That the third connecting layer having an organic insulating layer is formed thereon with display device according to claim. 6. A storage capacitor connected to at least a switching insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the switching insulated gate transistor, a signal line also serving as a source wiring, and a drain wiring. And a display medium comprising a display medium and a unit picture element having a driving insulated gate transistor and a display electrode connected to a drain wiring of the driving insulated gate transistor arranged in a two-dimensional matrix. In the device, either the power supply line or the scanning line is divided at an intersection of a power supply line also serving as a source wiring of the driving insulated gate transistor substantially parallel to the signal line and the scanning line, and a gate of the switching insulated gate transistor is provided. The separated power supply line or scanning line is connected through an insulating layer or an interlayer insulating layer and another insulating layer. Display apparatus characterized by a third connecting layer having a low resistance metal layer and the organic insulating layer is formed thereon while. 7. The display device according to claim 1, further comprising a second or third connection layer in addition to the first connection layer. 8. The display device according to claim 2, wherein the low-resistance metal layer is made of one of gold, silver, and copper. 9. The display device according to claim 1, wherein the switching insulated gate transistor and the driving insulated gate transistor are the same. 10. A main surface having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to a drain wiring. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which unit picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line and a signal line Either the scanning line or the signal line is divided at the intersection of the above, and any one of the divided scanning line or the signal line is connected via a gate insulating layer or an interlayer insulating layer of the insulated gate transistor and another insulating layer. And a first connection layer having an organic insulating layer formed thereon. 11. A semiconductor device having at least one insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to a drain wiring. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which unit picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter opposed to the insulating substrate, a scanning line and a signal line Either the scanning line or the signal line is divided at the intersection of the above, and any one of the divided scanning line or the signal line is connected via a gate insulating layer or an interlayer insulating layer of the insulated gate transistor and another insulating layer. And a first connection layer having a low resistance metal layer and an organic insulating layer formed thereon. 12. A main surface having at least an insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to a drain wiring. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which unit picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter facing the insulating substrate, a liquid crystal display device substantially parallel to a scanning line Either the common capacitance line or the signal line is divided at the intersection of the common capacitance line and the signal line, and the divided common capacitance is interposed between the gate insulating layer or the interlayer insulating layer of the insulated gate transistor and another insulating layer. A liquid crystal display device, wherein a second connection layer having an organic insulating layer formed thereon is connected to one of the line and the signal line. 13. A semiconductor device comprising at least one insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to a drain wiring on one main surface. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which unit picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter facing the insulating substrate, a liquid crystal display device substantially parallel to a scanning line Either the common capacitance line or the signal line is divided at the intersection of the common capacitance line and the signal line, and the divided common capacitance is interposed between the gate insulating layer or the interlayer insulating layer of the insulated gate transistor and another insulating layer. A liquid crystal display device, wherein a second connection layer having a low-resistance metal layer and an organic insulating layer is formed thereon while connecting either the line or the signal line. . 14. A semiconductor device comprising at least one insulated gate transistor, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to a drain wiring on one main surface. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which unit picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter facing the insulating substrate, a liquid crystal display device substantially parallel to a signal line is provided. Either the common capacitance line or the scanning line is divided at the intersection of the common capacitance line and the scanning line, and the divided common capacitance is interposed between the gate insulating layer or the interlayer insulating layer of the insulated gate transistor and another insulating layer. A liquid crystal display device, wherein a third connection layer having an organic insulating layer is formed thereon while connecting either the line or the scan line. 15. A semiconductor device having at least one insulated gate transistor on one main surface, a scanning line also serving as a gate electrode of the insulated gate transistor, a signal line also serving as a source wiring, and a picture element electrode connected to a drain wiring. In a liquid crystal display device in which liquid crystal is filled between an insulating substrate in which unit picture elements are arranged in a two-dimensional matrix and a transparent insulating substrate or a color filter facing the insulating substrate, a liquid crystal display device substantially parallel to a signal line is provided. Either the common capacitance line or the scanning line is divided at the intersection of the common capacitance line and the scanning line, and the divided common capacitance is interposed between the gate insulating layer or the interlayer insulating layer of the insulated gate transistor and another insulating layer. And a third connection layer having a low-resistance metal layer and an organic insulating layer formed thereon for connecting any one of the lines and the scanning lines. . 16. In addition to the first connection layer, the second or third connection layer
The liquid crystal display device according to claim 10, further comprising a connection layer. 17. The liquid crystal display device according to claim 11, wherein the low resistance metal layer is made of one of gold, silver and copper. 18. A scanning line comprising one or more metal layers and also serving as a gate electrode of an insulated gate transistor is formed on one main surface of an insulating substrate, and one or more gate insulating layers are interposed on the gate. A first semiconductor layer containing no impurities is formed in an island shape; a second semiconductor layer formed on the first semiconductor layer and containing the impurities so as to overlap with the gate is used as a source / drain; A drain wiring and a source wiring (signal line) separated except for the scanning line are formed of one or more metal layers on the semiconductor layer, and a pair of second wirings is provided at both ends of the separated source wiring (signal line). A passivation insulating layer having an opening and a second opening on the drain wiring; a pixel electrode including the second opening on the passivation insulating layer; Including the opening And a source wiring (signal line) that the connection layer having an organic insulating layer is formed thereon with connecting display device wherein a. 19. A scanning line comprising one or more metal layers and also serving as a gate electrode of an insulated gate transistor is formed on one main surface of an insulating substrate, and one or more gate insulating layers are formed on the gate via the gate insulating layer. A first semiconductor layer containing no impurities is formed in an island shape; a second semiconductor layer formed on the first semiconductor layer and containing the impurities so as to overlap with the gate is used as a source / drain; A drain wiring and a source wiring (signal line) separated except for a scanning line are formed of one or more metal layers on the semiconductor layer, and a pair of second wirings is provided at both ends of the separated source (signal line) wiring. A passivation insulating layer having a first opening and a second opening on the drain wiring; a pixel electrode including the second opening on the passivation insulating layer and a pair of first openings; Including the division A source wiring (signal line) that a connecting layer having a low resistance metal layer and the organic insulating layer is formed for a display device wherein a thereon with connecting that. 20. The image display device according to claim 18, wherein the picture element electrode and the connection layer are simultaneously formed of the same member.
4. The semiconductor device for a display device according to item 1. 21. An island-shaped semiconductor layer is formed on one main surface of an insulating substrate, and a gate electrode made of at least one metal layer also serving as a scanning line is formed on the semiconductor layer via a gate insulating layer. A semiconductor layer into which impurities are implanted except for a portion under the gate electrode is used as a source / drain, an interlayer insulating layer having an opening on the source / drain is formed, and a drain is formed on the interlayer insulating layer including the opening. A wiring and a source wiring (signal line) separated except on the scanning line are formed, and a pair of first openings and a second opening on the drain electrode at both ends of the source wiring (signal line). A passivation insulating layer having a first portion and a pixel electrode including a second opening and a pair of first openings including the divided source line (signal line) on the passivation insulating layer. Connect with A semiconductor device for a display device, wherein a connection layer having an organic insulating layer is formed thereon. 22. An island-shaped semiconductor layer is formed on one main surface of an insulating substrate, and a gate electrode made of at least one metal layer also serving as a scanning line is formed on the semiconductor layer via a gate insulating layer. A semiconductor layer into which an impurity is implanted except for a portion under the gate electrode is used as a source / drain, an interlayer insulating layer having an opening on the source / drain is formed, and a drain is formed on the interlayer insulating layer including the opening. A wiring and a source wiring (signal line) separated except on the scanning line are formed, and a pair of first openings and a second opening on the drain electrode at both ends of the source wiring (signal line). A passivation insulating layer having a second portion and a pixel electrode including a second opening and the divided source wiring (signal line) including a pair of first openings on the passivation insulating layer. Connect with A semiconductor device for a display device, wherein a connection layer having a low resistance metal layer and an organic insulating layer is formed thereon. 23. The picture element electrode and the connection layer are simultaneously formed of the same member.
4. The semiconductor device for a display device according to item 1.