JP2002237984A - Digital camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital camera that shortens the time, when a shutter button is operated until the corresponding image data are recorded in a memory card. SOLUTION: When a shutter button 58 is fully depressed, a CPU 42 conducts write processing to write image data, corresponding to an object image at a point of fully depressing time to an SDRAM(synchronous Dynamic RAM) 28 and recording processing to record image data written in the SDRAM 28 onto a memory card 48. The write processing includes compression of YUV data, outputted from a signal processing circuit 22, and writing of the compression data to the SDRAM 28 or the like, while the recording processing includes reading of the compression data from the SDRAM 28 and recording of the read compression data onto the memory card 48 or the like. A multitask OS, such as μiTRON, is installed in the CPU 42, and the write processing and the record processing such as above are conducted in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly, to a digital camera for photographing a subject in response to a photographing command and recording a photographed image signal on a recording medium.

[0002]

2. Description of the Related Art In a conventional digital camera, a subject image is photographed by an image sensor such as a CCD imager, and a photographed image signal is subjected to predetermined signal processing and then recorded on a recording medium by a CPU. Was.

[0003]

However, most recording media are removable, and such recording media are connected to a CPU via an interface. For this reason, in the related art, it takes a long time to record the image signal, and as a result, there is a problem that the operation interval of the shutter button, that is, the shooting interval becomes long.

[0004] Therefore, a main object of the present invention is to provide a digital camera capable of shortening a photographing interval.

[0005]

According to the present invention, a first input key for inputting a photographing instruction, a photographing circuit for photographing a subject image based on the photographing instruction, an internal memory, and an image signal of the subject image are written in the internal memory. The digital camera includes a multitask CPU that performs a writing process and a recording process of recording an image signal of an internal memory on a recording medium in parallel.

[0006]

When a photographing instruction is inputted by the first input key, the photographing circuit photographs a subject image. The image signal of the subject image is once written in the internal memory and then recorded on a recording medium. The writing process of writing the image signal to the internal memory and the recording process of recording the image signal of the internal memory on the recording medium are performed in parallel by the multitask CPU.

In one aspect of the present invention, the writing processing includes: a photographing instruction discriminating processing for discriminating the input of the photographing instruction at a predetermined timing; It includes an image writing process of writing an image signal into an internal memory and a creation process of creating a management table for managing address information of the image signal. The recording process includes an image reading process of reading an image signal from an internal memory based on the management table, and an image recording process of recording the image signal read by the image reading process on a recording medium.

That is, the address information of the image signal written to the internal memory by the writing process is managed by the management table. In the recording process, an image signal is read from the internal memory based on such a management table. Therefore, the image signal is appropriately recorded even though the writing processing and the recording processing are independent of each other.

In one embodiment of the present invention, the writing process includes a signal amount discriminating process for discriminating a signal amount of an image signal which has been written to an internal memory and has not yet been subjected to a recording process based on a management table, and a signal amount determining process. It further includes an interruption process for interrupting the writing process according to the processing result of the determination process. Further, the signal amount determination process includes a first determination process of determining whether the signal amount has exceeded a first predetermined value and a second determination process of determining whether the signal amount has exceeded a second predetermined value. The process includes a first interruption process for interrupting the writing process until a predetermined timing signal is generated when the signal amount exceeds a first predetermined value, and a signal amount exceeding a second predetermined value larger than the first predetermined value. At this time, a second interruption process for interrupting the writing process until the recording process is completed is included.

That is, image signals that have not been subjected to recording processing are accumulated in the internal memory, and when the remaining capacity of the internal memory is exhausted, the writing processing is interrupted and the recording processing is performed intensively. When the unprocessed signal amount exceeds the first predetermined value, the writing process is suspended until a predetermined timing signal is generated, and the second signal amount is larger than the first predetermined value.
If the value exceeds the predetermined value, the writing process is interrupted until the recording process ends.

In another embodiment of the present invention, a compression circuit compresses the output of the photographing circuit. At this time, the image writing process includes a compression activation process for activating the compression circuit and a compressed image writing process for writing the compressed image signal output from the compression circuit to the internal memory. As described above, the compression circuit compresses the output of the photographing circuit, so that a compressed image signal having a reduced size is generated in a short time. That is, the compression process is performed at a high speed, and the signal amount is reduced.

The writing process includes a prediction process for predicting a remaining capacity of the recording medium after the image writing process. In this prediction process, the remaining capacity is calculated based on the size of the compressed image signal. The time required for such a prediction process is shorter than detecting the remaining capacity by actually accessing the recording medium. The writing process further includes a number calculation process for calculating the number of images that can be recorded based on the remaining capacity, and a display process for displaying the number of images on a monitor. The operator grasps the number of images that can be taken after that based on the number of images displayed on the monitor.

In another embodiment of the present invention, there is further provided a second input key for inputting a photographing condition adjustment instruction. In addition, the writing process is performed in accordance with a processing result of an adjustment instruction determination process of determining an input of an adjustment instruction at a predetermined timing, an adjustment process of adjusting a shooting condition according to a processing result of the adjustment instruction determination process, and a shooting instruction determination process. A first disabling process for disabling the adjustment instruction determination process is further included.

Each of the input of the photographing instruction and the input of the adjustment instruction is determined at a predetermined timing. When the operator inputs an adjustment instruction instead of an imaging instruction, the imaging condition is adjusted based on the adjustment instruction. However, when the operator inputs a photographing instruction at a rapid timing following the previous photographing instruction, the adjustment processing of the photographing conditions is disabled. That is, in response to the current photographing instruction, the image writing process and the management table creation processing is performed.

The writing processing further includes a first detection processing for detecting a first timing at which a predetermined processing result is obtained by the photographing instruction determination processing, and a second timing at which a predetermined processing result is obtained by the adjustment instruction determination processing. A second detection process for detecting after one timing and a second disabling process for disabling the adjustment process according to a difference between the first timing and the second timing are included. Each of the predetermined processing results is a determination result indicating that there is an input.

That is, if the input timing of the previous shooting instruction and the input timing of the current adjustment instruction are short, the adjustment process is disabled. Then, in response to the current shooting instruction, an image writing process and a management table creation process are performed.

[0017]

According to the present invention, the writing process for writing the image signal to the internal memory and the recording process for recording the image signal from the internal memory on the recording medium are performed in parallel, so that the photographing interval can be shortened. it can. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0018]

Referring to FIG. 1, a digital camera 10 of this embodiment includes a focus lens 12 and an aperture unit 14. The light image of the subject is applied to the CCD imager 12 via such a member. When the mode setting switch 60 is switched to the “camera” side, the system controller 52 notifies the CPU 42 of the setting of the camera mode. At this time, the CPU 42 operates the signal generator (S
G) Signal processing block including 16, signal processing circuit 22, bank switching circuit 36 and the like, and video encoder 4
4. Start an encoding block including the monitor 46 and the like.

The bank switching circuit 36 outputs 1 /
A bank switching signal is generated in response to a vertical synchronizing signal output every 15 seconds, and supplied to the memory control circuit 26. Since the vertical synchronization signal is output every 1/15 second, the level of the bank switching signal is also switched every 1/15 second. The memory control circuit 26 specifies an image bank to be accessed by such a bank switching signal. In other words, SDRA
M28 has a display image area as shown in FIG. 2, and this display image area includes image bank 0 and image bank 1
Are formed. If the bank switching signal is low, the memory control circuit 26 sets the write destination to image bank 0
Is determined, and the reading destination is determined to be the image bank 1. Conversely, if the bank switching signal is at a high level, the memory control circuit 26 determines the write destination to be the image bank 1 and the read destination to be the image bank 0.

On the other hand, the TG 32 generates a timing signal based on the vertical synchronizing signal and the horizontal synchronizing signal output from the SG 34, and drives the CCD imager 12 in a progressive scan system. As a result, the camera signal of the subject is output from the CCD imager 12 every 1/15 second. The output camera signal is sent to the CDS / AGC circuit 1
At 8, well-known noise elimination and level adjustment are performed, and then the digital signal is converted by the A / D converter 16 into camera data which is a digital signal. The signal processing circuit 22 has an A / D
The YUV conversion is performed on the camera data output from the converter 16 to generate YUV data. As a result of the camera signal of each frame being generated every 1/15 second, the corresponding YUV data is also generated every 1/15 second. Signal processing circuit 2
2 gives the generated YUV data to the memory control circuit 26 together with the write request.

The memory control circuit 26 fetches the YUV data in response to the write request, and writes the YUV data to the specified image bank based on the bank switching signal. The YUV data of each frame is generated every 1/15 second, and the level of the bank switching signal is switched every 1/15 second. As a result, the YUV data of each frame is stored in the image bank 0.
And alternately written to image bank 1. In addition, YU
The V data is supplied to the memory control circuit 26 via the bus 24a, and then written to the SDRAM 28 via the bus 24b.

The YUV data written in the desired image bank in this manner is then transmitted to the video encoder 44.
Are read by the same memory control circuit 26 on the basis of the read request output from. The video encoder 44 issues a read request every 1/30 second, and the memory control circuit 26 repeatedly reads YUV data twice from the specified image bank based on the bank switching signal. YUV data is read out from an unwritten image bank by an interlaced scan method,
It is provided to the video encoder 44 via the bus 24a. The video encoder 44 converts the input YUV data into a composite image signal in the NTSC format, and supplies the converted composite image signal to the monitor 46. As a result, a moving image (through image) of the subject is displayed on the monitor screen in real time.

When the operator half-presses the shutter button 54, the system controller 52 provides the corresponding key state data to the CPU 42. Then, CP
U42 is active the AF control circuit 38 and an AE control circuit 40 to adjust the focus and exposure. As a result, the focus lens 12 moves to the optimum position,
4 is set to the optimal value. The shutter button 58
When but a half-pressed state, CPU42 is described later BG (Ba
ck Ground) Mode start-up processing and processing for determining the maximum number N _MAX of images that can be continuously shot are also performed.

When the shutter button 54 is fully pressed, the system controller 52 provides the corresponding key state data to the CPU 42. Then, the CPU 42 disables the bank switching circuit 36 in response to the vertical synchronization signal, and disables the signal processing circuit 22 after generating the YUV data of the subject image photographed at the time of full pressing. On the other hand, the video encoder 44 is not disabled, and the read request is sent to the memory control circuit 2 as before.
Continue giving to 6. When the bank switching is stopped, the memory control circuit 26 unifies the access destination to, for example, the image bank 0. Therefore, the YUV data output from the signal processing circuit 22 is written to the image bank 0, and the YUV data to be provided to the video encoder 44 is read from the image bank 0. As a result, the same YUV data is repeatedly provided to the video encoder 44, and the corresponding still image (freeze image) is displayed on the monitor 46. Note that Y of the subject image photographed at the time when the shutter button 58 is fully pressed is
UV data is defined as original image data for convenience of the following description.

After the original image data is secured in image bank 0, CPU 42 instructs JPEG codec 30 to perform a compression process. The JPEG codec 30 requests the memory control circuit 26 to read the original image data in response to such a compression processing command. The original image data is read from the image bank 0 by the memory control circuit 26 and supplied to the JPEG codec 30 via the bus 24a. JPEG codec 30
Generates thumbnail image data from the input original image data, and individually performs compression processing on the original image data and the thumbnail image data. This allows compressed data of the original image (original compressed data)
Then, compressed data of the thumbnail image (thumbnail compressed data) is generated.

The JPEG codec 30 writes the compressed data thus generated in the memory control circuit 2.
6 and the compressed data is written to the SDRAM 28 by the memory control circuit 26. SDRAM 28
In FIG. 2, an original image area and a thumbnail image area are formed as shown in FIG. 2, and the original compressed data and the thumbnail compressed data are written in the original image area and the thumbnail image area, respectively. Also, the corresponding header data is
42, the memory control circuit 26 is requested to write the created header data. As a result, the header data is written into the header area shown in FIG.

In this way, the original compressed data, thumbnail compressed data and header data for one sheet
When secured in the DRAM 28, the CPU 42 creates an instruction list 42a as shown in FIG. This instruction list 4
Address information and size information of the above-mentioned original compressed data, thumbnail compressed data and header data are written in 2a. The data written in the SDRAM 28 is managed by the instruction list 42a.
That is, the instruction list 42a is a management table for managing the original compressed data, the thumbnail compressed data, and the header data written in the SDRAM 28.

The CPU 42 operates as described above.
In parallel with the writing process to the SD card 28, the BG mode process is executed, and the original compressed data, the thumbnail compressed data and the header data stored in the SDRAM 28 are recorded on the memory card 48. At this time, the CPU 42 performs a read process from the SDRAM 28 with reference to the above-described instruction list 42a, and stores the read data in the memory card 4
Record in 8. On the memory card 48, an image file in which data is stored in the order of a header, a thumbnail image, and an original image is formed. Also at this time, the SDRAM 28
Is read by the memory control circuit 26.

The memory card 48 is detachable, and is connected to the bus 24a via the interface 47 when the memory card 48 is inserted. Therefore, the CPU 42 writes the data read by the memory control circuit 26 to the memory card 48 via the bus 24a and the interface 47. The original image area has a capacity for storing 20 pieces of original compressed data, and the thumbnail image area and the header area also have a capacity for storing 20 pieces of compressed thumbnail data and header data. Further, the process of writing these data to the SDRAM 28 and the process of recording from the SDRAM 28 to the memory card 48 are performed in parallel. For this reason, the shutter button 58
If the full press of is repeated, the original image data,
Thumbnail image data and header data are cyclically written to and read from the original image area, thumbnail image area, and header area.

Note that the CPU 42 executes the SDR operation as described above.
In addition to the writing process to the AM 28 and the recording process to the memory card 48, the remaining capacity of the memory card 48 is predicted, the remaining number is calculated based on the prediction result, and the display of the remaining number is updated. The memory control circuit 26 includes a signal processing circuit 22, a video encoder 44, a JPE
A request is input from each of the G codec 30 and the CPU 42. Therefore, the memory control circuit 26 accesses the SDRAM 28 while arbitrating each request.

The system controller 52 specifically processes the flowchart shown in FIG. On the other hand, the CPU 42
6 to 16 and FIGS. 17 and 18
Are processed in parallel. That is, the CPU 4
Reference numeral 2 denotes a multitask CPU on which a multitask OS (real-time OS) such as μiTRON is mounted, and a writing process shown in FIGS.
8 are executed in parallel with each other.

First, the processing of the system controller 52 will be described with reference to FIG. System controller 52
First, at step S1, the system flag f _SYS is set, and at step S3, all bits of the register 52a shown in FIG. 3 are reset. The 0th bit of the register 52a indicates whether or not the shutter button 58 is half-pressed.
Bit indicates whether the shutter button 58 indicates whether full-pressed state, and the second bit mode select switch 60 is on or reproducing side in the camera. The system controller 52 first sets such a register 52a to an initial state.

The system controller 52 then proceeds to step S4, where the shutter button 5
8 and the state of the mode changeover switch 60 are detected. Then, in a step S5, it is determined whether or not the state of the key has changed. If there is no change in the state, the CPU 42 proceeds to step S7, and determines the state of the system flag f _SYS . Returning to step S4 if the system flag f _SYS is in the set state, the system flag f _SYS is if the reset state, to determine whether there is any input from the at Step S9 CPU 42. If “NO” here, the process returns to the step S4 as described above, but if “YES”, the contents of the input signal are determined in the steps S11, S13 and S15.

If the input signal is a key state data transmission request, the system controller 52 determines YES in step S11, and determines in step S27 that the register 5
The key state data stored in 2a is transmitted to the CPU 42. Then, in step S29, the system flag f
After resetting _SYS , the process returns to step S4. If the input signal is a key state reset request, the system controller 52 determines YES in step S13, and returns to step S3. If the input signal is a processing end notification, the system controller 52 determines in step S15 that Y
Judge as ES, and return to step S1. Step S
If NO at 15, the system controller 52 returns to step S4.

If it is determined in step S5 that the state of the shutter button 58 or the mode setting switch 60 has changed, the system controller 52 proceeds to step S19 and sets the corresponding bit of the register 52a. For example, when the shutter button 58 is half-pressed, the system controller 52 sets the 0th bit of the register 52a to "1". Thereafter, in a step S21, it is determined whether or not the system flag f _SYS is set. If the determination is NO, the process returns to the step S4.
Proceed to 23.

In step S23, the remaining amount of the battery 54 is detected, and in step S25, the detected remaining amount data is stored in the register 56. Subsequently, the key state data stored in the register 52g in step S27 is
And resets the system flag f _SYS in step S29, and returns to step S4. System flag f _SYS
The set state indicates that the system controller 52 has the initiative, and the reset state indicates that the CPU 42 has the initiative. Since the system flag f _SYS is set in step S1, the system controller 52 takes the initiative immediately after the power is turned on, and transmits the current key state data to the CPU 42 in step S27. System flag f _SYS is reset after completion of transmission of the key state data, whereby initiative is transferred to the CPU 42.

While the initiative has been transferred to the CPU 42,
The system controller 52 performs a key scan at a predetermined timing, and updates the key state data of the register 52 if there is a change. If there is no change in the key state, the system controller 52 waits for an input from the CPU 42, and transmits the current key state data when a key state data transmission request is given. For this reason, a key operation while the CPU 42 is performing the predetermined process is valid every time a key state data transmission request is given. The transmitted key state data corresponds to the key state at the time of transmission request input.

When a processing end notification is output from the CPU 42, the system controller 52 sets the system flag f _SYS
And regain control. However, immediately after the system flag f _SYS is set, the register 52a is reset, and the shutter operation newly performed thereafter becomes effective. Next, the processing of the CPU 42 will be described with reference to FIG. The CPU 42 first processes a subroutine shown in FIG. 11 in a step S51. Specifically, it resets the BG flag f _BG in step S5101. Next, in step S5103, the write address V _WA and read address V _RA of the original compressed data are set to the start address V _SA of the original image area shown in FIG. 2, and the write address S _WA and read address S _RA of the thumbnail compressed data are set. set to start address S _SA thumbnail image area, and sets the write address H _WA and read address H _RA header data to the start address HSA in the header area. Further, in step S5105, the time data R _TIME indicating the time when the shutter button 58 is fully pressed is reset. Subsequently, in step S5107, the remaining capacity of the memory card 48 is detected, and in step S5109, the number of images that can be recorded on the memory card 58 is calculated according to equation 1.

[0039]

[Number 1] _{γ = REM SIZE / F MAXSIZE γ} : remaining number REM _SIZE: remaining capacity F _MAXSIZE: the maximum size of the image file CPU42 then the character of the calculated remaining number and OSD displayed on the monitor 46 at step S5111, FIG.
The process returns to step S51 shown in FIG. The remaining number of characters is displayed by controlling a character generator (not shown).

Subsequently, the CPU 42 determines whether or not key state data has been input from the system controller 52 in a step S53. If “YES” here, the process proceeds to a step S55 to determine from the key state data whether the mode desired by the operator is the camera mode or the reproduction mode. If the desired mode is the reproduction mode, NO is determined in step S55, and the reproduction process is executed in step S57. Upon completion of the process, the CPU outputs an end notification to the system controller in step S59, and returns to step S53.

On the other hand, if the desired mode is the camera mode, the CPU 42 activates the camera mode in step S61. That is, the signal processing block and the encoding block described above are activated. As a result, a through image of the subject is displayed on the monitor 46. Thereafter, the CPU 42 outputs an end notification to the system controller 52 in step S63, and waits for input of key state data in step S65.

When key state data is input from the system controller 52, the CPU 42 proceeds to step S6.
In each of steps 7 and S69, it is determined whether the key operation performed by the operator is a mode change and whether the shutter button 58 is half-pressed. If the key operation is a mode change, the CPU 42 proceeds to step S
From 67, the process proceeds to step S57. If the key operation is half-pressing of the shutter button 58, the process proceeds from step S69 to step S71.

Note that the digital camera 10 is also provided with a cursor key (not shown) not related to the camera mode, and the register 52a also holds bit data corresponding to the cursor key. When the input of the key state data is based on such an operation of the cursor key, the CPU 42 returns from the step S69 to the step S63. Step S71
Then, it is determined whether or not the BG flag f _BG is set. Since the BG flag f _BG is reset in the above-described step S5101, it is determined as NO in the first process in step S71. Then, the CPU 42 proceeds to step S7.
In step 3, the BG mode is started. In step S75, the BG flag _fBG is set, and the flow advances to step S77. If YES is determined in the process of step S71, the CPU 42
Directly proceeds to step S77.

[0044] At step S77, the subroutine shown in FIG. 12
The maximum number of images that can be shot continuously NMAX
Set. That is, steps S7701 to S7711
In each case, what percentage of battery 54 is full
Is determined. The judgment is held in the register 56.
Battery remaining data is used. When the remaining amount is 0% to 10%
If there is, in step S7713 the maximum number N_MAX= 0
And the process returns to step S63. When the remaining amount is 10% to 25%
If there is, in step S7715 the maximum number N_MAX= 1 is determined
If the remaining amount is 25% to 40%, step S7717
With the maximum number N_{MA X}= 6 and the remaining amount is 40% -60%
If so, in step S7719 the maximum number N_MAX= 12 and
decide. If the remaining amount is 60% to 75%, step S7
721 is the maximum number N_MAX= 18, 75% remaining
If it is up to 95%, the maximum number N at step S7723_MAX
= 36, and if the remaining amount is 95% to 100%,
The maximum number of sheets N in S7725_MAX= 48. S
Steps S7715 to S7725
In air, CPU 42 is returned to step S77 shown in FIG. 7
I do.

Subsequently, the CPU 42 proceeds to a step S79, in which the current time detected from the clock circuit 50 is stored in the time data C.
Set to _TIME . In step S81, the time data C
A time difference “R _TIME− C _TIME ” between the _TIME and the time data R _TIME is calculated, and it is determined whether or not the calculated time difference exceeds 1.2 seconds. If “NO” here, the process proceeds to the step S.
The process proceeds to step S85, but if YES, the focus and aperture are adjusted in step S83, and then the process proceeds to step S85. “R _TIME− C _TIME ” is the value of the last shutter button 58
Means the difference between the full-press time and the subsequent half-press time of the shutter button 58. If the time difference is short, the subject has not changed significantly, and there is little need to adjust the focus and the exposure amount again. Therefore, the process of step S83 is jumped according to the time difference.

In step S85, a request is made to the system controller 52 to transmit key state data. When the key state data is input in response thereto, the CPU 42 determines whether or not the shutter button 58 has been fully pressed based on this data. When the operator continues to half-press the shutter button 58 or releases the shutter button 58 after half-pressing, the CPU
42 determines NO in this step, and returns to step S63.

On the other hand, if the operator changes the shutter button 58 from the half-pressed state to the full-pressed state, the CPU 42 executes the processing from step S88 and records the subject image at the time of the full-pressing on the memory card 58. Specifically, first, it is determined in step S88 whether or not a vertical synchronization signal has been input, and if a determination result of YES is obtained, step S8 is performed.
At 9, the bank switching operation is stopped. By stopping the bank switching in response to the vertical synchronizing signal in this way, an image bank that is valid at the time of outputting a frozen image is specified at an optimum timing. The CPU 42 next proceeds to step S91.
The current time, that is, the time of the full press is detected from the clock circuit 50, and the detected time is set in the time data R _TIME .
Subsequently, in step S93, a request is made to the system controller 52 to reset the key state data.

In step S95, JPEG codec 3
In step S97, the signal processing circuit 22 is disabled when the original image data is stored in the image bank 0 of the SDRAM 28 in step S97. The processing in step S97 means that the signal processing circuit 22 is activated until the original image data is generated. When the shutter button 58 is fully pressed,
While it becomes necessary to perform processing such as compression on the corresponding YUV data, YUV data obtained thereafter is not necessary. For this reason, the signal processing circuit 22 is kept activated for a predetermined period after the determination result of full press is obtained, and the signal processing circuit 22 is disabled when the original image data is obtained.

The JPEG codec 30 requests the memory control circuit 26 to read the original image data in response to the image compression command. Therefore, the original image data is stored in the image bank 0 by the memory control circuit 26.
And supplied to the JPEG codec 30. The JPEG codec 30 compresses such original image data at an initial compression ratio. When the compression processing is completed, the JPEG codec 30 provides the CPU 42 with a data size of the generated original compressed data and a compression processing end signal.

When the end signal is input, CPU 42 determines YES in step S99. Then the CPU 42
Calculates an optimum compression ratio in step S101 based on the data size and the initial compression ratio. The optimal compression rate is a compression rate that allows the original compressed data to be suppressed to a predetermined data size (the maximum recordable size).

In step S103, the compression at the optimum compression ratio obtained as described above and the SDR of the compressed data are performed.
The writing to the AM 28 is instructed to the JPEG codec 30. At this time, the CPU 42 assigns the optimum compression ratio for compression and the above-mentioned write addresses V _WA and S _WA for writing to the SDRAM 28 by the JPEG codec 3.
Give to 0.

The JPEG codec 30 compresses the original image data at an optimum compression ratio to generate original compressed data. The JPEG codec 30 also creates thumbnail image data from the original image data and compresses the thumbnail image data at an optimal compression rate. Then, a request for writing these compressed data is given to the memory control circuit 26 together with the write addresses V _WA and S _WA . As a result, the original compressed data is written after the write address V _WA located in the original image area, and the thumbnail compressed data is written after the write address S _WA located in the thumbnail image area.

When the compression process is completed, the JPEG codec 30 gives the CPU 42 an end signal, the data size V _SIZE of the original compressed data and the data size S _SIZE of the thumbnail compressed data. CPU42
Is set to Y in step S105 when the end signal is given.
It is determined to be ES, and the data size V _SIZE and S _SIZE described above are acquired in the subsequent step S106. Step S107
Then, the write addresses V _WA and S _WA are updated according to Equation 2.

[0054]

V _WA = V _WA + V _SIZE S _WA = S _WA + S _SIZE Therefore, the original compressed data and thumbnail compressed data based on the next full press of the shutter button 58 are:
It is written following the current original compressed data and the current thumbnail compressed data.

Then, the CPU 42 proceeds to step S108, and creates header data corresponding to the current original compressed data and the current thumbnail compressed data. Step S1
In step 09, the request for writing the header data is _sent together with the write address _HWA to the memory control circuit 26.
Give to. Memory control circuit 26 writes the header data input to the write address after H _WA of SDRAM 28. After outputting the write request in step S109, the CPU 42 updates the write address _HWA according to equation 3 in step S110.

[0056]

H _WA = H _WA + H _SIZE As a result, the header data generated based on the next full-press operation is also stored following the current header data. Number 2
If there is no free area equal to or larger than the recordable maximum size after the write address updated by the above, the original compressed data obtained by the next full press operation cannot be continuously written in the original image area. Therefore, the CPU 42 determines whether or not the condition of Expression 4 is satisfied in step S111.

[0057]

V _WA + V _MAXSIZE > V _EA V _MAXSIZE : The maximum recordable size of the original compressed data V _EA : The end address of the original image area If this condition is satisfied, the next original compressed data will be written to the current write address V _WA or later. Can be written continuously. In this case, the CPU 42 proceeds to step S1
Proceed to 13. On the other hand, if the condition of Equation 3 is not satisfied, the write addresses V _WA , S _WA and H
_After setting _WA to the start addresses V _SA , S _SA and H _SA , the process proceeds to step S113. As a result, continuity is guaranteed for each of the original compressed data, the thumbnail compressed data, and the header data. Further, the writing positions of the original compressed data, thumbnail compressed data and header data related to each other are cyclically updated in the same manner.

In the step S113, as shown in FIGS.
The subroutine shown is processed, and the instruction list 42 shown in FIG.
Create a. The CPU first determines in step S1110
1 is the read address H of the header data_RAAnd header
Data size H of data_SIZEIs an instruction list 4 shown in FIG.
Write to 2a. Specifically, the mail writing number W _N
Email number with the same value as
Read address H at the corresponding position_RAAnd data size
Z H_SIZEWrite. Read address H_RAIs shown in FIG.
Initialized in the step S5103 shown in FIG.
Number W_NIs reset in step S201 shown in FIG.
And data size H_SIZEIs predetermined. This
Therefore, in the first process of step S11101, W
_NRead address H at the position corresponding to = 0_RA(=
H_SA) And a predetermined data size H_{SI ZE}Is written
You.

Thereafter, the CPU 42 proceeds to step S1110.
3 increments the mail write number W _N and count value m, to compare the current mail write number W _N maximum value of mail number and "L-1" in step S11105. "L-1" is, for example, "1999". Here, if W _N ≦ L−1, step S1110 is performed as it is.
9, the process proceeds to step S111 if W _N > L−1.
After the mail write number W _N is reset at 07, the process proceeds to step S11109.

In step S11109, the count value m
It is compared with the "L-1". Count value m represents the number of addresses of outstanding in the instruction list 42a, SDRA
It means the amount of data written to M28 and not read yet. Such a count value m is usually m ≦
Meet the L-1 of the conditions, in step S11109 YE
S is determined. At this time, the CPU 42 determines in step S1
Update the read address H _RA according to Equation 5 in 1113, then the process proceeds to step S11115.

[0061]

_HRA = _HRA + _HSIZE Since the BG mode processing is abnormally slow, the count value m
Is larger than the decrement speed, m> L−1, and YES is determined in the step S11109. At this time, the CPU 42 performs error processing in step S11111, and forcibly ends the writing processing.

[0062] In step S11115, the read address of the thumbnail compressed data S _RA and the data size of the thumbnail compressed data S _SIZE mail write number W _N
And writes it in the instruction list 42a. CPU42
Then, in steps S11117 to S11123, the same processing as in steps S11103 to S11109 described above is performed. Then, the process proceeds to step S11111 when YES in step S11123, updates the read address S _RA according to Equation 6 in step S11125 when the NO.

[0063]

[6] _{S RA = S RA + S SIZE} CPU42 then proceeds to step S11127, the instruction list 42 the data size V _SIZE read address V _RA and original compressed data of the original compressed data
Write to the position corresponding to the mail write number W _N of a. Then, in steps S11129 to S11135, the same processing as in steps S11103 to S11109 is performed. If NO is determined in the step S11135, the CP
U42 updates the read address V _RA according to Equation 7 in step S11137.

[0064]

V _RA = V _RA + V _{SIZE In} this way, the address information and the size information of the header data, the thumbnail compressed data and the original compressed data related to each other are stored in the instruction list 42 in this order.
is written to a. The CPU 42 then proceeds to step S1
Proceeding to 1139, it is determined whether the condition of Expression 8 is satisfied for the same reason as in step S112 described above.

[0065]

V _RA + V _MAXSIZE > V _EA If YES, step S shown in FIG.
The process returns to 113, but if NO, step S111
At 41, the read addresses V _RA , S _RA and H _RA are set to the start addresses V _SA , S _SA and H _SA , and the process returns to step S113.

In step S114, continuous shooting is possible.
Maximum number N_MAXIs decremented, and the following step S1
At 15, the signal processing circuit 22 is activated. As a result,
The through image is displayed on the monitor 46. However, out of bank
Exchange is still stopped and writing of YUV data
The reading and reading are performed on image bank 0. C
The PU 42 subsequently calculates Expression 9 in Step S117,
The remaining capacity of the memory card 48 is predicted. In other words,
Data size S obtained in step S106 _SIZEand
V_SIZE, A predetermined data size H_SIZEAnd
Raster size C_SIZEIs the remaining capacity REM_SIZESubtract from
Note that the image file is a FAT (File Allocation Table)
 ) Method to record one image file.
Cluster size C every time a file is recorded_SIZEEquivalent to
Capacity is consumed. For this reason, clustering is used in the calculation of Equation 9.
Is C_SIZEIs added.

[0067]

[Equation 9] REM _SIZE = REM _SIZE- (H _SIZE + S _SIZE +
V _SIZE + C _SIZE ) C _SIZE : cluster size In step S 119, the CPU 42 also calculates the above equation 1, and calculates the remaining number based on the estimated remaining capacity obtained by equation 8. When the remaining number of sheets is calculated, CPU 42 proceeds to step S121, and updates the remaining number is displayed on the monitor 46.

In a succeeding step S123, it is determined whether or not the calculated remaining number is larger than "1". Here, if the remaining number ≦ 1, CPU 42 determines NO, and resets the BG flag f _BG in step S135. further,
In step S137, it is determined whether the BG mode processing shown in FIGS. 17 and 18 has been completed, and if a determination result of YES is obtained, the process proceeds to step S141. In this step, a subroutine shown in FIG. 16 is processed. First, in step S14101, the write addresses V _WA , S _WA and H _WA are set to the start addresses V _SA , S _SA and H _SA , respectively. Next, in step S14103, the memory card 48 is actually accessed to detect the remaining capacity. . Further, in step S14105, the remaining number of sheets is calculated according to the above-described formula 1, and the remaining number is displayed on the monitor 46 in step S14107. Then, step S14 shown in FIG. 10
Return to 1. The CPU 42 then proceeds to step S143
To determine whether a vertical synchronizing signal has been input. And YE
When the determination result of S is obtained, the bank switching operation is restarted in step S143, and thereafter, the process returns to step S63.

As a result, if the remaining number ≦ 1, the process of step S137 is repeated, and substantially only the BG mode process is executed. As a result, when all data stored in the original image area, the thumbnail image area, and the header area are recorded on the memory card 48,
The bank switching operation is restarted, and the operation of the shutter button 58 becomes effective.

On the other hand, if it is determined in step S123 that the remaining number is greater than 1, the CPU 42 compares the count value m with a predetermined value m _A (= 50) in step S125, and proceeds to step S1.
At 27, the count value m is compared with a predetermined value m _B (= 55). As described above, the count value m indicates the number of unprocessed addresses in the instruction list 42a, and relates to the amount of data not read from the SDRAM 28. The original image area, the thumbnail image area, and the header area have only a capacity corresponding to data for 20 sheets, and the count value m = 60 means that these areas are full. Therefore, the count value m is changed to the predetermined values m _A and m _B
And the processing method is switched according to the comparison result.

Specifically, if m> 55,
The remaining capacity of the SDRAM 28 is small. At this time, C
The PU 42 determines YES in Step S127, and proceeds to Step S135. As a result, the writing process is suspended until the BG mode process is completed and the bank switching operation is restarted. If 50 <m ≦ 55, SDRAM2
Although the remaining capacity of 8 is not sufficient, the situation is not so urgent that data in the SDRAM 28 must be wiped out. At this time, the CPU 42 determines in step S143
To step S6 after restarting the bank switching operation.
Return to 3. Since the bank switching operation is restarted in response to the vertical synchronizing signal, the writing process is interrupted while waiting for the input of the vertical synchronizing signal, and the BG mode process is intensively executed. As a result, the remaining capacity of the SDRAM 28 is increased.

If m ≦ m _A , the CPU 42
It is determined that there is sufficient remaining capacity in M28, and step S
At 129, the maximum number _NMAX is compared with "0". Where N
_{If MAX} > 0, there is room for continuous shooting. At this time, the CPU requests the system controller 52 to transmit key state data in step S131, and determines in step S133 whether or not the shutter button 58 has been fully pressed based on the key state data. If “YES”, the process returns to the step S91. That is,
If the shutter button 58 is fully depressed at the time when the request is issued to the system controller 52 in step S131, the CPU 42 determines that the operator wants to shoot at a faster timing, and returns to step S91 instead of step S63. N _MAX ≦ 0 or N _MAX >
If the shutter button 58 is not fully pressed even if the value is 0, the CPU 42 proceeds to step S143. CPU
42 is a step S6 after the bank switching operation is restarted.
Return to 3.

Depending on the operation timing of the shutter button 58,
Therefore, the flow of processing changes as follows. In fact,
0.8 seconds from step S87 to step S133
The shutter button 58 is fully pressed at this time interval.
If pressed, the processes of steps S63 to S89 are skipped.
Will be On the other hand, as described above, the time difference “R_TIME-C
_TIMEIs less than 1.2 seconds, the process of step S83
Jumped. Therefore, the shutter is released every 0.8 seconds.
If the button 58 is fully pressed, step S91 and subsequent steps are performed.
Is repeated. On the other hand, after full press, 1.
Half-pressed within 2 seconds, and full-press after half-press last time
If 0.8 seconds or more have elapsed since the full press of
Only the process at 83 is jumped. Half a full press
If it takes more than 1.2 seconds to be pressed,
Step S83 is executed.

The BG mode processing will be described with reference to FIG. CPU42 is first reset mail write number W _N, the mail read number R _N and count value m in step S201. Next, in steps S203 and S205, it is determined whether the count value m is larger than “0” and whether the BG flag f _BG has been reset. If m> 0, the process proceeds from step S203 to step S207. If m ≦ 0 and the BG flag f _BG is set, the process proceeds to step S205, and m
If ≦ 0 and the BG flag f _BG is in the reset state, the process ends.

The count value m is reset in step S201, but is incremented by the instruction list creation processing in step S113. As a result, m> 0, and YES is determined in step S203. Then
The CPU 42 determines in step S207 that the file pointer FP
Is set to the reading start address corresponding to the mail reading number _RN , and the count value S is set to the mail reading number R
Set to the data size corresponding to _N. In the above-described step S113, an instruction list 32a as shown in FIG. 4 is created. According to FIG. 4, the read start address and the data size represented by the number of bytes are associated with each mail number. In step S207 and S209, it detects a mail numbers having the same value as the current mail read number R _N, reads the read start address and data size corresponding to the detected mail no. Then, the read address data and size data are set in the file pointer FP and the count value S, respectively.

Subsequently, CPU 42 determines whether or not access to SDRAM 28 is possible in step S211.
While the shutter button 58 is pressed, the memory control circuit 26 receives requests from a plurality of circuits and accesses the SDRAM 28 while arbitrating these requests. Therefore, in step S211, the read request is output to the memory control circuit 26 together with the address data held by the file pointer FP. Memory control circuit 2
6, when processing such a read request,
First, an enable signal is output to the CPU 42, and then one byte of data is read from the SDRAM 28 in accordance with the address data of the file pointer FP. The read 1-byte data is provided to the CPU 42 following the permission signal.

The CPU 42 determines YES in step S211 when the permission signal is returned from the memory control circuit 26, and records the subsequently input 1-byte data in the memory card 48 in step S213. Thereafter, the file pointer FP and the count value S are updated in steps S215 and S217. That is, the address data of the file pointer FP is incremented, and the count value S is decremented. In step S219, the count value S is compared with "0".
Return to 211. As a result, until the data corresponding to the current mail read number R _N is recorded all the memory card 48, the process of step S211~S219 are repeated.

When the count value S becomes "0", the CPU 4
2 determines that the read process of the data corresponding to the current mail read number R _N has been completed, decrements the count value m in step S221. The count value m is incremented by the instruction list creation process, and is decremented in this step. After that, the CPU 42
Increments the mail read number R _N in step S223, the current mail read number R _N in step S75
Is compared with "L-1". And while the process directly proceeds to step S225 if R _N ≦ L-1, if R _N> L-1, then, the process proceeds reset mail read number R _N in step S225 to step S229. As a result,
The mail read number _{RN is} also updated cyclically. In step S229, the count value m is compared with "L-1". Normally, the count value m does not exceed “L−1”, and the CPU 42 determines NO in this step and returns to step S203. As a result, the above-described step S203
To S229 are repeated, and the data stored in the header area, thumbnail image area and original image area of the SDRAM 28 are stored in the memory card 36.
Are sequentially recorded. On the other hand, when the count value m is "L-
If it exceeds 1 ", YE is determined in step S229.
S, and after error processing in step S231, BG
Terminates mode processing forcibly.

According to this embodiment, the multitask OS is mounted on the CPU, and the writing process to the SDRAM and the recording process to the memory card are performed simultaneously. For this reason,
The time from when the subject image is captured by operating the shutter button until the corresponding image data is recorded on the memory card can be reduced. In other words, the operation interval of the shutter button, that is, the shooting interval can be reduced.

The original compressed data, the thumbnail compressed data, and the header data are cyclically written to the original image area, the thumbnail image area, and the header area of the SDRAM, and the amount of data for which the recording process has not been completed exceeds a predetermined value. Then, the writing process is interrupted. The writing process is restarted when free space is secured by the recording process. Therefore, the access processing to the SDRAM does not fail.

Further, the remaining capacity of the memory card is obtained based on the data amount of data obtained by one photographing. That is, the remaining capacity is obtained without actually accessing the memory card. Therefore, the time required for detecting the remaining capacity can be reduced. Furthermore, the AF control processing and the AE control processing performed when the shutter button is half-pressed are jumped according to the full-press timing of the shutter button. For this reason, it is possible to reduce the time until the subject image captured by the full press this time is recorded on the memory card.

In this embodiment, as can be seen from FIG. 10, whether or not to interrupt the writing process is determined from the count value m. That is, the count value m
Exceeds the predetermined value, the writing process is suspended until the BG mode ends or a vertical synchronization signal is input. Such a determination method can be applied not only to the case of shooting a still image as in this embodiment, but also to the case of shooting a moving image including a plurality of still images.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing an SDRAM;

FIG. 3 is an illustrative view showing a register provided in the system controller;

FIG. 4 is an illustrative view showing an instruction list;

FIG. 5 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 6 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 7 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 8 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 9 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 10 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 11 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 12 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 13 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 14 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 15 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 16 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 17 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 18 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

[Explanation of symbols]

 10 ... digital camera 22 ... signal processing circuit 26 ... memory control circuit 28 ... SDRAM 30 ... JPEG CODEC 42 ... CPU 44 ... video encoder 48 ... memory card

Claims (12)

[Claims] A first input key for inputting a photographing instruction; a photographing circuit for photographing a subject image based on the photographing instruction; an internal memory; A digital camera including a multitask CPU that performs a recording process of recording an image signal of a memory on a recording medium in parallel. Wherein said write process, photographic imaging instruction determination process for determining at a predetermined timing an input of an instruction, the imaging instruction determination processing of the processing result the imaging circuit photographing activation process for activating the in accordance with the image An image writing process of writing a signal to the internal memory, and a creating process of creating a management table for managing address information of the image signal, wherein the recording process converts the image signal from the internal memory based on the management table. Image reading processing to read,
2. The digital camera according to claim 1, further comprising an image recording process of recording the image signal read by the image reading process on the recording medium. 3. A signal amount discriminating process for discriminating a signal amount of an image signal which has been written into the internal memory and has not yet been recorded based on the management table, and the signal amount discriminating process. processing results further comprising a suspend interrupt processing the write process according to claim 2 digital camera according. 4. The signal amount discriminating process includes the step of:
A first determination process for determining whether or not the signal amount has exceeded a second predetermined value; and a second determination process for determining whether or not the signal amount has exceeded a second predetermined value. A first interruption process for interrupting the writing process until a predetermined timing signal is generated when the signal amount exceeds a value, and the recording process ends when the signal amount exceeds a second predetermined value larger than the first predetermined value. The write process is interrupted until the second
4. The digital camera according to claim 3, including a suspension process. 5. The image writing process according to claim 1, further comprising a compression circuit for compressing an output of the photographing circuit, wherein the image writing process includes a compression activation process for activating the compression circuit, and a compression image signal output from the compression circuit. 5. The digital camera according to claim 2, further comprising a compressed image writing process for writing the compressed image into an internal memory. 6. The digital camera according to claim 5, wherein said writing process further includes a prediction process for predicting a remaining capacity of said recording medium after said image writing process. 7. The writing process further includes a detection process for detecting a size of the compressed image signal, and the prediction process includes a remaining capacity calculation process for calculating the remaining capacity based on the size of the compressed image signal. , Claim 6
Digital camera as described. 8. The writing process according to claim 6, further comprising a number calculation process for calculating the number of images that can be recorded based on the remaining capacity, and a display process for displaying the number of images on a monitor. Digital camera. 9. A processing method according to claim 9, further comprising a second input key for inputting an instruction for adjusting a photographing condition, wherein said writing processing includes an adjustment instruction determination processing for determining input of said adjustment instruction at a predetermined timing, and a processing result of said adjustment instruction determination processing. 9. The image processing apparatus according to claim 2, further comprising: an adjustment process for adjusting the photographing condition in accordance with the first instruction, and a first disabling process for disabling the adjustment instruction determination process in accordance with a processing result of the photographing instruction determination process. A digital camera according to claim 1. 10. The writing process includes a first detection process for detecting a first timing at which a predetermined processing result is obtained by the photographing instruction determination process, and a first detection process at which a predetermined processing result is obtained by the adjustment instruction determination process. 2 timings for the first
The digital camera according to claim 9, further comprising: a second detection process for detecting after the timing; and a second disabling process for disabling the adjustment process according to a difference between the first timing and the second timing. 11. The digital camera according to claim 10, wherein each of the predetermined processing results is a determination result indicating that there is an input. 12. The digital camera according to claim 1, wherein said recording medium is detachable.