JP2002231731A - Method for fabricating compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a compound semiconductor device having such a structure as elements fabricated on a GaAs substrate are isolated by making a trench and the state of a wafer is sustained by a metal layer of PHS structure in which the wafer is prevented from being warped. SOLUTION: A trench 15 is made along a dicing line on the surface of a substrate 1 on which elements are fabricated and the bottom of the trench 15 is exposed by back lapping thus isolating each chip. A PHS structure is formed and a metal layer 10 for interlinking the isolated chips is formed by copper plating. Finally, a flash plating 13 of gold is formed on the entire surface of copper plating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-power GaAsM.
The present invention relates to a method for manufacturing an ESFET, and particularly to a method for manufacturing a GaAs MESFET which is easy to handle in a wafer state.

[0002]

2. Description of the Related Art A GaAs power MESFET as an example of a semiconductor device has a structure shown in FIGS. 6A and 6B, for example.

In FIG. 1, reference numeral 1 denotes a semi-insulating substrate;
Reference numerals 3 and 4 denote source, gate, and drain electrodes formed on the substrate 1, respectively, 5, 6, and 7 denote bonding pads for the source, gate, and drain, 8 denotes an N-type active layer formed on the surface of the substrate 1, Reference numeral denotes a metal layer formed of gold plating or the like formed on the back surface of the substrate 1, which is a heat sink electrode and a plate heat sink (hereinafter, abbreviated as PHS) provided for improving the mechanical strength of the thinned substrate 1.

Usually, in the manufacture of a semiconductor device, a large number of elements are formed on a wafer, and then the wafer is diced into individual chips. However, GaAs wafers are brittle in material, and in particular, GaAs employing a PHS structure.
In the sMESFET, the thickness of the substrate 1 is formed as extremely thin as 10 to 30 μm in order to lower the thermal resistance, and thus there is a disadvantage that the wafer is frequently cracked or chipped during dicing.

Therefore, a manufacturing method as shown in FIG. 7 has been devised. That is, as shown in FIG.
After forming the element in the mold active layer 8, a groove 15 having a depth obtained by adding 5 to 10 μ to the final substrate thickness is formed on the dicing line. As shown in FIG. 7B, the back surface of the substrate 1 is polished until the groove 15 is exposed in a state where the support plate 11 is adhered to the surface of the substrate 1 with the wax 12, and then the plating electrode 18 is formed on the entire back surface. Then, a metal layer 9 having a PHS structure is formed by performing gold plating. As shown in FIG. 7C, the substrate 1 is peeled from the support plate 11, and the wax 12 is removed. Each board 1
Are already separated, but since the wafer state is maintained by the metal layer 9, the quality of the device as a wafer is determined (wafer check), and then the groove 1 is formed by a dicing blade.
The chips are separated for each substrate 1 by cutting the metal layer 9 through 5.

[0006]

However, in the above manufacturing method, the metal layer 9 having the PHS structure is formed by gold plating, and the gold plating generation process is at a high temperature (around 70 ° C.). (About 25 ° C.), the contraction rate of gold is large due to the difference in the coefficient of thermal expansion between the substrate 1 and gold.
The warpage of the wafer occurs as shown in FIG. For this reason, in the wafer checking step in which the probe is brought into contact with each of the bonding pads 5, 6, and 7 to measure the electrical characteristics of the device, the contact positions of the probe are shifted between the central portion and the peripheral portion of the wafer.
Also, when cutting into individual chips with a dicing blade, the cutting position is shifted between the central part and the peripheral part of the wafer.

Although the metal layer 9 having the PHS structure is formed by gold plating, gold is a noble metal and the production cost is high.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and comprises a step of forming a groove 15 on a dicing line after forming an element on the surface of a substrate 1; Polishing the back surface of the substrate 1 until the groove 15 is exposed, forming a metal layer 9 having a PHS structure on the entire surface of the substrate 1 by copper plating, and flash plating of thin gold on the surface of the copper plating 13 and a step of peeling the substrate 1 from the support plate 11 and dicing the copper-plated metal layer 10 through the grooves 15 to separate the chips into individual chips. An object of the present invention is to provide a method of manufacturing a compound semiconductor device that can be handled as a wafer without warpage.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 4 show a GaAs MESFE of the present invention.
It is sectional drawing for demonstrating the manufacturing method of T step by step.

First, referring to FIG. 1A, a source, a gate and a drain are formed on the surface of a GaAs substrate 1 to form a MESF.
An ET element is formed. Reference numeral 8 denotes an N-type active layer formed by diffusion to be an active region of the MESFET. At this stage, the substrate 1 has a thickness of 400 to 500 μ, and if it has such a thickness, it can be handled as a wafer in a production line. The surface of the element is covered with a final passivation film, and the surface of each of the bonding pads 5, 6, 7 is provided with an opening for probe contact and wire connection.

Referring to FIG. 1B, a resist mask 14 is formed on the surface of the substrate 1 and wet etching is performed to add 5 to 10 μm to the final substrate thickness at a portion to be a dicing line on the surface of the substrate 1. A groove 15 having a depth is formed.

Referring to FIG. 1C, wax 12 is applied to the surface of substrate 1 and the surface of substrate 1 is adhered to support plate 11. The support plate 11 is a substrate 1 that has been thinned in the process.
And plays a role of facilitating processing such as handling while maintaining the mechanical strength.

Referring to FIG. 2A, the thickness of substrate 1 is 1
The back surface of the substrate 1 is polished so as to have a thickness of 0 to 30 μm. Groove 1
If the depth of 5 is larger than the thickness of substrate 1, the bottom of groove 15 is exposed by this processing, and substrate 1 is separated into chips for each element. Each chip is held by the support plate 11. Since the inside of the groove 15 is filled with the wax 12, the surface of the wax 12 is exposed by polishing.

Referring to FIG. 2B, a resist mask 16 is formed on the back side of the substrate 1, and the substrate 1 under the active layer 8 is etched by about 5 to 25 μ by wet etching to form a concave portion 17. . This processing is to further reduce the distance from the active layer to the PHS to improve the heat radiation efficiency. When a via hole for penetrating the substrate 1 to directly connect the PHS and the source electrode is formed, an etching process is performed before and after this step.

Referring to FIG. 2C, resist mask 1
After removing 6, a Ti / Au electrode 18 having a thickness of several hundreds to several thousand degrees is formed on the entire back surface of the substrate 1 by a sputtering method.

Referring to FIG. 3A, Ti / Au electrode 1
Then, a resist mask 19 is formed on the surface of the substrate 8 again, and copper 20 is selectively plated only on the concave portions 17 formed in the previous step. This plating is performed until the copper 20 in the concave portion 17 has a thickness enough to bury the concave portion 17.

Referring to FIG. 3B, resist mask 1
9 is removed and copper plating is performed again to form a copper plated metal layer 10 having a PHS structure on the entire back surface of the substrate 1. The copper plating metal layer 10 and the copper 20 inside the recess 17 are integrated. Since the chips are already separated individually,
The thickness of the copper-plated metal layer 10 is set to a thickness capable of connecting individual chips by itself and maintaining a wafer state.
If it has a film thickness of 10 to 30 μm, it can be handled as a wafer. However, one of the conditions is that the thickness is such that dicing is possible.

Further, since copper plating is performed at room temperature (about 25 ° C.), no temperature difference occurs during and after copper plating, so that warpage of the wafer due to a difference in thermal expansion coefficient does not occur.

Next, the copper forming the copper plated metal layer 10 is easily oxidized.
Is subjected to flash plating 13 of thin gold having a thickness of several hundreds to several thousand Å on the entire surface of the substrate. Since the gold flash plating 13 is extremely thin compared to the thickness of the substrate 1 and the copper plating metal layer 10, it does not cause warpage of the wafer which is a practical problem.

Referring to FIG. 3C, the substrate 1 divided into chips is peeled from the support plate 11, and the wax 12 is removed. Each substrate 1 is kept in a wafer state by a copper plating metal layer 10.

Referring to FIG. 4, after the quality of the device is determined (wafer check) using bonding pads 5, 6, 7 on the surface of substrate 1, gold flash plating on the surface of copper plating metal layer 10 is performed. A dicing sheet 21 is attached to the substrate 13, and the copper plating metal layer 10 and the gold flash plating 13 are cut through the grooves 15 by a dicing blade, so that chips are separated for each substrate 1.

According to the manufacturing method of the present invention, GaAs
In a structure in which the elements formed on the substrate 1 are separated by forming the grooves 15 and the state of the wafer is maintained by the copper plated metal layer 10 having the PHS structure, no warpage occurs in the wafer. Therefore, handling is facilitated in the wafer check process and the dicing process.

FIG. 5 is a sectional view of a wafer manufactured by the manufacturing method of the present invention.

Although this embodiment has been described by taking a GaAs MESFET as an example, a diode using a GaAs substrate
It is also applicable to C, MMIC, and the like.

[0026]

As described above, according to the present invention, the copper plating process for forming the copper plating metal layer having the PHS structure is performed at room temperature (around 25 ° C.), and the subsequent wafer check process and dicing process are performed. There is no temperature difference from the working environment of the above, and no warping of the wafer occurs. In order to prevent oxidation, which is the weak point of copper plating, flash plating of thin gold with a thickness of several hundred to several thousand square meters is performed on the surface of copper plating,
Due to its small thickness, no warping occurs.

As described above, since there is no warp in the wafer, in the wafer check step of measuring the electrical characteristics of the device by bringing the probe into contact with each bonding pad, the probe is located at the contact position of the probe at the central portion and the peripheral portion of the wafer. There is no deviation, and a non-defective product is not erroneously determined as a defective product. In addition, it is possible to prevent the occurrence of a scratch defect or the like due to a shift in the contact position of the probe.
Further, in the dicing step of cutting into individual chips by the dicing blade, the displacement of the cutting position between the central portion and the peripheral portion of the wafer is eliminated, and the occurrence of a new defect due to the displacement of the cutting position is eliminated.

Copper forming the PHS-structured copper plating metal layer has a higher thermal conductivity than gold and sufficiently satisfies the original function of heat dissipation, and is inexpensive and lower in manufacturing cost than gold.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 5 is a cross-sectional view of a wafer manufactured by the manufacturing method of the present invention.

6A is a plan view and FIG. 6B is a cross-sectional view showing a GaAs power MESFET.

FIG. 7 is a cross-sectional view for explaining a conventional manufacturing method.

FIG. 8 is a cross-sectional view of a wafer manufactured by a conventional manufacturing method.

Claims (4)

[Claims] A step of forming a plurality of circuit elements on a main surface of a semi-insulating substrate; a step of forming a groove by etching a substrate surface on a dicing line for dividing the plurality of circuit elements into individual chips; A step of bonding the main surface of the substrate to a holding plate, a step of shaving the back surface of the substrate until the groove is exposed, and a good thermal conductivity having a thickness sufficient to hold the plurality of chips on the entire back surface of the substrate. A step of attaching a metal material, a step of attaching a noble metal to the surface of the metal material, a step of separating the substrate from the support plate, and dicing the metal material located in the groove into individual chips. A method for manufacturing a compound semiconductor device, comprising: 2. The method for manufacturing a compound semiconductor device according to claim 1, wherein a metal material mainly composed of copper is used as said metal material. A step of forming a plurality of circuit elements on a main surface of the semi-insulating substrate; a step of forming a groove by etching a substrate surface on a dicing line for dividing the plurality of circuit elements into individual chips; Bonding the main surface of the substrate to a holding plate; shaving the back surface of the substrate until the groove is exposed; forming a concave portion by partially etching the back surface of the substrate corresponding to the active region of the circuit element Performing a step of selectively depositing a metal material having good thermal conductivity and burying the concave portion with the metal material; a thermal conductivity having a thickness sufficient to hold the plurality of chips on the entire back surface of the substrate. Attaching the same metal material and integrating the metal material with the metal material in the concave portion, attaching a noble metal to the surface of the metal material, separating the substrate from the support plate, and positioning the substrate in the groove. Method for producing a compound semiconductor device characterized by comprising a step of dividing into individual chips by dicing the metal material. 4. The method for manufacturing a compound semiconductor device according to claim 3, wherein a metal material mainly composed of copper is used as said metal material.