JP2002208610A - Bonding pad for integrated circuit, and its manufacturing method - Google Patents
Bonding pad for integrated circuit, and its manufacturing methodInfo
- Publication number
- JP2002208610A JP2002208610A JP2001339918A JP2001339918A JP2002208610A JP 2002208610 A JP2002208610 A JP 2002208610A JP 2001339918 A JP2001339918 A JP 2001339918A JP 2001339918 A JP2001339918 A JP 2001339918A JP 2002208610 A JP2002208610 A JP 2002208610A
- Authority
- JP
- Japan
- Prior art keywords
- conductive film
- island
- bonding pad
- continuous
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000012212 insulator Substances 0.000 claims description 169
- 239000010410 layer Substances 0.000 claims description 84
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 14
- 229910052721 tungsten Inorganic materials 0.000 claims description 14
- 239000010937 tungsten Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 239000007787 solid Substances 0.000 claims description 9
- 238000003491 array Methods 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000000523 sample Substances 0.000 abstract description 23
- 230000008569 process Effects 0.000 abstract description 12
- 238000007689 inspection Methods 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 3
- 230000003252 repetitive effect Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- 239000004020 conductor Substances 0.000 description 9
- 239000013068 control sample Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000000644 propagated effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/05089—Disposition of the additional element
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- H01L2224/05096—Uniform arrangement, i.e. array
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は集積回路及びその形
成方法に係り、特に、集積回路のためのボンディングパ
ッド及びその製造方法に関する。The present invention relates to an integrated circuit and a method of forming the same, and more particularly, to a bonding pad for an integrated circuit and a method of manufacturing the same.
【0002】[0002]
【従来の技術】“チップ”と呼ばれる集積回路は、民生
用及び業務用電子製品に広く使用されている。当業者に
よく知られたように、集積回路は、一般に、半導体基板
などの基板及びその基板上のボンディングパッド配列を
含む。前記ボンディングパッドは、集積回路の外部を集
積回路の内部のマイクロ電子回路と電気的に接続させ
る。2. Description of the Related Art Integrated circuits called "chips" are widely used in consumer and commercial electronic products. As is well known to those skilled in the art, an integrated circuit generally includes a substrate, such as a semiconductor substrate, and an array of bonding pads on the substrate. The bonding pads electrically connect the outside of the integrated circuit to the microelectronic circuit inside the integrated circuit.
【0003】図1は、複数のボンディングパッドを含む
集積回路パッケージの概略図である。図1に示されたよ
うに、集積回路100、例えば、メモリセルアレイ部1
10及び周辺回路部115を含むメモリ集積回路は、複
数のボンディングパッド200を含む。ボンディングパ
ッド200は、集積回路100の回路端子に対するゲー
トの役目をし、周辺回路部115内の入出力I/Oバッ
ファ回路に内部的に接続される。図1に示されたよう
に、集積回路100は、リードフレーム300に接合さ
れる。ワイヤボンディングまたは他の従来の技術が各々
のワイヤ320をボンディングパッド200及びリード
フレーム300の内部リードチップ310に接続するの
に用いられる。FIG. 1 is a schematic diagram of an integrated circuit package including a plurality of bonding pads. As shown in FIG. 1, an integrated circuit 100, for example, a memory cell array unit 1
The memory integrated circuit including the peripheral circuit unit 115 and the peripheral circuit unit 115 includes a plurality of bonding pads 200. The bonding pad 200 serves as a gate for a circuit terminal of the integrated circuit 100, and is internally connected to an input / output I / O buffer circuit in the peripheral circuit unit 115. As shown in FIG. 1, the integrated circuit 100 is joined to a lead frame 300. Wire bonding or other conventional techniques are used to connect each wire 320 to the bonding pad 200 and the internal lead chip 310 of the lead frame 300.
【0004】図2は、図1のボンディングパッド200
の拡大平面図である。図3は、図2に示されたボンディ
ングパッドの斜視図である。図4は、図2のIV-IV'線に
沿って切り取ったボンディングパッドの断面図である。
図5は、図2のV-V'線に沿って切り取ったボンディング
パッドの断面図である。FIG. 2 shows the bonding pad 200 of FIG.
FIG. FIG. 3 is a perspective view of the bonding pad shown in FIG. FIG. 4 is a cross-sectional view of the bonding pad taken along line IV-IV ′ of FIG.
FIG. 5 is a cross-sectional view of the bonding pad taken along line VV 'of FIG.
【0005】図2ないし図5に示されたように、従来の
ボンディングパッドの構造において、独立的な導電性プ
ラグ245、例えば、タングステンプラグが配線間の絶
縁膜250内の複数個のビアホール240を充填してい
る。導電性プラグ245は、下部アルミニウム配線23
0及び上部アルミニウム配線260を電気的に接続す
る。参照符号210は集積回路基板を、220は層間絶
縁膜を、270はワイヤボンディング領域を各々示す。As shown in FIGS. 2 to 5, in a conventional bonding pad structure, an independent conductive plug 245, for example, a tungsten plug is used to form a plurality of via holes 240 in an insulating film 250 between wirings. Is filling. The conductive plug 245 is connected to the lower aluminum wiring 23.
0 and the upper aluminum wiring 260 are electrically connected. Reference numeral 210 indicates an integrated circuit substrate, 220 indicates an interlayer insulating film, and 270 indicates a wire bonding region.
【0006】[0006]
【発明が解決しようとする課題】図2ないし図5に示さ
れているパッドの構造は、下記のような問題点を有して
いる。例えば、ウェハから良好な集積回路100を分離
するソーティング(sorting)時に、ワイヤボン
ディング領域270上に置かれる検査器のプローブピン
(図示せず)により加わる力により配線間絶縁膜250
に亀裂が生じる。亀裂330はまた、ワイヤボンディン
グ領域270にワイヤ320をボンディングする間に加
わる機械的な衝撃及び圧力により生じるストレスによっ
ても配線間絶縁膜250内に生じる。The structure of the pad shown in FIGS. 2 to 5 has the following problems. For example, at the time of sorting for separating the good integrated circuit 100 from the wafer, the inter-wiring insulating film 250 is formed by a force applied by a probe pin (not shown) of an inspection device placed on the wire bonding region 270.
Cracks in the The crack 330 is also generated in the inter-wiring insulating film 250 due to stress generated by mechanical shock and pressure applied during bonding the wire 320 to the wire bonding region 270.
【0007】亀裂は、相対的に軟性である上部アルミニ
ウム配線260及び下部アルミニウム配線230がソー
ティングまたはワイヤボンディング時に加わるストレス
により変形されて生じる。しかし、相対的に硬い配線間
絶縁膜250は容易に変形されない。このため、一定値
以上のストレスが加わると、不安定なタングステンプラ
グ245が抜けてしまうか、或いは配線間絶縁膜250
に亀裂が生じる。このような亀裂は、図5に示されたよ
うに、タングステンプラグ245を覆っている絶縁膜2
50の内部に伝播される。[0007] The cracks are generated when the relatively soft upper aluminum wiring 260 and lower aluminum wiring 230 are deformed by stress applied during sorting or wire bonding. However, the relatively hard inter-wiring insulating film 250 is not easily deformed. For this reason, when a stress equal to or more than a certain value is applied, the unstable tungsten plug 245 may come off, or the inter-wiring insulating film 250
Cracks in the As shown in FIG. 5, such a crack is caused by the insulating film 2 covering the tungsten plug 245.
Propagated inside 50.
【0008】配線間絶縁膜250に生じた亀裂は、上部
及び下部アルミニウム配線260,230が剥がれてし
まう配線オープンの問題を引き起こす。あるいは、ワイ
ヤ320と上部アルミニウム配線260との間の接触が
不良となって、ワイヤ320が上部アルミニウム配線2
60から剥がれるパッドオープンの問題が生じる。[0008] The cracks generated in the inter-wiring insulating film 250 cause a wiring open problem in which the upper and lower aluminum wirings 260 and 230 are peeled off. Alternatively, the contact between the wire 320 and the upper aluminum wiring 260 becomes poor, and the wire 320 is
The problem of the pad opening peeling off from 60 occurs.
【0009】図6は、配線間絶縁膜の亀裂を低減させ、
しかも、配線膜またはワイヤが剥がれることを低減させ
るためにタングステンプラグ245を中央のワイヤボン
ディング領域の外部の周辺領域に限って形成した従来の
他のボンディングパッド構造の平面図である。図7は、
図6のVII-VII'線に沿って切り取ったボンディングパッ
ド構造の断面図である。このようなボンディングパッド
の構造は、米国特許第5,248,903及び第5,5
02,337号に開示されている。FIG. 6 shows that the cracks in the inter-wiring insulating film are reduced.
In addition, it is a plan view of another conventional bonding pad structure in which a tungsten plug 245 is formed only in a peripheral region outside a central wire bonding region in order to reduce peeling of a wiring film or a wire. FIG.
FIG. 7 is a sectional view of the bonding pad structure taken along the line VII-VII ′ of FIG. 6. The structure of such a bonding pad is disclosed in U.S. Patent Nos. 5,248,903 and 5,5.
02,337.
【0010】図6及び図7と前記二つの特許によるボン
ディングパッドの構造は、配線間絶縁膜250の亀裂を
ある程度低減できる。しかし、タングステンプラグ24
5の数が減少するため、タングステンプラグ245と上
部アルミニウム配線膜260との間の付着力が弱い。そ
の結果、ワイヤボンディング時に上部アルミニウム配線
膜260が割れる配線オープン現象が頻繁に生じる。ま
た、プラグの数が減少するため、上部アルミニウム配線
膜260との接触面積が縮まり、その結果、抵抗Rsが
増え、電流が減少する。このため、十分な量の電流を集
積回路内のスイッチング素子に供給できず、これは、素
子の動作を劣化させる原因となる。The bonding pad structure according to FIGS. 6 and 7 and the two patents can reduce cracks in the inter-wiring insulating film 250 to some extent. However, tungsten plug 24
5, the adhesive force between the tungsten plug 245 and the upper aluminum wiring film 260 is weak. As a result, a wiring open phenomenon in which the upper aluminum wiring film 260 is broken at the time of wire bonding frequently occurs. Also, since the number of plugs is reduced, the contact area with the upper aluminum wiring film 260 is reduced, and as a result, the resistance Rs increases and the current decreases. As a result, a sufficient amount of current cannot be supplied to the switching element in the integrated circuit, which causes the operation of the element to deteriorate.
【0011】本発明は上記事情に鑑みてなされたもので
あり、その目的は、チップ分類及びワイヤボンディング
時に配線間絶縁膜内の亀裂を最小化しつつ十分な量の電
流をチップ内に供給でき、しかも写真食刻工程時に回折
される光の量を低減できるほか、検査プローブによる反
復的な接触により上部配線が上部導電性プラグから剥が
れる現象を低減できることから、集積回路の信頼性を向
上させることができる集積回路のためのボンディングパ
ッド構造を提供することにある。The present invention has been made in view of the above circumstances, and has as its object to supply a sufficient amount of current to a chip while minimizing cracks in an insulating film between wires during chip classification and wire bonding. In addition, the amount of light diffracted during the photolithography process can be reduced, and the phenomenon that the upper wiring separates from the upper conductive plug due to repeated contact with the inspection probe can be reduced, thereby improving the reliability of the integrated circuit. It is to provide a bonding pad structure for a possible integrated circuit.
【0012】本発明の他の目的は、配線間絶縁膜内の亀
裂を最小化しつつ十分な量の電流をチップ内に供給で
き、しかも写真食刻工程時に回折される光の量を低減で
きるほか、検査プローブによる反復的な接触により上部
配線が上部導電性プラグから剥がれる現象を低減できる
ことから、集積回路の信頼性を向上させることができる
ボンディングパッド構造を製造するのに好適な方法を提
供することにある。It is another object of the present invention to supply a sufficient amount of current to a chip while minimizing cracks in an inter-wiring insulating film, and to reduce the amount of light diffracted during a photolithography process. To provide a method suitable for manufacturing a bonding pad structure capable of improving the reliability of an integrated circuit because a phenomenon that an upper wiring is separated from an upper conductive plug due to repeated contact by a test probe can be reduced. It is in.
【0013】[0013]
【課題を解決するための手段】本発明による集積回路の
ためのボンディングパッドは、所定距離離隔された第1
導電膜及び第2導電膜と、前記所定距離離隔された第1
導電膜及び第2導電膜間に存在し、前記所定距離離隔さ
れた第1導電膜及び第2導電膜に電気的に接続された連
続的な第3導電膜と、前記連続的な第3導電膜内に存在
し、前記連続的な第3導電膜を貫通するように延びてそ
の側壁が前記連続的な第3導電膜により覆われた非整列
で、かつ所定距離離隔された島状絶縁体の配列とを含
む。SUMMARY OF THE INVENTION A bonding pad for an integrated circuit according to the present invention includes a first pad spaced a predetermined distance apart.
A conductive film and a second conductive film, the first conductive film being separated from the first conductive film by the predetermined distance;
A continuous third conductive film existing between the conductive film and the second conductive film and electrically connected to the first conductive film and the second conductive film separated by the predetermined distance; A non-aligned, spaced-apart island-shaped insulator that extends within the film and extends through the continuous third conductive film and has sidewalls covered by the continuous third conductive film; And an array of
【0014】前記配列は非整列で、かつ所定距離離隔さ
れた島状絶縁体の横配列及び非整列で、かつ所定距離離
隔された縦配列を含みうる。前記非整列で、かつ所定距
離離隔された島状絶縁体の配列は、第1方向の第1エッ
ジを有する第1島状絶縁体と、前記第1方向の第1島状
絶縁体に隣接し、第1エッジと非整列とされた第1方向
の第2エッジを有する第2島状絶縁体とを含みうる。The array may include a horizontal array of island-shaped insulators that are non-aligned and spaced a predetermined distance and a vertical array that is non-aligned and spaced a predetermined distance. The array of non-aligned and spaced apart island-shaped insulators includes a first island-shaped insulator having a first edge in a first direction and a first island-shaped insulator adjacent to the first direction in the first direction. , A second island-shaped insulator having a second edge in a first direction misaligned with the first edge.
【0015】前記ボンディングパッドは、前記連続的な
第3導電膜及び前記第2導電膜間に存在し、前記連続的
な第3導電膜及び前記第2導電膜に電気的に接続された
連続的な第4導電膜をさらに含みうる。所定距離離隔さ
れた島状絶縁体の第2配列は前記連続的な第4導電膜内
に存在し、前記連続的な第4導電膜を貫通するように延
びて前記島状絶縁体の側壁が前記第4導電膜により覆わ
れており、前記所定距離離隔された島状絶縁体の第2配
列は前記非整列で、かつ所定距離離隔された島状絶縁体
の第1配列と非整列とされている。[0015] The bonding pad is present between the continuous third conductive film and the second conductive film, and is electrically connected to the continuous third conductive film and the second conductive film. And a fourth conductive film. A second array of island-shaped insulators separated by a predetermined distance is present in the continuous fourth conductive film, and extends so as to penetrate the continuous fourth conductive film so that sidewalls of the island-shaped insulator are formed. A second array of island-shaped insulators covered by the fourth conductive film and separated by a predetermined distance is non-aligned with the first array of island-shaped insulators separated by a predetermined distance. ing.
【0016】前記ボンディングパッドは、前記第1導電
膜上の金属バンパ層及びワイヤとボンディングするため
に形成された前記金属バンパ層上の上部ボンディングパ
ッド層をさらに含みうる。前記金属バンパ層は、タング
ステンでありうる。前記金属バンパ層は、約4,000
Åの厚さを有しうる。前記金属バンパ層及び前記上部ボ
ンディングパッド層は、約12,000Åないし14,
000Åの範囲の厚さを有する単一層よりなりうる。前
記上部ボンディングパッド層は、前記金属バンパ層の真
上にありうる。[0016] The bonding pad may further include a metal bumper layer on the first conductive film and an upper bonding pad layer on the metal bumper layer formed for bonding to a wire. The metal bumper layer may be tungsten. The metal bumper layer has a thickness of about 4,000.
Å thickness. The metal bumper layer and the upper bonding pad layer may have a thickness of about 12,000 to 14,
It may consist of a single layer having a thickness in the range of 000 °. The upper bonding pad layer may be directly above the metal bumper layer.
【0017】前記金属バンパ層は、該金属バンパ層の外
部エッジ側に位置した島状絶縁体を含みうる。前記金属
バンパ層の内部領域には、島状絶縁体がない。The metal bumper layer may include an island-shaped insulator located on an outer edge side of the metal bumper layer. There is no island insulator in the inner region of the metal bumper layer.
【0018】本発明によるボンディングパッドの構造
は、所定距離離隔された第1導電膜及び第2導電膜と、
前記所定距離離隔された第1導電膜及び第2導電膜間に
存在し、前記所定距離離隔された第1導電膜及び第2導
電膜に電気的に接続された連続的な第3導電膜とを含み
うる。前記ボンディングパッドの構造は、前記連続的な
第3導電膜内にジグザグ状に配列され、前記連続的な第
3導電膜を貫通するように延びてその側壁が前記連続的
な第3導電膜により覆われた所定距離離隔された島状絶
縁体の配列をさらに含みうる。The structure of the bonding pad according to the present invention includes a first conductive film and a second conductive film separated by a predetermined distance,
A continuous third conductive film existing between the first conductive film and the second conductive film separated by the predetermined distance and electrically connected to the first conductive film and the second conductive film separated by the predetermined distance; May be included. The structure of the bonding pad is arranged in a zigzag manner in the continuous third conductive film, extends so as to penetrate the continuous third conductive film, and has a side wall formed by the continuous third conductive film. It may further include an array of covered island-shaped insulators at a predetermined distance.
【0019】本発明による集積回路のためのボンディン
グパッドの製造方法は、先ず、集積回路基板上に下部導
電膜を形成する。次に、前記下部導電膜上に前記下部導
電膜に電気的に接続される連続的な導電膜を形成する。
前記連続的な導電膜は、その内部に前記連続的な導電膜
を貫通するように延びて島状絶縁体の側壁が前記連続的
な導電膜により覆われている非整列の所定距離離隔され
た島状絶縁体の配列を含む。次に、前記連続的な導電膜
上に前記連続的な導電膜に電気的に接続される上部導電
膜を形成する。In the method of manufacturing a bonding pad for an integrated circuit according to the present invention, first, a lower conductive film is formed on an integrated circuit substrate. Next, a continuous conductive film electrically connected to the lower conductive film is formed on the lower conductive film.
The continuous conductive film extends inside the continuous conductive film so as to extend through the continuous conductive film, and is separated by a predetermined non-aligned distance in which a sidewall of the island-shaped insulator is covered by the continuous conductive film. Includes array of island insulators. Next, an upper conductive film electrically connected to the continuous conductive film is formed on the continuous conductive film.
【0020】前記連続的な導電膜を形成する段階は、非
整列の所定距離離隔された島状絶縁体の横配列を含む連
続的な導電膜を形成する段階を含みうる。前記連続的な
導電膜を形成する段階は、非整列の所定距離離隔された
島状絶縁体の横配列及び非整列の所定距離離隔された島
状絶縁体の縦配列を含む連続的な導電膜を形成する段階
を含みうる。The step of forming the continuous conductive film may include the step of forming a continuous conductive film including a horizontal array of island-shaped insulators that are non-aligned and separated by a predetermined distance. The step of forming the continuous conductive layer includes a horizontal array of non-aligned island-shaped insulators spaced apart by a predetermined distance and a vertical array of non-aligned island-shaped insulators spaced by a predetermined distance. May be included.
【0021】前記連続的な導電膜を形成する段階は、前
記連続的な導電膜内に第1方向の第1エッジを有する第
1島状絶縁体を形成する段階と、前記第1方向の前記第
1島状絶縁体に隣接し、第1エッジと非整列とされた第
1方向の第2エッジを有する第2島状絶縁体を前記連続
的な導電膜内に形成する段階とを含みうる。The step of forming the continuous conductive film includes forming a first island-shaped insulator having a first edge in a first direction in the continuous conductive film. Forming a second island insulator in the continuous conductive film having a second edge in a first direction adjacent to the first island insulator and non-aligned with the first edge. .
【0022】[0022]
【発明の実施の形態】以下、添付した図面に基づき、本
発明の望ましい実施形態を説明することにより本発明を
詳細に説明する。しかし、本発明は以下に開示される実
施形態に限定されることなく、相異なる各種の形態に具
現できる。本実施形態は単に本発明の開示を完全たるも
のにし、かつ通常の知識を有した者に本発明の範ちゅう
を完全に知らせるために提供される。添付した図面にお
いて、各種の膜及び領域の厚さは明瞭性のために強調さ
れている。また、ある膜が他の膜または基板上に存在す
ると記載されるとき、ある膜が他の膜または基板の真上
にあることもあれば、それらの間に層間膜が存在するこ
ともある。図中、同一の参照符号は、同一の要素を表わ
す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. This embodiment is provided merely to complete the disclosure of the present invention and to make those skilled in the art completely aware of the scope of the present invention. In the accompanying drawings, the thickness of various films and regions are exaggerated for clarity. Also, when a film is described as being on another film or substrate, one film may be directly on the other film or substrate, or an interlayer film may be between them. In the drawings, the same reference numerals represent the same elements.
【0023】図8は、本発明の第1実施形態によるボン
ディングパッド構造の平面図であり、図9は、図8に示
されたボンディングパッド構造の斜視図であり、図10
は、図8のX-X'線に沿って切り取ったボンディングパッ
ド構造の断面図であり、図11は、図8のXI-XI'線に沿
って切り取ったボンディングパッド構造の断面図であ
る。FIG. 8 is a plan view of the bonding pad structure according to the first embodiment of the present invention. FIG. 9 is a perspective view of the bonding pad structure shown in FIG.
FIG. 11 is a cross-sectional view of the bonding pad structure taken along the line XX ′ of FIG. 8, and FIG. 11 is a cross-sectional view of the bonding pad structure taken along the line XI-XI ′ of FIG.
【0024】図8において、参照番号920は下部配線
を、925Iは下部島状絶縁体を、930は下部一体型
導電性プラグを、940は中間配線を各々表わす。参照
番号945Iは上部島状絶縁体を、950は上部一体型
導電性プラグを、960は最上部配線を、970はワイ
ヤボンディング領域を各々表わす。参照番号925及び
945は下部及び上部一体型導電性プラグパターンの外
壁を覆っている層間絶縁膜を各々表わす。一体型導電性
プラグはまた、連続的な導電膜と呼ばれうる。配線は導
電膜と呼ばれ、島状絶縁体は絶縁島と呼ばれる。“上
部”/“下部”及び“上”/“下”などの用語は絶対的
な方向を表わすのではなく、集積回路基板から隣接して
いるか、或いは離れているかの相対的な関係を表わすも
のである。In FIG. 8, reference numeral 920 indicates a lower wiring, 925I indicates a lower island-shaped insulator, 930 indicates a lower integrated conductive plug, and 940 indicates an intermediate wiring. Reference numeral 945I denotes an upper island insulator, 950 denotes an upper integrated conductive plug, 960 denotes an uppermost wiring, and 970 denotes a wire bonding region. Reference numerals 925 and 945 denote interlayer insulating films covering the outer walls of the lower and upper integrated conductive plug patterns, respectively. An integral conductive plug may also be referred to as a continuous conductive film. The wiring is called a conductive film, and the island-shaped insulator is called an insulating island. Terms such as "upper" / "lower" and "upper" / "lower" do not indicate an absolute direction but a relative relationship between being adjacent to or away from the integrated circuit substrate. It is.
【0025】図9、図10及び図11を参照すれば、集
積回路基板900上に層間絶縁膜910が形成されてお
り、層間絶縁膜910上に下部配線920、中間配線9
40及び最上部配線960を含む3層配線を有するボン
ディングパッド構造が形成されている。最上部配線96
0は、ワイヤ990がボンディングされるワイヤボンデ
ィング領域970を備える。ワイヤ990は、周辺回路
を構成する入出力バッファ回路(図1の115参考)な
どと接続された回路端子のゲートの役目を果たしうる。Referring to FIGS. 9, 10 and 11, an interlayer insulating film 910 is formed on an integrated circuit substrate 900, and a lower wiring 920 and an intermediate wiring 9 are formed on the interlayer insulating film 910.
A bonding pad structure having a three-layer wiring including the uppermost wiring 960 and the uppermost wiring 960 is formed. Top wiring 96
0 comprises a wire bonding area 970 to which the wire 990 is bonded. The wire 990 can serve as a gate of a circuit terminal connected to an input / output buffer circuit (refer to 115 in FIG. 1) which forms a peripheral circuit.
【0026】最上部配線960の下面と中間配線940
の上面との間に上部一体型導電性プラグ950が配され
て、最上部配線960と中間配線940とを電気的に接
続させている。上部一体型導電性プラグ950内には一
体型導電性プラグによりその側壁が完全に覆われ、最上
部配線960及び中間配線940により上面及び下面が
覆われている少なくとも一つ以上の上部島状絶縁体94
5Iが形成されている。図示されたような上部島状絶縁
体945Iのアレイが望ましい例として形成される。The lower surface of the uppermost wiring 960 and the intermediate wiring 940
An upper integrated conductive plug 950 is arranged between the upper wiring 960 and the upper wiring, and electrically connects the uppermost wiring 960 and the intermediate wiring 940. At least one or more upper island-shaped insulating plugs in which the side wall is completely covered by the integral conductive plug and the upper surface and the lower surface are covered by the uppermost wiring 960 and the intermediate wiring 940 in the upper integrated conductive plug 950. Body 94
5I are formed. An array of upper island insulators 945I as shown is formed as a preferred example.
【0027】上部島状絶縁体945Iの数及び/又は大
きさは上部一体型導電性プラグ950と最上部配線96
0とが接触する面積を最上部配線960の面積の10%
以上にできる範囲内で決定する。接触面積を10%以上
にすることにより、一定値以上の電流をボンディングパ
ッド部に流しうる。望ましくは、離隔された島状絶縁体
の配列とも呼ばれる複数個の島状絶縁体945Iは島状
絶縁体945Iの幅を縮める。すなわち、最上部配線9
60と中間配線940との間に挟まれる絶縁膜は、上部
一体型導電性プラグ950内に複数個の島状絶縁体94
5Iに区画される。このため、もし、一つの島状絶縁体
945Iに亀裂が生じたとしても、残りの島状絶縁体9
45Iは亀裂されない。一般に、ボンディングパッドと
して機能する最上部配線960は四角形であり、100
μm×100μmの大きさを有する。上部島状絶縁体9
45I間の間隔は、望ましくは、約0.3μmないし1
0μmにする。特に、複数個の島状絶縁体945Iは上
部一体型導電性プラグ950が篩状に形成され、このた
め、島状絶縁体945Iが所定値以上のストレス下でも
亀裂されないようにマトリックス状に配される。The number and / or size of the upper island-shaped insulator 945I depends on the upper integrated conductive plug 950 and the uppermost wiring 96.
The area where 0 contacts is 10% of the area of the uppermost wiring 960
The determination is made within the above range. By setting the contact area to 10% or more, a current equal to or more than a certain value can flow to the bonding pad portion. Preferably, the plurality of island-shaped insulators 945I, also referred to as an array of spaced-apart island-shaped insulators, reduces the width of the island-shaped insulators 945I. That is, the uppermost wiring 9
The insulating film sandwiched between the intermediate wiring 60 and the intermediate wiring 940 includes a plurality of island-shaped insulators 94 in the upper integrated conductive plug 950.
It is divided into 5I. Therefore, even if one island-shaped insulator 945I is cracked, the remaining island-shaped insulator
45I is not cracked. Generally, the uppermost wiring 960 functioning as a bonding pad is rectangular,
It has a size of μm × 100 μm. Upper island insulator 9
The spacing between 45I is preferably between about 0.3 μm and 1 μm.
0 μm. In particular, the plurality of island-shaped insulators 945I are formed such that the upper integrated conductive plug 950 is formed in a sieve shape. You.
【0028】中間配線940と下部配線920との間の
接続構造も、中間配線940と最上部配線960との間
の接続構造と同一に構成する。すなわち、少なくとも一
つ以上の下部島状絶縁体925Iを内在した下部一体型
導電性プラグ930により中間配線940及び下部配線
920を電気的に接続させる。The connection structure between the intermediate wiring 940 and the lower wiring 920 is configured the same as the connection structure between the intermediate wiring 940 and the uppermost wiring 960. That is, the intermediate wiring 940 and the lower wiring 920 are electrically connected by the lower integrated conductive plug 930 including at least one or more lower island-shaped insulators 925I.
【0029】前述したボンディングパッドの構造は、本
発明の第1実施形態による3層配線である。しかし、前
記ボンディングパッドの構造は最上部配線960及び中
間配線940を含む2層配線または多層配線でありう
る。The structure of the bonding pad described above is a three-layer wiring according to the first embodiment of the present invention. However, the structure of the bonding pad may be a two-layer wiring or a multi-layer wiring including the uppermost wiring 960 and the intermediate wiring 940.
【0030】本発明の第1実施形態によるボンディング
パッドの構造の効果を最上部配線960及び中間配線9
40を接続させる構造を参照して述べる。本発明による
ボンディングパッドの構造は、最上部配線(図3の26
0参照)及び最下部配線(図3の230参照)が一体型
絶縁膜(図3の250参照)により絶縁され、絶縁膜2
50内の独立的な複数個の導電性プラグ(図3の245
参照)が最上部配線260及び最下部配線230を接続
させる従来のボンディングパッド構造とは完全に逆の構
造を採用している。すなわち、本発明によれば、最上部
配線960及び中間配線940を接続させる導電性プラ
グ950は連続的な導電性プラグよりなっており、最上
部配線960と中間配線940との間に挟まれる絶縁膜
のほとんどが一体型導電性プラグ950内に少なくとも
一つ以上の島状絶縁体945Iに区画される。The effect of the structure of the bonding pad according to the first embodiment of the present invention will be described with reference to the uppermost wiring 960 and the intermediate wiring 9.
A description will be given with reference to the structure for connecting 40. The structure of the bonding pad according to the present invention corresponds to the uppermost wiring (26 in FIG.
0) and the lowermost wiring (see 230 in FIG. 3) are insulated by an integrated insulating film (see 250 in FIG. 3), and the insulating film 2
A plurality of independent conductive plugs (245 in FIG. 3)
) Employs a structure completely opposite to the conventional bonding pad structure for connecting the uppermost wiring 260 and the lowermost wiring 230. That is, according to the present invention, the conductive plug 950 connecting the uppermost wiring 960 and the intermediate wiring 940 is a continuous conductive plug, and the insulating plug sandwiched between the uppermost wiring 960 and the intermediate wiring 940. Most of the film is partitioned into at least one or more island-shaped insulators 945I in the integrated conductive plug 950.
【0031】島状絶縁体945Iは、一体型導電性プラ
グ950により側壁が完全に覆われており、配線96
0,940により上面及び下面が覆われているので、極
めて安定した構造を有している。このため、チップ分類
及び/又はワイヤボンディング時に一定の機械的なスト
レスが加わるとしても、島状絶縁体945Iには亀裂が
生じない。また、島状絶縁体945Iに亀裂が生じると
しても、亀裂が隣接した島状絶縁体945Iには伝播さ
れない。The side wall of the island-shaped insulator 945I is completely covered by the integral conductive plug 950, and the wiring 96
Since the upper and lower surfaces are covered by 0,940, the structure is extremely stable. Therefore, even if a certain mechanical stress is applied at the time of chip classification and / or wire bonding, the island-shaped insulator 945I does not crack. Further, even if a crack occurs in the island-shaped insulator 945I, the crack is not propagated to the adjacent island-shaped insulator 945I.
【0032】図12は、本発明の第2実施形態によるボ
ンディングパッド構造の平面図であり、図13は、図1
2に示されたボンディングパッド構造の斜視図であり、
図14は、図12のXIV-XIV'線に沿って切り取ったボン
ディングパッド構造の断面図であり、図15は、図12
のXV-XV'線に沿って切り取ったボンディングパッド構造
の断面図である。FIG. 12 is a plan view of a bonding pad structure according to a second embodiment of the present invention, and FIG.
2 is a perspective view of the bonding pad structure shown in FIG.
FIG. 14 is a cross-sectional view of the bonding pad structure taken along the line XIV-XIV ′ of FIG. 12, and FIG.
5 is a cross-sectional view of the bonding pad structure taken along line XV-XV ′ of FIG.
【0033】図12ないし図15を参照すれば、第2実
施形態において、中間配線940'は連続的な板状に形
成されるのではなく、上部及び下部一体型導電性プラグ
950,930のように島状絶縁体935Iを含む。こ
のため、中間配線内の島状絶縁体は上部及び下部一体型
導電性プラグ950,930内の島状絶縁体と重複され
る。望ましくは、上部一体型導電性プラグ950内の島
状絶縁体945I及び下部一体型導電性プラグ930内
の島状絶縁体925Iが中間配線940'内の島状絶縁体
935Iに接続されて一つの島状絶縁体Iを構成する。上
部及び下部一体型導電性プラグ950,930内の島状
絶縁体945I,925I及び中間配線940'内に内在
した島状絶縁体935Iが接続されて一つの島状絶縁体I
を構成する場合、島状絶縁体Iの厚さが3つの絶縁体9
25I,935I,945Iの厚さの合計となるので、ス
トレスに対する耐性が大きくなる。Referring to FIGS. 12 to 15, in the second embodiment, the intermediate wiring 940 'is not formed as a continuous plate, but is formed as upper and lower integrated conductive plugs 950 and 930. Includes an island-shaped insulator 935I. Therefore, the island-shaped insulator in the intermediate wiring overlaps with the island-shaped insulator in the upper and lower integrated conductive plugs 950 and 930. Preferably, the island-shaped insulator 945I in the upper integrated conductive plug 950 and the island-shaped insulator 925I in the lower integrated conductive plug 930 are connected to the island-shaped insulator 935I in the intermediate wiring 940 'to form one The island-shaped insulator I is formed. The island-shaped insulators 945I and 925I in the upper and lower integrated conductive plugs 950 and 930 and the island-shaped insulator 935I existing in the intermediate wiring 940 'are connected to each other to form one island-shaped insulator I.
Is formed, the thickness of the island-shaped insulator I is three insulators 9
The sum of the thicknesses of 25I, 935I, and 945I increases the resistance to stress.
【0034】図16は、本発明の第3実施形態によるボ
ンディングパッド構造の平面図である。図16を参照す
れば、第3実施形態において、複数個の島状絶縁体92
5I,945Iはジグザグ状の配列であって、交互に形成
される。FIG. 16 is a plan view of a bonding pad structure according to a third embodiment of the present invention. Referring to FIG. 16, in the third embodiment, a plurality of island-shaped insulators 92 are formed.
5I and 945I are zigzag arrangements, which are alternately formed.
【0035】図17は、本発明の第4実施形態によるボ
ンディングパッド構造の平面図である。図17を参照す
れば、第4実施形態において、島状絶縁体945I',9
25I'は円柱状である。また、島状絶縁体は三角柱また
は五角柱のように、各種の多角柱状に形成できる。FIG. 17 is a plan view of a bonding pad structure according to a fourth embodiment of the present invention. Referring to FIG. 17, in the fourth embodiment, island-shaped insulators 945I ′, 9
25I 'is cylindrical. Further, the island-shaped insulator can be formed in various polygonal pillar shapes such as a triangular pillar or a pentagonal pillar.
【0036】図18は、本発明の第5実施形態によるボ
ンディングパッド構造の平面図である。図18を参照す
れば、第5実施形態において、一体型導電性プラグ93
0',950'は最上部配線のワイヤボンディング領域9
70により覆われた領域の外部の周辺領域の下部に限っ
て形成され、絶縁体929,949は中央のワイヤボン
ディング領域970の下部に形成される。この第5実施
形態によれば、ワイヤボンディング領域970の下部に
は亀裂の発生地として機能するプラグが形成されていな
いため、絶縁体929,949に亀裂が生ぜず、ワイヤ
ボンディング領域の周りの領域の下部に形成された一体
型導電性プラグ930',950'により最上部配線96
0との所定の接触面積が確保される。FIG. 18 is a plan view of a bonding pad structure according to a fifth embodiment of the present invention. Referring to FIG. 18, in the fifth embodiment, an integrated conductive plug 93 is provided.
0 ', 950' is the wire bonding area 9 of the uppermost wiring
The insulator 929 and 949 are formed only below the peripheral region outside the region covered by 70, and the insulators 929 and 949 are formed below the central wire bonding region 970. According to the fifth embodiment, since no plug functioning as a crack generation site is formed below the wire bonding region 970, no crack is generated in the insulators 929 and 949, and the region around the wire bonding region is not formed. The uppermost wiring 96 is formed by integrated conductive plugs 930 'and 950' formed at the bottom of
A predetermined contact area with zero is secured.
【0037】図19は、本発明の第6実施形態によるボ
ンディングパッド構造の平面図である。図19を参照す
れば、第6実施形態において、一体型導電性プラグ93
0',950'の内部に形成される島状絶縁体925I',
945I'は帯状である。FIG. 19 is a plan view of a bonding pad structure according to a sixth embodiment of the present invention. Referring to FIG. 19, in the sixth embodiment, an integrated conductive plug 93 is formed.
0 ', 950', the island-shaped insulator 925I ',
945I 'is a strip.
【0038】図20を参照して、本発明の第1実施形態
によるボンディングパッド構造(図9参照)を形成する
方法について述べる。先ず、中間配線940及び最上部
配線960を形成する段階を述べる。下地層910,9
20,930が形成されている集積回路基板900上に
中間配線940を形成する(ステップ2000)。次
に、中間配線940上に配線間絶縁膜945を形成する
(ステップ2010)。配線間絶縁膜945は中間配線
940上に絶縁物を堆積した後、これをエッチバック及
び/又は化学機械的研磨工程により平坦化して形成す
る。Referring to FIG. 20, a method of forming the bonding pad structure (see FIG. 9) according to the first embodiment of the present invention will be described. First, a step of forming the intermediate wiring 940 and the uppermost wiring 960 will be described. Underlayers 910, 9
An intermediate wiring 940 is formed on the integrated circuit substrate 900 on which the substrates 20 and 930 are formed (Step 2000). Next, an inter-wiring insulating film 945 is formed on the intermediate wiring 940 (Step 2010). The inter-wiring insulating film 945 is formed by depositing an insulator on the intermediate wiring 940 and flattening the insulating material by an etch back and / or a chemical mechanical polishing process.
【0039】次に、上部一体型導電性プラグが形成され
る領域を限定するマスクを使って配線間絶縁膜945を
パターニングする(ステップ2020)。これにより、
中間配線940が部分的に露出され、少なくとも一つ以
上の島状絶縁体945Iを限定する連続的なトレンチが
形成される。Next, the inter-wiring insulating film 945 is patterned using a mask for defining a region where the upper integrated conductive plug is to be formed (step 2020). This allows
The intermediate wiring 940 is partially exposed to form a continuous trench defining at least one or more island-shaped insulators 945I.
【0040】複数個の島状絶縁体945Iは、望ましく
は、マトリックス状にまたはジグザグ状に配列されるよ
うにパターニングする。島状絶縁体945I間の間隔、
すなわち、トレンチの幅は約0.3μmないし10μm
とする。0.3μmまたはそれ以上の間隔に形成する理
由は、一つの島状絶縁体945Iで生じた亀裂が他の島
状絶縁体945Iに伝播されないようにするためであ
る。また、10μmまたはそれ以下の間隔に形成する理
由は、島状絶縁体間のトレンチを導電性プラグにより十
分に充填するためである。The plurality of island-shaped insulators 945I are preferably patterned so as to be arranged in a matrix or zigzag. The spacing between the island-shaped insulators 945I,
That is, the width of the trench is about 0.3 μm to 10 μm.
And The reason for forming the gap at 0.3 μm or more is to prevent a crack generated in one island-shaped insulator 945I from being propagated to another island-shaped insulator 945I. The reason for forming the gap at 10 μm or less is to sufficiently fill the trench between the island-shaped insulators with the conductive plug.
【0041】次に、導電物質、例えば、タングステン、
銅またはアルミニウムなどを使ってトレンチを充填する
導電膜を形成する(ステップ2030)。続いて、トレ
ンチを充填する導電膜をエッチバック及び/又は化学機
械的研磨工程により平坦化して島状絶縁体945Iの側
壁を覆う上部一体型導電性プラグ950を完成させる
(ステップ2040)。上部一体型導電性プラグ950
の上面の総面積は、望ましくは、形成される最上部配線
960の面積の10%以上にする。Next, a conductive material, for example, tungsten,
A conductive film for filling the trench is formed using copper or aluminum (step 2030). Subsequently, the conductive film filling the trench is planarized by an etch-back and / or chemical mechanical polishing process to complete the upper integrated conductive plug 950 covering the side wall of the island-shaped insulator 945I (step 2040). Upper integrated conductive plug 950
Is preferably 10% or more of the area of the uppermost wiring 960 to be formed.
【0042】また、他の方法としては、まず下部の導電
膜と電気的に接続される固体導電膜を前記下部の導電膜
上に形成する。次に、前記固体導電膜をエッチングし
て、固体導電膜を貫通し、互いに所定距離離隔された複
数個のビアを形成する。次に、絶縁膜を前記固体導電膜
上に、そして前記ビア内に形成する。最後に、前記絶縁
膜をエッチバック及び/又は化学機械的研磨により前記
固体導電膜上から除去し、前記絶縁膜をビア内に残留さ
せる。As another method, first, a solid conductive film electrically connected to the lower conductive film is formed on the lower conductive film. Next, the solid conductive film is etched to form a plurality of vias that penetrate the solid conductive film and are separated from each other by a predetermined distance. Next, an insulating film is formed on the solid conductive film and in the via. Finally, the insulating film is removed from the solid conductive film by etch back and / or chemical mechanical polishing, and the insulating film remains in the via.
【0043】図20の説明を続ければ、上部一体型導電
性プラグ950の上面にボンディングパッドとして機能
する最上部配線960を形成する(ステップ205
0)。次に、最上部配線960上を含む全面にパッシベ
ーション膜980を形成する(ステップ2060)。こ
のパッシベーション膜980は、望ましくは、水分を浸
透させず、ストレスに耐性があり、段差塗布性が大き
く、さらに、均一に形成できる膜から形成する。続い
て、パッシベーション膜980をパターニングして最上
部配線960のワイヤボンディング領域970を露出さ
せる(ステップ2070)。Continuing with the description of FIG. 20, an uppermost wiring 960 functioning as a bonding pad is formed on the upper surface of the upper integrated conductive plug 950 (step 205).
0). Next, a passivation film 980 is formed on the entire surface including the uppermost wiring 960 (Step 2060). Desirably, the passivation film 980 is formed of a film that does not allow moisture to permeate, is resistant to stress, has high step coverage, and can be formed uniformly. Subsequently, the passivation film 980 is patterned to expose the wire bonding region 970 of the uppermost wiring 960 (Step 2070).
【0044】中間配線940の下部層、すなわち、下部
配線920及び下部一体型導電性プラグ930を形成す
る方法は、ステップ2000(配線形成段階)ないしス
テップ2040(一体型導電性プラグ及び島状絶縁体の
形成段階)の工程と同様にして、中間配線940の形成
段階前に行われる。下部層状構造を形成する段階を繰り
返し行うことにより、多層配線構造のボンディングパッ
ドの構造を形成できるのは言うまでもない。The method for forming the lower layer of the intermediate wiring 940, that is, the lower wiring 920 and the lower integrated conductive plug 930, includes steps 2000 (wiring forming step) to step 2040 (integrated conductive plug and island-shaped insulator). Is performed before the step of forming the intermediate wiring 940 in the same manner as in the step of (formation step). It is needless to say that the structure of the bonding pad of the multilayer wiring structure can be formed by repeating the step of forming the lower layered structure.
【0045】第2実施形態によるボンディングパッド構
造(図13及び図14参照)の製造方法の場合、中間配
線940'は上部及び下部一体型導電性プラグ950,
930と同一の形態に形成する。すなわち、ステップ2
000ないし2040を通じて下部島状絶縁体925I
を内在した下部一体型導電性プラグ930を形成した
後、ステップ2010ないしステップ2040を同一に
行い、下部一体型の導電性プラグ930と部分的に重複
する中間島状絶縁体935Iを内在した一体型の中間配
線940'を形成する。上部一体型導電性プラグ950
及び最上部配線960の形成段階は、第1実施形態の方
法と同様にして行う。望ましくは、下部、中間及び上部
島状絶縁体925I,935I,945Iが一つに接続さ
れるように形成する。In the case of the method of manufacturing the bonding pad structure (see FIGS. 13 and 14) according to the second embodiment, the intermediate wiring 940 ′ includes the upper and lower integrated conductive plugs 950,
930 is formed in the same form. That is, step 2
Lower island insulator 925I through 000 to 2040
After forming the lower integrated conductive plug 930 having the internal shape, the steps 2010 to 2040 are performed in the same manner, and the integrated type having the intermediate island-shaped insulator 935I partially overlapping the lower integrated conductive plug 930 is formed. Is formed. Upper integrated conductive plug 950
The step of forming the uppermost wiring 960 is performed in the same manner as in the method of the first embodiment. Preferably, the lower, middle, and upper island-shaped insulators 925I, 935I, and 945I are formed to be connected together.
【0046】本発明は下記の実験例を参考としてより詳
細に説明されるが、この実験例が本発明を制限すること
はない。 <実験例1>本発明によるボンディングパッド構造を有
する第1試料を用意した。すなわち、基板上に4層のア
ルミニウム配線を形成し、約3.4μm間隔に離隔され
た島状絶縁体が内在した一体型タングステンプラグを各
配線間に形成し、各配線を電気的に接続させた。最上部
配線上にパッシベーション膜を形成した後、これをパタ
ーニングしてワイヤボンディング領域を露出させた。次
に、ウェッジ方法によりワイヤをボンディングして試料
を用意した。The present invention will be described in more detail with reference to the following experimental examples, which do not limit the present invention. Experimental Example 1 A first sample having a bonding pad structure according to the present invention was prepared. That is, four layers of aluminum wiring are formed on a substrate, an integral tungsten plug having an island-shaped insulator separated by about 3.4 μm is formed between the wirings, and the wirings are electrically connected. Was. After a passivation film was formed on the uppermost wiring, it was patterned to expose a wire bonding region. Next, a wire was bonded by a wedge method to prepare a sample.
【0047】ボンディングパッド構造を完成した後、ワ
イヤ引き強度測定装置を用い、ワイヤ引き強度を測定し
た。本発明によるボンディングパッド構造を有する第1
試料の数は170である。また、図3に示されているよ
うな従来のボンディングパッドを有する第1対照試料1
97個及び図7に示されたような従来のボンディングパ
ッド構造を有する第2対照試料170個を各々用意し
た。対照試料に対しても同一の方法によりワイヤ引き強
度を測定した。After completing the bonding pad structure, the wire pulling strength was measured using a wire pulling strength measuring device. First Embodiment Having a Bonding Pad Structure According to the Present Invention
The number of samples is 170. Also, a first control sample 1 having a conventional bonding pad as shown in FIG.
97 samples and 170 second control samples each having the conventional bonding pad structure as shown in FIG. 7 were prepared. The wire pulling strength was measured for the control sample by the same method.
【0048】測定結果を下記表1及び図21に示す。図
21において、-○-にてプロットされたグラフは本発明
によるボンディングパッド(第1試料)のワイヤ引き強
度を、-△-にてプロットされたグラフは従来のボンディ
ングパッド(第1対照試料)のワイヤ引き強度を、-□-
にてプロットされたグラフは他の従来のボンディングパ
ッド(第2対照試料)のワイヤ引き強度を各々表わす。
累積分布(%)は引張り力を0g重から10g重まで増
やしつつ、ワイヤが剥がれる試料の数を百分率にて示し
た値である。表1において、累積分布は引き強度6g重
以下の値でワイヤが分離された試料の数を百分率にて示
した値である。The measurement results are shown in Table 1 below and FIG. In FIG. 21, the graph plotted with --- shows the wire pulling strength of the bonding pad (first sample) according to the present invention, and the graph plotted with-△-shows the conventional bonding pad (first control sample). -□-
The graphs plotted in each represent the wire pulling strength of another conventional bonding pad (second control sample).
The cumulative distribution (%) is a value indicating, as a percentage, the number of samples from which the wire is peeled while increasing the tensile force from 0 g weight to 10 g weight. In Table 1, the cumulative distribution is a value indicating, as a percentage, the number of samples from which the wire was separated at a pull strength of 6 g weight or less.
【0049】[0049]
【表1】 表1及び図21の結果から、本発明によるパッドが従来
のパッドよりもワイヤ引き強度が大きいということが分
かる。[Table 1] From the results shown in Table 1 and FIG. 21, it can be seen that the pad according to the present invention has higher wire pulling strength than the conventional pad.
【0050】<実験例2>実験例1の方法と同様にして
形成した第1試料と第1及び第2対照試料を対象とし
て、ワイヤと、ボンディングパッドとして機能するアル
ミニウム配線間の接触が不良なためにワイヤが剥がれる
パッドオープン現象及びボンディング時に配線膜が剥が
れる配線オープン現象を各々測定した。さらに、パッド
オープン及び配線オープンを測定した後、第1試料15
8個、第1対照試料140個及び第2対照試料142個
に対して最上部アルミニウム配線下部の島状絶縁体また
は配線間絶縁膜で生じる亀裂の数を測定した。亀裂の数
は各試料のパッシベーション膜及び最上部アルミニウム
配線を適切なエッチング液を使って除去した後、走査電
子顕微鏡を使って測定した。その結果を下記表2及び図
22に示す。<Experimental Example 2> For the first sample and the first and second control samples formed in the same manner as in Experimental Example 1, the contact between the wire and the aluminum wiring functioning as a bonding pad is poor. Therefore, a pad open phenomenon in which a wire is peeled off and a wire open phenomenon in which a wiring film is peeled off during bonding were measured. Further, after measuring the pad open and the wiring open, the first sample 15
The number of cracks generated in the island-shaped insulator or the inter-wiring insulating film below the uppermost aluminum wiring was measured for eight, 140 first control samples, and 142 second control samples. The number of cracks was measured using a scanning electron microscope after removing the passivation film and the uppermost aluminum wiring of each sample using an appropriate etchant. The results are shown in Table 2 below and FIG.
【0051】[0051]
【表2】 [Table 2]
【0052】表2及び図22を参照すれば、従来のパッ
ド構造を採用した第1対照試料及び第2対照試料では亀
裂が多数生じたのに対し、本発明によるパッド構造を採
用した第1試料では亀裂が全く生じなかった。また、亀
裂が生じなかったため、第1試料では配線オープン現象
も見られず、パッドオープン現象の頻度も従来のパッド
構造に比べて著しく減った。Referring to Table 2 and FIG. 22, the first control sample and the second control sample using the conventional pad structure had many cracks, while the first sample using the pad structure according to the present invention. Did not crack at all. Further, since no crack was generated, no wiring open phenomenon was observed in the first sample, and the frequency of the pad open phenomenon was significantly reduced as compared with the conventional pad structure.
【0053】本発明のボンディングパッド構造によれ
ば、最上部配線及び最上部配線下部の配線が連続的な導
電性プラグにより連結されるため、所定大きさ以上の接
触面積を確保できる。このため、十分な量の電流をボン
ディングパッド構造内に伝達できる。According to the bonding pad structure of the present invention, since the uppermost wiring and the wiring below the uppermost wiring are connected by the continuous conductive plug, a contact area of a predetermined size or more can be secured. Therefore, a sufficient amount of current can be transmitted into the bonding pad structure.
【0054】また、最上部配線と下部配線との間の絶縁
膜が一体型導電性プラグ内に閉じ込められた島状絶縁体
から形成される。このため、チップ分類のためにプロー
ブピンが置かれるとき、またはワイヤがボンディングさ
れるときに加わる物理的なストレスにより絶縁体内に亀
裂が生じることが減る。しかも、絶縁体が島状に形成さ
れるので、周りの他の絶縁体に亀裂が伝播されることが
防止される。The insulating film between the uppermost wiring and the lower wiring is formed from an island-shaped insulator confined in an integrated conductive plug. For this reason, the occurrence of cracks in the insulator due to physical stress applied when the probe pins are placed for chip classification or when the wires are bonded is reduced. In addition, since the insulator is formed in an island shape, the propagation of cracks to other insulators around the insulator is prevented.
【0055】図8ないし図11を参照すれば、本発明に
よる各種の実施形態において、複数の島状絶縁体945
Iが一列に配列され、上部一体型導電性プラグ950が
篩パターンとなっている。この上部一体型導電性プラグ
950の篩配列は、上部一体型導電性プラグ950及び
島状絶縁体945Iの間にストレスがあっても、不安定
な上部一体型導電性プラグ950がずれる可能性を低め
る。したがって、所定値以上のストレス下でも島状絶縁
体945Iに亀裂が生じない。あるいは、亀裂が生じて
も、他の島状絶縁体945Iに亀裂が伝播されない。Referring to FIGS. 8-11, in various embodiments according to the present invention, a plurality of island-shaped insulators 945 are provided.
I are arranged in a row, and the upper integrated conductive plug 950 has a sieve pattern. This sieve arrangement of the upper integrated conductive plug 950 reduces the possibility that the unstable upper integrated conductive plug 950 may shift even if there is stress between the upper integrated conductive plug 950 and the island-shaped insulator 945I. Lower. Therefore, cracks do not occur in the island-shaped insulator 945I even under a stress equal to or more than a predetermined value. Alternatively, even if a crack occurs, the crack does not propagate to another island-shaped insulator 945I.
【0056】図8に示される島状絶縁体945I間の間
隔D1は他の島状絶縁体945Iへの亀裂の伝播有無及
び製造工程条件を考慮して決定される。すなわち、島状
絶縁体945I間の間隔D1は一つの島状絶縁体945I
で生じた亀裂が他の島状絶縁体945Iに伝播されない
ように十分に大きい必要がある。また、島状絶縁体94
5Iを先に形成し、これらの間及び上部にタングステン
などの導電物質を形成した後、この導電物質を平坦化し
て上部一体型導電性プラグ950を形成する本発明によ
る実施形態において、島状絶縁体945Iが前記導電物
質により完全に取り囲まれるように島状絶縁体945I
間の最大の間隔は製造工程中に形成される導電物質の厚
さの2倍以下となることが望ましい。The distance D1 between the island-shaped insulators 945I shown in FIG. 8 is determined in consideration of the propagation of cracks to other island-shaped insulators 945I and the manufacturing process conditions. That is, the distance D1 between the island-shaped insulators 945I is one island-shaped insulator 945I.
Must be large enough to prevent the cracks generated in the above from being propagated to other island-shaped insulators 945I. The island-shaped insulator 94
5I is formed first, a conductive material such as tungsten is formed between and above the conductive material, and the conductive material is planarized to form the upper integrated conductive plug 950. Island-shaped insulator 945I such that body 945I is completely surrounded by the conductive material.
It is desirable that the maximum distance between them is less than twice the thickness of the conductive material formed during the manufacturing process.
【0057】上部島状絶縁体945I間の間隔D1は
0.3μmないし10μm程度にすることが望ましい。
上部一体型導電性プラグ950を形成するために使用さ
れる導電物質が0.4μmないし1μm程度の厚さを有
する本発明による実施形態において、上部島状絶縁体9
45I間の間隔は0.3μmないし2μm程度にするこ
とが望ましい。一般に、最上部配線960はボンディン
グパッドとして機能し、四角形で約100μm×100
μmの大きさである。It is desirable that the distance D1 between the upper island-shaped insulators 945I is about 0.3 μm to 10 μm.
In an embodiment according to the present invention, the conductive material used to form the upper integrated conductive plug 950 has a thickness of about 0.4 μm to 1 μm.
It is desirable that the interval between 45I is about 0.3 μm to 2 μm. Generally, the uppermost wiring 960 functions as a bonding pad, and has a square shape of about 100 μm × 100.
It is a size of μm.
【0058】図23ないし図26は本発明のさらに他の
実施形態として、非整列の所定距離離隔された島状絶縁
体の配列を示した平面図である。図23及び図24に示
された実施形態では、横配列の島状絶縁体が互いに非整
列とされているか、またはオフセットされている。この
ため、島状絶縁体の頂点の部分が2つずつだけ互いに隣
接されている。互いに隣接した島状絶縁体の頂点の部分
またはエッジ数を減らすことにより、写真エッチング工
程時に回折される光の量を減らしうる。FIGS. 23 to 26 are plan views showing an array of non-aligned island-shaped insulators separated by a predetermined distance according to still another embodiment of the present invention. In the embodiment shown in FIGS. 23 and 24, the horizontal array of island insulators is misaligned or offset from one another. For this reason, only two apexes of the island-shaped insulator are adjacent to each other. By reducing the number of vertices or edges of adjacent island-shaped insulators, the amount of light diffracted during the photolithography process can be reduced.
【0059】本発明による他の実施形態として、縦配列
の島状絶縁体が互いに非整列とされているか、またはオ
フセットされている場合がある。さらに、横及び縦配列
両方の島状絶縁体が非整列とされている場合もある。隣
接する横配列及び/又は縦配列は例えば半距離だけ互い
にオフセットされている。1つおきに横配列及び/又は
縦配列は整列されており、隣接する横配列及び/又は縦
配列はその間が半距離だけ非整列であるか、或いはオフ
セットされている。他の間隔を使用できることもちろん
である。In another embodiment according to the present invention, the vertical array of island insulators may be misaligned or offset from one another. Further, the island-shaped insulators in both the horizontal and vertical arrangements may be misaligned. Adjacent horizontal and / or vertical arrays are offset from each other by, for example, a half distance. Every other horizontal and / or vertical array is aligned, and adjacent horizontal and / or vertical arrays are misaligned or offset by half a distance between them. Of course, other intervals could be used.
【0060】本発明によるさらに他の実施形態として、
島状絶縁体のエッジが例えば図25に示されたように非
整列とされている場合がある。図25に示されたよう
に、非整列配列の横方向のエッジ2501〜2506は
隣接するエッジ同士が非整列となっている。非整列のエ
ッジ2501〜2506は写真エッチング工程中に回折
される光の量を一層低減できる。縦方向のエッジが非整
列とされている場合もある。As still another embodiment according to the present invention,
In some cases, the edges of the island-shaped insulator are not aligned as shown in FIG. 25, for example. As shown in FIG. 25, adjacent edges 2501 to 2506 of the non-aligned arrangement have non-aligned adjacent edges. The non-aligned edges 2501-2506 can further reduce the amount of light diffracted during the photographic etching process. Vertical edges may be misaligned.
【0061】図26に示されたように、横方向及び縦方
向両方のエッジ2601〜2609が互いに非整列とさ
れている場合がある。特に、非整列配列の横方向のエッ
ジ2601〜2605は互いに対して非整列であり、非
整列配列の縦方向のエッジ2606〜2609も互いに
対して非整列である。横及び縦方向共に非整列であるエ
ッジは写真エッチング工程中に回折される光の量をより
一層低減できる。As shown in FIG. 26, there may be cases where both the horizontal and vertical edges 2601 to 2609 are not aligned with each other. In particular, the lateral edges 2601-2605 of the non-aligned array are non-aligned with each other, and the vertical edges 2606-2609 of the non-aligned array are also non-aligned with each other. Edges that are misaligned in both the horizontal and vertical directions can further reduce the amount of light diffracted during the photoetching process.
【0062】本発明の図25及び図26による実施形態
と違って、図8において例として説明した島状絶縁体の
横配列及び縦配列は整列されている。このように整列さ
れた配列においては、島状絶縁体の4つの頂点が互いに
隣接している。したがって、写真エッチング工程におい
て、島状絶縁体の各頂点で生じる回折が重複されて頂点
に当たるパターン部を丸めて島状絶縁体の臨界値を変え
る。したがって、島状絶縁体を取り囲む導電膜の厚さ
は、島状絶縁体を導電膜により完全に取り囲むために厚
い必要がある。要するに、図8の配列においては、4つ
の頂点が互いに隣接されているため、一層多くの回折が
引き起こされ、これは不明確なエッジを作る。Unlike the embodiment according to FIGS. 25 and 26 of the present invention, the horizontal and vertical arrangement of the island insulators described as an example in FIG. 8 are aligned. In such an aligned array, the four vertices of the island insulator are adjacent to each other. Therefore, in the photo-etching process, the diffraction generated at each vertex of the island-shaped insulator is overlapped, and the pattern portion corresponding to the vertex is rounded to change the critical value of the island-shaped insulator. Therefore, the thickness of the conductive film surrounding the island-shaped insulator needs to be large in order to completely surround the island-shaped insulator with the conductive film. In short, in the arrangement of FIG. 8, the four vertices are adjacent to each other, causing more diffraction, which creates ambiguous edges.
【0063】上部島状絶縁体945I及び下部島状絶縁
体925Iは相互で非整列とされている場合がある。例
えば、上部島状絶縁体945Iは図23に示されたよう
に非整列で配列され、下部島状絶縁体925Iは例えば
図8に示されたように整列配列される。The upper island insulator 945I and the lower island insulator 925I may be non-aligned with each other. For example, the upper island insulators 945I are arranged in a non-aligned manner as shown in FIG. 23, and the lower island insulators 925I are arranged in an aligned manner as shown in FIG.
【0064】再び図24を参照すれば、検査器のプロー
ブピンがワイヤボンディング領域970に横方向に置か
れる場合、検査器のプローブピンにより加わる力は下部
及び上部一体型導電性プラグ930,950に沿って連
続的に伝播され、上部及び下部島状絶縁体945I,9
25Iにより遮断される。したがって、プローブピンの
力(すなわち、せん断力)に対する抵抗が例えば、図8
に示された整列された配列の抵抗に比べて増える。望ま
しくは、島状絶縁体間の間隔D2は一つの島状絶縁体で
生じた亀裂が他の島状絶縁体に伝播できない程度に十分
大きくする。島状絶縁体間の最大の間隔は、望ましく
は、下部及び上部一体型導電性プラグを形成するための
導電物質の厚さの2倍以下にする。Referring again to FIG. 24, when the probe pins of the tester are placed laterally on the wire bonding area 970, the force applied by the probe pins of the tester applies to the lower and upper integrated conductive plugs 930 and 950. Along the upper and lower island insulators 945I, 9
Blocked by 25I. Therefore, the resistance of the probe pin to the force (ie, the shear force) is, for example, as shown in FIG.
As compared with the resistance of the aligned array shown in FIG. Desirably, the distance D2 between the island-shaped insulators is sufficiently large that a crack generated in one island-shaped insulator cannot propagate to another island-shaped insulator. The maximum spacing between the island-shaped insulators is preferably less than twice the thickness of the conductive material for forming the lower and upper integrated conductive plugs.
【0065】この実施形態において、固体中間配線94
0を図10に示すように板状に形成でき、または図14
に示すように、島状絶縁体が内在するようにも形成でき
る。したがって、固体中間配線940は上部及び下部一
体型導電性プラグ950,930と重複され、さらに図
14の固体中間配線940'である場合は上部及び下部
一体型導電性プラグ950,930と一致する。In this embodiment, the solid intermediate wiring 94
0 can be formed in a plate shape as shown in FIG.
As shown in (1), an island-shaped insulator can be formed inside. Therefore, the solid intermediate wiring 940 is overlapped with the upper and lower integrated conductive plugs 950 and 930, and in the case of the solid intermediate wiring 940 'of FIG. 14, it coincides with the upper and lower integrated conductive plugs 950 and 930.
【0066】本発明によるさらに他の実施形態として、
ボンディングパッドは図27に示されたように金属バン
パ層2700を含みうる。金属バンパ層2700は絶縁
物質2745により取り囲まれた導電性プラグ2750
上に形成された上部配線2760上にある。上部ボンデ
ィングパッド層2705は金属バンパ層2700上に形
成される。上部ボンディングパッド層2705は金属バ
ンパ層2700の真上にある。As still another embodiment according to the present invention,
The bonding pad may include a metal bumper layer 2700 as shown in FIG. The metal bumper layer 2700 includes a conductive plug 2750 surrounded by an insulating material 2745.
It is on the upper wiring 2760 formed thereon. The upper bonding pad layer 2705 is formed on the metal bumper layer 2700. The upper bonding pad layer 2705 is directly above the metal bumper layer 2700.
【0067】製造時に、検査プローブは集積回路の部分
が検査可能のように上部ボンディングパッド層2705
と繰り返し接触する。その後、ワイヤが例えば、図10
に示されたように、上部ボンディングパッド層2705
にボンディングされる。金属バンパ層2700は検査プ
ローブの反復的な接触が上部導電性プラグ2750と上
部配線2760との間の機械的な結合を減少させる可能
性を減らす。したがって、この実施形態は検査プローブ
による反復的な接触の結果として上部配線2760が上
部導電性プラグ2750から剥がれる可能性を減らすこ
とにより、集積回路の信頼性を向上できる。At the time of manufacture, a test probe is used to test the upper bonding pad layer 2705 so that portions of the integrated circuit can be tested.
Contact repeatedly. Then, the wire is, for example, as shown in FIG.
As shown in FIG.
Bonding. The metal bumper layer 2700 reduces the likelihood that repeated contact of the test probe will reduce the mechanical coupling between the upper conductive plug 2750 and the upper interconnect 2760. Therefore, this embodiment can improve the reliability of the integrated circuit by reducing the possibility that the upper wiring 2760 may be peeled off from the upper conductive plug 2750 as a result of repeated contact with the test probe.
【0068】従来のボンディングパッド構造において、
検査プローブは上部導電性プラグ及び絶縁物質の部分が
露出されるように上部配線に食い込む。したがって、ボ
ンディングパッドにワイヤをボンディングするのに使用
されるソルダは十分なボンディング接着力を与えない露
出された絶縁物質と接触し、上部配線は上部導電性プラ
グから剥がれる。In the conventional bonding pad structure,
The inspection probe cuts into the upper wiring so that the upper conductive plug and the insulating material are exposed. Therefore, the solder used to bond the wires to the bonding pads comes into contact with the exposed insulating material that does not provide sufficient bonding strength, and the upper wiring is stripped from the upper conductive plug.
【0069】本発明によるボンディングパッド構造は、
第1絶縁膜2710上に下部配線2740を形成するこ
とにより製造できる。下部配線2740はアルミニウム
または銅などの金属でありうる。もちろん、他の金属も
使用できる。下部配線2740がパターニングされ、酸
化膜などの第2絶縁膜2745がその上部に形成され
る。第2絶縁膜2745はその内部にビアを形成するた
めにパターニングされる。上部導電性プラグ2750は
エッチバック工程または化学機械的研磨(CMP)を利
用してビア内に形成される。上部導電性プラグ2750
はタングステン(W)、アルミニウム(Al)、銅(C
u)などの導電物質でありうる。もちろん、他の導電物
質も使用できる。TiまたはTiNなどのバリア層(図
示せず)を下部配線2740と第2絶縁膜2745との
間に蒸着することもできる。The bonding pad structure according to the present invention
It can be manufactured by forming the lower wiring 2740 on the first insulating film 2710. The lower wiring 2740 may be a metal such as aluminum or copper. Of course, other metals can be used. The lower wiring 2740 is patterned, and a second insulating film 2745 such as an oxide film is formed thereon. The second insulating film 2745 is patterned to form a via therein. The upper conductive plug 2750 is formed in the via using an etch-back process or a chemical mechanical polishing (CMP). Upper conductive plug 2750
Are tungsten (W), aluminum (Al), copper (C
u) and the like. Of course, other conductive materials can be used. A barrier layer (not shown) such as Ti or TiN may be deposited between the lower wiring 2740 and the second insulating layer 2745.
【0070】第2配線2760は第2絶縁膜2745及
び上部導電性プラグ2750上に形成される。金属バン
パ層2700は、図27に示されたように、エッチバッ
ク工程、または図28に示されたように、化学機械的研
磨(CMP)を利用して第2配線2760上に形成され
る。金属バンパ層2700は400Å程度の厚さであり
うる。金属バンパ層2700は集積回路の内部領域のプ
ラグと同時に形成できる。上部ボンディングパッド層2
705は8,000Åないし10,000Å程度の厚さ
で金属バンパ層2700上に形成できる。金属バンパ層
2700及び上部ボンディングパッド層2705の結合
厚さは12,000Åないし14,000Å程度の範囲
にある。図28に示されたように、金属バンパ層270
0及び上部ボンディングパッド層2705の厚さはエッ
チバック工程または化学機械的研磨(CMP)を補償す
るように調節できる。The second wiring 2760 is formed on the second insulating film 2745 and the upper conductive plug 2750. The metal bumper layer 2700 is formed on the second wiring 2760 using an etch back process as shown in FIG. 27 or a chemical mechanical polishing (CMP) as shown in FIG. Metal bumper layer 2700 may be as thick as 400 °. The metal bumper layer 2700 can be formed simultaneously with the plug in the internal region of the integrated circuit. Upper bonding pad layer 2
705 may be formed on the metal bumper layer 2700 to a thickness of about 8,000 to 10,000 degrees. The combined thickness of the metal bumper layer 2700 and the upper bonding pad layer 2705 is in the range of about 12,000 to 14,000. As shown in FIG. 28, the metal bumper layer 270
The thickness of the 0 and upper bonding pad layers 2705 can be adjusted to compensate for an etch-back process or chemical mechanical polishing (CMP).
【0071】金属バンパ層2700はタングステンを含
む。もちろん、他の金属も使用できる。金属バンパ層2
700はまた、図8ないし図22及び図23ないし図2
6を参照して説明した本発明による所定距離離隔された
島状絶縁体及び一体型導電性プラグを含むボンディング
パッド構造として形成できる。The metal bumper layer 2700 contains tungsten. Of course, other metals can be used. Metal bumper layer 2
700 also corresponds to FIGS. 8 to 22 and FIGS.
6 may be formed as a bonding pad structure including an island-shaped insulator and an integrated conductive plug separated by a predetermined distance according to the present invention described with reference to FIG.
【0072】図29は、本発明による島状絶縁体290
5が内在された金属バンパ層2900を有するボンディ
ングパッド構造の実施形態を説明する断面図である。図
29に示されたように、島状絶縁体2905は金属バン
パ層2900内に位置され、外部エッジ側に位置する。
したがって、金属バンパ層2900の内部領域は外部エ
ッジ側に位置する島状絶縁体2905よりも少数の島状
絶縁体2905を有する。ある具体例においては、金属
バンパ層2900の内部領域には島状絶縁体2905が
ない。したがって、本発明による実施形態は金属バンパ
層2900の内部領域に加わったストレスにより敏感で
はなく、このため、接着が緩む可能性はほとんどない。FIG. 29 shows an island-shaped insulator 290 according to the present invention.
FIG. 5 is a cross-sectional view illustrating an embodiment of a bonding pad structure having a metal bumper layer 2900 with embedded 5. As shown in FIG. 29, the island-shaped insulator 2905 is located in the metal bumper layer 2900 and located on the outer edge side.
Therefore, the inner region of metal bumper layer 2900 has fewer island-shaped insulators 2905 than island-shaped insulators 2905 located on the outer edge side. In one embodiment, there is no island insulator 2905 in the interior region of the metal bumper layer 2900. Therefore, embodiments according to the present invention are less sensitive to stress applied to the interior regions of the metal bumper layer 2900, and there is little likelihood of loosening the bond.
【0073】図30は、本発明による金属バンパ層30
00を有するボンディングパッド構造の他の実施形態を
説明する断面図である。図30に示されたように、第2
導電膜3010及び上部導電性プラグ3020はダマシ
ン工程を利用して形成される。また、金属バンパ層30
00及び上部ボンディングパッド層3005は12,0
00Åないし14,000Å程度の範囲の厚さを有する
単一層で形成される。FIG. 30 shows a metal bumper layer 30 according to the present invention.
FIG. 9 is a cross-sectional view illustrating another embodiment of a bonding pad structure having a 00. As shown in FIG.
The conductive film 3010 and the upper conductive plug 3020 are formed using a damascene process. Also, the metal bumper layer 30
00 and the upper bonding pad layer 3005
It is formed of a single layer having a thickness in the range of about 00-14,000.
【0074】[0074]
【発明の効果】以上述べたように、本発明のボンディン
グパッド構造によれば、最上部配線と最上部配線下部の
配線が連続的な導電性プラグにより連結されるため、所
定大きさ以上の接触面積を確保できる。このため、十分
な量の電流をボンディングパッド構造内に伝達できる。As described above, according to the bonding pad structure of the present invention, the uppermost wiring and the wiring below the uppermost wiring are connected by a continuous conductive plug, so that a contact having a predetermined size or more is formed. The area can be secured. Therefore, a sufficient amount of current can be transmitted into the bonding pad structure.
【0075】また、最上部配線と下部配線との間の絶縁
膜は一体型導電性プラグ内に閉じ込められた島状絶縁体
から形成される。したがって、チップ分類のためにプロ
ーブピンが置かれるとき、またはワイヤがボンディング
されるときに加わる物理的なストレスにより絶縁体内に
亀裂が生じることが減る。しかも、絶縁体が島状に形成
されるため、周りの他の絶縁体に亀裂が伝播されること
も防止される。The insulating film between the uppermost wiring and the lower wiring is formed of an island-shaped insulator confined in an integrated conductive plug. Accordingly, cracks are less likely to occur in the insulator due to the physical stress applied when the probe pins are placed for chip sorting or when the wires are bonded. In addition, since the insulator is formed in an island shape, the propagation of a crack to other surrounding insulators is also prevented.
【0076】上部一体型導電性プラグは一具体例では複
数個の島状絶縁体が一列に配列され、篩の形となってい
る。したがって、上部一体型導電性プラグと島状絶縁体
との間にストレスがあっても、上部一体型導電性プラグ
の篩配列は不安定な上部一体型導電性プラグが剥がれる
可能性を減らす。このため、所定値以上のストレス下で
も島状絶縁体に亀裂が生じない。あるいは、亀裂が生じ
ても、他の島状絶縁体に亀裂が伝播されない。In one specific example, the upper integrated conductive plug has a plurality of island-shaped insulators arranged in a line and is in the form of a sieve. Therefore, even if there is a stress between the upper integrated conductive plug and the island-shaped insulator, the sieve arrangement of the upper integrated conductive plug reduces the possibility of the unstable upper integrated conductive plug coming off. Therefore, cracks do not occur in the island-shaped insulator even under a stress equal to or more than a predetermined value. Alternatively, even if a crack occurs, the crack does not propagate to other island-shaped insulators.
【0077】一方、横配列及び/又は縦配列の島状絶縁
体は一具体例では互いに非整列とされているか、或いは
オフセットされており、このとき、島状絶縁体の頂点の
部分が2つずつだけ互いに隣接されている。したがっ
て、互いに隣接した島状絶縁体の頂点の部分またはエッ
ジの数を減らすことにより、写真エッチング工程時に回
折される光の量を低減できる。On the other hand, the island-shaped insulators in the horizontal and / or vertical arrangement are, in one embodiment, non-aligned or offset with respect to each other. Are adjacent to each other. Accordingly, the amount of light diffracted during the photolithography process can be reduced by reducing the number of apexes or edges of the adjacent island-shaped insulators.
【0078】ボンディングパッドは金属バンパ層を含み
うるが、金属バンパ層は検査プローブの反復的な接触に
よって上部導電性プラグと上部配線との間の機械的な結
合が低減することを減らす。このため、本発明は検査プ
ローブによる反復的な接触の結果として上部配線が上部
導電性プラグから剥がれることを減らすことにより、集
積回路の信頼性を向上できる。Although the bonding pad may include a metal bumper layer, the metal bumper layer reduces the reduction in mechanical coupling between the upper conductive plug and the upper wiring due to repeated contact of the test probe. Thus, the present invention can improve the reliability of the integrated circuit by reducing the possibility that the upper wiring peels off from the upper conductive plug as a result of repeated contact by the test probe.
【0079】また、本発明は島状絶縁体が内在された金
属バンパ層を有するボンディングパッド構造でありうる
が、島状絶縁体が内在された金属バンパ層を有するボン
ディングパッド構造は金属バンパ層の内部領域に加わっ
たストレスにより敏感ではなく、このため、接着が緩む
可能性はほとんどない。Further, the present invention can be a bonding pad structure having a metal bumper layer having an island-shaped insulator therein. However, the bonding pad structure having a metal bumper layer having an island-shaped insulator therein is formed of a metal bumper layer. It is less sensitive to stresses applied to the interior area, so there is little likelihood of loosening of the bond.
【図1】リードフレームに接合された集積回路の概略図
である。FIG. 1 is a schematic diagram of an integrated circuit bonded to a lead frame.
【図2】図1に示された従来のボンディングパッド構造
の拡大平面図である。FIG. 2 is an enlarged plan view of the conventional bonding pad structure shown in FIG.
【図3】図2に示されたボンディングパッド構造の斜視
図である。FIG. 3 is a perspective view of the bonding pad structure shown in FIG. 2;
【図4】図2のIV-IV'線に沿って切り取ったボンディン
グパッド構造の断面図である。FIG. 4 is a cross-sectional view of the bonding pad structure taken along the line IV-IV ′ of FIG. 2;
【図5】図2のV-V'線に沿って切り取ったボンディング
パッド構造の断面図である。FIG. 5 is a cross-sectional view of the bonding pad structure taken along line VV ′ of FIG. 2;
【図6】従来の他のボンディングパッド構造の平面図で
ある。FIG. 6 is a plan view of another conventional bonding pad structure.
【図7】図6のVII-VII'線に沿って切り取ったボンディ
ングパッド構造の断面図である。7 is a cross-sectional view of the bonding pad structure taken along the line VII-VII 'of FIG.
【図8】本発明の第1実施形態によるボンディングパッ
ド構造の平面図である。FIG. 8 is a plan view of a bonding pad structure according to the first embodiment of the present invention.
【図9】図8に示されたボンディングパッド構造の斜視
図である。FIG. 9 is a perspective view of the bonding pad structure shown in FIG. 8;
【図10】図8のX-X'線に沿って切り取ったボンディン
グパッド構造の断面図である。FIG. 10 is a sectional view of the bonding pad structure taken along line XX ′ of FIG. 8;
【図11】図8のXI-XI'線に沿って切り取ったボンディ
ングパッド構造の断面図である。11 is a cross-sectional view of the bonding pad structure taken along the line XI-XI 'of FIG.
【図12】本発明の第2実施形態によるボンディングパ
ッド構造の平面図である。FIG. 12 is a plan view of a bonding pad structure according to a second embodiment of the present invention.
【図13】図12に示されたボンディングパッド構造の
斜視図である。13 is a perspective view of the bonding pad structure shown in FIG.
【図14】図12のXIV-XIV'線に沿って切り取ったボン
ディングパッド構造の断面図である。14 is a cross-sectional view of the bonding pad structure taken along the line XIV-XIV ′ of FIG.
【図15】図12のXV-XV'線に沿って切り取ったボンデ
ィングパッド構造の断面図である。15 is a cross-sectional view of the bonding pad structure taken along the line XV-XV 'of FIG.
【図16】本発明の第3実施形態によるボンディングパ
ッド構造の平面図である。FIG. 16 is a plan view of a bonding pad structure according to a third embodiment of the present invention.
【図17】本発明の第4実施形態によるボンディングパ
ッド構造の平面図である。FIG. 17 is a plan view of a bonding pad structure according to a fourth embodiment of the present invention.
【図18】本発明の第5実施形態によるボンディングパ
ッド構造の平面図である。FIG. 18 is a plan view of a bonding pad structure according to a fifth embodiment of the present invention.
【図19】本発明の第6実施形態によるボンディングパ
ッド構造の平面図である。FIG. 19 is a plan view of a bonding pad structure according to a sixth embodiment of the present invention.
【図20】本発明によるボンディングパッド構造の製造
方法を示すブロック図である。FIG. 20 is a block diagram illustrating a method for manufacturing a bonding pad structure according to the present invention.
【図21】本発明によるボンディングパッド構造にボン
ディングされたワイヤの引き強度を従来のボンディング
パッドと比較して示した特性図である。FIG. 21 is a characteristic diagram showing the pulling strength of a wire bonded to a bonding pad structure according to the present invention in comparison with a conventional bonding pad.
【図22】本発明によるボンディングパッド構造におけ
るパッドオープン及び配線オープンを従来のボンディン
グパッド構造と比較して示した特性図である。FIG. 22 is a characteristic diagram showing pad open and wire open in a bonding pad structure according to the present invention, as compared with a conventional bonding pad structure.
【図23】本発明による非整列の所定距離離隔された島
状絶縁体の配列を含むボンディングパッド構造の実施形
態を説明する平面図である。FIG. 23 is a plan view illustrating an embodiment of a bonding pad structure including an array of non-aligned island-shaped insulators separated by a predetermined distance according to the present invention.
【図24】本発明による非整列の所定距離離隔された島
状絶縁体の配列を含むボンディングパッド構造の実施形
態を説明する平面図である。FIG. 24 is a plan view illustrating an embodiment of a bonding pad structure including an array of non-aligned island-shaped insulators separated by a predetermined distance according to the present invention.
【図25】本発明による非整列の所定距離離隔された島
状絶縁体の配列を含むボンディングパッド構造の実施形
態を説明する平面図である。FIG. 25 is a plan view illustrating an embodiment of a bonding pad structure including an array of non-aligned island-shaped insulators separated by a predetermined distance according to the present invention.
【図26】本発明による非整列の所定距離離隔された島
状絶縁体の配列を含むボンディングパッド構造の実施形
態を説明する平面図である。FIG. 26 is a plan view illustrating an embodiment of a bonding pad structure including an array of non-aligned island-shaped insulators separated by a predetermined distance according to the present invention.
【図27】本発明による金属バンパ層を含むボンディン
グパッド構造の実施形態を説明する断面図である。FIG. 27 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
【図28】本発明による金属バンパ層を含むボンディン
グパッド構造の実施形態を説明する断面図である。FIG. 28 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
【図29】本発明による金属バンパ層を含むボンディン
グパッド構造の実施形態を説明する断面図である。FIG. 29 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
【図30】本発明による金属バンパ層を含むボンディン
グパッド構造の実施形態を説明する断面図である。FIG. 30 is a cross-sectional view illustrating an embodiment of a bonding pad structure including a metal bumper layer according to the present invention.
920 下部配線 930 下部一体型導電性プラグ 940 中間配線 950 上部一体型導電性プラグ 960 最上部配線 925I 下部島状絶縁体 945I 上部島状絶縁体 925,945 層間絶縁膜 970 ワイヤボンディング領域 920 Lower wiring 930 Lower integrated conductive plug 940 Intermediate wiring 950 Upper integrated conductive plug 960 Uppermost wiring 925I Lower island insulator 945I Upper island insulator 925,945 Interlayer insulating film 970 Wire bonding area
───────────────────────────────────────────────────── フロントページの続き (72)発明者 孫 京 睦 大韓民国ソウル特別市江西区禾谷2洞870 −24番地 ビジョンビラーB01号 (72)発明者 丁 武 鎮 大韓民国京畿道龍仁市器興邑貢税里107− 1102番地 青丘アパート449棟900号 (72)発明者 王 善 鐘 大韓民国京畿道水原市八達区靈通洞 住公 アパート517棟402号 (72)発明者 柳 在 哲 大韓民国京畿道水原市八達区梅灘洞 韓国 アパート114棟608号 (72)発明者 申 憲 宗 大韓民国京畿道龍仁市水枝邑上▲ヒュン▼ 里99番地 碧山アパート106棟507号 (72)発明者 李 恵 令 大韓民国京畿道城南市盆唐区九美洞202番 地 ムジゲマウルLGアパート210棟802号 (72)発明者 金 栄 泌 大韓民国京畿道城南市盆唐区九美洞 大宇 アパート104棟1002号 Fターム(参考) 5F033 HH08 HH19 JJ08 JJ11 JJ19 KK08 MM01 MM05 NN33 NN38 QQ08 QQ09 QQ31 QQ37 QQ48 VV07 WW02 XX17 XX19 5F044 EE06 EE11 EE12 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sun Kyo Mutsumi 870-24, Haeok-dong 2-dong, Gangseo-gu, Seoul, Republic of Korea Vision Bler B01 (72) Inventor Ding Takezhen Gonggi-eup, Gongki-do, Republic of Korea 107-1102, Tae-ri, Aooka Apartment 449, Building 900 (72) Inventor Wang Zhen Jong, Apartment 517, 402, Sukong-dong, Paldal-gu, Suwon-si, Gyeonggi-do, Republic of Korea No. 114, Building 608, Apartment 114, Umedan-dong, Paldal-gu, Seoul (72) Inventor Shen Jong-song Buksan Apartment 106, Building 507, No. 99, Suyeong-eup, Suwon-eup, Yongin-si, Gyeonggi-do, Republic of Korea 202, Jeong-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, Republic of Korea Over preparative 104 houses 1002 No. F term (Reference) 5F033 HH08 HH19 JJ08 JJ11 JJ19 KK08 MM01 MM05 NN33 NN38 QQ08 QQ09 QQ31 QQ37 QQ48 VV07 WW02 XX17 XX19 5F044 EE06 EE11 EE12
Claims (25)
導電膜と、 前記所定距離離隔された第1導電膜及び第2導電膜間に
存在し、前記所定距離離隔された第1導電膜及び第2導
電膜に電気的に接続された連続的な第3導電膜と、 前記連続的な第3導電膜内に存在し、前記連続的な第3
導電膜を貫通するように延びてその側壁が前記連続的な
第3導電膜により覆われた非整列で、かつ所定距離離隔
された島状絶縁体の配列とを含むことを特徴とする集積
回路のためのボンディングパッド。A first conductive film and a second conductive film separated by a predetermined distance;
A conductive film, and a continuous first conductive film present between the first conductive film and the second conductive film separated by the predetermined distance and electrically connected to the first conductive film and the second conductive film separated by the predetermined distance; A third conductive film, the third conductive film being present in the continuous third conductive film,
An array of non-aligned and spaced apart island-shaped insulators extending through the conductive film and having sidewalls covered by the continuous third conductive film. Bonding pads for.
された島状絶縁体の横配列を含むことを特徴とする請求
項1に記載の集積回路のためのボンディングパッド。2. The bonding pad of claim 1, wherein the array includes a non-aligned, horizontal array of island-shaped insulators separated by a predetermined distance.
された島状絶縁体の横配列及び非整列で、かつ所定距離
離隔された島状絶縁体の縦配列を含むことを特徴とする
請求項1に記載の集積回路のためのボンディングパッ
ド。3. The arrangement of claim 2, wherein the arrangement includes a non-aligned, horizontal arrangement of island-shaped insulators separated by a predetermined distance and a non-aligned, vertical arrangement of island-shaped insulators, separated by a predetermined distance. A bonding pad for an integrated circuit according to claim 1.
島状絶縁体の配列は、 第1方向の第1エッジを有する第1島状絶縁体と、 前記第1方向の第1島状絶縁体に隣接し、第1エッジと
非整列とされた第1方向の第2エッジを有する第2島状
絶縁体とを含むことを特徴とする請求項1に記載の集積
回路のためのボンディングパッド。4. An array of non-aligned and island-shaped insulators separated by a predetermined distance includes: a first island-shaped insulator having a first edge in a first direction; a first island-shaped insulator in the first direction. The bonding for an integrated circuit according to claim 1, including a second island-like insulator adjacent to the insulator and having a first edge and a second edge in a first direction misaligned. pad.
島状絶縁体の配列は、非整列で、かつ所定距離離隔され
た島状絶縁体の第1配列であり、 前記ボンディングパッドは、 前記連続的な第3導電膜及び前記第2導電膜間に存在
し、前記連続的な第3導電膜及び前記第2導電膜に電気
的に接続された連続的な第4導電膜と、 前記連続的な第4導電膜内に存在し、前記連続的な第4
導電膜を貫通するように延びてその側壁が前記連続的な
第4導電膜により覆われた所定距離離隔された島状絶縁
体の第2配列とをさらに含み、前記所定距離離隔された
島状絶縁体の第2配列は、前記非整列で、かつ所定距離
離隔された島状絶縁体の第1配列と非整列とされている
ことを特徴とする請求項1に記載の集積回路のためのボ
ンディングパッド。5. The array of non-aligned and island-shaped insulators separated by a predetermined distance is a first array of non-aligned and island-shaped insulators separated by a predetermined distance. A continuous fourth conductive film present between the continuous third conductive film and the second conductive film and electrically connected to the continuous third conductive film and the second conductive film; The continuous fourth conductive film exists in the continuous fourth conductive film.
A second array of island-shaped insulators extending a predetermined distance apart and extending through the conductive film and having side walls covered by the continuous fourth conductive film; 2. The integrated circuit according to claim 1, wherein a second array of insulators is non-aligned with the first array of island-shaped insulators spaced apart by a predetermined distance. Bonding pad.
ンパ層上の上部ボンディングパッド層をさらに含むこと
を特徴とする請求項1に記載の集積回路のためのボンデ
ィングパッド。6. The method of claim 1, further comprising a metal bumper layer on the first conductive film, and an upper bonding pad layer on the metal bumper layer formed for bonding with a wire. Bonding pads for integrated circuits.
むことを特徴とする請求項6に記載の集積回路のための
ボンディングパッド。7. The bonding pad according to claim 6, wherein the metal bumper layer includes tungsten.
厚さを有することを特徴とする請求項6に記載の集積回
路のためのボンディングパッド。8. The bonding pad of claim 6, wherein the metal bumper layer has a thickness of about 4,000 degrees.
ングパッド層は、約12,000Åないし14,000
Åの範囲の厚さを有する単一層であることを特徴とする
請求項6に記載の集積回路のためのボンディングパッ
ド。9. The metal bumper layer and the upper bonding pad layer may have a thickness of about 12,000 to 14,000.
7. The bonding pad for an integrated circuit according to claim 6, wherein the bonding pad is a single layer having a thickness in the range of Å.
記金属バンパ層の真上にあることを特徴とする請求項6
に記載の集積回路のためのボンディングパッド。10. The method of claim 6, wherein the upper bonding pad layer is directly above the metal bumper layer.
3. A bonding pad for an integrated circuit according to claim 1.
の外部エッジ側に位置した島状絶縁体を含むことを特徴
とする請求項6に記載の集積回路のためのボンディング
パッド。11. The bonding pad according to claim 6, wherein the metal bumper layer includes an island-shaped insulator located on an outer edge side of the metal bumper layer.
状絶縁体がないことを特徴とする請求項11に記載の集
積回路のためのボンディングパッド。12. The bonding pad for an integrated circuit according to claim 11, wherein there is no island-shaped insulator in an inner region of the metal bumper layer.
と、 ワイヤとボンディングするために形成された前記金属バ
ンパ層上の上部ボンディングパッド層とを含むことを特
徴とする集積回路のためのボンディングパッド。13. A conductive film including an insulating portion inside, a metal bumper layer on the conductive film and the insulating portion inside the conductive film, and an upper bonding pad on the metal bumper layer formed for bonding to a wire. And a bonding pad for an integrated circuit.
含むことを特徴とする請求項13に記載の集積回路のた
めのボンディングパッド。14. The bonding pad according to claim 13, wherein the metal bumper layer includes tungsten.
記金属バンパ層の直上にあることを特徴とする請求項1
3に記載の集積回路のためのボンディングパッド。15. The semiconductor device according to claim 1, wherein the upper bonding pad layer is immediately above the metal bumper layer.
A bonding pad for an integrated circuit according to claim 3.
の外部エッジ側に位置した島状絶縁体を含むことを特徴
とする請求項13に記載の集積回路のためのボンディン
グパッド。16. The bonding pad according to claim 13, wherein the metal bumper layer includes an island-shaped insulator located on an outer edge side of the metal bumper layer.
状絶縁体がないことを特徴とする請求項16に記載の集
積回路のためのボンディングパッド。17. The bonding pad according to claim 16, wherein the metal bumper layer has no island-shaped insulator in an inner region of the metal bumper layer.
むことを特徴とする請求項13に記載の集積回路のため
のボンディングパッド。18. The bonding pad according to claim 13, wherein the metal bumper layer includes a solid metal film.
2導電膜と、 前記所定距離離隔された第1導電膜及び第2導電膜間に
存在し、前記所定距離離隔された第1導電膜及び第2導
電膜に電気的に接続された連続的な第3導電膜と、 前記連続的な第3導電膜内にジグザグ状に配列され、前
記連続的な第3導電膜を貫通するように延びてその側壁
が前記連続的な第3導電膜により覆われた所定距離離隔
された島状絶縁体の配列とを含むことを特徴とする集積
回路のためのボンディングパッド。19. The first conductive film and the second conductive film separated by a predetermined distance, and the first conductive film present between the first conductive film and the second conductive film separated by the predetermined distance and separated by the predetermined distance. A continuous third conductive film electrically connected to the film and the second conductive film; and a zigzag arrangement in the continuous third conductive film to penetrate the continuous third conductive film. And an array of spaced apart island-shaped insulators, the sidewalls of which are covered by the continuous third conductive film.
る段階と、 前記下部導電膜上に前記下部導電膜に電気的に接続され
るように連続的な導電膜を形成する段階であり、前記連
続的な導電膜は、その内部に非整列の所定距離離隔され
た島状絶縁体の配列を含み、島状絶縁体の配列は前記連
続的な導電膜を貫通するように延び、島状絶縁体の側壁
は前記連続的な導電膜で覆われる段階と、 前記連続的な導電膜上に前記連続的な導電膜に電気的に
接続される上部導電膜を形成する段階とを含むことを特
徴とする集積回路のためのボンディングパッドの製造方
法。20. A step of forming a lower conductive film on an integrated circuit substrate; and forming a continuous conductive film on the lower conductive film so as to be electrically connected to the lower conductive film. The continuous conductive film includes an array of non-aligned, spaced-apart island-shaped insulators therein, the array of island-shaped insulators extending through the continuous conductive film, and Covering a sidewall of an insulator with the continuous conductive film; and forming an upper conductive film on the continuous conductive film, the conductive film being electrically connected to the continuous conductive film. A method of manufacturing a bonding pad for an integrated circuit.
は、非整列の所定距離離隔された島状絶縁体の横配列を
含む連続的な導電膜を形成する段階を含むことを特徴と
する請求項20に記載の集積回路のためのボンディング
パッドの製造方法。21. The method of claim 21, wherein forming the continuous conductive layer comprises forming a continuous conductive layer including a horizontal array of non-aligned, spaced-apart island-shaped insulators. A method for manufacturing a bonding pad for an integrated circuit according to claim 20.
は、非整列の所定距離離隔された島状絶縁体の横配列及
び非整列の所定距離離隔された島状絶縁体の縦配列を含
む連続的な導電膜を形成する段階を含むことを特徴とす
る請求項20に記載の集積回路のためのボンディングパ
ッドの製造方法。22. The step of forming the continuous conductive layer includes a horizontal arrangement of non-aligned island-shaped insulators spaced apart by a predetermined distance and a vertical alignment of non-aligned island-shaped insulators spaced by a predetermined distance. The method of claim 20, further comprising forming a continuous conductive film.
は、 前記連続的な導電膜内に第1方向の第1エッジを有する
第1島状絶縁体を形成する段階と、 前記第1方向の前記第1島状絶縁体に隣接し、第1エッ
ジと非整列とされた第1方向の第2エッジを有する第2
島状絶縁体を前記連続的な導電膜内に形成する段階とを
含むことを特徴とする請求項20に記載の集積回路のた
めのボンディングパッドの製造方法。23. The step of forming the continuous conductive film, comprising: forming a first island-shaped insulator having a first edge in a first direction in the continuous conductive film; A second edge in a first direction adjacent to the first island-shaped insulator and non-aligned with the first edge.
Forming an island-shaped insulator in the continuous conductive film. 21. The method of claim 20, further comprising the steps of:
絶縁体の配列は、非整列の所定距離離隔された島状絶縁
体の第1配列であり、 前記方法は、 前記連続的な導電膜と前記下部導電膜間に存在し、前記
連続的な導電膜及び前記下部導電膜に電気的に接続され
た連続的な第4導電膜を形成する段階と、 前記非整列の所定距離離隔された島状絶縁体の第1配列
と非整列である所定距離離隔された島状絶縁体の第2配
列を前記連続的な第4導電膜内に、前記連続的な第4導
電膜を貫通するように延びてその側壁が前記連続的な第
4導電膜により覆われるように形成する段階とをさらに
含むことを特徴とする請求項20に記載の集積回路のた
めのボンディングパッドの製造方法。24. The array of non-aligned, spaced-apart, island-shaped insulators is a first array of non-aligned, spaced-apart, island-shaped insulators. Forming a continuous fourth conductive film between the film and the lower conductive film and electrically connected to the continuous conductive film and the lower conductive film; Penetrating the continuous fourth conductive film into the continuous fourth conductive film, a second array of island-like insulators separated by a predetermined distance that is not aligned with the first array of formed island-shaped insulators. 21. The method of claim 20, further comprising forming the second conductive layer so as to cover the sidewall by the fourth conductive layer.
隣接する横配列は半距離だけ非整列であることを特徴と
する請求項1に記載の集積回路のためのボンディングパ
ッド。25. Every other horizontal array is aligned,
The bonding pad for an integrated circuit according to claim 1, wherein adjacent horizontal arrays are misaligned by a half distance.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/745241 | 2000-12-21 | ||
US09/745,241 US6552438B2 (en) | 1998-06-24 | 2000-12-21 | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002208610A true JP2002208610A (en) | 2002-07-26 |
JP3952260B2 JP3952260B2 (en) | 2007-08-01 |
Family
ID=24995845
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001339918A Expired - Fee Related JP3952260B2 (en) | 2000-12-21 | 2001-11-05 | Bonding pads for integrated circuits |
Country Status (3)
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---|---|
JP (1) | JP3952260B2 (en) |
KR (1) | KR100421043B1 (en) |
TW (1) | TW510015B (en) |
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JP2005123587A (en) * | 2003-09-26 | 2005-05-12 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
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JPH06196526A (en) * | 1992-12-25 | 1994-07-15 | Toyota Motor Corp | Manufacture of semiconductor device |
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KR100319896B1 (en) * | 1998-12-28 | 2002-01-10 | 윤종용 | Bonding pad structure of semiconductor device and fabrication method thereof |
KR20000009043A (en) * | 1998-07-21 | 2000-02-15 | 윤종용 | Semiconductor device having a multi-layer pad and manufacturing method thereof |
-
2001
- 2001-06-22 KR KR10-2001-0035764A patent/KR100421043B1/en not_active IP Right Cessation
- 2001-10-02 TW TW090124229A patent/TW510015B/en not_active IP Right Cessation
- 2001-11-05 JP JP2001339918A patent/JP3952260B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
JP3952260B2 (en) | 2007-08-01 |
TW510015B (en) | 2002-11-11 |
KR20020051816A (en) | 2002-06-29 |
KR100421043B1 (en) | 2004-03-04 |
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