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JP2002299102A - Chip resistor - Google Patents

Chip resistor

Info

Publication number
JP2002299102A
JP2002299102A JP2001095241A JP2001095241A JP2002299102A JP 2002299102 A JP2002299102 A JP 2002299102A JP 2001095241 A JP2001095241 A JP 2001095241A JP 2001095241 A JP2001095241 A JP 2001095241A JP 2002299102 A JP2002299102 A JP 2002299102A
Authority
JP
Japan
Prior art keywords
resistor
electrode
protective film
chip resistor
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001095241A
Other languages
Japanese (ja)
Inventor
Jun Kinoshita
順 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koa Corp
Original Assignee
Koa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koa Corp filed Critical Koa Corp
Priority to JP2001095241A priority Critical patent/JP2002299102A/en
Publication of JP2002299102A publication Critical patent/JP2002299102A/en
Withdrawn legal-status Critical Current

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  • Details Of Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a chip resistor that is not mounted defectively, even if the resistor is mounted in bulk, and can obtain good characteristics as a resistor. SOLUTION: This chip resistor is provided with a glass layer 31 baked at a high temperature on the surface of an insulating substrate 11, a pair of projecting sections 33 and 33 separately arranged on the layer 31, and a pair of electrodes 13 and 13 arranged on the sections 33 and 33. The resistor is also provided with a resistor 15 connected to the electrodes 13 and 13 and is arranged between the projecting sections 33 and 33, protective films 17 and 19 covering the resistor 15 and arranged between the sections 33 and 33, and plated electrodes 23 and 23, arranged at least on the electrodes 13 and 13. The surfaces of the plated electrodes 23 and 23 are made higher than those of the protective films 17 and 19.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップ抵抗器に係
り、特に多数のチップ部品を収納したバルクカセットか
ら該チップ部品を回路基板に実装する、いわゆるバルク
実装に好適なチップ抵抗器に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip resistor, and more particularly to a chip resistor suitable for so-called bulk mounting, in which a chip cassette is mounted on a circuit board from a bulk cassette containing a large number of chip components. is there.

【0002】[0002]

【従来の技術】図4(a)は従来の厚膜チップ抵抗器の
構造例を示す。従来のチップ抵抗器は、アルミナ等の絶
縁性基板11の表面両端部に厚膜電極13,13を備
え、この電極間に厚膜抵抗体15が配置されている。抵
抗体15はガラス絶縁膜17および樹脂保護膜19によ
り被覆され保護されている。絶縁性基板11の両端部で
ある表面の電極13と裏面の電極21の上面および側端
面にはめっき電極23,23が形成されている。
2. Description of the Related Art FIG. 4A shows an example of the structure of a conventional thick film chip resistor. The conventional chip resistor includes thick film electrodes 13 at both ends of an insulating substrate 11 made of alumina or the like, and a thick film resistor 15 is arranged between the electrodes. The resistor 15 is covered and protected by the glass insulating film 17 and the resin protective film 19. Plating electrodes 23 are formed on the upper surface and side end surfaces of the front electrode 13 and the rear electrode 21 which are both ends of the insulating substrate 11.

【0003】この場合、基板中央部の保護膜19の部分
の高さが電極部23の高さよりも高くなる。絶縁性基板
11の表面側のめっき電極23と保護膜19のそれぞれ
の表面の段差が30−50μm程度発生している場合が
多い。
In this case, the height of the protective film 19 at the center of the substrate is higher than the height of the electrode portion 23. In many cases, a step on the surface of the plating electrode 23 on the surface side of the insulating substrate 11 and the surface of the protective film 19 are generated at about 30-50 μm.

【0004】ところで、従来のチップ抵抗器は、工場出
荷の際にテープに1個ずつ、抵抗体が存在する面を表面
として固定するいわゆるテーピングによる荷姿で出荷さ
れる場合が多い。そして、回路基板に実装する際には、
そのままの状態で、即ち、保護膜が存在する面を表面と
して実装機(マウンタ)により回路基板に固定されてい
た。この場合には、図4(b)に示すように回路基板2
5のランド部27に絶縁性基板11の裏面側の電極2
3,23の裏面側が密着し、はんだリフロー等による固
定が行われる。
[0004] By the way, conventional chip resistors are often shipped one by one on a tape at the time of shipment from the factory in a so-called taping package in which the surface on which the resistor exists is fixed as the surface. And when mounting on a circuit board,
It was fixed to the circuit board by a mounting machine (mounter) as it was, that is, with the surface on which the protective film is present as the surface. In this case, as shown in FIG.
The electrode 2 on the back surface side of the insulating substrate 11 is
The back surfaces of the substrates 3 and 23 are in close contact with each other, and are fixed by solder reflow or the like.

【0005】しかしながら、実装方法にはバルクカセッ
トに多数のチップ部品をそのままの状態で収容し、この
チップ部品を一個ずつバルクカセットから取り出して回
路基板に実装する、バルク実装機によるバルク実装が存
在する。図4に示す従来のチップ抵抗器をバルク実装機
にてバルク実装した場合に、図4(c)に示すように、
チップ抵抗器の表面側(保護膜側)が回路基板25に接
するように逆向きに実装される場合が50%程度の確率
で発生する。この時、チップ抵抗器が傾いて実装される
可能性が強く、最悪の場合、片側のはんだ付けができな
い、または、チップ立等の現象が発生するという問題が
ある。従って、従来のチップ抵抗器は、いわゆるバルク
実装には対応できないという問題がある。
However, as a mounting method, there is a bulk mounting using a bulk mounting machine in which a large number of chip components are stored in a bulk cassette as they are, and the chip components are taken out of the bulk cassette one by one and mounted on a circuit board. . When the conventional chip resistor shown in FIG. 4 is bulk-mounted by a bulk mounting machine, as shown in FIG.
A case where the chip resistor is mounted in the opposite direction so that the surface side (protective film side) of the chip resistor is in contact with the circuit board 25 occurs with a probability of about 50%. At this time, there is a strong possibility that the chip resistor is mounted inclined, and in the worst case, there is a problem that one side cannot be soldered or a phenomenon such as chip standing occurs. Therefore, there is a problem that the conventional chip resistor cannot cope with so-called bulk mounting.

【0006】[0006]

【発明が解決しようとする課題】本発明は上述した事情
に鑑みて為されたもので、バルク実装に際しても実装不
良が生ぜず、且つ良好な抵抗器としての特性が得られる
チップ抵抗器を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a chip resistor which does not cause mounting failure even in bulk mounting and has good characteristics as a resistor. The purpose is to do.

【0007】[0007]

【課題を解決するための手段】このような従来技術にお
ける問題点を解決するために、本発明の一態様は、絶縁
性基板の表面に高温で焼成されたガラス層を備え、該ガ
ラス層に互いに離隔して配置された一対の凸状部と、該
凸状部上に配置された一対の電極と、該電極に接続され
て前記一対の凸状部間に配置された抵抗体と、該抵抗体
を被覆する前記一対の凸状部間に配置された保護膜と、
少なくとも前記一対の電極上に配置されためっき電極と
を備え、該めっき電極の表面の高さが前記保護膜の表面
の高さよりも高いことを特徴とするチップ抵抗器であ
る。
In order to solve the problems in the prior art, one embodiment of the present invention includes a glass layer fired at a high temperature on a surface of an insulating substrate, and the glass layer is provided with a glass layer. A pair of convex portions disposed apart from each other, a pair of electrodes disposed on the convex portions, a resistor connected to the electrodes and disposed between the pair of convex portions, A protective film disposed between the pair of convex portions covering the resistor,
A chip electrode comprising at least a plated electrode disposed on the pair of electrodes, wherein the height of the surface of the plated electrode is higher than the height of the surface of the protective film.

【0008】前記絶縁性基板の裏面には裏面電極が配置
され、側端面には端面電極が配置されていることが好ま
しく、前記凸状部は、高温で焼成されたガラス層である
ことが好ましい。
It is preferable that a back surface electrode is disposed on a back surface of the insulating substrate and an end surface electrode is disposed on a side end surface, and the convex portion is a glass layer fired at a high temperature. .

【0009】また、本発明のチップ抵抗器の製造方法
は、絶縁性基板の表面にガラス層を高温で焼成して形成
し、前記ガラス層上に一対の凸状部を形成し、該凸状部
上と前記絶縁性基板の裏面に電極を配置し、該凸状部間
の凹部に抵抗体を前記電極と接続して配置し、前記抵抗
体を被覆する保護膜を前記凸状部間の凹部に形成し、前
記基板両端部にめっきによりめっき電極を前記保護膜の
高さよりも高く形成することを特徴とするものである。
Further, according to a method of manufacturing a chip resistor of the present invention, a glass layer is formed on a surface of an insulating substrate by firing at a high temperature, and a pair of convex portions are formed on the glass layer. An electrode is arranged on the upper portion and the back surface of the insulating substrate, a resistor is connected to the electrode in a concave portion between the convex portions, and a protective film covering the resistor is provided between the convex portions. It is characterized in that it is formed in a concave portion, and plating electrodes are formed on both ends of the substrate by plating so as to be higher than the height of the protective film.

【0010】上述した本発明のチップ抵抗器によれば、
あらかじめ絶縁性基板表面に凸状部を設けて嵩上げを行
っておくことにより、めっき電極を保護膜の高さよりも
高く形成し、保護膜面においてもスタンドオフを確保す
ることができる。従って、バルク実装対応の実装機を用
いて実装を行っても、100%の確率でチップ抵抗器の
回路基板への実装が可能となる。また、あらかじめ絶縁
性基板表面へ絶縁層を形成しておくことにより、基板表
面の平滑性が確保され、基板表面の凹凸の影響による特
性バラツキを非常に小さくすることが可能となる。従っ
て、高精度なチップ抵抗器を歩留まり良く生産すること
ができる。
According to the above-described chip resistor of the present invention,
By providing a convex portion on the surface of the insulating substrate in advance and raising the height, the plating electrode can be formed higher than the height of the protective film, and the stand-off can be secured also on the protective film surface. Therefore, even if mounting is performed using a mounting machine that supports bulk mounting, the chip resistor can be mounted on the circuit board with a 100% probability. In addition, by forming an insulating layer on the surface of the insulating substrate in advance, the smoothness of the substrate surface is ensured, and the variation in characteristics due to the influence of unevenness on the substrate surface can be extremely reduced. Therefore, highly accurate chip resistors can be produced with high yield.

【0011】絶縁性基板表面に凸状部を設けて嵩上げを
行っておくことにより、めっき電極を保護膜の高さより
も高く形成することができるので、はんだフィレットを
設けないいわゆるフィレットレス実装にも対応が可能で
ある。
By providing a raised portion on the surface of the insulating substrate and raising the height, the plated electrode can be formed higher than the height of the protective film. Response is possible.

【0012】[0012]

【発明の実施の形態】以下、本発明に係るチップ抵抗器
の実施形態について図1乃至図3を参照して詳細に説明
する。図1は、本発明の実施形態におけるチップ抵抗器
の全体構成を示す図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a chip resistor according to the present invention will be described below in detail with reference to FIGS. FIG. 1 is a diagram illustrating an overall configuration of a chip resistor according to an embodiment of the present invention.

【0013】このチップ抵抗器は、アルミナ等の絶縁性
基板11の表面に高温の焼成により形成された均一な厚
さのガラス層31を備え、更に絶縁性基板の両端部に配
置された一対の同様に高温の焼成により形成されたガラ
ス層からなる凸状部33を備えている。ガラス層31,
33の焼成温度は1000〜1300℃程度が好適であ
る。ここで、ガラス層31は、厚さ1−5μm程度に形
成することが好ましく、凸状部33は厚さ20−50μ
m程度に形成することが好ましい。
This chip resistor is provided with a glass layer 31 of uniform thickness formed on a surface of an insulating substrate 11 made of alumina or the like by firing at a high temperature, and furthermore, a pair of glass layers disposed at both ends of the insulating substrate. Similarly, a projection 33 made of a glass layer formed by firing at a high temperature is provided. Glass layer 31,
The firing temperature of 33 is preferably about 1000 to 1300 ° C. Here, the glass layer 31 is preferably formed to have a thickness of about 1-5 μm, and the convex portion 33 is formed to have a thickness of 20-50 μm.
Preferably, it is formed to about m.

【0014】凸状部33,33上には電極13,13が
配置され、電極13,13間に抵抗体15が配置されて
いる。抵抗体15は酸化ルテニウム等の厚膜ペーストの
スクリーン印刷および焼成により形成され、厚さ10−
15μm程度に形成することが好ましい。抵抗体15は
一対の凸状部33,33間の凹部に配置され、電極1
3,13に接続されている。
The electrodes 13, 13 are arranged on the convex portions 33, 33, and the resistor 15 is arranged between the electrodes 13, 13. The resistor 15 is formed by screen printing and baking of a thick film paste such as ruthenium oxide and has a thickness of 10−
Preferably, it is formed to a thickness of about 15 μm. The resistor 15 is disposed in a concave portion between the pair of convex portions 33, 33, and the electrode 1
3, 13 are connected.

【0015】抵抗体15はガラス絶縁膜17および樹脂
保護膜19により被覆され保護されている。ガラス絶縁
膜17および樹脂保護膜19は一対の凸状部33,33
間の凹部に配置されている。ガラス絶縁膜17は厚さ1
5−20μm程度に形成することが好ましく、樹脂保護
膜19は厚さ20μm程度に形成することが好ましい。
The resistor 15 is covered and protected by a glass insulating film 17 and a resin protective film 19. The glass insulating film 17 and the resin protective film 19 are formed of a pair of convex portions 33, 33.
It is arranged in a concave portion between them. The glass insulating film 17 has a thickness of 1
The thickness is preferably about 5 to 20 μm, and the thickness of the resin protective film 19 is preferably about 20 μm.

【0016】絶縁性基板11の側端面にはニッケルクロ
ム(Ni−Cr)のスパッタリング等により形成された
端面電極が形成されている。基板表面側の電極13およ
び裏面側の電極21、さらに基板側端面の端面電極には
めっきにより形成されためっき電極23が配置されてい
る。めっき電極23はニッケルめっき層およびはんだま
たはスズめっき層により構成されている。ニッケルめっ
き層は厚さ3−10μm程度に形成することが好まし
く、はんだまたはスズめっき層は厚さ5−15μm程度
に形成することが好ましい。
On the side end surface of the insulating substrate 11, an end surface electrode formed by sputtering of nickel chromium (Ni-Cr) or the like is formed. A plating electrode 23 formed by plating is arranged on the electrode 13 on the front surface side of the substrate, the electrode 21 on the rear surface side, and the end surface electrode on the end surface on the substrate side. The plating electrode 23 is composed of a nickel plating layer and a solder or tin plating layer. The nickel plating layer is preferably formed to a thickness of about 3-10 μm, and the solder or tin plating layer is preferably formed to a thickness of about 5-15 μm.

【0017】従って、めっき電極23,23は一対の凸
状部33,33により嵩上げされ、その間の凹部に保護
膜17,19が配置された構造が得られる。即ち、めっ
き電極23の表面の高さが前記保護膜19の表面の高さ
よりも高くなっている。図2はこのチップ抵抗器を回路
基板に実装した状態を示し、(a)はチップ抵抗器の保
護膜側が上側に向いて実装され、(b)はチップ抵抗器
の保護膜側が回路基板に向いて(逆向きに)実装された
状態をそれぞれ示している。
Accordingly, a structure is obtained in which the plating electrodes 23, 23 are raised by the pair of convex portions 33, 33, and the protective films 17, 19 are disposed in the concave portions therebetween. That is, the height of the surface of the plating electrode 23 is higher than the height of the surface of the protective film 19. 2A and 2B show a state in which the chip resistor is mounted on a circuit board. FIG. 2A shows a state where the protective film side of the chip resistor faces upward, and FIG. 2B shows a state where the protective film side of the chip resistor faces the circuit board. Respectively (in the opposite direction).

【0018】上述した構造を持ったチップ抵抗器は、チ
ップ抵抗器の保護膜19の表面より突出した電極23が
形成されているため、図2(b)に示すようにチップ抵
抗器が逆向きに実装されてもチップ抵抗器の傾きを抑え
ることができ、これにより確実に回路基板に実装され
る。このため、バルク実装機によるバルクカセットから
の実装を行い、チップ抵抗器の表側(保護膜側)が回路
基板に面するように(逆向きに)実装されても、問題無
くはんだ付けによる固定が可能である。
In the chip resistor having the above-described structure, since the electrode 23 protruding from the surface of the protective film 19 of the chip resistor is formed, the chip resistor is turned upside down as shown in FIG. Even if the chip resistor is mounted, the inclination of the chip resistor can be suppressed, whereby the chip resistor can be reliably mounted on the circuit board. For this reason, even if the chip resistor is mounted from the bulk cassette by the bulk mounting machine and mounted so that the front side (protective film side) of the chip resistor faces the circuit board (in the opposite direction), the chip resistor can be fixed by soldering without any problem. It is possible.

【0019】また、あらかじめ絶縁性基板11の表面へ
絶縁層(ガラスコート)31が形成されており、基板表
面の平滑性が向上している。これにより、基板表面の凹
凸から発生する抵抗値のバラツキ、抵抗温度係数(TC
R)のバラツキを非常に小さくすることが可能となる。
また、このガラス層31の存在により抵抗体15の密着
性が向上し、製品の電気的特性の精度および信頼性が向
上する。
Further, an insulating layer (glass coat) 31 is formed on the surface of the insulating substrate 11 in advance, so that the smoothness of the substrate surface is improved. As a result, variations in the resistance value caused by unevenness on the substrate surface and the temperature coefficient of resistance (TC
R) can be made very small.
In addition, the presence of the glass layer 31 improves the adhesion of the resistor 15 and improves the accuracy and reliability of the electrical characteristics of the product.

【0020】次に、本発明のチップ抵抗器の製造方法に
ついて、図3を参照しながら説明する。まず、(a)に
示すように、アルミナ等の絶縁性基板11を準備する。
図示の例では1個のチップ領域を示すが、実際には多数
のチップ抵抗器を一括して製造する多数個取りの基板が
用いられる。
Next, a method of manufacturing a chip resistor according to the present invention will be described with reference to FIG. First, as shown in (a), an insulating substrate 11 of alumina or the like is prepared.
Although one chip area is shown in the illustrated example, a multi-chip substrate for manufacturing a large number of chip resistors at once is used.

【0021】次に、(b)に示すように、絶縁性基板1
1上に絶縁層(ガラス層)31をスクリーン印刷および
焼成にて形成する。この時のガラス層の焼成は、100
0℃〜1300℃程度の高温で行う。このガラス層31
は、上下層との密着性の向上、およびその上に形成され
る抵抗体に対して平滑面を提供するという点で重要な役
割を果たしている。そして、絶縁層31上に基板両端部
に1対の凸状部パターンをスクリーン印刷にて形成し、
焼成を行うことで凸状部33を形成する。この凸状部3
3も、ガラス層であり、1000℃〜1300℃の高温
で焼成して形成することが好ましい。この凸状部33
も、その上に形成される電極を嵩上げするという点で重
要な役割を果たしている。
Next, as shown in FIG.
An insulating layer (glass layer) 31 is formed on screen 1 by screen printing and firing. The firing of the glass layer at this time is 100
This is performed at a high temperature of about 0 ° C. to 1300 ° C. This glass layer 31
Plays an important role in improving the adhesion between the upper and lower layers and providing a smooth surface to the resistor formed thereon. Then, a pair of convex patterns are formed on both sides of the substrate by screen printing on the insulating layer 31,
The protruding portion 33 is formed by baking. This convex part 3
Reference numeral 3 also denotes a glass layer, which is preferably formed by firing at a high temperature of 1000C to 1300C. This convex portion 33
Also play an important role in raising the electrodes formed thereon.

【0022】次に、(c)に示すように、凸状部33上
に電極13を形成する。この電極13はAg又はAg−
Pdペーストパターンをスクリーン印刷により形成し、
例えば850℃程度の温度で焼成することで形成する。
この電極13は一対の凸状部間に形成された凹部に回り
込ませる様に形成する。裏面電極21も同様にAg又は
Ag−Pdペーストパターンをスクリーン印刷により配
置し、焼成することで形成する。表面側の電極13と裏
面側の電極21とは、どちらを先に形成してもよい。
Next, as shown in FIG. 3C, the electrode 13 is formed on the convex portion 33. This electrode 13 is made of Ag or Ag-
Forming a Pd paste pattern by screen printing,
For example, it is formed by firing at a temperature of about 850 ° C.
The electrode 13 is formed so as to extend around a concave portion formed between a pair of convex portions. Similarly, the back electrode 21 is formed by arranging an Ag or Ag-Pd paste pattern by screen printing and firing. Either the front-side electrode 13 or the rear-side electrode 21 may be formed first.

【0023】次に、(d)に示すように、電極13,1
3間に抵抗体15をスクリーン印刷および焼成にて形成
する。抵抗体としては酸化ルテニウム等を用いることが
好ましく、例えば850℃程度の温度で焼成する。抵抗
体15は一対の凸状部間に形成された凹部に形成する。
抵抗体15には必要に応じてレーザートミリングを行
い、抵抗値を調整する。
Next, as shown in FIG.
The resistor 15 is formed between the three by screen printing and firing. As the resistor, it is preferable to use ruthenium oxide or the like. For example, firing is performed at a temperature of about 850 ° C. The resistor 15 is formed in a concave portion formed between a pair of convex portions.
Laser resistance is applied to the resistor 15 as necessary to adjust the resistance value.

【0024】次に、(e)に示すように、スクリーン印
刷にて抵抗体パターン15上へ第1保護層パターンを形
成して焼成する。第1保護層17はガラス層であり、6
00℃程度の温度で焼成することが好ましい。次に、ス
クリーン印刷および加温硬化にて、第2保護層19を形
成する。第2保護層19はエポキシ系樹脂であり、20
0℃程度の温度で加温硬化することが好ましい。第1保
護層17および第2保護層19は一対の凸状部33,3
3間に形成された凹部に配置する。
Next, as shown in (e), a first protective layer pattern is formed on the resistor pattern 15 by screen printing, and baked. The first protective layer 17 is a glass layer,
It is preferable to fire at a temperature of about 00 ° C. Next, the second protective layer 19 is formed by screen printing and heat curing. The second protective layer 19 is an epoxy resin,
It is preferable to heat and cure at a temperature of about 0 ° C. The first protective layer 17 and the second protective layer 19 are formed of a pair of convex portions 33 and 3.
It is arranged in a recess formed between the three.

【0025】以上の処理は多数個取りの基板の一括処理
であるが、次に短冊状に分割する加工を行う。加工はダ
イシング、またはブレークのどちらでも良い。次に基板
側端面に端面電極を形成する。端面電極は例えばスパッ
タリングによりNi・Cr層を形成する。そして、チッ
プ単体に分割する加工を行う。加工はダイシング、ブレ
ークどちらでも良い。次に、(f)に示すように、電解
メッキを行いめっき電極23,23を形成する。電極く
われ防止およびはんだ付けの信頼性向上のために、電解
めっきによってNiめっき層とSn−Pbめっき層(S
nめっき層でもよい)とからなるめっき電極23を形成
している。
The above process is a batch process of a multi-piece substrate, and then a process of dividing into strips is performed. The processing may be either dicing or break. Next, an end face electrode is formed on the end face on the substrate side. The end electrode forms a Ni / Cr layer by, for example, sputtering. Then, a process of dividing into single chips is performed. Processing may be dicing or break. Next, as shown in (f), electrolytic plating is performed to form plated electrodes 23,23. To prevent electrode cracking and improve the reliability of soldering, Ni plating layer and Sn-Pb plating layer (S
(a n-plated layer may be used).

【0026】これにより、絶縁性基板の両端部の電極が
嵩上げされ、中央の保護膜の部分にスタンドオフが生じ
る、バルク実装に好適なチップ抵抗器が完成する。この
チップ抵抗器は、バルク実装に好適であるばかりでな
く、絶縁性基板の表面に高温で焼成されたガラス層を備
えるので、この平滑面の影響で良好な電気的特性が得ら
れる。
As a result, the electrodes at both ends of the insulating substrate are raised, and a stand-off is generated at the central protective film, thereby completing a chip resistor suitable for bulk mounting. This chip resistor is not only suitable for bulk mounting, but also has a glass layer fired at a high temperature on the surface of the insulating substrate, so that good electrical characteristics can be obtained due to the effect of the smooth surface.

【0027】なお、上記実施形態においては、絶縁性基
板の表面および裏面に電極を設け、チップ抵抗器が表向
きにも逆向きにも実装可能な例について説明したが、表
面のみに電極を設け、逆向きに実装するいわゆるフィレ
ットレス実装にも適用が可能である。即ち、あらかじめ
絶縁性基板表面に凸状部を設けて嵩上げを行っておくこ
とにより、めっき電極を保護膜の高さよりも高く形成
し、保護膜面においてもスタンドオフを確保することが
できる。
In the above embodiment, an example has been described in which electrodes are provided on the front and back surfaces of the insulating substrate, and the chip resistor can be mounted face up or reverse. It is also applicable to so-called filletless mounting in which mounting is performed in the opposite direction. That is, by providing a convex portion on the surface of the insulating substrate and raising the height in advance, the plating electrode can be formed to be higher than the height of the protective film, and the stand-off can be secured also on the protective film surface.

【0028】これまで本発明の一実施形態について説明
したが、本発明は上述の実施形態に限定されず、その技
術的思想の範囲内において種々異なる形態にて実施され
てよいことは言うまでもない。
Although one embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention may be embodied in various forms within the scope of the technical idea.

【0029】[0029]

【発明の効果】上述したように、本発明によれば、チッ
プ抵抗器の保護膜の表面より嵩上げされた電極が形成さ
れていることにより、チップ抵抗器が裏向きに実装され
た場合でも確実にプリント基板へのはんだ付けが可能と
なる。これにより、バルク実装に好適なチップ抵抗器を
提供することができる。また、あらかじめ基板表面へ表
面平滑性を目的とした絶縁層(ガラス層)を形成してお
くことにより、従来、基板表面の凹凸に影響されていた
特性のバラツキを小さく抑え、また、基板絶縁層・抵抗
体層の密着性が向上することにより、信頼性の高い高精
度な抵抗器を提供することができる。
As described above, according to the present invention, since the electrode raised above the surface of the protective film of the chip resistor is formed, even if the chip resistor is mounted face down, it is ensured. This allows soldering to a printed circuit board. Thereby, a chip resistor suitable for bulk mounting can be provided. In addition, by forming an insulating layer (glass layer) for the purpose of surface smoothness on the substrate surface in advance, variations in characteristics conventionally affected by unevenness of the substrate surface can be suppressed to a small level. -By improving the adhesion of the resistor layer, a highly reliable and highly accurate resistor can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態におけるチップ抵抗器の全体
構成を示す断面図である。
FIG. 1 is a cross-sectional view illustrating an overall configuration of a chip resistor according to an embodiment of the present invention.

【図2】上記チップ抵抗器の実装状態を示す図であり、
(a)はチップ抵抗器の保護膜側が上側に向いて実装さ
れ、(b)は保護膜側が回路基板に向いて裏向きに実装
された状態をそれぞれ示している。
FIG. 2 is a diagram showing a mounting state of the chip resistor.
(A) shows a state in which the chip resistor is mounted with the protective film side facing upward, and (b) shows a state in which the protective film is mounted face down with the protective film side facing the circuit board.

【図3】上記チップ抵抗器の製造工程を示す図である。FIG. 3 is a view showing a manufacturing process of the chip resistor.

【図4】従来のチップ抵抗器について、(a)は全体構
成を示す断面図であり、(b)は保護膜側が表面側に向
いて実装され、(c)は保護膜側が回路基板に向いて実
装された状態をそれぞれ示している図である。
4A is a cross-sectional view showing the entire configuration of a conventional chip resistor, FIG. 4B is mounted with the protective film side facing the front side, and FIG. 4C is mounted with the protective film side facing the circuit board; It is a figure which shows the state respectively mounted.

【符号の説明】[Explanation of symbols]

11 絶縁性基板 13,21 電極 15 抵抗体 17,19 保護膜 23 めっき電極 31 ガラス層 33 凸状部(ガラス層) DESCRIPTION OF SYMBOLS 11 Insulating substrate 13, 21 Electrode 15 Resistor 17, 19 Protective film 23 Plating electrode 31 Glass layer 33 Convex part (glass layer)

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E028 BA11 BB01 CA02 EA01 EB05 JC03 JC05 JC12 5E032 BA15 BB01 CA02 CC14 CC16 TB02 5E033 AA03 BC01 BD01 BE02 BE04 BH02  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E028 BA11 BB01 CA02 EA01 EB05 JC03 JC05 JC12 5E032 BA15 BB01 CA02 CC14 CC16 TB02 5E033 AA03 BC01 BD01 BE02 BE04 BH02

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板の表面に高温で焼成されたガ
ラス層を備え、該ガラス層に互いに離隔して配置された
一対の凸状部と、該凸状部上に配置された一対の電極
と、該電極に接続されて前記一対の凸状部間に配置され
た抵抗体と、該抵抗体を被覆する前記一対の凸状部間に
配置された保護膜と、少なくとも前記一対の電極上に配
置されためっき電極とを備え、該めっき電極の表面の高
さが前記保護膜の表面の高さよりも高いことを特徴とす
るチップ抵抗器。
An insulating substrate includes a glass layer fired at a high temperature on a surface thereof, a pair of convex portions arranged on the glass layer so as to be separated from each other, and a pair of convex portions disposed on the convex portion. An electrode, a resistor connected to the electrode and disposed between the pair of protrusions, a protective film disposed between the pair of protrusions covering the resistor, and at least the pair of electrodes; And a plating electrode disposed thereon, wherein the height of the surface of the plating electrode is higher than the height of the surface of the protective film.
【請求項2】 前記絶縁性基板の裏面には裏面電極が配
置され、側端面には端面電極が配置されていることを特
徴とする請求項1記載のチップ抵抗器。
2. The chip resistor according to claim 1, wherein a back surface electrode is arranged on a back surface of the insulating substrate, and an end surface electrode is arranged on a side end surface.
【請求項3】 前記凸状部は、高温で焼成されたガラス
層であることを特徴とする請求項1記載のチップ抵抗
器。
3. The chip resistor according to claim 1, wherein the convex portion is a glass layer fired at a high temperature.
【請求項4】 絶縁性基板の表面にガラス層を高温で焼
成して形成し、前記ガラス層上に一対の凸状部を形成
し、該凸状部上と前記絶縁性基板の裏面に電極を配置
し、該凸状部間の凹部に抵抗体を前記電極と接続して配
置し、前記抵抗体を被覆する保護膜を前記凸状部間の凹
部に形成し、前記基板両端部にめっきによりめっき電極
を前記保護膜の高さよりも高く形成することを特徴とす
るチップ抵抗器の製造方法。
4. A glass layer is formed on the surface of the insulating substrate by firing at a high temperature, a pair of convex portions are formed on the glass layer, and electrodes are provided on the convex portions and on the back surface of the insulating substrate. And a resistor is connected to the electrode in the concave portion between the convex portions, and a protective film covering the resistor is formed in the concave portion between the convex portions, and plating is performed on both ends of the substrate. Forming a plated electrode higher than the height of the protective film.
JP2001095241A 2001-03-29 2001-03-29 Chip resistor Withdrawn JP2002299102A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001095241A JP2002299102A (en) 2001-03-29 2001-03-29 Chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001095241A JP2002299102A (en) 2001-03-29 2001-03-29 Chip resistor

Publications (1)

Publication Number Publication Date
JP2002299102A true JP2002299102A (en) 2002-10-11

Family

ID=18949317

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002299102A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313602A (en) * 2001-04-10 2002-10-25 Koa Corp Chip resistor and method of manufacturing the same
JP2008251751A (en) * 2007-03-29 2008-10-16 Tdk Corp Electronic component, and manufacturing method thereof
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226107A (en) * 1992-02-13 1993-09-03 Rohm Co Ltd Chip resistor
JPH08138903A (en) * 1994-11-08 1996-05-31 Hokuriku Electric Ind Co Ltd Chip electronic part
JPH09320803A (en) * 1996-05-29 1997-12-12 Matsushita Electric Ind Co Ltd Resistor
JPH10173083A (en) * 1996-12-05 1998-06-26 Ngk Spark Plug Co Ltd Wiring board for mounting electronic component and its manufacturing method
JPH11168003A (en) * 1997-12-04 1999-06-22 Taiyo Yuden Co Ltd Chip component and manufacture thereof
JPH11176603A (en) * 1997-12-05 1999-07-02 Rohm Co Ltd Chip resistor
JP2000188204A (en) * 1998-12-21 2000-07-04 Matsushita Electric Ind Co Ltd Resistor and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05226107A (en) * 1992-02-13 1993-09-03 Rohm Co Ltd Chip resistor
JPH08138903A (en) * 1994-11-08 1996-05-31 Hokuriku Electric Ind Co Ltd Chip electronic part
JPH09320803A (en) * 1996-05-29 1997-12-12 Matsushita Electric Ind Co Ltd Resistor
JPH10173083A (en) * 1996-12-05 1998-06-26 Ngk Spark Plug Co Ltd Wiring board for mounting electronic component and its manufacturing method
JPH11168003A (en) * 1997-12-04 1999-06-22 Taiyo Yuden Co Ltd Chip component and manufacture thereof
JPH11176603A (en) * 1997-12-05 1999-07-02 Rohm Co Ltd Chip resistor
JP2000188204A (en) * 1998-12-21 2000-07-04 Matsushita Electric Ind Co Ltd Resistor and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313602A (en) * 2001-04-10 2002-10-25 Koa Corp Chip resistor and method of manufacturing the same
JP2008251751A (en) * 2007-03-29 2008-10-16 Tdk Corp Electronic component, and manufacturing method thereof
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10418157B2 (en) 2015-10-30 2019-09-17 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation

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