JP2002289611A - Manufacturing method and manufacturing apparatus of semiconductor device - Google Patents
Manufacturing method and manufacturing apparatus of semiconductor deviceInfo
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- JP2002289611A JP2002289611A JP2001087920A JP2001087920A JP2002289611A JP 2002289611 A JP2002289611 A JP 2002289611A JP 2001087920 A JP2001087920 A JP 2001087920A JP 2001087920 A JP2001087920 A JP 2001087920A JP 2002289611 A JP2002289611 A JP 2002289611A
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- oxide film
- film
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体基板に絶
縁膜を形成する工程を有する半導体装置の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a step of forming an insulating film on a semiconductor substrate.
【０００２】[0002]
【従来の技術】シリコンを用いた半導体素子、特にＭＩ
ＳＦＥＴの性能は、集積回路技術の進歩により年々向上
している。しかし近年、リソグラフィ技術の微細化の限
界や、シリコンのキャリア移動度の飽和等が指摘されて
おり、ＭＩＳＦＥＴの更なる高性能化には、製造プロセ
スのより精密な制御が求められている。具体的に、ＭＩ
ＳＦＥＴの性能の指標である電子移動度を向上させるた
めに、ゲート絶縁膜とシリコン基板との界面の精密制御
を行う技術が注目されている。ＭＩＳＦＥＴの性能は、
シリコン基板内での不純物散乱の他、界面散乱や界面準
位密度の影響を受けるためである。2. Description of the Related Art A semiconductor device using silicon, especially MI
The performance of SFETs is improving year by year with advances in integrated circuit technology. However, in recent years, the limit of miniaturization of lithography technology, saturation of carrier mobility of silicon, and the like have been pointed out, and more precise control of the manufacturing process is required for further improving the performance of MISFET. Specifically, MI
In order to improve the electron mobility, which is an index of the performance of the SFET, a technique for precisely controlling the interface between the gate insulating film and the silicon substrate has been attracting attention. The performance of MISFET is
This is because, in addition to impurity scattering in the silicon substrate, interface scattering and interface state density are affected.
【０００３】本発明者等も、購入シリコン基板に酸化膜
を形成した場合の酸化膜と基板の界面の粗さ（ラフネ
ス）について種々の検討を行ってきた。図３は、シリコ
ン基板に熱酸化を行った場合の、酸化膜除去後の表面粗
さをＡＦＭにより評価した酸化膜厚依存性を示してい
る。購入シリコン基板の平均表面粗さは通常、２００ｎ
ｍ平方の範囲の二乗平均値（Ｒｍｓ）で０．２ｎｍとい
う保証がされている。以下、この明細書で“平均表面粗
さ”というときは、日本工業規格ＪＩＳ Ｂ０１５３２
に基づいて測定された、２００ｎｍ平方の範囲でのＲｍ
ｓ値で表すものとする。図３は、この様なシリコン基板
について、自然酸化膜を１％ＨＦ溶液で除去した後、９
００℃の大気圧下で熱酸化（ドライ酸化）した場合のデ
ータである。The present inventors have also conducted various studies on the roughness of the interface between an oxide film and a substrate when the oxide film is formed on a purchased silicon substrate. FIG. 3 shows the dependency on the oxide film thickness obtained by AFM evaluation of the surface roughness after removing the oxide film when the silicon substrate is subjected to thermal oxidation. The average surface roughness of the purchased silicon substrate is typically 200n
The mean square value (Rms) in the range of m squares is guaranteed to be 0.2 nm. Hereinafter, in this specification, "average surface roughness" is referred to as Japanese Industrial Standard JIS B01532.
Rm in the range of 200 nm square, measured based on
It is represented by the s value. FIG. 3 shows that after removing a natural oxide film from such a silicon substrate with a 1% HF solution, FIG.
This is data when thermal oxidation (dry oxidation) is performed under the atmospheric pressure of 00 ° C.
【０００４】図３のデータから、平均表面粗さは、およ
そ１０ｎｍの酸化膜が形成されるまでは増加し、それ以
上酸化膜が厚くなると減少する傾向が認められる。現状
のＬＳＩで用いられるＭＩＳＦＥＴでは、ゲート酸化膜
厚はおよそ５ｎｍかそれよりも薄い。従ってドライ酸化
によりこの様なゲート酸化膜を形成すると、基板との界
面の粗さは増加し、ＭＩＳＦＥＴの性能を劣化させるこ
とになる。この様な酸化による界面粗さの増加は、自然
酸化膜除去後、ゲート酸化膜形成直前までの基板保持状
態、或いはその後の酸化膜形成機構のいずれか、或いは
両方に起因する。From the data shown in FIG. 3, it is recognized that the average surface roughness tends to increase until an oxide film of about 10 nm is formed, and to decrease as the oxide film becomes thicker. In MISFETs used in current LSIs, the gate oxide film thickness is about 5 nm or less. Therefore, when such a gate oxide film is formed by dry oxidation, the roughness of the interface with the substrate increases, which degrades the performance of the MISFET. Such an increase in interface roughness due to oxidation is caused by either or both of the substrate holding state after the removal of the natural oxide film and immediately before the formation of the gate oxide film, and / or the subsequent oxide film formation mechanism.
【０００５】通常、ドライ酸化の前処理として、自然酸
化膜の除去と非酸化性雰囲気での基板加熱工程が含まれ
る。自然酸化膜除去は、プロセス開始前の自然酸化膜表
面や内部に含まれる汚染物質の除去と、その後の表面清
浄化が目的である。またその後の基板加熱工程は、ドラ
イ酸化工程の９００℃程度への昇温工程として、酸化速
度の確保及び酸化膜質の向上にとって不可欠である。[0005] Usually, pretreatment for dry oxidation includes a step of removing a natural oxide film and a step of heating the substrate in a non-oxidizing atmosphere. The purpose of the removal of the natural oxide film is to remove contaminants contained in or on the surface of the natural oxide film before starting the process, and to clean the surface thereafter. Further, the subsequent substrate heating step is indispensable for securing the oxidation rate and improving the quality of the oxide film as a temperature raising step to about 900 ° C. in the dry oxidation step.
【０００６】しかし、自然酸化膜除去後、酸素を含む雰
囲気に晒すと局所的な酸化が生じ、当初平坦であった基
板表面が、不均一な酸化膜で覆われて界面粗さの大きい
状態に変化してしまう。一方、ドライ酸化に移行するま
での昇温工程でも、雰囲気中の残留酸素による局所的酸
化が生じるだけでなく、基板温度が６００℃を越える
と、シリコン基板表面からＳｉ原子が脱離する表面エッ
チングが生じる。図３に示すように、ドライ酸化により
界面粗さが増加する現象には、これらの要因が考えられ
る。However, when the substrate is exposed to an atmosphere containing oxygen after the removal of the natural oxide film, local oxidation occurs, and the initially flat substrate surface is covered with a non-uniform oxide film and the interface roughness becomes large. Will change. On the other hand, even in the temperature increasing step before the shift to dry oxidation, not only local oxidation due to residual oxygen in the atmosphere occurs, but also, when the substrate temperature exceeds 600 ° C., surface etching in which Si atoms are desorbed from the silicon substrate surface. Occurs. As shown in FIG. 3, these factors are considered for the phenomenon that the interface roughness increases due to dry oxidation.
【０００７】これに対して、活性酸素を用いて酸化膜を
形成する方法（ラジカル酸化）がある。このラジカル酸
化を９００℃で行った場合について、シリコン基板の平
均表面粗さの酸化膜厚依存性を測定した結果が、図４で
ある。酸化の前処理として自然酸化膜除去を行っている
ことは、先のドライ酸化の場合と同様である。なおこの
結果は、本発明者等により既に公表されている（ＩＳＳ
Ｓ−３，ＰＳ−２−５８，Ｎｏｖ．２９，１９９９）。On the other hand, there is a method of forming an oxide film using active oxygen (radical oxidation). FIG. 4 shows the results of measuring the dependence of the average surface roughness of the silicon substrate on the oxide film thickness when the radical oxidation was performed at 900 ° C. The removal of the natural oxide film as a pretreatment for oxidation is the same as in the case of the dry oxidation. The results have already been published by the present inventors (ISS
S-3, PS-2-58, Nov. 29, 1999).
【０００８】図３の結果と比較して明らかなように、ラ
ジカル酸化を行った場合には、酸化膜厚の増大と共に、
界面粗さは単調に減少している。従って、５ｎｍ程度の
ゲート酸化膜を形成した場合に、ラフネスをより小さく
抑えるためには、ドライ酸化よりもラジカル酸化が好ま
しいことがわかる。As is apparent from the comparison with the results shown in FIG. 3, when radical oxidation is performed, the oxide film thickness increases and
The interface roughness monotonously decreases. Therefore, it is understood that radical oxidation is preferable to dry oxidation in order to suppress roughness when a gate oxide film of about 5 nm is formed.
【０００９】[0009]
【発明が解決しようとする課題】しかし、図３と図４の
データからは、酸化膜厚が１０ｎｍ以上、特に２０ｎｍ
以上になると、熱酸化の場合とラジカル酸化の場合とで
界面粗さに顕著な差が認められるものの、５ｎｍ以下の
微小膜厚では、それほど大きな相違はない。次世代の微
細ＭＩＳＦＥＴの高性能化を考えた場合には、ゲート酸
化膜厚５ｎｍ以下で界面粗さのより小さい状態を実現す
る技術が望まれる。However, the data of FIGS. 3 and 4 show that the oxide film thickness is 10 nm or more, especially 20 nm.
Above, there is a remarkable difference in the interface roughness between the case of thermal oxidation and the case of radical oxidation, but there is not so much difference with a small film thickness of 5 nm or less. In order to improve the performance of next-generation fine MISFETs, a technique for realizing a state in which the gate oxide film thickness is 5 nm or less and the interface roughness is small is desired.
【００１０】この発明は、上記事情を考慮してなされた
もので、界面粗さを小さくできる絶縁膜形成工程を持つ
半導体装置の製造方法及び製造装置を提供することを目
的としている。The present invention has been made in view of the above circumstances, and has as its object to provide a method and an apparatus for manufacturing a semiconductor device having an insulating film forming step capable of reducing interface roughness.
【００１１】[0011]
【課題を解決するための手段】この発明は、半導体基板
に絶縁膜を形成する工程を有する半導体装置の製造方法
において、前記絶縁膜を形成する工程は、半導体基板の
自然酸化膜を除去し且つ、その表面の平均表面粗さを
０．１６ｎｍ以下に低減させる前処理工程と、この前処
理工程を経た前記半導体基板の表面に活性酸素を含む雰
囲気でのラジカル酸化により絶縁膜を形成する成膜工程
とを有することを特徴とする。According to the present invention, in a method of manufacturing a semiconductor device having a step of forming an insulating film on a semiconductor substrate, the step of forming the insulating film includes removing a natural oxide film of the semiconductor substrate; A pre-treatment step of reducing the average surface roughness of the surface to 0.16 nm or less; and a film formation of forming an insulating film on the surface of the semiconductor substrate after the pre-treatment step by radical oxidation in an atmosphere containing active oxygen. And a process.
【００１２】本発明者等の研究によると、酸化膜形成に
際して、予め半導体基板の自然酸化膜を除去すると共に
その表面粗さを低減させる前処理を行うと、その後薄い
酸化膜を形成する場合に酸化膜形成法によって界面粗さ
に明確な差が生じることが明らかになった。即ち、熱酸
化の場合には、前処理において十分に表面粗さを小さい
状態としても、５ｎｍ程度の酸化膜を形成すると界面粗
さの大きな増加が認められるのに対して、ラジカル酸化
では界面粗さの増加はごく小さく抑えられる。つまり、
１０ｎｍ程度以下、更には５ｎｍ以下の酸化膜形成にと
って、前処理とラジカル酸化の組み合わせの優位性が初
めて明らかになった。According to the study of the present inventors, when forming an oxide film, if a pretreatment for removing the natural oxide film of the semiconductor substrate and reducing the surface roughness thereof is performed in advance, a thin oxide film may be formed thereafter. It became clear that the oxide film formation method caused a clear difference in the interface roughness. That is, in the case of thermal oxidation, even if the surface roughness is sufficiently small in the pretreatment, a large increase in the interface roughness is observed when an oxide film of about 5 nm is formed, whereas in the case of radical oxidation, the interface roughness is large. The increase in height is kept very small. That is,
For the formation of an oxide film of about 10 nm or less, and even 5 nm or less, the superiority of the combination of pretreatment and radical oxidation has been clarified for the first time.
【００１３】図１は、この発明の優位性を示す、本発明
者等による実験データを示している。購入時のシリコン
基板の平均表面粗さは、前述のように、０．２ｎｍ程度
が保証されている。これに対して、実験では、予めＣＶ
Ｄによりシリコン層をエピタキシャル成長させること
で、平均表面粗さを０．１５ｎｍ以下にまで平坦化した
試料を用意した。この試料基板に対して更に、自然酸化
膜除去等の前処理を行い、９００℃で熱酸化を行った場
合と、９００℃でラジカル酸化を行った場合の、平均表
面粗さの酸化膜厚依存性を測定した結果が、図１であ
る。FIG. 1 shows experimental data by the present inventors showing the superiority of the present invention. The average surface roughness of the silicon substrate at the time of purchase is guaranteed to be about 0.2 nm as described above. On the other hand, in the experiment, CV
A sample was prepared by flattening the average surface roughness to 0.15 nm or less by epitaxially growing a silicon layer by D. The average surface roughness depends on the thickness of the oxide film when the sample substrate is further subjected to a pretreatment such as removal of a natural oxide film and the like, and thermally oxidized at 900 ° C. and radical oxidized at 900 ° C. FIG. 1 shows the results of measuring the properties.
【００１４】この結果から、酸化膜厚５ｎｍについて見
ると、熱酸化を行った場合には界面粗さが大きく増加し
ているのに対し、ラジカル酸化を行った場合には、僅か
の増加が認められるものの、熱酸化に比べるとごく小さ
い。即ち、５ｎｍの酸化膜形成においてその界面状態に
ついて、平均表面粗さ０．１６ｎｍ以下を実現するに
は、熱酸化は不適当であり、ラジカル酸化でなければな
らないことがわかる。From these results, when the oxide film thickness is 5 nm, the interface roughness is greatly increased when the thermal oxidation is performed, whereas a slight increase is recognized when the radical oxidation is performed. Although it is possible, it is very small compared to thermal oxidation. In other words, it can be understood that thermal oxidation is inappropriate and must be radical oxidation in order to achieve an average surface roughness of 0.16 nm or less in the interface state in forming a 5 nm oxide film.
【００１５】図１のデータは、前処理工程で平均表面粗
さを０．１５ｎｍ以下まで低下させた場合を示している
が、購入当初に保証されている平均表面粗さを少なくと
も０．１６ｎｍ以下まで低減させる前処理工程を入れる
ことによって、その後熱酸化を行った場合とラジカル酸
化を行った場合の表面粗さ変化の相違は、図１のデータ
と同様に顕著に認められている。従ってこの発明は、少
なくとも前処理工程において、平均表面粗さを０．１６
ｎｍ以下にすれば、有効である。The data in FIG. 1 shows the case where the average surface roughness was reduced to 0.15 nm or less in the pretreatment step, but the average surface roughness guaranteed at the time of purchase was reduced to at least 0.16 nm or less. The difference in the change in surface roughness between the case where thermal oxidation is performed and the case where radical oxidation is performed by adding a pretreatment step to reduce the surface roughness is remarkably recognized similarly to the data in FIG. Therefore, according to the present invention, the average surface roughness is set to 0.16 at least in the pretreatment step.
It is effective if it is less than nm.
【００１６】前処理の一環として、半導体基板の表面粗
さを低減するために、実験ではエピタキシャル成長を行
ったが、他の方法として、犠牲酸化膜を形成してこれを
除去する方法、非酸化性雰囲気で高温加熱を行う方法、
溶液処理を行う方法等が有効である。これらの方法によ
って、酸化膜形成前の基板の平均表面粗さを、０．１６
ｎｍ以下にする。その後ラジカル酸化を行うことによっ
て、１０ｎｍ以下の酸化膜厚で、平均表面粗さ０．１６
ｎｍ以下を実現することが可能になる。In order to reduce the surface roughness of the semiconductor substrate, epitaxial growth was performed in an experiment as a part of the pretreatment. However, as another method, a method of forming and removing a sacrificial oxide film, a method of removing non-oxidizing High temperature heating in an atmosphere,
A method of performing a solution treatment or the like is effective. By these methods, the average surface roughness of the substrate before forming the oxide film is reduced to 0.16.
nm or less. Thereafter, radical oxidation is performed to obtain an oxide film thickness of 10 nm or less and an average surface roughness of 0.16.
nm or less can be realized.
【００１７】ラジカル酸化は、４１０℃〜７００℃以下
で行うことが望ましい。即ち４１０℃未満では、実用上
必要な酸化速度が得られない。また７００℃を越えると
昇温工程終了直後から酸化開始直前までの間にラフネス
が増加する可能性がある。The radical oxidation is desirably performed at 410 ° C. to 700 ° C. or lower. That is, if it is lower than 410 ° C., a practically necessary oxidation rate cannot be obtained. On the other hand, when the temperature exceeds 700 ° C., the roughness may increase from immediately after the completion of the temperature raising step to immediately before the start of oxidation.
【００１８】前処理工程を経た後、成膜工程までの間に
も、例えば昇温工程で微量な残留酸素があると、局所的
な酸化により表面粗さを増大させ、また保持雰囲気が適
当でないと基板原子が脱離してやはり表面粗さを増大さ
せる。従って、前処理後、成膜までの間、表面粗さ増加
の要因を作らないことも重要であり、好ましくは、前処
理した半導体基板を成膜工程まで、酸素分圧が１０-2Ｔ
ｏｒｒ以下、より好ましくは１０-3Ｔｏｒｒ以下の非酸
化性雰囲気に保つようにする。Even after the pretreatment step and before the film formation step, for example, if there is a small amount of residual oxygen in the temperature raising step, the surface roughness is increased by local oxidation, and the holding atmosphere is not appropriate. Then, the substrate atoms are desorbed, which also increases the surface roughness. Therefore, it is also important not to cause a factor of surface roughness increase after the pre-treatment until the film formation. Preferably, the oxygen partial pressure of the pre-processed semiconductor substrate is 10 −2 T until the film formation step.
The atmosphere is kept at a non-oxidizing atmosphere of not more than orr, more preferably not more than 10 -3 Torr.
【００１９】[0019]
【発明の実施の形態】以下、この発明の実施の形態を説
明する。図２は、この発明の実施の形態による酸化膜
（ＳｉＯ2膜）形成装置を示している。この装置は、前
処理室１と成膜室２及び、これらの間で基板を搬送する
搬送室３とから構成されている。Embodiments of the present invention will be described below. FIG. 2 shows an oxide film (SiO 2 film) forming apparatus according to an embodiment of the present invention. This apparatus includes a pre-processing chamber 1, a film forming chamber 2, and a transfer chamber 3 for transferring a substrate therebetween.
【００２０】シリコン基板１０は、前処理室１にセット
してまず、自然酸化膜を除去すると共に、平均表面粗さ
が０．１６ｎｍ以下になるような前処理を行う。具体的
に前処理室１は、高純度窒素雰囲気に保たれるように
し、１％希フッ酸（ＨＦ）溶液にシリコン基板１０を１
分浸して自然酸化膜を除去した後、連続して、超純水で
リンスする。超純水は、溶残酸素が１００ｐｐｂ以下の
ものを用いる。また雰囲気は、自然酸化膜除去後のシリ
コン基板１０の表面に再度酸素付着による酸化が生じな
いように、酸素濃度を１ｐｐｍ以下にする。The silicon substrate 10 is set in the pre-processing chamber 1 and, first, a natural oxide film is removed and pre-processing is performed so that the average surface roughness becomes 0.16 nm or less. Specifically, the pretreatment chamber 1 is maintained in a high-purity nitrogen atmosphere, and the silicon substrate 10 is placed in a 1% diluted hydrofluoric acid (HF) solution.
After the natural oxide film is removed by soaking, the substrate is continuously rinsed with ultrapure water. Ultrapure water having a residual oxygen content of 100 ppb or less is used. In addition, the atmosphere is set to have an oxygen concentration of 1 ppm or less so that the surface of the silicon substrate 10 after the removal of the natural oxide film is not oxidized again by the adhesion of oxygen.
【００２１】なお自然酸化膜除去と表面平坦化の方法
は、上述したＨＦ溶液処理の他、超高真空下で６００℃
以上に加熱する方法、気体状のＨＦ雰囲気下或いは不活
性ガス（Ｎ２，Ａｒ，Ｈｅ等）や水素雰囲気下で加熱す
る方法、電子線照射後加熱する方法等を用い得る。また
基板の平坦化は、前処理室１にセットする前に、エピタ
キシャル成長する方法、或いは犠牲酸化膜を形成してこ
れを前処理室１にセットして除去する方法等も用いう
る。基板加熱は、基材載置台１１に設置されたヒータに
より行う。The method of removing the natural oxide film and flattening the surface is performed at 600 ° C. under ultra-high vacuum in addition to the HF solution treatment described above.
A method of heating as described above, a method of heating in a gaseous HF atmosphere or an inert gas (N2, Ar, He, or the like) or hydrogen atmosphere, a method of heating after electron beam irradiation, or the like can be used. For flattening the substrate, a method of epitaxial growth or a method of forming a sacrificial oxide film and setting it in the preprocessing chamber 1 before setting it in the preprocessing chamber 1 may be used. The substrate is heated by a heater installed on the base table 11.
【００２２】前処理が済んだシリコン基板１０は、高純
度窒素雰囲気に保たれた搬送室３を介して、成膜室２に
搬送する。成膜室２においても実際に成膜が開始される
までは高純度窒素雰囲気に保たれることが必要であり、
このため成膜室２には、酸化原料（活性酸素種）を供給
するラインと別に高純度Ｎ２ガス供給ラインが接続され
ている。即ち、酸化開始までは、高純度Ｎ２ガスを成膜
室２に供給し、搬送室３から成膜室２まで、酸素分圧が
１０-2Ｔｏｒｒ以下、より好ましくは、１０-3Ｔｏｒｒ
以下に保つ。これにより、前処理されたシリコン基板１
０の無用な酸化、或いはＳｉ脱離等による表面粗さ増加
が防止される。The pretreated silicon substrate 10 is transferred to the film forming chamber 2 via the transfer chamber 3 maintained in a high-purity nitrogen atmosphere. Even in the film forming chamber 2, it is necessary to maintain the high-purity nitrogen atmosphere until film formation is actually started.
For this reason, a high-purity N2 gas supply line is connected to the film forming chamber 2 separately from a line for supplying an oxidizing raw material (active oxygen species). That is, high-purity N2 gas is supplied to the film forming chamber 2 until the start of oxidation, and the oxygen partial pressure from the transfer chamber 3 to the film forming chamber 2 is 10 −2 Torr or less, more preferably 10 −3 Torr.
Keep below. Thereby, the pre-processed silicon substrate 1
Unnecessary oxidation of 0 or increase in surface roughness due to Si desorption or the like is prevented.
【００２３】成膜室２に搬送されたシリコン基板１０に
対して、供給ガスを切り換えてラジカル酸化を行う。具
体的に、活性酸素種は、周知の方法例えば、ＲＦプラズ
マ、マイクロ波放電、紫外線照射、レーザ照射等により
発生させることができる。活性酸素種としては、励起さ
れた酸素分子、励起された酸素原子（3Ｐ，1Ｄ，1Ｓ状
態）、或いはオゾン（Ｏ3）を用い得る。The silicon substrate 10 transported to the film forming chamber 2 is subjected to radical oxidation by switching the supply gas. Specifically, the active oxygen species can be generated by a known method such as RF plasma, microwave discharge, ultraviolet irradiation, laser irradiation, or the like. As the active oxygen species, excited oxygen molecules, excited oxygen atoms (3 P, 1 D, 1 S state), or may use ozone (O 3).
【００２４】基板載置台２１にはヒータが設けられ、基
板を加熱することにより成膜速度を制御することができ
る。具体的に、ラジカル酸化の工程で表面粗さを増加さ
せないためには、ラジカル酸化の間、基板温度を４１０
℃〜７００℃の範囲で制御することが好ましい。より好
ましくは、６５０℃以下に抑える。A heater is provided on the substrate mounting table 21, and the film formation rate can be controlled by heating the substrate. Specifically, in order not to increase the surface roughness in the radical oxidation step, the substrate temperature is set to 410 ° during the radical oxidation.
It is preferable to control the temperature in the range of from 700C to 700C. More preferably, the temperature is controlled to 650 ° C. or lower.
【００２５】この様な方法によりシリコン酸化膜形成を
行うと、１０ｎｍ或いはそれ以下の酸化膜を形成した場
合に、平均表面粗さを０．１６ｎｍ以下に抑えることが
できる。この方法を微細ＭＩＳＦＥＴのゲート酸化膜形
成に適用すれば、高性能ＭＩＳＦＥＴを得ることができ
る。即ち、極薄ゲート酸化膜を持つＭＩＳＦＥＴでは、
ゲート酸化膜／基板界面の散乱や界面準位等によりキャ
リア移動度が制限されるが、この実施の形態の方法によ
りゲート酸化膜／基板の界面粗さを低減することによっ
て、ＭＩＳＦＥＴの高性能化を図ることができる。When a silicon oxide film is formed by such a method, the average surface roughness can be suppressed to 0.16 nm or less when an oxide film having a thickness of 10 nm or less is formed. If this method is applied to the formation of a gate oxide film of a fine MISFET, a high-performance MISFET can be obtained. That is, in a MISFET having an extremely thin gate oxide film,
The carrier mobility is limited by the scattering of the gate oxide film / substrate interface and the interface level, but the method of this embodiment reduces the gate oxide film / substrate interface roughness, thereby improving the performance of the MISFET. Can be achieved.
【００２６】この発明は、上記実施の形態に限られな
い。実施の形態では、シリコン基板にシリコン酸化膜を
形成する場合を説明したが、他の半導体基板例えば、Ｇ
ａＡｓ，ＳｉＣ，ＧａＮ，ＺｎＳｅ等の化合物半導体基
板に薄い絶縁膜を形成する場合にも有効である。また絶
縁膜として、シリコン酸化膜の他、シリコン窒化膜（Ｓ
ｉxＮy）、シリコン酸窒化膜（ＳｉxＯyＮz）を形成す
る場合、更に、Ｔａ，Ｂａ，Ｔｉ，Ｚｒ，Ｈｆ，Ａｌ，
Ｙ，Ｐｒ，Ｌａのいずれか或いはそれらの組み合わせを
含む金属酸化物膜を形成する場合にも同様にこの発明を
適用することができる。The present invention is not limited to the above embodiment. In the embodiment, the case where the silicon oxide film is formed on the silicon substrate has been described.
This is also effective when a thin insulating film is formed on a compound semiconductor substrate such as aAs, SiC, GaN, ZnSe, or the like. As an insulating film, in addition to a silicon oxide film, a silicon nitride film (S
i x N y), the case of forming a silicon oxynitride film (Si x O y N z) , further, Ta, Ba, Ti, Zr , Hf, Al,
The present invention can be similarly applied to the case of forming a metal oxide film containing any of Y, Pr, and La or a combination thereof.
【００２７】[0027]
【発明の効果】以上述べたようにこの発明によれば、半
導体基板表面の表面粗さを低減させる前処理を行い、活
性種を含む比較的低温の雰囲気で絶縁膜を形成すること
により、界面粗さを抑制した薄い絶縁膜を得ることがで
きる。As described above, according to the present invention, the pretreatment for reducing the surface roughness of the surface of the semiconductor substrate is performed, and the insulating film is formed in a relatively low temperature atmosphere containing active species. A thin insulating film with suppressed roughness can be obtained.
【図１】この発明の原理を説明するための半導体基板の
平均表面粗さの酸化膜厚依存性を示す図である。FIG. 1 is a graph showing the dependence of the average surface roughness of a semiconductor substrate on the thickness of an oxide film for explaining the principle of the present invention.
【図２】この発明の実施の形態による酸化膜形成工程及
び装置を説明するための図である。FIG. 2 is a view for explaining an oxide film forming step and an apparatus according to the embodiment of the present invention.
【図３】シリコン基板の熱酸化による平均表面粗さの酸
化膜厚依存性を示す図である。FIG. 3 is a diagram showing the dependence of the average surface roughness of a silicon substrate on the thickness of an oxide film due to thermal oxidation.
【図４】シリコン基板のラジカル酸化による平均表面粗
さの酸化膜厚依存性を示す図である。FIG. 4 is a graph showing the dependence of the average surface roughness of a silicon substrate on the oxide film thickness due to radical oxidation.
１…前処理室、２…成膜室、３…搬送室、１０…シリコ
ン基板、１１，２１…基板載置台。DESCRIPTION OF SYMBOLS 1 ... Pre-processing chamber, 2 ... Film formation chamber, 3 ... Transport chamber, 10 ... Silicon substrate, 11, 21 ... Substrate mounting table.
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F058 BA09 BC02 BE01 BF54 BF55 BF73 BF77 BF78 BJ01 5F140 AA00 AA19 BA01 BA02 BA06 BA07 BA10 BD07 BD09 BD11 BD12 BE02 BE03 BE07 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F058 BA09 BC02 BE01 BF54 BF55 BF73 BF77 BF78 BJ01 5F140 AA00 AA19 BA01 BA02 BA06 BA07 BA10 BD07 BD09 BD11 BD12 BE02 BE03 BE07
Claims (5)
する半導体装置の製造方法において、前記絶縁膜を形成
する工程は、 半導体基板の自然酸化膜を除去し且つ、その表面の平均
表面粗さを０．１６ｎｍ以下に低減させる前処理工程
と、 この前処理工程を経た前記半導体基板の表面に活性酸素
を含む雰囲気でのラジカル酸化により絶縁膜を形成する
成膜工程とを有することを特徴とする半導体装置の製造
方法。In a method of manufacturing a semiconductor device having a step of forming an insulating film on a semiconductor substrate, the step of forming the insulating film comprises removing a natural oxide film of the semiconductor substrate and obtaining an average surface roughness of the surface. And a film-forming step of forming an insulating film on the surface of the semiconductor substrate after the pre-treatment step by radical oxidation in an atmosphere containing active oxygen. Semiconductor device manufacturing method.
の開始までの間、前記半導体基板を、酸素分圧が１０-3
Ｔｏｒｒ以下の非酸化性雰囲気に保持することを特徴と
する請求項１記載の半導体装置の製造方法。2. After passing through the pretreatment step, the semiconductor substrate is kept at an oxygen partial pressure of 10 −3 until the start of the film formation step.
2. The method according to claim 1, wherein the semiconductor device is maintained in a non-oxidizing atmosphere of Torr or less.
リコン基板にシリコン酸化膜を形成するものであること
を特徴とする請求項１記載の半導体装置の製造方法。3. The method according to claim 1, wherein the semiconductor substrate is a silicon substrate, and wherein the film forming step forms a silicon oxide film on the silicon substrate in an atmosphere of 410 ° C. to 700 ° C. Of manufacturing a semiconductor device.
膜厚で且つ、シリコン酸化膜／シリコン基板の界面の平
均表面粗さを０．１６ｎｍ以下に抑えて形成することを
特徴とする請求項３記載の半導体装置の製造方法。4. The silicon oxide film according to claim 3, wherein the silicon oxide film has a thickness of 10 nm or less and an average surface roughness of an interface between the silicon oxide film and the silicon substrate is suppressed to 0.16 nm or less. The manufacturing method of the semiconductor device described in the above.
の表面の平均表面粗さを０．１６ｎｍ以下に低減させる
前処理室と、 この前処理室で処理された前記半導体基板の表面に活性
種を含む雰囲気で絶縁膜を形成する成膜室と、 前記前処理室で処理された前記半導体基板を、酸素分圧
が１０-3Ｔｏｒｒ以下の雰囲気に保持して前記成膜室に
搬送する搬送室と、を有することを特徴とする半導体装
置の製造装置。5. A pretreatment chamber for removing a natural oxide film of a semiconductor substrate to reduce the average surface roughness of the surface to 0.16 nm or less, and a pretreatment chamber for treating the surface of the semiconductor substrate treated in the pretreatment chamber. A film formation chamber for forming an insulating film in an atmosphere containing active species, and the semiconductor substrate treated in the pretreatment chamber is transported to the film formation chamber while maintaining the oxygen partial pressure in an atmosphere of 10 −3 Torr or less. A semiconductor device manufacturing apparatus, comprising:
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064392A (en) * | 2003-08-19 | 2005-03-10 | Neomax Co Ltd | METHOD OF MANUFACTURING SiC SINGLE-CRYSTAL SUBSTRATE |
| JP2005093562A (en) * | 2003-09-12 | 2005-04-07 | Tadahiro Omi | Method of manufacturing semiconductor device |
| KR100780637B1 (en) * | 2005-12-06 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| WO2008004513A1 (en) * | 2006-07-03 | 2008-01-10 | Osaka Industrial Promotion Organization | Precision processing method and precision processing apparatus |
| JP2010045362A (en) * | 2004-06-11 | 2010-02-25 | Soi Tec Silicon On Insulator Technologies | Wafer, and method of manufacturing the same |
| JP2010109356A (en) * | 2008-10-02 | 2010-05-13 | Semiconductor Energy Lab Co Ltd | Method for manufacturing soi substrate |
| US8183670B2 (en) | 2002-12-02 | 2012-05-22 | Foundation For Advancement Of International Science | Semiconductor device and method of manufacturing the same |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8183670B2 (en) | 2002-12-02 | 2012-05-22 | Foundation For Advancement Of International Science | Semiconductor device and method of manufacturing the same |
| JP2005064392A (en) * | 2003-08-19 | 2005-03-10 | Neomax Co Ltd | METHOD OF MANUFACTURING SiC SINGLE-CRYSTAL SUBSTRATE |
| JP2005093562A (en) * | 2003-09-12 | 2005-04-07 | Tadahiro Omi | Method of manufacturing semiconductor device |
| JP2010045362A (en) * | 2004-06-11 | 2010-02-25 | Soi Tec Silicon On Insulator Technologies | Wafer, and method of manufacturing the same |
| KR100780637B1 (en) * | 2005-12-06 | 2007-11-29 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| WO2008004513A1 (en) * | 2006-07-03 | 2008-01-10 | Osaka Industrial Promotion Organization | Precision processing method and precision processing apparatus |
| JPWO2008004513A1 (en) * | 2006-07-03 | 2009-12-03 | 財団法人大阪産業振興機構 | Precision processing method and precision processing equipment |
| JP4644858B2 (en) * | 2006-07-03 | 2011-03-09 | 財団法人大阪産業振興機構 | Precision processing method and precision processing equipment |
| JP2010109356A (en) * | 2008-10-02 | 2010-05-13 | Semiconductor Energy Lab Co Ltd | Method for manufacturing soi substrate |
| US8871610B2 (en) | 2008-10-02 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
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