JP2002287798A - Audio decoding device and audio decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an audio decoding device which has a small memory capacity and a short operation processing time. SOLUTION: In the audio decoding device, data subjected to MPEG compression is subjected to inverse MDCT operation after butterfly operation and is subjected to sub-band synthesis processing after window function processing to decode data. The audio decoding device is provided with an overlap buffer 123 where the inverse MDCT operation result is held, and data held in the overlap buffer 123 is subjected to window function processing. Since data is temporarily stored in the overlap buffer before window function processing by which symmetry is lost, and window function of the stored data is performed to start following addition processing, sub-band synthesis processing, etc., symmetry of operation processing can be utilized, and the memory capacity is reduced, and the operation time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an audio decoding apparatus and an audio decoding method, and more particularly to an MPEG (MPEG).
oving Picture Experts Grou
p) The present invention relates to an audio decoding device and an audio decoding method for decoding audio data compressed according to a standard.

[0002]

2. Description of the Related Art In general, decoding of audio data compressed according to the MPEG standard includes bit stream analysis and analysis, Huffman decoding, inverse quantization, stereo decoding, and the like.
Butterfly operation, inverse MDCT (Inverse Mod)
ifed DiscreteCosine Tran
sform) processing, window function processing, subband synthesis processing,
And so on. With reference to the drawings, a description will be given, with reference to the drawings, of a hardware configuration that performs the processes after the butterfly operation. 12 and 13 are block diagrams each showing a configuration of a main part of the audio decoding device.

As shown in FIG. 12, an audio decoding device includes a butterfly operation module 13-1, an inverse MDCT module 13-2, a window function processing module 13-4, an overlap buffer 123, an adder It is configured to include a processing module 13-5 and a buffer 124 for rearranging data. Referring to FIG. 13, the audio decoding device writes a sub-band synthesizing module 13-3 that performs a sub-band synthesizing process on data written in the rearrangement buffer 124, and data after the sub-band synthesizing process. And a windowing processing cycle addition module 13-6 for performing windowing processing and cycle addition processing on the data written in the subband synthesis buffer 125.

A butterfly operation module 13 shown in FIG.
-1 is bit stream analysis and analysis of data compressed according to the MPEG standard,
This is data that has been subjected to Huffman decoding, inverse quantization, and stereo decoding. In this example, one per band
Eight samples of data are input for 32 bands. That is, data of 18 × 32 = 576 samples is input.

[0005] The butterfly operation module 13-1 performs a predetermined butterfly operation on input data.
In this example, butterfly operation is performed on data of 18 samples per band to obtain data of 18 samples. The result of the butterfly operation performed by the butterfly operation module 13-1 is input to the inverse MDCT module 13-2.

[0006] In the inverse MDCT module 13-2, inverse MDCT processing is performed according to equation (1).

[0007]

(Equation 1)

In the equation (1), 0 ≦ i ≦ n−
It is one. In this example, a product-sum operation is performed on data of 18 samples per band to obtain data of 36 samples. The processing result by the inverse MDCT module 13-2 is subjected to window function processing by the window function processing module 13-4. This window function process multiplies each of the input 36-sample data by a window function to obtain 36-sample data.

The latter half (18 samples) of the current data multiplied by the window function by the window function processing module 13-4 is written to the overlap buffer 123 provided for each band. Overlap buffer 1
For 23 as a whole, data for 18 × 32 = 576 samples will be written. Window function processing module 13-
4, the first half of the current data multiplied by the window function (1
(8 samples) is added to the latter half (18 samples) of the past data read from the overlap buffer 123 in the addition processing module 13-5. The first half (18 samples) and the second half of past data (1
8 samples), so that 18 samples of data are obtained. The result of the addition by the addition processing module 13-5 is written to the rearrangement buffer 124 for rearrangement.

Referring to FIG. 13, the data of 18 × 32 = 576 samples input to the rearranging buffer 124 for rearranging is obtained by dividing data of 32 samples by 1 with respect to the time axis.
It is rearranged in a state where eight are arranged. That is, 32 × 18
= 576 samples of data. That is, the inverse MDC
One time sample is extracted from each of the 32 data blocks included in the output signal of the T module 13-2, and the data of the extracted 32 samples (sample data in the frequency domain) is rearranged.
PCM (Pulse Code Modulati)
on) A data block is generated in units of samples (sample data in the time domain). By performing such processing on all the output signals of the inverse MDCT module 13-2, an input data string S, which will be described later, including 18 data blocks is obtained.

These data written in the rearrangement buffer 124 are stored in the subband synthesis module 13-3.
And a sub-band combining process is performed. In the sub-band processing by the sub-band synthesis module 13-3, a product-sum operation is performed on data of 32 samples. This calculation process is performed according to equation (2).

[0012]

(Equation 2)

However, in equation (2), 0 ≦ i ≦ 63
It is. Here, when Expression (2) is expressed by a determinant, Expression (3) below is obtained.

[0014]

(Equation 3)

The subband synthesizing module 13-3 calculates an output data string V (PCM sample data) composed of 32 data blocks from the input data string S based on the equation (3). The input data string S is obtained by subjecting the output signal of the inverse MDCT module 13-2 to window function processing, overlap processing, and addition processing.
The data has been subjected to data rearrangement processing by the rearrangement buffer 124.

The result of the sub-band processing by the sub-band synthesis module 13-3 is stored in the
Is written to. The data written in the subband synthesis buffer 125 is 64 × 16 = 1024 samples. The data written in the subband synthesizing buffer 125 is read out by the windowing cycle addition module 13-6 and subjected to windowing processing and cycle addition.
In the windowing process and the period addition, a product-sum operation is performed on data of 16 samples to obtain data of 32 samples. This windowing cycle addition module 1
In the windowing processing and the cycle addition according to 3-6, processing is performed according to equation (4).

[0017]

(Equation 4)

However, in equation (4), i = 0, 1,
..., 31. FIGS. 14 and 15 show timing charts of the processes shown in FIGS. 12 and 13 described above. FIG. 14 is a timing chart showing butterfly computation, inverse MDCT processing, window function processing, and the like. As shown in the figure, a butterfly operation is performed on data of 16 samples. After this butterfly operation, the inverse M
A product-sum operation in units of 18 samples is performed by DCT processing.
The number of clocks required for butterfly operation, inverse MDCT processing, window function processing, and addition processing is roughly estimated without considering overhead due to pipeline control. Processing is performed at 18 × 36 = 648 clocks per band,
Since it is for a band, processing is performed at 648 × 32 = 20736 clocks.

Thereafter, a window function process of multiplying the window function,
Write processing to the overlap buffer is performed for the latter half of the data. Finally, data is read from the overlap buffer and an addition process is performed. When a series of processing is time-divisionally controlled by hardware, the buffer read time and the addition time are shorter than the time required for the inverse MDCT processing. Therefore, the number of clocks required for the inverse MDCT processing may be estimated. The processing that becomes a bottleneck in this series of processing is inverse MDC
Since the T processing is performed, the number of clocks required for this is the number of clocks required for the butterfly operation, the inverse MDCT processing, the window function processing, and the addition processing.

Accordingly, the operation speed in the case of performing the time-division processing from butterfly operation to rearrangement by one hardware is 20736 clocks / 576 = 36 clocks / sample. FIG. 15 is a timing chart showing the subband synthesis processing, the windowing processing, the cycle addition processing, and the like. As shown in the figure, in this example, the product-sum operation is performed 64 times in units of 32 samples. The data subjected to the subband synthesis processing is written to the subband synthesis buffer.

In the windowing process and the period addition performed thereafter, reading from the subband synthesizing buffer is performed, and a product-sum operation is performed. The data after the above processing is P
Write to CM buffer. The clock required for the above processing is 32 × 64 = 2048 clocks. The calculation speed is 2048 clocks / 32 = 64 clocks / sample.

[0022]

The above-mentioned conventional apparatus has the disadvantage that the memory capacity is large and the calculation processing time is long. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the related art, and an object of the present invention is to provide an audio decoding device and an audio decoding method which have a small memory capacity and a short arithmetic processing time.

[0023]

SUMMARY OF THE INVENTION An audio decoding apparatus according to the present invention decodes MPEG-compressed data by performing a butterfly operation, performing an inverse MDCT operation, performing a window function process, and performing a subband synthesis process. An audio decoding apparatus comprising: a first buffer that holds the result of the inverse MDCT operation; and performs the window function process on the data held in the first buffer. The apparatus further includes a second buffer that holds the data that has been subjected to the subband synthesis processing, and further includes a correction unit that performs code correction on the data held in the second buffer.

The audio decoding method according to the present invention uses the MP
After butterfly computation on the EG compressed data, the inverse M
An audio decoding method for decoding the data by performing a DCT operation, performing a window function process, and then performing a sub-band combining process, wherein the step of storing the inverse MDCT operation result in a first buffer; Performing the window function process on the data held in the buffer. Then, the method further includes a step of holding the data subjected to the subband synthesis processing in a second buffer, and further includes a step of performing code correction on the data held in the second buffer.

In short, in the present invention, the present apparatus temporarily stores the data in the overlap buffer before performing the window function processing that loses the symmetry, and performs the window function processing on the stored data. It can be used, the memory capacity can be reduced, and the calculation time can be shortened. Further, in addition to the reduction of the memory capacity of the overlap buffer and the speeding up of the arithmetic processing as described above, the reduction of the memory capacity of the subband synthesis buffer and the speeding up of the arithmetic processing can be realized.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals. FIGS. 1 and 2 are block diagrams showing a configuration of a main part in an embodiment of an audio decoding device according to the present invention.

In FIG. 1, the present apparatus comprises a butterfly operation module 13-1 and an inverse MDCT module 13-2.
, An overlap buffer 123, a window function processing module 13-4, an addition processing module 13-5, and a rearrangement buffer 124. FIG.
The apparatus moves to the sub-band synthesis module 13-3.
, Subband synthesis buffer 125, sign inversion module 125 a, windowing cycle addition module 1
3-6.

The operation of the present apparatus will be described with reference to FIGS. A butterfly operation is performed on the input data by the butterfly operation module 13-1. The inverse MDCT module 13-2 performs an inverse MDCT process on the butterfly operation result.
The inverse MDCT processing result is written into the overlap buffer 123. The preceding data is read from the overlap buffer 123 and a window function is applied by the window function processing module 13-4. A window function is applied to the data after the current inverse MDCT. The past data subjected to the window function and the current data are added by the addition processing module 13-5. The result of this addition is written into the rearrangement buffer 124.

The sub-band synthesizing module 13-3 executes a sub-band synthesizing process on the data written in the rearrangement buffer 124. The calculation result of the sub-band synthesis filter processing is stored in the sub-band synthesis buffer 1
Write 25. The sign inversion module 125a inverts the sign of the data to be inverted, and the windowing processing cycle addition module 13-6 executes the cycle addition processing.

Here, the inverse MDCT processing in the present apparatus will be described. In the inverse MDCT module 13-2, the input data sequence X, which is the result of the butterfly operation, is multiplied by the following transformation matrix _{PN × N / 2} .

[0031]

(Equation 5)

Equation (5) is derived by decomposing the inverse MDCT transform matrix P _{N × N / 2} of the following equation into a sparse matrix.

[0033]

(Equation 6)

In the inverse MDCT process, an output data string x composed of 32 data blocks is calculated from the input data string X based on equation (6). In equation (5), I _{N / 4} is a unit matrix of N / 4 × N / 4, and J _{N / 4} is
N / 4 × N / 4 inversion matrix, C ^IV is a DCT-IV transformation matrix,
“0” represents a zero matrix.

FIG. 3 is a diagram showing the process of the matrix operation in equation (5). As shown in the figure, since the first and second matrices on the right side in Equation (5) are composed of an identity matrix, an inversion matrix, and a zero matrix, matrices that only perform data exchange and distribution are provided. It is. That is, in Equation (5), only the processing related to the DCT-IV transform matrix C ^IV involves actual multiplication and addition.

Therefore, based on the equation (5), the inverse MDC
When performing the T-transformation processing, the inverse MDCT is performed based on Equation (6).
Since the number of operations is １ ／ compared to the case where the conversion process is performed, 36 product-sum operations can be reduced to 18 times.
The inverse MDCT module 13-2 has a 36-point inverse MD
CT is performed, and 36 data are generated from a data block composed of 18 data obtained by the DCT-IV transform. At this time, DCT-
Of the 18 data obtained by the IV conversion, the latter 9 data are folded back into 18 data, which are used as they are with the preceding data block. The first nine data are folded back into eighteen data, which are used for processing with the subsequent data block.
Therefore, in the processing of the subsequent data block, it is necessary to hold 18 data generated by folding the first 9 data. Here, instead of storing these 18 data, the first nine data of the data block composed of the 18 data obtained by the DCT-IV transform are stored in the overlap buffer 123. Therefore, the amount of data stored until the processing of the subsequent data block is halved, and the storage capacity is reduced.

As described above, the inverse MDCT module 13
Since the inverse MDCT processing by -2 includes a cosine function (cos) having symmetry, by using this symmetry, 36 product-sum operations can be reduced to 18 times. That is, the input 18 from 0 to 17
Originally, 36 sum-of-products operations must be performed for each type of data, whereas the DCT-IV
Since processing is performed using the transformation matrix C ₁₈ ^IV and the processing result is used, the product-sum operation itself can be performed 18 times. Note that DCT
The processing result by the −IV conversion matrix C ₁₈ ^IV is output as it is 0 to
In addition to 8, the output is 9 to 35 after the sign is inverted.

Next, the subband synthesizing process in the present apparatus will be described. Subband synthesis module 13-3
Is a window function processing by the window function processing module 13-4 on the processing result of the inverse MDCT module 13-2,
The addition processing is performed by the addition processing module 13-5, and the input data string S input to the rearrangement buffer 124 is multiplied by the following conversion matrix P _{64 × 32} .

[0039]

(Equation 7)

Equation (7) is obtained by converting the transformation matrix P of equation (3).
It is derived by sparse matrix decomposition of _{64 × 32} . In equation (7), I ₁₆ is a 16 × 16 unit matrix, and J ₃₁ is 3
1 × 31 inversion matrix, C ^II is a DCT-II transformation matrix,
“0” represents a zero matrix. FIG. 4 is a diagram showing a process of the matrix operation in equation (7). As shown in FIG. 4, the first matrix on the right side in Expression (7) is composed of a unit matrix, an inversion matrix, and a zero matrix, and therefore, only performs data exchange and distribution. That is, in equation (7), only the processing related to the DCT-II transform matrix C ^II involves actual multiplication and addition.

Therefore, since the sub-band synthesis processing is performed based on the equation (7), the product-sum operation of 64 times can be reduced to 32 times, and the conventional method of performing the sub-band synthesis processing based on the equation (2) The number of operations is １ ／ compared to. The sign inversion module 125a performs sign inversion processing on the data written in the subband synthesis buffer 125. With respect to the data after the sign inversion processing, the windowing processing cycle addition processing module 13-6 executes the windowing processing and the cycle addition processing.

Since the sub-band synthesis filter processing by the sub-band synthesis module 13-3 includes a cosine function (cos) having symmetry, 64 times of multiply-accumulate operations are performed by utilizing this symmetry. Can be reduced to times. Therefore, the inverse MDCT processing, which has been a bottleneck in the first half of the processing up to the rearrangement buffer in the conventional apparatus, can be doubled in speed. The processing performance can be doubled as compared with the conventional apparatus. Further, the capacity of the overlap buffer can be reduced to half. Then, in the sub-band combining process performed on the data once held in the rearrangement buffer, 64 product-sum operations can be reduced to 32 times, so that the number of product-sum operations can be reduced to ２. . For this reason, the performance of the subband synthesizing process can be improved, and the capacity of the subband synthesizing buffer for holding the processing result can be reduced by 1 /
Can be 2.

Here, the improvement of the processing performance will be described with reference to FIG. As shown in the figure, in the conventional apparatus, after performing subband synthesis processing on 32 samples out of 64 samples, and then performing subband synthesis processing on the remaining 32 samples, processing of the former 32 samples is performed. The result is subjected to windowing processing and periodic addition processing, and the processing result for the latter 32 samples is stored in the subband synthesis buffer. The above processing time is set to "10
0 ".

On the other hand, in the present apparatus, windowing processing and periodic addition are performed on the result of 16 samples in parallel with the subband synthesis processing of 16 samples. Then, after these processes, the sub-band combining process is performed on the remaining 16 samples. The above processing time is 25 + 12.5 + 25 = 62.5. Therefore, the processing performance is improved by about 40% compared with the conventional apparatus. Furthermore, the capacity of the subband synthesis buffer is reduced by 1 /
Can be 2.

Therefore, in the audio decoding processing, the processing with the heaviest computational load can be performed at high speed, and real-time processing (real-time processing) can be performed even with a low-performance CPU. The memory capacity in the case of stereo is as follows. The capacity of the overlap buffer is 57
In contrast to 6 × 2 (sample), in the present invention, it is 288 × 2 (sample). The capacity of the subband synthesis buffer is 1024 × 2 (sam
ple), whereas in this apparatus, 512 × 2 (s
sample). In the case of monaural, the memory capacity is 1/2 that of the case of stereo. When the buffer capacity when the effective data width is set to 24 bits is expressed in bytes, the above value may be tripled.

FIGS. 6 and 7 show timing charts of the processing shown in FIGS. 1 and 2 described above.
FIG. 6 is a timing chart showing butterfly computation, inverse MDCT processing, window function processing, and the like. As shown in the figure, a butterfly operation is performed on data of 16 samples. After this butterfly operation, a product-sum operation in units of 18 samples is performed by inverse MDCT processing. Inverse MDCT without considering overhead due to circuit pipeline control
Roughly estimate the number of clocks required for processing. Processing is performed at 18 × 18 = 324 clocks per band, and the processing for 32 bands is performed at 324 × 32 = 10368 clocks.

Thereafter, the first half of the data is subjected to a write / read process to the overlap buffer and a window function process of multiplying by a window function. In this case, unlike the conventional device, the writing / reading process to the overlap buffer is performed before the window function process. Therefore, in the window function processing, the latter half of the data is multiplied by the window function, and the first half of the data is written in the overlap buffer. At the same time, the first half of the previous stage is read from the overlap buffer and multiplied by the window function. Then, an addition process is performed on the processing result of the window function.

FIG. 7 is a timing chart showing the sub-band synthesizing process, the windowing process, and the cycle addition.
As shown in the figure, in this example, a sub-band synthesizing process, a read process from a sub-band synthesizing buffer, a sign inversion process, a windowing process, a period adding process, and a writing process to a PCM buffer are sequentially performed. Here, in the related art, after performing the window function processing, the data is held in the overlap buffer. On the other hand, in the present apparatus, data is first stored in the overlap buffer, and window function processing is performed on the stored data. By doing so, the data held in the buffer can be read, and the window function processing can be performed using the read data. The former half of the data to be processed in the preceding stage is added to the latter half of the data to be currently processed. Thereby, the symmetry of the arithmetic processing can be used.

In the decoding processing of the conventional apparatus, since the number of product-sum operations in the subband synthesizing processing is large, the capacity of the subband synthesizing buffer for holding the result of the subband synthesizing processing becomes large. On the other hand, since the present apparatus utilizes the symmetry of the sub-band synthesis processing, the number of product-sum operations in the sub-band synthesis processing is small, the capacity of the sub-band synthesis buffer can be reduced, and the calculation time can be shortened. be able to. Here, the symmetry means the symmetry of the cosine function, which is described in Japanese Patent Application Laid-Open No. 8-27975.
No. 9 is also mentioned.

By the way, in the audio decoding apparatus described above, the following audio decoding method is realized. That is, an audio decoding method for decoding the data by performing an inverse MDCT operation on the MPEG-compressed data after performing a butterfly operation, performing a window function process, and then performing a subband synthesis process.
Holding the inverse MDCT operation result in a first buffer; and performing the window function process on the data held in the first buffer, reducing the number of product-sum operations in the subband synthesis process. This means that the audio decoding method is realized by the present apparatus. The method may further include a step of holding the data subjected to the subband synthesis processing in a second buffer.
The method may further include the step of performing code correction on the data held in the second buffer. By adopting such a decoding method, the memory capacity can be reduced and the processing time can be shortened.

[0051]

Next, an example of application of the present invention to a more specific apparatus will be described. FIG. 8 shows a schematic configuration of the audio decoding device according to the present embodiment. Referring to FIG. 1, the present device includes an LSI 1 with a built-in CPU core and an external memory 2 provided outside the LSI. The LSI 1 with a built-in CPU core and the external memory 2 are connected by a bus 3 so that data can be mutually exchanged via the bus 3.

In the LSI 1 with a built-in CPU core, a CP
U11, built-in memory 12, and dedicated hardware 13 are provided. The CPU 11 performs processing to be described later according to a program (software) given in advance.
The following buffer functions are assigned to the built-in memory 12. That is, as shown in FIG. 9, the built-in memory 12 includes an input buffer 121 used by software, an interface (In) between software and hardware by writing software and reading hardware.
terface; hereinafter abbreviated as "IF")
HW IF buffer 122, overlap buffer 1
23, a function as a rearrangement buffer 124 for rearranging data between the inverse MDCT module and the subband synthesis module, a subband synthesis buffer 125 used for subband synthesis processing, and an output buffer 126.

Regular processing is assigned to the dedicated hardware 13 in FIG. The dedicated hardware performs a process to be described later such as an inverse MDCT operation process and a subband synthesis process. For this reason, the dedicated hardware 13 is, as shown in FIG.
3-1, Inverse MDCT module 13-2, Subband synthesis module 13-3, Window function processing module 13-
4, an addition processing module 13-5 and a windowing processing cycle addition processing module 13-6.

The inverse MDCT module 13-2 has the overlap buffer 1 realized by the built-in memory 12.
23, the result of the inverse MDCT operation is sequentially written. Also,
The sub-band synthesizing module 13-3 includes the built-in memory 12
In the sub-band synthesis buffer 125 realized by
The results of the subband synthesis processing are sequentially written. Built-in memory 12
The reordering buffer 124 realized by
CT module 13-2 and subband synthesis module 1
This is a buffer for rearranging the data between 3-3.

The sub-band combining process is a process of combining signals for each of the plurality of frequency bands. Referring back to FIG. 8, software (program) executed by the CPU 11 in FIG. 8 needs the following functions. That is, a function of transferring sequentially input data from the external memory to the input buffer for each processing unit,
A bit stream analysis and analysis function, a Huffman decoding function, an inverse quantization function, and a stereo coding function are required.
Further, a function of transferring data processed by the dedicated hardware 13 from an output buffer to an external memory is required.

Here, the processing indicated by reference numerals in the figure is the following processing. That is, the bit stream to be decrypted, which is written in the external memory 2, is
The data is transferred from the external memory 2 to the input buffer in the CPU core built-in LSI 1. Then, analysis and analysis processing are performed on the transferred bit stream. Further, Huffman decoding, inverse quantization, and stereo decoding are sequentially performed. The above processing result is written into the built-in memory 12. By reading the contents of the internal memory 12 by the dedicated hardware 13, intermediate data being processed can be transferred to the dedicated hardware 13. That is, the built-in memory 12 is also used for transferring data between software and hardware.

The processing indicated by reference numerals in the figure is the following processing. That is, the decoded result P
The CM data is transferred from the built-in memory of the CPU core built-in LSI to the external memory. FIG. 10 shows the external memory 2 in FIG.
FIG. 2 is a conceptual diagram showing data transfer between a device and a built-in memory 12 and role sharing between software and hardware in the apparatus. In the figure, “SW” indicates software, and “HW” indicates hardware. In FIG. 1, audio data compressed according to the MPEG standard is written in an external memory 2. This external memory 2
The data written in the device becomes a target of processing by the present apparatus.

The data written in external memory 2 is read out by software and written into input buffer 121 realized by internal memory 12. For the data written in the input buffer 121, C
The following processing is performed by the PU executing the program (software). That is, the software reads the data in the input buffer 121 and executes each process of bit stream analysis and analysis, Huffman decoding, inverse quantization, and stereo decoding. Then, the software processing result data is transferred to the hardware.

When transferring the data resulting from the software processing to the hardware, the SW / HW IF buffer 1 serving as an interface between the software and the hardware
22. That is, this SW / HW I
The data written in the F buffer 122 is read out by hardware, the butterfly operation and the inverse MDCT process are performed on the read out data, and the data resulting from these processes is written in the overlap buffer 123.

In the inverse MDCT processing, since processing is performed in block units, distortion (block distortion) occurs due to discontinuity of blocks. In order to reduce this distortion, after applying a window function, a process of adding one second half of the continuous block and the first half of the other block is performed. After this window function processing, the overlap buffer 12
The data written in 3 is rearranged,
The rearranged data is written to the rearrangement buffer 124.

The data written in the rearrangement buffer 124 is further subjected to subband synthesis processing, and the result of the subband synthesis processing is written to the subband synthesis buffer 125. The data written in the subband synthesizing buffer 125 is read out, written into the output buffer 126 after performing windowing processing and period addition processing. The data written to output buffer 126 is read by software and written to external memory 2.

The above operation will be further described with reference to FIG. FIG. 2 is a timing chart showing processing of hardware and software in the present apparatus. In the figure, software performs the above-described processing.
In this process, the data in the external memory is intermittently written to the input buffer, and the data after the process
Written to W / HW IF buffer. After this writing, the hardware is started. Then, the hardware reads the data written in the SW / HW IF buffer, processes the first half of the read data by a butterfly operation, an inverse MDCT process, a window function process, and an addition process; The processing, the windowing processing, and the latter half of processing including the cycle addition processing are sequentially performed.

When the hardware processing is completed, the processed data is transferred to the software again. In this case, the data after the subband synthesizing process is written to the output buffer, and the contents of the output buffer are read out by the software side, whereby the data is transferred. The software further writes the data read from the output buffer into the external memory 2. This writing to the external memory 2
This is performed via the bus 3.

By the way, while the dedicated hardware 13 is performing the above-described subband synthesizing process, the software side performs the above-described process for the next frame. Further, while the dedicated hardware 13 performs the above-described inverse MDCT processing, the software performs the above-described processing on the frame before the decoding processing is completed. As described above, the dedicated hardware 13 and the software cooperate with each other to perform processing, thereby shortening the entire processing time. And when performing this cooperative processing,
The following conditions must be satisfied. That is, condition (A): execution time of the above process> calculation time of the latter half process Condition (B): execution time of the above process> calculation time of the first half process needs to be satisfied. Here, the first half processing 51
Is configured by butterfly computation, inverse MDCT processing, window function processing, and addition processing. The latter half of the process 52 is composed of a sub-band combining process, a windowing process, and a period adding process. If the configuration is such that the above conditions (A) and (B) are satisfied, hardware control becomes easy.

In the present apparatus, the calculation processing time can be shortened as described above.
And (B) can be easily satisfied, and irregular processing can be assigned to software, regular processing can be assigned to hardware, and software and hardware processing can be performed first, and then software processing. The overall control can be facilitated without complicated processing of the wear.

[0066]

As described above, the present invention provides an MPEG
Inverse MDC after butterfly operation on compressed data
When decoding data by performing a T operation, performing a window function process, and then performing a sub-band combining process, a first buffer that holds the result of the inverse MDCT operation is included, and the data held in the first buffer By performing the window function processing, the processing order is different from that of the conventional device, and the memory capacity can be reduced and the processing time can be shortened by utilizing the symmetry of the arithmetic processing. There is.

Further, irregular processing is assigned to software, regular processing is assigned to hardware, and software processing and hardware processing are not complicated, such as first software processing and then hardware processing. Therefore, overall control can be facilitated. Since software and hardware can be executed in parallel, real-time processing can be realized with an inexpensive (low-performance) CPU and a small-scale circuit. Further, there is an effect that the processing with the heaviest calculation load in the audio decoding processing can be performed at high speed. There is also an effect that real-time processing (real-time processing) becomes possible even with a low-performance CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part in an embodiment of an audio decoding device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a main part in one embodiment of the audio decoding device according to the present invention, and is a diagram showing a configuration of a continuation part of FIG. 1;

FIG. 3 is a diagram illustrating a process of a matrix operation in equation (5).

FIG. 4 is a diagram showing a process of a matrix operation in equation (7).

FIG. 5 is a diagram for explaining a performance improvement rate of the present invention over a conventional technique.

FIG. 6 is a timing chart showing a butterfly operation, an inverse MDCT process, a window function process, and the like in the audio decoding device of the present invention.

FIG. 7 is a timing chart showing subband synthesis processing, windowing processing, period addition processing, and the like in the audio decoding device of the present invention.

FIG. 8 is a block diagram illustrating a schematic configuration of an audio decoding device according to an embodiment of the present invention.

FIG. 9 is a block diagram showing an internal configuration of dedicated hardware in FIG. 8;

FIG. 10 is a conceptual diagram showing data transfer between an external memory and a built-in memory in FIG. 8, and role sharing between software and hardware.

FIG. 11 is a timing chart showing hardware and software processing in the audio decoding device of FIG. 8;

FIG. 12 is a block diagram illustrating a configuration of a main part of a conventional audio decoding device.

13 is a block diagram illustrating a configuration of a main part of the conventional audio decoding device, and is a diagram illustrating a configuration of a continuation part of FIG. 12;

FIG. 14 shows a butterfly operation and an inverse MDC in a conventional device.
6 is a timing chart illustrating T processing, window function processing, and the like.

FIG. 15 is a timing chart showing a sub-band combining process, a windowing process, a period adding process, and the like in the conventional device.

[Explanation of symbols]

 Reference Signs List 1 LSI with built-in CPU core 2 External memory 3 Bus 11 CPU 12 Built-in memory 13 Dedicated hardware 13-1 Butterfly operation module 13-2 Inverse MDCT module 13-3 Subband synthesis module 13-4 Window function processing module 13-5 Addition processing Module 13-6 Windowing cycle addition module 121 Input buffer 122 SW / HW IF buffer 123 Overlap buffer 124 Rearrangement buffer 125 Subband synthesis buffer 125a Sign inversion module 126 Output buffer

Claims (6)

[Claims] 1. After performing a butterfly operation on MPEG-compressed data, an inverse MDCT operation is performed.
An audio decoding device that decodes the data by performing subband synthesis processing, the audio decoding device including a first buffer that holds the inverse MDCT operation result, wherein the window function processing is performed on the data held in the first buffer. An audio decoding device. 2. The audio decoding apparatus according to claim 1, further comprising a second buffer for holding the data subjected to the subband synthesis processing. 3. The audio decoding apparatus according to claim 2, further comprising a correction unit that performs code correction on the data held in said second buffer. 4. After performing a butterfly operation on MPEG-compressed data, an inverse MDCT operation is performed.
An audio decoding method for decoding the data by performing subband synthesis processing, the method comprising: holding the inverse MDCT operation result in a first buffer;
Performing the window function process on the data held in the buffer. 5. The audio decoding method according to claim 4, further comprising a step of holding the data subjected to the subband synthesis processing in a second buffer. 6. The audio decoding method according to claim 5, further comprising the step of performing code correction on the data held in said second buffer.