JP2002280286A - Method of manufacturing electronic equipment, exposure control system, electronic component, and method of manufacturing the component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing electronic equipment by which the occurrence of defects caused by distortion errors can be prevented, even when the margin of alignment accuracy is small manufacturing of a system LSI, etc., having fine wiring, and to provide an exposure control system. SOLUTION: In the method of manufacturing electronic equipment, alignment parameters of an aligner is corrected, so that the positional deviation of a circuit pattern caused by a distortion error represented by the aberrations of the optical system of the aligner becomes minimal in a region, where the permitted limit of alignment for exposure becomes minimal by setting the permitted limit of alignment for exposure, according to the pattern density of each functional region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring board and an LSI.
In particular, the present invention relates to a method for manufacturing an electronic device and an electronic component that requires fine and multilayer wiring, such as a memory, a main processing unit, a digital signal processor, etc. in one LSI chip.
The present invention relates to an LSI having a plurality of areas having different functions, an exposure method used for manufacturing those electronic devices, and a control system therefor.

[0002]

2. Description of the Related Art Along with miniaturization of LSI wiring, an exposure apparatus used for manufacturing the LSI has a pattern of one or several chips of LSI formed on a reticle serving as a mask on a wafer coated with a photosensitive material. Steppers and scanners that repeatedly reduce and project are mainly used. To form transistors, capacitors, and multiple layers of wiring on an LSI,
For each exposure, it is necessary to align the pattern already formed on the wafer with the pattern projected from the reticle. This alignment must be controlled so that the resist pattern formed by the exposure step and the circuit pattern formed on the wafer are equal to or less than a predetermined positional shift amount. Alignment is performed as follows in a current stepper.

(1) A reticle placed on a reticle stage of an exposure apparatus is aligned with the exposure apparatus. This alignment is performed by an optical detection device reading a reticle alignment mark on the reticle, and a shift amount (x, y offset, rotation) of the exposure device with respect to a reference coordinate system.
Is calculated. Then, the reticle stage and / or the wafer stage are adjusted according to the calculated shift amount.

(2) The wafer set on the wafer stage is aligned with the exposure apparatus. The position of the alignment mark formed for each shot of the first layer (reference layer) formed on the wafer is read by an optical detection device, and the shift amount of the exposure device from the reference coordinate system is calculated. ,
Make corrections. There is a method to perform this position detection and correction for each shot, but usually to improve throughput,
A global alignment scheme is used. In this method, alignment marks are read at two or more shot positions on a wafer, the amount of deviation is statistically processed (least square method is generally used), separated into a linear component and a residue, and the linear component is adjusted and a correction parameter is set. It is a method.

[0005] The alignment correction parameters in the stepper type exposure apparatus include a parallel shift (x, y wafer offset Wof).
fx, Woffy), rotation deviation (wafer rotation Wrot), shot distance deviation (x, y wafer scale Wsclx, Wscl)
y), orthogonal deviation (wafer orthogonality error Worth), rotational deviation for each shot (chip rotation Crot), and magnification deviation for each shot (chip magnification Cscl).

In the case of a scanner type exposure apparatus, the chip magnification is divided into x and y (Csclx, Cscly), and a shot orthogonality shift (chip orthogonality error Corth) is added.

However, the measurement time is often shortened by setting an offset value without measuring the chip rotation and the chip magnification.

(3) After the above parameters are corrected for errors inherent in the exposure apparatus and the like, exposure is performed in accordance with the parameters.

(4) A plurality of misalignments (alignment errors) between the first layer alignment marks and the resist images of the second layer alignment marks formed on the wafer as a result of exposure are measured by an alignment inspection apparatus. And confirm that it is within the range of the standard. Here, when the alignment error exceeds the standard, the exposure is performed again after the regenerating step of removing the resist.

Conventionally, alignment has been performed with reference to alignment marks on the wafer and on the reticle, and alignment errors (shift amounts) have also been measured with alignment inspection marks on the wafer and alignment inspection projected from the reticle. Since the measurement was performed between the resist images of the marks, the amount of displacement of the circuit pattern inside the LSI (or inside the shot area) could not be detected. Therefore, the alignment standard value in a layer formed in a single exposure process is usually constant within the layer, and if the detected alignment mark deviation is within the standard, the circuit pattern deviation falls within the standard. Thus, the standards for alignment inspection have been determined.

In practice, the position of the projected reticle pattern shifts (distortion error) from the designed pattern position due to, for example, a reticle drawing error or an aberration of the optical system of the exposure machine. Therefore, the position of the resist pattern formed by the exposure is shifted. For example, even if the alignment performed at the time of exposure is perfect and no alignment error is detected in the alignment inspection, the distortion between the first-layer circuit pattern and the second-layer circuit pattern is different. Can occur. If the distortion is large and the allowable range of the alignment is small, a short circuit or an open failure due to the distortion error may occur in the actual circuit pattern even though the alignment error in the alignment inspection is within the standard.

Heretofore, the positional deviation caused by such distortion has been ignored because it is small compared to the accuracy of alignment in the exposure apparatus, or the amount of distortion error generated between the first and second layers has been reduced. This has been dealt with by predicting and performing error distribution with the alignment error standard.

In particular, when a mix-and-match system in which the first layer and the second layer are exposed by different exposure apparatuses is employed, since the aberration of the optical system differs depending on the exposure apparatus, the pattern of the first layer and the second layer is different. The difference in distortion becomes large, and the distortion error becomes larger than in a device limited system in which exposure is repeated in the same device. For this reason, it is important to measure or estimate the magnitude of the distortion error and manage the combination of the exposure apparatuses so that the magnitude is within an allowable range.

As a method of positively correcting the distortion error, Japanese Patent Application Laid-Open No. 9-92609 discloses a method in which the distortion data of the projection optical system of each exposure machine is recorded in a database, and the first layer and the second layer are recorded. A method of correcting the projection magnification for a combination of apparatuses for exposing two layers is described.
Further, Japanese Patent Application Laid-Open No. 2000-124125 describes a method of storing a distortion due to a reticle drawing error in a database and correcting the distortion with an offset parameter for positioning.

[0015]

In the future, as the miniaturization of LSIs further progresses and the allowable range of alignment becomes smaller, it is important to correct the positional deviation of a circuit pattern due to a distortion error. In addition, a method of expanding the allowable range of the alignment at the LSI design stage is required. In particular, in system LSIs that produce a small number of products,
Since the adoption of the mix-and-match method is required to increase the production efficiency of the line, it is more important to correct the distortion error and to expand the permissible alignment range.

An object of the present invention is to solve the above-mentioned problems.
An object of the present invention is to provide a method of manufacturing an electronic component and an exposure control system that can prevent the occurrence of a defect due to a distortion error even when a margin of alignment accuracy is small in manufacturing a system LSI or the like having fine wiring.

Another object of the present invention is to provide a method for manufacturing a system LSI having fine wiring and the like, wherein Mix & M
An object of the present invention is to provide a method of manufacturing an electronic component and an exposure control system which enable application of an exposure method of an attach method and improve the efficiency of a manufacturing line.

[0018]

A system LSI has an operation processing area in which an operation is performed and a DRAM in which a temporary storage is performed.
It is divided into areas, ROM and EPROM areas for storing instructions, and the pattern density differs depending on the area. For example, in the gate layer, the wiring density of the operation processing area is lower than that of the DRAM area. Conventionally, in the same layer, the allowable width of the alignment is set according to the area where the wiring density is the highest, but the allowable width of the alignment is changed according to the wiring density, and the position shift is performed in the area where the allowable width is the smallest. The above problem can be solved by optimizing the alignment parameter at the time of exposure so that is smaller.

Specifically, the present invention provides, in one layer,
In an area where the wiring density is low, the LS is designed to increase the wiring width and the diameter of the contact hole to the limit of the allowable range in the design, and to install a pad for receiving the contact hole.
I is designed.

The present invention also relates to a method of manufacturing an electronic device having a plurality of areas having different functions and fineness within a chip or product unit, wherein at least one of the plurality of layers constituting the chip or product is provided. A setting step of setting the standard of the alignment accuracy to a different value according to the fineness of each area in the layer, and a reticle drawing error, an optical aberration of an exposure apparatus, and the like, and a distortion error factor in the chip. An exposure step of correcting a change in a pattern position due to a distortion error caused by at least one of the areas in accordance with an alignment accuracy standard for each area set in the setting step.

Further, according to the present invention, in the exposing step,
It is characterized by including a calculation step of calculating a matching parameter correction value so as to satisfy the matching accuracy standard for each area.

The present invention is also directed to a pad or the like having a size necessary for a junction point with a previous layer or a next layer in at least one of a plurality of layers constituting the chip or the product. It is characterized by having been installed.

According to the present invention, there is provided an exposure apparatus for exposing an object to be exposed to a drawing pattern formed on a reticle having a plurality of areas having different functions and fineness within a chip or a product unit. First storage means for storing at least one of error, distortion data such as distortion due to optical aberration of the exposure apparatus, and second storage means for storing alignment accuracy standards for each product, process, and area in a chip; And an arithmetic system for calculating an adjustment parameter correction value so as to satisfy an alignment accuracy standard for each area using the data of the first and second storage means and presenting the adjusted parameter correction value to the exposure apparatus. It is a control system.

Further, according to the present invention, in the above exposure control system, the result of the alignment inspection performed after the exposure is corrected in accordance with the alignment parameter correction value calculated by the calculation system, and the alignment inspection for determining whether the alignment inspection is acceptable or not. It is characterized by comprising means.

Further, the present invention is a method for manufacturing an electronic component, wherein the electronic component is manufactured using the above-described exposure control system.

Further, the present invention provides an electronic component manufactured by the above-mentioned method for manufacturing an electronic component.

The present invention also provides a database for storing the amount of image distortion caused by optical aberrations of each exposure device and the drawing error of the reticle of each layer, and a first database formed on a wafer based on these data. Calculate the distortion of the circuit pattern of the layer and the distortion of the circuit pattern of the second layer to be formed thereon, and adjust the matching parameters so that the combined result of various distortions is minimized in the region where the positional deviation allowable width is the smallest. A system that performs calculations for optimization, an exposure machine controller that controls the alignment of the exposure machine according to the calculated parameters, and calculates the misalignment of the alignment test mark caused by changing the parameters, and calculates the result of the alignment test. It is characterized in that a determination system is provided for making a correction and determining whether the test is successful or not.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for manufacturing an electronic circuit device (semiconductor such as a system LSI) and an exposure control system according to the present invention will be described with reference to the drawings.

First, the configuration of a system LSI according to the present invention will be described with reference to FIG. System LSI chip 1
Are, for example, a main calculation circuit 1a, a ROM circuit 1b,
It includes a cache memory circuit 1c, an AD conversion circuit 1d, a floating point calculation circuit 1e, and a peripheral circuit 1f. FIG. 2 shows an exposure unit 2 which is a reticle pattern. As described above, the exposure unit 2 is formed by the arrangement of the plurality of chips 1. Therefore, in the case of a system LSI or the like, since circuit patterns having various line densities are formed within the exposure unit, the required alignment accuracy in the exposure apparatus also differs.

Further, in the ROM circuit 1b, the cache memory circuit 1c, etc., 0.13 .mu.m or less
Due to the tendency to miniaturization of μm and 0.07 μm, the margin for the target accuracy (about 30 nm or less) as the alignment accuracy as an exposure apparatus such as an excimer stepper or an excimer scanner is decreasing.

Therefore, in the present invention, it is necessary to reduce error factors other than the alignment accuracy of the exposure apparatus such as an excimer stepper and an excimer scanner.

Next, an embodiment of a specific method and system configuration for reducing an error factor other than the alignment accuracy of an exposure apparatus such as an excimer stepper or an excimer scanner according to the present invention will be described.

FIG. 3 shows a functional configuration of the exposure control system according to the present invention, and FIG. 4 shows a hardware configuration of the system according to the present invention. In FIG. 3, the system according to the present invention is generally a manufacturing management system unit (MES: Manufacturing Exercise).
System), a dispatcher unit 32 for making inquiries and the like, and an advance process control unit (APC: Advanc)
ed Process Control) 33. The manufacturing management system unit 31 is instructed by a history management system unit 311, a device operation management system unit 312, and a start instruction unit 313 for issuing a start device instruction based on the determination by the start device determination unit 324 of the dispatcher unit 32. An exposure parameter inquiry unit 314 that inquires an exposure parameter DB 335 about an exposure parameter of the started construction device;
And a start-of-construction unit 315 for starting the construction of the starter based on the exposure parameter of the inquiry result. The dispatcher unit 32 includes the history management system 311
A reference layer starter inquiry unit 321 for inquiring about a starter of the reference layer, a startable apparatus and a correction value inquiry for inquiring about a startable apparatus and a correction value in the correction value calculation system 334 based on the inquiry result. Unit 322, an operation status inquiry unit 323 that inquires the operation status of the device operation management system 312 about the operation status of the startable device, and determines the start device based on the inquiry result (makes a matching rule a dispatch rule). And a start-up device determining unit 324. The forward process control unit 33 performs a matching process between the units based on the lens distortion data in each of the exposure apparatuses and the drawing data on the reticle used therein, and further creates a reticle in-line alignment permissible accuracy map 3315 by mix-and-match. A calculation unit 331, an exposure parameter calculation unit 332 that calculates in advance an exposure parameter (alignment correction and exposure amount) unique to each exposure apparatus and stores it in an exposure parameter DB 335, a reticle management system unit 333 that manages a reticle, Match calculator 33
A correction value calculation system unit 334 that selects a device that can be started based on the matching process between the first and second units and the reticle alignment accuracy map and calculates alignment correction values (vertical and horizontal magnification, shot rotation, skew, etc.). It is composed of

Hereinafter, description will be made with reference to FIG. In the following description, a process in which a wiring is formed as a first layer and a resist pattern for forming a contact hole is formed in an insulating layer formed thereon is exposed as an example, and one exposure area (one shot) in a stepper is used. ) And LSI chip part 2
Is formed.

The step-and-repeat type stepper alignment in the present invention is performed as follows. The step-and-repeat exposure apparatus is configured as shown in FIG. The exposure apparatus includes a stage 64 on which the wafer 43 is placed, an illumination system 61 for illuminating the reticle 62 with an excimer laser beam, and a reduction lens 63 for reducing and projecting a circuit pattern on the reticle 62 onto the wafer 43. You.

First, the distortion data 3311 due to the aberration of the projection optical system of each exposure apparatus is measured in advance and stored in the distortion database 41. That is, for example, the image distortion d11 (3311) of the first exposure apparatus M1 (44a) that has exposed the first layer (reference layer) is measured. This is expressed as a set of vectors representing the position of each point and the displacement of the image of the reticle pattern projected on each point at a plurality of points in the shot area of the exposure apparatus (FIG. 5A). It is desirable that the number of measurement points is large and that the measurement points are uniformly distributed in the shot area. As a measuring method, the position of a pattern transferred onto a wafer using a reference reticle having a known writing error or the like is measured by a position measuring device, and the exposure apparatus is used for a wafer on which a reference pattern is formed. In general, a method is used in which the same pattern is overlapped and formed, and the deviation between the patterns is aligned and measured with a measuring instrument.

Further, the drawing error data 3312 of each reticle is measured in the same manner, and the reticle along with the positional deviation amount of the alignment mark formed on the reticle and the alignment inspection mark formed by exposing the wafer. Stored in the database 42. That is, for example, the drawing error d12 of the first layer (reference layer) reticle R1 (44b)
(3312) is measured. Generally, an error from the design position of the reticle device area pattern, the alignment pattern, and the alignment inspection pattern is measured as a vector using a position measuring device with reference to the reticle alignment mark (FIG. 5B). The device area pattern is measured at a plurality of points in the area in the same manner as the image distortion, but if there is no appropriate pattern, it is necessary to create a position measurement pattern with a line width smaller than the resolution limit. In addition, it is necessary to convert to a scale after wafer transfer for later calculation.

Next, the first layer (reference layer) of the wafer 43 is exposed using a first exposure device 44a and a reticle 44b of the first layer, and after a predetermined processing step, the circuit pattern of the first layer is exposed. An insulating layer is formed on 43c and the circuit pattern 43c.

At this time, in the region 43a where the wiring density is high, 4
Although the wiring 43c has no pad as shown by 3f, the wiring 43c as shown by 43g in the region 43b where the wiring density is low.
Is provided with a pad 43d that can tolerate a large displacement from the contact hole thereabove. Subsequently, in order to form a contact hole, the second layer is exposed using a second exposure device 45a and a second layer reticle 45b different from the first layer. At this time, the correction system 46 acquires the reticle 44b used in the first layer of the wafer 43 and the ID number of the first exposure apparatus 44a from the history database 47. Subsequently, the correction system 46 acquires the distortion data 3311 and 3312 corresponding to the ID numbers from the distortion database 41 and the reticle database 42, calculates the distribution of the distortion amount of the first layer from these data, and stores it. That is, the correction system 46 (mix and match calculation unit 331) combines the image distortion d11 of the first exposure apparatus M1 (44a) with the drawing error d12 of the first layer reticle R1 (44b) to synthesize the first layer wafer. The above error d13
(3313) is calculated. This is the sum of the displacement vectors at each position of d11 and d12. When the measurement positions of d11 and d12 are different, one of them is used by interpolation.

Next, the position information of the area A having a small alignment margin is obtained from the design database 48. Of course,
The setting database 48 may store a matching accuracy standard 3315 for each product, process, and area within a chip. Since the alignment accuracy standard 3315 is determined by product information, process information, and area information (circuit pattern information) in a chip, it can be included in the design database 48.

The correction value calculation system 46 (correction value calculation system 334) calculates a set p11 of an adjustment correction parameter for the first layer device area from the error d13 of the first layer on the wafer by using the least square method. Note that p1
The correction parameters included in 1 include, for a stepper, parallel displacement (x, y wafer offset Woffx, Woffy), chip rotation Crot, chip magnification Cscl, and for a scanner, parallel displacement (Woffx, Woffy), chip rotation Crot, chip Magnification (Csclx, Cscly) and chip orthogonality error Corth. The measurement points of the device area of d13 are 1 to m, the coordinates of the i point are (xi, yi), and the displacement vector corresponding to the i point is d.
13 (i) = (dx (i), dy (i)). In the case of the stepper, the parameters that minimize the sum ΣΔd ² of the residual square components with respect to the following equations (1) and (2) are obtained.

Dx (i) = Woffx + Crot × y (i) + Cscl × x (i) + Δdx (i) (1) dy (i) = Woffy + Crot × x (i) + Cscl × y (i) + Δdy (i) (2) Here, in order to weight the area A (43a), the measurement points included in the area A (43a) are 1 to n, and the measurement points in the remaining device area are n + 1 to m. The sum of the residual square components is obtained by the equation (3).

[0043]

(Equation 1) Here, [lambda] 1 and [lambda] 2 are matching weighting coefficients for the region A (43a), and are [lambda] 2 = 1 / [lambda] 1 ([lambda] 1> 1) or [lambda] 1 = 1 and [lambda] 2 = 0. If λ1 = 1 and λ2 = 0, a correction parameter optimized for the region A (43a) can be obtained. Further, the matching standard of the area A is k1,
Assuming that the matching standard other than the above is k2, a correction parameter optimized in inverse proportion to the matching standard can be obtained by the following equation (4).

Λ1 = k2 / k1, λ2 = λ1 / λ2 (4) Alignment correction parameters p12 and p13 for the first layer reticle alignment mark and wafer alignment inspection mark are calculated from the synthesis error d13 by the ordinary least square method. The type of correction parameter (parallel shift, rotation shift, magnification shift, etc.) is p
Same as 11.

Subsequently, the correction value calculation system 46 obtains the position data of the position 43a and the data of the position deviation allowable range (the alignment allowable accuracy map 3315) from the design database 48.

Further, the correction value calculation system 46 acquires the distortion data 3311 of the second exposure apparatus used in the second layer from the distortion database 41, and obtains the reticle database 4
From 2, the distortion data 3312 of the reticle 45 b of the second layer is obtained. That is, the second exposure apparatus M2 for exposing the second layer
The image distortion d21 (3311) of (45a) and the drawing error d22 (3312) of the second layer reticle R2 (45b) were also measured in the same manner as the above d11 and d12, and the combined error d2 was measured.
3, the correction parameter p21 of the second layer device area,
Second layer reticle alignment mark correction parameter p2
2. The wafer alignment inspection mark correction parameter p23 is similarly calculated.

The offset value p02 of the alignment correction parameter set is input to the second exposure device M2 (45a). This offset value p02 is a correction value specific to M2 (for example, a shift between the alignment mark detection device and the device reference grating,
A correction parameter set p01 including a deviation between a set magnification and an actual magnification, and a correction value specific to a process (for example, a deviation of a detection position due to a shape of an alignment mark);
The sum of the parameters included in 11, p12, p21, and p22 (the magnification correction parameters Wscl and Cscl are products).

The sum of the parameters included in p11, p12, p21, and p22 is, for example, expressed by the following (5)
Expression (6) and expression (6).

Woffx (02) = Woffx (01) + Woffx (11) + Woffx (12) + Woffx (22) (5) Cscl (02) = Cscl (01) × Cscl (11) × Cscl (12) × Cscl (21) ) × Cscl (22) (6) Here, X (ij) indicates the correction parameter X included in the correction parameter set pij. The other parameters are similarly calculated. Hereinafter, such calculation is expressed as a sum (p01 + p11) between the correction parameter sets.

Next, the first exposure apparatus M1 and the reticle R1
The wafer W1 on which the pattern of the first layer is formed by using and the resist is formed is set in the second exposure apparatus M2, the alignment position is measured, and the correction parameter p00 is calculated.

The exposure alignment correction parameter p03 is calculated from p00 and p02 based on the following equation (7).
Calculated in the same way as 1.

P03 = p00 + p02 (7) As described above, the strain amount distribution data d13 of the first layer
The offset, rotation, and rotation of the region 43a and the region 43b are set such that the amount of displacement between the first layer and the second layer is within the allowable range (the reticle alignment allowable accuracy map 3315).
Calculate magnification parameters. Finally, the first layer (reference layer)
The correction value p of the alignment parameter used when the second exposure apparatus M2 (45a) performs the alignment based on the positional deviation amount of the alignment mark of the second layer and the parameter calculated previously.
03 is calculated and transmitted to the second exposure device 45a.

The second exposure device 45a performs exposure using the calculated exposure correction parameter p03. That is, the second exposure device 45a measures the alignment mark between the wafer 43 coated with the resist and the reticle 45b, and calculates the alignment parameter. The alignment value and the exposure are performed by adding the above correction value and, if necessary, an offset value specific to the exposure apparatus and the process.

Then, the wafer 43 on which a predetermined developing process has been performed and a resist pattern has been formed is sent to an alignment inspection apparatus. The alignment inspection device 49 detects the resist images of the alignment inspection mark of the first layer and the alignment inspection mark of the second layer, and measures a shift amount between the marks as an alignment error. The correction system 46 calculates an alignment inspection correction parameter from the previously calculated correction value and the positional deviation amount of the alignment inspection mark of the first layer and the second layer, and calculates the alignment error corrected by subtracting from the measured deviation amount. And the judgment system 48
Hand over to The determination system 48 determines whether the alignment accuracy is within the standard from the corrected alignment error.

That is, an alignment inspection error parameter p04 is calculated from the measured positional deviation amount of the alignment inspection mark between the first layer and the second layer.

Then, the alignment error parameter p05 based on the alignment mark is calculated by the following equation (8), the measured alignment error is corrected, and comparison with the alignment standard is performed to determine whether or not the alignment is within the standard. I do.

P05 = p02−p12−p22−p03 + p01 (8) (p02−p12 is an inverse calculation of p02 + p12, that is, X (02) −X (12) for each parameter X (ij) (X (02) for the magnification correction parameter 02) ÷ X (12)).) In the above embodiment, the distortions 3311 and 331 are generated for each exposure.
The correction value of the alignment parameter for the second layer is calculated. This value is calculated in advance, stored in the databases 41 and 42 for each reticle and exposure apparatus used in each layer, and corrected from the databases 41 and 42 at the time of exposure. The value may be obtained. Also, if possible, directly send the inspection correction parameter to the inspection device 49,
By adding to the correction parameter unique to the inspection apparatus, the pass / fail judgment of the alignment inspection may be made directly from the data of the alignment inspection apparatus.

Next, an embodiment of the method of calculating the correction value of the alignment parameter according to the present invention will be described.

First, in order to measure the image shift due to the aberration of the projection optical system of the exposure apparatus, a predetermined position, for example, FIG.
As shown in (a), a reticle having a grid-like position display pattern, for example, a cross is formed on a resist-coated wafer, and a predetermined process is performed to form a resist image of the position display pattern. The position of the resist image is measured. Separately, the position of the position display pattern on the reticle is measured, and from these data, the image shift at each position display mark position due to the aberration of the projection optical system is calculated as a vector. Since the aberration of the projection optical system differs depending on the numerical aperture (NA) and the coherency (σ) of the illumination system, measurement is performed by combining a plurality of NAs and σ if necessary. If the projection optical system has coma aberration, the amount of displacement differs depending on the line width and density of the pattern.
You may perform the measurement which changed the pattern shape.

From the data obtained by these measurements, a first-order or polynomial fitting is performed so that correction between the measurement points can be performed. For example, the equation of the displacement vector expressed as a function of the distance from the center of the exposure area and the residual error are obtained. Decompose.

Instead of actually measuring the resist image as described above, the aberration of the projection optical system is changed to an aberration coefficient, for example, Ze.
It can also be measured as a rnik coefficient and calculated using a simulation such as a ray tracing method.

On the other hand, the writing error of the reticle can be determined by writing a position measurement pattern on the reticle used in each step in advance or by using a pattern whose position can be identified by using a position measurement device ( (Not shown), and the deviation from the designed position is recorded as vector data with reference to, for example, a reticle alignment mark. Subsequently, as in the case of the exposure machine, the linear (or polynomial) component capable of interpolating between measurement points is separated into residual errors.

When actually calculating the correction value of the alignment parameter, first, the reticle used for the exposure of the first layer and the displacement vector data of the exposure apparatus are synthesized, and the displacement at each position of the circuit pattern of the first layer is calculated. The vector is calculated by the mix and match calculation unit 331 or the correction value calculation system 334 based on the alignment mark on the wafer side. As a result, the shift amount of the circuit pattern at an arbitrary position on the first layer can be represented by a root mean square of the combined shift vector and each residual error.

Subsequently, the shift between the reticle used in the second layer and the exposure apparatus is similarly calculated based on the reticle-side alignment mark, and the shift amount of the circuit pattern is calculated by the mix-and-match calculator 331 or the correction value calculator 334. Is calculated.

The correction value of the matching parameter is calculated in accordance with the two shift amount data, the position data of each functional area of the circuit pattern, and the shift allowable amount 3315 corresponding to the functional area. The correction value calculation system 334 (correction system 46)
Is calculated. As this method, for example, using the reciprocal of the ratio of the ratio of the deviation allowable amount 3315 in each of the areas 1a to 1f as a weighting factor, the respective adjustment parameters (X, Y offset, chip rotation, magnification, etc.) by the least square method of the deviation vector. A method of performing the fitting is considered. The sum of the scalar amount of the shift vector in each of the areas 1a to 1f and the root mean square of the residual error of each layer is the shift amount due to the distortion of the circuit pattern in each of the areas 1a to 1f. The deviation tolerance of each of the areas 1a to 1f is error-distributed to the tolerance of the alignment error of the exposure apparatus and the tolerance of the deviation of the distortion, and the deviation calculated previously in all the areas 1a to 1f is the tolerance of the distortion. If it is within the range, the calculated correction value is adopted.

If the value exceeds the allowable range, the correction value calculation system 334 sends the ME value via the dispatcher unit 32 to the ME.
Change the exposure apparatus by inquiring of S31, or change the reticle if there is more than one reticle of the same layer by inquiring of the reticle management system 333,
A combination in which the displacement due to the distortion is within an allowable range is obtained.

As described above, the present invention relates to an electronic device such as an LSI having two or more areas 1a to 1f having different functions and fineness within one chip or product unit, as represented by a system LSI. In the manufacturing method, in at least one or more of the layers constituting the product, a standard of alignment accuracy in the photo process (alignment allowable accuracy map 3315) according to the fineness of each area 1a to 1f in the layer. ) Is set to a different value, and the pattern position is determined by a distortion error caused by at least one of the distortion error factors in the chip such as a reticle drawing error and an optical aberration of an exposure apparatus. A second feature is that the variation is corrected in accordance with the above-described alignment accuracy standard 3315.

In order to realize the above manufacturing method, a first storage device 41, 42 for storing at least one of distortion data such as a reticle drawing error and a distortion due to an optical aberration of the exposure device as a control system of the exposure device. And a second storage device 48 for storing the alignment accuracy standard for each product, process, and area in the chip, and these storage devices 41, 42,
A correction value calculation system 46 for calculating a matching parameter correction value so as to satisfy a matching accuracy standard for each area using the data of 48; and a communication for communicating or presenting the matching parameter obtained as a result of the calculation to the exposure apparatus 44 or an operator. And a system 51.

Further, in order to apply the manufacturing method, the result of the alignment inspection performed after the exposure is corrected according to the alignment parameter correction value calculated as described above, and the pass / fail of the alignment inspection is determined.

Further, in order to realize the above manufacturing method, L
In the SI or the electronic device (product), at least one or more of the layers constituting the product, the preceding layer, or It is characterized in that a pad or the like having a necessary size is provided at a junction with the next layer. This makes it possible to narrow the region where the alignment accuracy is the strictest in the exposure unit, and to reduce the area of 0.1 μm or less to 0.1 μm.
It is possible to expose a system LSI or the like having a region having a tendency to miniaturization of m and 0.07 μm by a mix-and-match method.

[0071]

According to the present invention, in the manufacture of a system LSI or the like having fine wiring, the distortion error due to the aberration of the exposure apparatus or the like can be reduced in the entire exposure unit by narrowing the region where the alignment accuracy is the strictest. As a result, even when the margin of the alignment accuracy is small, it is possible to prevent the occurrence of the defect due to the distortion error.

According to the present invention, even if an exposure apparatus and a reticle having relatively large distortion are used, Mix & Matc can be used.
The h-type exposure can be applied, and there is an effect that the efficiency of the production line can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a system LSI according to the present invention.

FIG. 2 is a view showing an exposure unit according to the present invention.

FIG. 3 is a diagram showing a functional configuration as an embodiment of an exposure control system according to the present invention.

FIG. 4 is a diagram showing a hardware configuration as an embodiment of the exposure control system according to the present invention.

5A is a diagram illustrating a measurement example of a lens distortion, and FIG. 5B is a diagram illustrating a measurement example of a reticle drawing error based on an alignment mark. FIG.

FIG. 6 is a diagram showing a schematic configuration of a stepper type exposure apparatus.

FIG. 7 is a diagram for explaining a state of alignment between a first layer and a second layer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... System LSI chip (electronic component), 1a ... Main calculation circuit, 1b ... ROM circuit, 1c ... Cache memory circuit, 1d ... AD conversion circuit, 1e ... Floating point calculation circuit,
1f: peripheral circuit, 2: exposure unit, 31: manufacturing management system unit, 311: history management system unit, 312: apparatus operation management system unit, 313: start instruction unit, 314: exposure parameter inquiry unit, 315: start operation unit , 32... Dispatcher unit, 321... Reference layer starting device inquiry unit, 322
... Startable device / correction value inquiry unit, 323 ... Operation status inquiry unit, 324 ... Start device determination unit 324, 33 ... Progress process control unit, 3315 ... Adjustment allowable accuracy map, 33
1: Mix and match calculation unit, 3311: lens distortion data, 3312: reticle drawing data, 3313:
Distortion error, 332: Exposure parameter calculation unit, 333: Reticle management system unit, 334: Correction value calculation system unit, 335: Exposure parameter database, 41: Strain database, 42: Reticle database, 43: Wafer being processed, 43a ... Area with high wiring density, 43b ...
Region with low wiring density, 43c... First-layer wiring, 43d.
Pads of the first layer, 43e...
3f: enlarged view of the area 43a, 43g: enlarged view of the area 43b, 44a: an exposure apparatus that exposed the first layer, 44b: first
A reticle used for exposing the layer; 45a: an exposure device for exposing the second layer; 45b: a reticle used for exposing the second layer;
6: correction value calculation system, 47: wafer history database, 48: design database, 49: alignment inspection device,
50: Matching inspection determination system, 51: Communication system (network).

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiharu Miwa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Production Technology Research Laboratories 5F046 AA17 AA25 BA03 DA13 DD03 DD06 EB01 EB02 ED01 FC03 FC04

Claims (7)

[Claims] 1. A method of manufacturing an electronic device having a plurality of areas having different functions and fineness within a unit of a chip or a product, wherein at least one layer among a plurality of layers constituting the chip or a product is: A setting step of setting a standard of alignment accuracy to a different value according to the fineness of each area in the layer; and at least one of distortion error factors in the chip such as a reticle drawing error and an optical aberration of an exposure apparatus. An electronic device manufacturing method, comprising: correcting a change in pattern position due to a distortion error caused by one or more of them according to an alignment accuracy standard for each area set in the setting step. . 2. The method of manufacturing an electronic device according to claim 1, wherein said exposing step includes a calculating step of calculating an alignment parameter correction value so as to satisfy said alignment accuracy standard for each area. 3. A pad or the like having a size necessary for a junction point with a previous layer or a next layer in at least one of a plurality of layers constituting the chip or the product. The method for manufacturing an electronic device according to claim 1, wherein: 4. An exposure apparatus for exposing a drawing pattern formed on a reticle having a plurality of areas having different functions and fineness within a chip or product unit to an object to be exposed, a drawing error of the reticle, and the exposure. A first storage unit for storing at least one of distortion data such as a distortion due to an optical aberration of the apparatus, a second storage unit for storing an alignment accuracy standard for each product, a process, and an area in a chip; An exposure control system comprising: an arithmetic system that calculates an adjustment parameter correction value so as to satisfy an alignment accuracy standard for each area using data in a second storage unit and presents the adjusted parameter correction value to the exposure apparatus. 5. The apparatus according to claim 1, further comprising an alignment inspection unit that corrects a result of the alignment inspection performed after the exposure according to the alignment parameter correction value calculated by the calculation system, and determines whether the alignment inspection is successful or not. 5. The exposure control system according to 4. 6. A method for manufacturing an electronic component, comprising manufacturing an electronic component using the exposure control system according to claim 4. 7. An electronic component manufactured by the method for manufacturing an electronic component according to any one of claims 1 to 3.