JP2002268662A - Method and device for receiving audio data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently conduct a processing to absorb the deviation in the sampling frequency at a receiving side employing a simple processing and a simple constitution while conducting asynchronous transmission of digital audio data. SOLUTION: Audio data which are sampled employing a prescribed sampling frequency are received. The received audio data are temporarily accumulated and a thinning of the data is conducted when the amount of data that are temporarily accumulated exceeds an overflow threshold value. When the amount of the data being temporarily accumulated becomes equal to or less than an underflow threshold value, insertion of the audio data is conducted. When a thinning or an insertion of audio data is conducted, an audio waveform consecutive processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio data receiving method and an audio data receiving apparatus applied to a receiving process when digital audio data is transmitted in a state where a transmitting side and a receiving side are asynchronous.

[0002]

2. Description of the Related Art Conventionally, digital audio data reproduced from a medium such as a CD (compact disk) and digital audio data obtained by receiving broadcast data are generally digital audio data having a fixed sampling frequency.
When transmitting the digital audio data, a clock component corresponding to the sampling frequency is transmitted simultaneously with the audio data, and the receiving side performs processing based on the received clock component (so-called synchronous transmission). Such a clock component may not be transmitted, and may be processed asynchronously between the transmitting side and the receiving side.

FIG. 5 is a diagram showing an example of a configuration in the case of performing conventional synchronous transmission. In this example, in the transmitting device 80,
An audio signal source 81 for outputting an audio signal is provided. As the audio signal source 81, for example, a radio broadcast (audio broadcast) receiving device, a tape cassette reproducing device, or the like can be considered. The audio signal output from the audio signal source 81 is supplied to an analog / digital converter 82 and converted into digital audio data having a fixed sampling frequency. At this time, for example, the clock generated by the clock generation circuit 86 in the transmission device 80 is supplied to the frequency divider 87, and a clock of the sampling frequency is generated by the frequency division, and in synchronization with the clock of the sampling frequency, The conversion operation is performed by the analog / digital converter 82.

[0004] The digital audio data output from the analog / digital converter 82 is supplied to a compression circuit 83, where the audio data is compressed and encoded for wireless transmission. The compression-encoded audio data is supplied to a modulation circuit 84, which modulates the audio data for radio transmission, and transmits the modulated radio data to
Wireless transmission. A clock for wireless transmission processing is supplied to the compression circuit 83 and the modulation circuit 84 by the clock generation circuit 8.
Supplied from 6.

[0005] A receiving device 90 that receives a radio signal from a transmitting device 80 demodulates a signal supplied to a demodulation circuit 92 via an antenna 91. The demodulated signal is supplied to a decompression circuit 93, which performs decoding for decompressing the data compressed and encoded at the time of transmission to the original data. Expansion circuit 9
As a result of the decoding in step 3, digital audio data of the original fixed sampling frequency is obtained, and this digital audio data is supplied to a digital / analog converter 94 to be converted into an analog audio signal. The converted analog audio signal is supplied to an audio output circuit 95 that performs analog processing such as amplification, and outputs audio from left and right two-channel speakers 96L and 96R connected to the audio output circuit 95.

The demodulation circuit 92 has a PLL circuit (phase locked loop circuit) 92a which is locked to a clock component included in the received data. The clock generated by the PLL circuit 92a is converted into a digital signal. /
The signal is supplied to the analog converter 94 as a clock for conversion. By doing so, the conversion cycle of the analog / digital converter 82 in the transmission device 80 and the conversion cycle of the digital / analog converter 94 in the reception device 90 can be matched with each other. So-called synchronous transmission in which the receiving side is synchronized can be performed.

It is ideal if synchronous transmission as shown in FIG. 5 can be performed. However, there are many cases where synchronous transmission cannot be actually performed. That is, for example, in the case of the transmission example of FIG. 5, it is necessary to transmit the clock component of the sample period simultaneously with the audio data, but such a clock component may not be transmitted depending on the wireless transmission system. . When the clock component of the sample frequency cannot be obtained on the receiving side, it is necessary to perform data processing such as analog conversion with reference to a clock determined by the accuracy of a crystal oscillator or the like provided in the clock generating circuit in the receiving device. .

[0008]

When such asynchronous transmission is performed and the receiving process is executed with the clock generated in the receiving apparatus, the clock frequency handled on the transmitting side and the clock frequency handled on the receiving side are different. Are difficult to completely equalize, and a slight shift occurs. This slight difference in clock frequency is basically no problem in terms of reproduction sound quality, etc., but from the viewpoint of data processing, the difference in sampling frequency between the transmission side and the reception side indicates that the data on the reception side is excessive or insufficient. Will come. That is, if the sampling frequency for performing analog conversion on the receiving side is slightly lower than the sampling frequency on the transmitting side, the amount of data stored in a buffer memory or the like gradually increases at the receiving side before analog conversion. Go. Such a problem is not a problem in a short transmission, but for example, if it is continuously transmitted for tens of minutes,
The buffer memory overflows, and the sound received and output is temporarily interrupted.

On the other hand, if the sampling frequency for performing analog conversion on the receiving side is slightly higher than the sampling frequency on the transmitting side, the amount of data stored in the buffer memory or the like at the receiving side before the analog conversion is performed. Gradually decreases, and in continuous transmission, the data stored in the buffer memory is lost and an underflow occurs.
Also, the sound received and output is temporarily interrupted.

As a technique for preventing the overflow and underflow of the buffer memory, various types of techniques have been conventionally proposed. However, the conventionally proposed processing reduces the sound quality of the sound output on the receiving side. It could not be said that the process could efficiently absorb the deviation of the sampling frequency while securing a certain level.

The present invention has been made in view of the foregoing, and has been made to make it possible to efficiently perform processing for absorbing a deviation of a sampling frequency on a receiving side with a simple processing and configuration when asynchronously transmitting digital audio data. Aim.

[0012]

According to the present invention, audio data sampled at a predetermined sampling frequency is received, the received audio data is temporarily stored, and the amount of temporarily stored data is equal to a threshold value for overflow. Is exceeded, audio data is decimated, and when the temporarily stored data amount falls below the underflow threshold,
Audio data is inserted, and when the audio data is thinned out or inserted, the audio waveform connection processing is performed.

By doing so, it is possible to prevent overflow or underflow of the storage amount when temporarily storing received data by thinning out or inserting audio data. At this time, at the time of thinning or inserting the audio data, a connection process of the audio waveform is performed, and the sound quality of the output audio is ensured.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described.
This will be described with reference to FIGS.

In this embodiment, the present invention is applied to a system for wirelessly transmitting digital audio data by asynchronous transmission. As a wireless transmission system for performing the asynchronous transmission, a wireless transmission system of a standard called Bluetooth is applied here. This standard allows transmission of voice data for telephone communications, image data for facsimile, data for computers, etc. between multiple devices at 2.4 GHz.
Wireless transmission is performed using the frequency band of z. The wireless transmission distance between the devices is assumed to be a relatively short distance network from several meters to at most about 100 m. For each type of data to be transmitted, a profile is defined which defines how the data is transmitted.

The wireless transmission system of the Bluetooth standard will be described. Such wireless transmission is one in 2.4 GHz band.
Transmission is performed on channels set at MHz intervals. However, the signal of each channel is subjected to a process called frequency hopping in which a transmission frequency is changed at a slot interval described later. If frequency hopping is performed for each slot, one slot is 625 μm.
Since it is seconds, the frequency is switched 1600 times per second, and interference with other wireless communication is prevented. As a modulation method of the wireless transmission signal, GFSK (Gaussian f
A modulation scheme called “ilterd FSK” is applied. This modulation method is a frequency shift keying method in which the frequency transfer characteristic is band-limited by a low-pass filter having a Gaussian distribution.

[0017] In the Bluetooth standard, a TDD (Time Division Duple) that basically performs transmission and reception alternately.
x) The system is applied, and processing of transmission slots and reception slots are alternately arranged. That is, as shown in FIG. 2, for example, when one device performing wireless transmission is set as a master and the other device is set as a slave, 1
The data of the slot configuration is transmitted during the slot (625 μsec) (A in FIG. 2), and the data of the slot configuration is transmitted from the slave to the master during the next one slot (B in FIG. 2). Hereinafter, the alternate transmission is repeated as long as the transmission continues. However, the frequency for wireless transmission is changed to frequency f (k), f (k + 1), f (k + 2)... For each slot as described above. Note that a plurality of slots may be continuously used depending on the transmission rate at that time. The cycle at which this slot is transmitted is a cycle set independently of the sampling cycle of audio data described later.

FIG. 3 is a diagram showing a packet structure of one slot of data wirelessly transmitted according to the Bluetooth standard. As shown in FIG. 3A, a 72-bit access code is added to the head of one packet, followed by 5 bits.
A 4-bit header is added, and the remaining section is a payload that is actual transmission data. In the case of this example, audio data is arranged in the section of the payload. The section of the payload is set to a variable length according to the amount of data to be transmitted.

The access code is composed of a 4-bit preamble and a 64-bit sync word as shown in FIG. 3B, and no data is arranged in the remaining section. As shown in FIG. 3C, the header includes an address (AM ADR) for each device, a type representing the type of payload, and bits (FLOW, FLOW,
ARQN, SEQN) and an error check bit (HEC).

For details of the Bluetooth communication system, see Bluetooth SI, a standardization body that has established standards.
G has published.

Next, the configuration of the transmitting apparatus and the receiving apparatus of the present embodiment for transmitting voice data wirelessly by such a wireless transmission method will be described with reference to FIG. In this example, the system configuration is such that an audio signal output from an audio signal source 11 built in the transmission device 10 is wirelessly transmitted to the reception device 20 and output from speakers 28L and 28R connected to the reception device 20. is there.

First, the configuration of the transmitting device 10 will be described. In the transmitting device 10 of the present embodiment, an audio signal source 11 for outputting an audio signal is prepared. Further, the audio signal source 11 may be configured separately from the transmitting device 10 and the separate audio signal source may be connected to the transmitting device 10.

The audio signal output from the audio signal source 11 is supplied to an analog / digital converter 12 and converted into digital audio data having a fixed sampling frequency. A clock supplied from the clock generation circuit 16 is used as a clock for conversion by the analog / digital converter 12. When the audio signal source 11 outputs digital audio data, the analog / digital converter 12 is not required.

The digital audio data output from the analog / digital converter 12 is supplied to a compression circuit 13 and compressed and encoded so that the audio data can be arranged in the above-mentioned payload section of the Bluetooth standard packet. Data. For example, the sampling frequency 44.1k
In order to transmit the digital audio data of two channels of 1 Hz in the packet of the Bluetooth standard described above,
It is necessary to compress the data at a transmission rate of about 00 kbps.

The compression-encoded audio data is supplied to a modulation circuit 14 to be converted into transmission data having the above-described packet structure, and the transmission data is transmitted by radio from an antenna 15 using a predetermined transmission channel. The clock generated by the clock generation circuit 17 is used for the transmission processing in the modulation circuit 14. The clock for transmission processing is asynchronous with the clock for modulation in the analog / digital converter 12, and the frequency does not have a direct relationship in the case of the present embodiment.

Next, the structure of the receiving apparatus 20 will be described. The signal supplied to the demodulation circuit 22 via the antenna 21 is demodulated by the demodulation circuit 22 and the demodulated signal is converted into a payload section of each packet. The arranged transmission data is extracted and supplied to the decompression circuit 23. Expansion circuit 2
In step 3, decoding is performed to expand the audio data compressed and encoded at the time of transmission to the original data. By the decoding in the decompression circuit 93, the original digital audio data having a constant sampling frequency, that is, audio data in units of one sample is obtained.

The demodulation circuit 22 includes a PLL circuit 22a for locking to a clock component in the received data.
The processing in the demodulation circuit 22 and the processing in the decompression circuit 23 are executed using the clock generated by the LL circuit 22a.

The digital audio data expanded by the expansion circuit 23 is supplied to a buffer memory 24 to be temporarily stored. The buffer memory 24 is a memory for accumulating audio data for a certain period of time and reading data in the order in which the audio data is normally written. In, the amount of accumulated data is constant. The audio data stored in the buffer memory 24 is transmitted to a digital signal processor (DS).
P: Digital Signal Processor) 25. DS
P25 is a circuit that can correct and process the audio waveform by digital processing. Writing and reading of data to and from the buffer memory 24 and data processing by the DSP 25 are executed under the control of the control unit 30.

The details of an example of control by the control unit 30 will be described later. For example, the audio data written in the buffer memory 24 is read out by thinning out one sample, or conversely, during one sample period written in the buffer memory 24. Can be continuously read out and one sample of the audio data is inserted. Such control of reading from the memory 24 is executed in accordance with the amount of data stored in the buffer memory 24. When such audio data is decimated or inserted, the DSP 25 executes processing for improving the connection of audio waveforms by the control unit 30.
Is executed under the control of.

The audio data processed by the DSP 25 is supplied to a digital / analog converter 26 and converted into an analog audio signal. For the conversion by the digital / analog converter 26, a clock corresponding to the sampling frequency of the audio data supplied from the clock generation circuit 29 is used. The frequency of the clock output from the clock generation circuit 29 can be finely adjusted by the control unit 30. The adjustment of the clock frequency is performed by, for example, the clock generation circuit 2.
When the reference signal oscillator in 9 is a voltage control type oscillator, the voltage applied to the oscillator is changed and adjusted. Further, when the frequency division ratio of the frequency divider for dividing the output of the reference signal oscillator can be variably set, the clock frequency may be adjusted by adjusting the frequency division ratio. Such adjustment of the clock frequency is performed, for example, in accordance with the amount of data stored in the buffer memory 24.

The clock output from the clock generation circuit 29 is also supplied to a circuit other than the digital / analog converter 26 in the receiving device 20 to a circuit requiring a clock of the same frequency. For example, for reading data stored in the buffer memory 24 and for processing in the DSP 25,
The output of the clock generation circuit 29 may be supplied.

The analog audio signal converted by the digital / analog converter 26 is supplied to an audio output circuit 27 that performs analog processing such as amplification, and a left and right two-channel speaker 28 connected to the audio output circuit 27.
The sound is output from L, 28R. Note that the audio output circuit 27 may be configured by an audio amplifier device or the like separate from the receiving device 20 in some cases.

Next, when audio data is asynchronously transmitted in such a configuration, the control unit 30 in the receiving apparatus 20 of the present embodiment will be described.
An example of processing performed based on the amount of data stored in the buffer memory 24 will be described with reference to the flowchart of FIG. First, the control unit 30 sets an appropriate range as the amount of data stored in the buffer memory 24, sets an upper limit of the range as a threshold for overflow, and sets a lower limit as a threshold for underflow. Then, the control unit 30
Determines whether the amount of data stored in the buffer memory 24 exceeds the overflow threshold (step 101). When it is determined that the amount of data stored in the memory 24 has exceeded the overflow threshold value, it is determined whether or not it can be dealt with by fine adjustment of the clock frequency (step 102). When it is determined that the clock frequency can be dealt with, the clock frequency is slightly increased (step 103).

When it is determined in step 102 that the situation cannot be dealt with by fine adjustment of the clock frequency,
A process of thinning out the audio data read from the buffer memory 24 for one sample period is performed (step 104). At this time, the DSP 25 causes the DSP 25 to execute a waveform connection process that improves the connection between the audio data waveforms before and after the thinned sample period.

When it is determined in step 101 that the amount of data stored in the buffer memory 24 does not exceed the threshold value for overflow, it is determined whether the amount of data stored in the buffer memory 24 has fallen below the threshold value for underflow. Is determined (step 105). When it is determined that the value does not fall below the underflow threshold value, the process returns to step 101 and the amount of data stored in the memory 24 is monitored.

If it is determined in step 105 that the value is below the threshold value for underflow, it is determined whether or not it can be dealt with by fine adjustment of the clock frequency (step 106). When it is determined that it is possible, the clock frequency is changed slightly lower (step 107).

When it is determined in step 106 that the situation cannot be dealt with by fine adjustment of the clock frequency,
As reading of audio data from the buffer memory 24,
Read the same sample data continuously for two sample periods,
A process for inserting one sample is performed (step 108).
At this time, the DSP 25 executes a waveform connection process such that the connection between the inserted sample period and the audio data waveforms before and after the inserted sample period becomes good.

Then, steps 103, 104 and 10
When the processes in steps 7 and 108 are completed, the process returns to the determination in step 101, and the determination of the overflow or the underflow of the memory 24 is repeatedly performed.

Steps 102 and 106
The control unit 30 determines whether to fine-adjust the clock cycle or to thin or insert the sample data based on the condition stored in the memory 24 at that time based on a preset condition. You can do it. For example,
When the storage amount of the memory 24 simply exceeds or falls below the threshold value, sample data is thinned out or inserted, and when the storage amount slightly exceeds or falls below the threshold value, the clock cycle may be finely adjusted. good. Alternatively, when the increase or decrease in the amount of data stored in the memory 24 per unit time is small or exceeds or falls below the threshold, the clock cycle is finely adjusted and the memory 2
When the data storage amount of No. 4 increases or decreases in a short time, sample data may be thinned out or inserted.

As described above, according to the present embodiment, even if the digital audio data is transmitted asynchronously, the receiving device 20 can perform a good audio output without any temporary interruption of sound. That is,
By performing the process of thinning out the sample data and the process of inserting the sample data, the amount of data stored in the buffer memory 24 is adjusted, so that the buffer memory 24 does not overflow or underflow. Temporary interruption of sound can be prevented. In this case, when the sample data is thinned or inserted, the data before and after the sample data is used to connect the audio waveforms. Therefore, even if the sample data is thinned or inserted, the sound quality of the output audio is not changed. And sound quality can be reproduced without deteriorating the sound quality.

In the case of the present embodiment, overflow and underflow of the buffer memory 24 can be prevented by finely adjusting the frequency of the clock required for audio processing of the digital / analog converter 26 and the like. The output state of the audio data on the side can be controlled well. In particular, in the present example, as described above, the adjustment process by inserting or thinning out sample data and the adjustment process by changing the clock frequency are selectively executed based on certain conditions. Appropriate processing can be selected according to the reception situation, and a good reception state can be maintained.

In the embodiment described so far,
I applied Bluetooth as a wireless network,
It goes without saying that the processing of the present invention can also be applied to wireless transmission using another similar wireless network.
In addition, the asynchronous transmission is also applicable to the case of processing audio data transmitted by wire.

The processing for changing the clock frequency includes processing for controlling the oscillation frequency of the reference signal, processing for controlling the frequency division ratio of the frequency divider in the clock generation circuit, and the like.
Various processes can be applied. When the clock frequency is changed, the clock frequency is temporarily changed so that when the data storage amount of the buffer memory no longer has the risk of overflow or underflow, the clock frequency is returned to the original clock frequency. Simple control processing may be used.

[0044]

According to the present invention, it is possible to prevent overflow or underflow of the storage amount when temporarily storing received data by thinning out or inserting voice data, and to output received voice data without interrupting sound. Becomes possible. At this time, when thinning or inserting audio data,
The connection processing of the audio waveform is performed, the sound quality of the output audio is secured, and the audio data received by the asynchronous transmission can be output well.

In this case, when the amount of temporarily stored data exceeds the threshold value for overflow, the clock frequency for analog conversion of audio data is changed to a high value, and the amount of temporarily stored data is changed to the value for underflow. When the frequency falls below the threshold value, the clock frequency for analog conversion of audio data is changed to a low value, which prevents overflow and underflow of received data during asynchronous transmission even with a change in clock frequency. It can be processed effectively.

When the amount of temporarily stored data exceeds the threshold value for overflow, the thinning-out of the audio data and the process of changing the clock frequency to a high level are selectively executed according to a predetermined condition. When the temporarily accumulated data amount becomes less than the threshold value for underflow, it is possible to selectively execute the insertion of the audio data and the process of lowering the clock frequency by determining a predetermined condition. By doing so, each process is appropriately selected and executed according to the transmission state at that time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a transmission configuration example according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating an example of a packet configuration according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating a configuration example of transmission data according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a processing example of received data according to an embodiment of the present invention;

FIG. 5 is a block diagram illustrating an example of a conventional transmission configuration.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Transmission apparatus, 11 ... Audio signal source, 12 ... Analog / digital converter, 13 ... Compression circuit, 14 ... Modulation circuit, 15 ... Antenna, 16, 17 ... Clock generation circuit,
Reference numeral 20: receiving device, 21: antenna, 22: demodulation circuit, 2
2a PLL circuit, 23 expansion circuit, 24 buffer memory, 25 digital signal processor (DSP),
26 ... Digital / analog converter, 27 ... Audio output circuit, 28L, 28R ... Speaker, 29 ... Clock generation circuit, 30 ... Control unit

Claims (6)

[Claims] An audio data sampled at a predetermined sampling frequency is received, and the received audio data is temporarily stored. When the temporarily stored data amount exceeds an overflow threshold, the audio data is received. When the amount of temporarily stored data is less than the threshold value for underflow, audio data is inserted. When the audio data is thinned or inserted, the connection of audio waveforms is performed. An audio data receiving method for performing processing. 2. The audio data receiving method according to claim 1, wherein when the temporarily stored data amount exceeds a threshold value for overflow, a clock frequency for analog conversion of the audio data is changed to a high value. An audio data receiving method for changing a clock frequency for analog conversion of audio data to a low value when the temporarily stored data amount becomes smaller than a threshold value for underflow. 3. The audio data receiving method according to claim 2, wherein when the temporarily accumulated data amount exceeds a threshold value for overflow, the thinning of the audio data is performed by a predetermined condition judgment. A process of changing the clock frequency to a high value, and selectively executing the process. When the temporarily stored data amount becomes less than the underflow threshold value, insertion of the audio data and determination of a predetermined condition are performed. And a process for selectively changing the clock frequency to a low value. 4. A receiving means for receiving audio data sampled at a predetermined sampling frequency, a storing means for temporarily storing the audio data received by the receiving means, and a voice for processing the voice data stored by the storing means. A data processing means, a reproducing means for reproducing the output audio data of the audio data processing means, and a data amount stored by the storage means, and when the determined data amount exceeds a threshold value for overflow. , The audio data processing means thins out audio data,
The connection of the audio waveforms is performed so as not to be disturbed. When the determined data amount becomes less than the underflow threshold value, the audio data processing means inserts the audio data of the audio data, and the connection of the audio waveforms is performed. An audio data receiving apparatus comprising: a control unit that performs control so as not to disturb. 5. The audio data receiving apparatus according to claim 4, wherein said control means sets a clock frequency for audio data processing of said reproduction means when said discriminated data amount exceeds a threshold value for overflow. An audio data receiving apparatus that changes the clock frequency for audio data processing of the reproducing means to be lower when the data amount is changed to a high value and the determined data amount becomes less than an underflow threshold value. 6. The audio data receiving apparatus according to claim 5, wherein the control means determines a predetermined condition when the determined data amount exceeds a threshold value for overflow.
The audio data thinning and the process of changing the clock frequency to high are selectively executed, and when the determined data amount becomes less than the underflow threshold, a predetermined condition is determined. And an audio data receiving device for performing control to selectively execute the insertion of the audio data and the process of lowering the clock frequency.