JP2002258805A - Liquid crystal display, information display device using the same, and drive method for the liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive method by which a flicker will not occur even to a low frame rate in a display panel of liquid crystal, etc., for portable use. SOLUTION: MLS4 consists of four fields and a gradation display which is one of 'on' with 7 frames is realized with 1/7 gradations of 7FRC. Data of 4 fields × 7 frames = 28 are made into series data, the data are calculated sequentially in the arrow direction and converted into voltage data, and the voltage data are outputted sequentially from a segment signal line. When 28 data are applied to pixels, the 1/7 gradations are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a liquid crystal display device capable of realizing high image quality in a transmission mode and a reflection mode, and an information device such as a portable telephone.

[0002]

2. Description of the Related Art Liquid crystal display panels are widely used in portable devices and the like because of their advantages of being thin and having low power consumption. Therefore, devices such as word processors, personal computers, televisions (TVs), and viewfinders for video cameras are used. , Monitors, etc. In recent years, a reflective liquid crystal display panel using external light as a light source without using a backlight has been adopted.

At present, liquid crystal display panels are widely used in notebook computers, portable information tools, and other amusement equipment, high-quality AV equipment, navigation systems, televisions, and the like, and their use is expected to continue to increase in the future.

[0004] As the LCD market grows, the demand for liquid crystal polarizers, which are the key materials, will further expand.

[0005]

However, a reflection type liquid crystal display panel utilizing external light has a drawback that a display image becomes extremely dark when external light is dark. On the other hand, in the case of a transmissive liquid crystal display panel, there is a drawback that a display image cannot be seen at all when the external light is bright. STN (Su
Per Twisted Nematic liquid crystal display panels and the like have a drawback that gradation display characteristics are poor. Also, if ultra low power consumption is required for mobile phones,
There is a problem that the power consumption is larger than the required power. The present invention solves these disadvantages and the like.

[0006]

The liquid crystal display panel according to the present invention mainly relates to a matrix type display device such as a simple matrix type liquid crystal display panel, and comprises a first signal line formed in the Y direction and an X direction. And a liquid crystal layer sandwiched between the first signal line and the second signal line.

[0007] In addition, multi-gradation display is mainly realized by a frame rate control (FRC) technique. The realization circuit mainly performs a shift process on the gradation register by one field or one frame signal and one horizontal scanning signal. The output is processed by a gradation processing circuit formed on each segment signal line. The output of the gradation register supplied to each of these segment signal lines is subjected to the repetition processing by the most significant bit, and the number is about half. Therefore, the chip size of the driver IC is reduced.

The present invention mainly describes a driving method (MLS: multi-line selection or MLA: multi-line addressing) for simultaneously selecting a plurality of common signal lines in a simple matrix liquid crystal display device, but is not limited thereto. However, the present invention can also be applied to an APT or IAPT driving method or a voltage swing method. However, the present invention is not limited to the frame control (FRC).
(Pulse height modulation method).

In addition, the present invention can be applied to an active matrix type liquid crystal display panel or device, or an EL display device or panel. For example, a case is shown in which an active matrix liquid crystal display panel displays multiple gradations by FRC (frame rate control) and an analog gradation display method. Naturally, PL
The present invention can be applied to a display device in which a light modulation layer such as ZT is solid.
It is needless to say that an active matrix may be a diode type (TFD) other than a thin film transistor (TFT) as a switching element.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION In the present specification, some drawings are omitted or / and enlarged / reduced in order to facilitate understanding and / or drawing. For example, in the liquid crystal display panel of FIG. 1, the substrates 11 and 12 are shown to be sufficiently thick. In FIG. 21 and the like, peripheral circuits and the like are omitted. Further, in the display device and the like of the present invention, a phase film for phase compensation and the like are omitted, but it is desirable to add the film as appropriate. The above applies to the following drawings. In addition, portions with the same numbers or symbols have the same or similar forms or materials, or functions or operations.

Note that the contents described in each drawing and the like can be combined with other embodiments and the like without particular notice. For example, a lighting unit such as a backlight can be added to the liquid crystal display panel of FIG. Further, a reflection mirror or the like may be added to configure the reflection. Others
A prism plate or the like can be added. The viewfinder can be configured using a liquid crystal display panel or a display device as shown in FIG. In addition, it can be adopted for a liquid crystal television. The matters described in the drawings and the specification of the display panel and the like of the present invention can be combined with each other without individually describing the display device and the like of the embodiment.

As described above, even if not specifically exemplified in the specification, the matters described or explained in the specification and drawings,
The contents and specifications can be described in the claims in combination with each other. This is because it is impossible to describe all combinations in a specification or the like.

Hereinafter, the liquid crystal display panel of the present invention will be described with reference to FIG. Stripe-shaped electrodes (not shown) are formed on a substrate 11 made of glass or an organic material. Examples of the glass substrate include sapphire glass, soda glass, and quartz glass. The substrate made of an organic material may be in the form of a plate, a substrate having an appropriate curved surface, or a film, and examples thereof include substrates made of epoxy resin, polyimide resin, acrylic resin, and polycarbonate resin. These are formed by integral molding by pressure. It is preferable that the plate thickness is 0.2 mm or more and 0.8 mm or less.

It is sufficient that at least one of the substrates 11 has a light transmitting property. Even if one of the substrates is made of silicon or a metal substrate of aluminum, copper, stainless steel or the like, it is made of a colored plastic substrate. May be. Alternatively, a substrate having a composite structure in which a resin film is bonded to a metal substrate may be used. Further, a configuration in which a plurality of resin films, glass, or the like is bonded to a multilayer may be employed. Alternatively, the viewing angle may be narrowed or widened by adding (applying or forming) a diffusing material (agent) to the substrate 12 or by forming appropriate fine irregularities. Further, a reflection film for reflecting light incident on the pixel may be formed directly on the substrate.

When the reflection film is used as the pixel electrode, the display panel is of a reflection type. Also, even in the case of the transmission type, I
By forming minute irregularities on the TO, the effect of improving the viewing angle and the like by changing the alignment characteristics and the like of the liquid crystal for each part is exhibited. In addition, by forming a minute reflecting portion or uneven portion with a metal film or the like in ITO serving as a pixel, an image can be recognized even in a reflection method.

A reflective pixel that reflects transmitted light is obtained by forming the pixel electrode 561 from aluminum, chromium, silver, or the like. The scattering means for scattering the transmitted light of the optical shutter means can be obtained by providing a convex portion (or an uneven portion) 562 on the surface of the pixel electrode 561 (or a striped electrode). The transmitted light is scattered by the convex portion 562.

The color filter is generally provided with a pigment dispersion type resin as a dyeing filter. The pigment absorbs light in a specific wavelength band and transmits light in a wavelength band not absorbed.

The unit area density of the projection 562 at the portion where the pixel electrode (including the stripe-shaped electrode) 561 is formed on the substrate is adjusted according to the characteristics of the color filter. The light scattering properties will be adjusted according to the characteristics of the color filters.

In the step of providing the pixel electrode 561 on the substrate, first, a photosensitive organic insulating film is spin-coated on the substrate 12 to form a projection, and aluminum is formed on the projection by sputtering. Then, silver or the like is further evaporated, and a pixel electrode (including a stripe electrode) 561 is formed by a photolithography method.

An alignment film is provided on the pixel electrode 561. A projection 562 is formed on the surface state of the pixel electrode 561 thus obtained on the liquid crystal layer side. And the substrate 1
The unit area density of the convex portion 562 in the portion where the pixel electrode 561 on the second 2 is formed is adjusted and provided in accordance with the characteristics of the color filter that is opposed.

In the step of providing a light-transmitting pixel electrode on the light-transmitting substrates 11, 12 and the like, first, a color filter is formed on the light-transmitting substrate 11 and the like using a pigment-dispersed resin by a photolithography method. I do. The color filters are arranged in a band shape. Next, a transparent flat layer (not shown) is provided on the color filter, and a translucent electrode made of indium tin oxide (ITO) is further provided on the transparent flat layer.
Further, an alignment film (not shown) is provided over the light-transmitting pixel electrode 561.

The alignment film is made of N-methyl-polyimide resin.
After printing a 5 wt% solution of 2-pyrrolidinone and curing it at 220 ° C., it is preferable to form it by performing an alignment treatment by a rubbing method using a rayon cloth so that the rubbings are antiparallel to each other.

When the pixel is of a reflection type, a metal thin film of aluminum of about 200 nm is formed by a sputtering method to form the pixel electrode 62. The projection 562 is provided on the surface of the pixel electrode 561 on the liquid crystal layer side. In the case of a simple matrix type liquid crystal display panel, the image electrodes 561 are used.
Is a striped electrode. Further, the convex portion 61 is not limited to the convex shape, but may be a concave shape. Further, the concave and the convex may be formed simultaneously.

The relationship between the unit area density of the projection 562 and the scattering property will be described. Due to the Rayleigh scattering, the shorter the wavelength of the light, the more strongly the projection 562 of the same size is scattered. Therefore, when observing a reflective liquid crystal display element having a projection on the pixel electrode 62 from a certain direction, the light intensity decreases as the wavelength of light decreases. Light scattering also varies with the number of protrusions.

The reflectance is measured by a spectrophotometer (Minolta, Inc.).
CM508) was used. The measuring method is a method of irradiating a measuring object with diffused light from all directions of a hemispherical shape and receiving light reflected in a fixed direction (a direction inclined by 8 ° from a direction perpendicular to the surface of the measuring object). is there. The reflectance R is measured in two measurement modes, one that includes regular reflection (SCI) and one that does not include regular reflection (SCE). Here, the reflectance R is a value for a standard white plate. The scattering property of the reflection characteristics was evaluated as a reflectance ratio r defined by the following equation.

R = reflectance (SCE) / reflectance (SCI) It can be evaluated that the larger the ratio r, the stronger the scattering.

The size of the projection is about 4 μm, the average value of the distance between adjacent projections is 10 μm, 20 μm, and 40 μm, and the unit area density of the projection is 10,000 to 12 respectively.
000 pieces / mm ² , 2800 to 3200 pieces / mm ² , 6
The reflectance was measured from 00 to 800 pieces / mm ² .
Then, it was found that the higher the unit area density of the protrusions, the stronger the scattering was. Therefore, it can be seen that by changing the unit area density of the protrusions on the pixel electrode 561, the scattering state can be adjusted by changing the surface state of the pixel electrode on the liquid crystal layer side.

In FIG. 56, the surface state of each pixel electrode 561 on the liquid crystal layer side is classified into three types. That is, the unit area density of the projection of the pixel electrode relative to the red color filter is set to the highest density, and the unit area density of the projection of the pixel electrode relative to the blue color filter is set to the lowest density. The unit area density of the pixel electrode protrusion relative to the green color filter is between the unit area density of the pixel electrode protrusion relative to the red color filter and the pixel electrode protrusion relative to the blue color filter. did.

As a result, the light scattering characteristics of each of the three primary colors of red, green and blue can be made equal, and a color display with good color reproducibility can be realized. The reflectance was 15% and the contrast was 10: 1.

A pixel electrode such as a stripe electrode is made of a metal material such as aluminum (Al). Further, it is made of a transparent conductive material such as ITO. Alternatively, an insulating film (not shown) is formed on these transparent materials, and electrodes are formed on the insulating film. With this configuration, a semi-transmissive film having an arbitrary transmittance or reflectance can be easily obtained by controlling the thickness of the laminated Al film. Usually, the transmittance of the semi-permeable membrane is 1
It is preferable that the content be 0% or more and 30% or less. Alternatively, a semi-transmissive film may be formed as a whole by forming one or many holes in the reflective film. It is to be noted that the insulating film formed on the ITO is formed by sputtering twice or more to prevent generation of pinholes. The reflection film or the transflective film may be an interference film formed by laminating a plurality of dielectric films.

When the electrode (striped electrode, pixel electrode) is used as a reflection film, it is preferable to form a fine projection (not shown) on the surface. The height of the projection is 0.5μ
m or more and 1.5 μm or less. Protrusions can be made by making the insulating film uneven, using color filters mixed with beads or other convex parts forming material, or by forming convex parts directly on the reflective film. it can.

FIG. 57 shows a semi-transmissive specification in which a light transmitting window is provided in the pixel electrode 561 (including the striped electrode). The hatched part in each drawing is the transmission part 571. The transmissive portion 571 may be one in which a hole is actually formed in the reflective portion (reflective electrode) 572 or one in which a reflective electrode (reflective film) is formed on a transparent electrode such as ITO.

FIG. 57A shows an example in which a plurality of short transmitting portions 571 are formed on a reflective electrode.
(B) is an example in which one transmission unit 571 is configured. FIG. 57C shows an example in which the transmission portion 571 is formed in a ring shape, and FIG. 57D shows an example in which the transmission portion 571 is formed in a plurality of short shapes.

In order to improve the heat radiation of the substrates 11 and 12,
The substrate 11 may be formed of sapphire glass. Also,
A thin film or a thick film having good heat conductivity may be formed. For example, use of a substrate on which a diamond thin film is formed is exemplified. In addition, a ceramic substrate made of alumina or the like, a metal plate made of copper or the like, or an insulating film coated with a metal film by vapor deposition or coating may be used.

It goes without saying that a plastic substrate may be used as the substrate. Plastic substrates are difficult to break,
In addition, since it is lightweight, it is most suitable as a substrate for a display panel of a mobile phone. This plastic substrate is shown in FIGS.
3 will be described.

As shown in FIG. 32, a plastic substrate for a liquid crystal display panel according to the present invention comprises a base substrate 32 serving as a core material.
1 is provided with an auxiliary substrate 322 on one side and a base substrate 32
An auxiliary substrate 323 is attached to the other surface of the substrate 1 via an adhesive to form a laminated substrate. Of course, these substrates 321 and the like are not limited to plates, and have a thickness of 0.3 m.
m or a film having a thickness of 0.05 mm or more may be used.

As shown in FIG. 33A, it is preferable to use an alicyclic polyolefin resin as the substrate 321 of the base substrate. As such alicyclic polyolefin resin, ARTON manufactured by Nippon Synthetic Rubber Co., Ltd.
A single plate is exemplified. Also, as shown in FIG.
Polyester resin, polyethylene resin, polyether sulfone resin, or the like in which a hard coat layer having a heat resistance, a solvent resistance, or a moisture resistance function and a gas barrier layer having an air resistance function are formed on one surface of the base substrate 321 An auxiliary substrate (or film or film) 322 made of

On the other surface of the base substrate 321, an auxiliary substrate (or film or film) 323 made of a polyether sulfone resin or the like on which a hard coat layer and a gas barrier layer are formed as described above is disposed. The laminated substrate is bonded together with an adhesive or an adhesive so that the angle between the optical slow axis of the auxiliary substrate 322 and the optical slow axis of the auxiliary substrate 323 becomes 90 degrees.

As the adhesive, a UV (ultraviolet) curable acrylic resin is preferably used.
Further, it is preferable to use an acrylic resin having a fluorine group. In addition, an epoxy adhesive or a pressure-sensitive adhesive may be used. It is preferable to use an adhesive or a pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. In addition, it is preferable that the difference between the refractive index of the substrate 31 and the refractive index is 0.03 or less. In particular, it is preferable to add a diffusing agent to the adhesive to function as a light scattering layer.

When bonding the auxiliary substrate 322 and the auxiliary substrate 323 to the base substrate 321, the auxiliary substrate 322
It is preferable that the angle formed by the optical slow axis of the auxiliary substrate 323 and the optical slow axis of the auxiliary substrate 323 is not less than 45 degrees and not more than 120 degrees. More preferably, the angle is set to 80 degrees or more and 100 degrees or less. By setting it in this range, the auxiliary substrate 322
In addition, the retardation of the auxiliary substrate 323 such as polyether sulfone resin can be completely canceled in the laminated substrate. Therefore, the plastic substrate for a liquid crystal display panel can be handled as an isotropic substrate having no phase difference.

According to this configuration, the versatility is remarkably expanded as compared with a film substrate or a film laminated substrate having a phase difference. That is, by combining with a retardation film, it becomes possible to convert linearly polarized light into elliptically polarized light as designed. If there is a phase difference in the substrate 11 or the like, an error from a design value occurs due to the phase difference.

Here, as the hard coat layer, an epoxy-based resin, a urethane-based resin, an acrylic-based resin, or the like can be used, and the striped electrodes or pixel electrodes also serve as the first undercoat layer of the transparent conductive film. .

As the gas barrier layer, SiO ₂ ,
An inorganic material such as SiO _X or an organic material such as polyvinyl alcohol or polyimide can be used. As the pressure-sensitive adhesive or the adhesive, an epoxy-based adhesive, a polyester-based adhesive, or the like can be used in addition to the acrylic-based adhesive described above. The thickness of the adhesive layer is 1
The thickness is set to 00 μm or less. However, in order to smooth irregularities on the surface of a substrate or the like, the thickness is preferably 10 μm or more.

The auxiliary substrate 322 and the auxiliary substrate 32
As 3, it is preferable to use one having a thickness of 40 μm or more. Further, by setting the thicknesses of the auxiliary substrate 322 and the auxiliary substrate 323 to 120 μm or less, unevenness or phase difference at the time of melt extrusion molding called die line of polyethersulfone resin can be suppressed. Preferably, the thickness of auxiliary substrate 322 is 50 μm or more and 80 μm or less.

Next, on this laminated substrate, SiO _X was formed as an auxiliary undercoat layer of a transparent conductive film, and FIG.
As shown in (c), a transparent conductive film 325 made of ITO is used.
Is formed by sputtering. The transparent conductive film 325 of the plastic substrate for a liquid crystal display panel manufactured in this manner is
Its film characteristics include a sheet resistance of 25Ω / □ and a transmittance of 8
0% can be achieved.

If this plastic substrate for a liquid crystal display panel is used, a liquid crystal display element having a duty drive of 1/200 duty and a screen size of the liquid crystal display element of up to about 6 inches can be manufactured. The panel can be mounted on a product such as a mobile phone, a pager, an electronic organizer, or a notebook computer. Of course, an active matrix panel can be formed by forming switching elements such as TFTs and pixel electrodes arranged in a matrix on this substrate.

The thickness of the base substrate 321 is 50 μm to 1
When the thickness is as thin as 00 μm, the plastic substrate for the liquid crystal display panel is curled by the heat treatment in the manufacturing process of the liquid crystal display panel. In addition, cracks occur in the ITO constituting the striped electrodes and the like, and subsequent transport becomes impossible, and good results cannot be obtained even in connection of circuit components. When the thickness of the base substrate is 200 μm or more and 500 μm or less, the substrate is not deformed, has excellent smoothness, has good transportability, has stable transparent conductive film characteristics, and has a problem in connection of circuit components. It can be implemented without. Further, the thickness is particularly preferably 250 μm or more and 450 μm or less. This is probably due to its moderate flexibility and flatness.

When an organic material such as the above-mentioned plastic substrate is used as the substrate 11, it is preferable to form a thin film made of an inorganic material as a barrier layer on the surface in contact with the liquid crystal layer. The barrier layer made of this inorganic material is made of A
It is preferable to use the same material as the IR coat.

When the barrier film is formed on the stripe-shaped electrode, it is preferable to use a low dielectric constant material in order to minimize the loss of the voltage applied to the liquid crystal layer. For example, a fluorine-added amorphous carbon film (dielectric constant: 2.0 to 2.5) is exemplified. Other, JSR
LKD series (LKD-T20) manufactured and sold by
0 series (relative permittivity 2.5 to 2.7), LKD-T4
00 series (relative permittivity 2.0 to 2.2). The LKD series is MSQ (methy-silse
It is a spin coating type based on squioxane) and has a low relative dielectric constant of 2.0 to 2.7, which is preferable. In addition, organic materials such as polyimide, urethane, and acrylic,
An inorganic material such as SiN _x or SiO ₂ may be used. It goes without saying that these barrier film materials may be used for the auxiliary substrates 322 and 323.

By using the substrates described with reference to FIGS. 32 and 33 for the substrates 11 and 12 in FIG. 1, in addition to the advantages of not breaking and reducing the weight, there is also an advantage of being able to press work. That is, a substrate having an arbitrary shape can be manufactured by pressing or cutting. Further, it can be processed into an arbitrary shape and thickness by melting or chemical treatment. For example, forming into a circle, making into a spherical shape (curved surface, etc.), or processing into a conical shape is exemplified. In addition, by the press working, at the same time as the manufacture of the substrate, unevenness can be formed on one of the substrate surfaces and the scattering surface can be formed at the same time. Further, it is easy to form a scattering surface by subjecting one or both sides of the substrate to a chemical treatment or the like.

In addition, conventionally, a sealing resin was formed around the glass substrate.
12 can be formed at the same time. The projections are made substantially the same as the thickness of the liquid crystal layer. Since the manufacturing time can be shortened by forming the sealing resin portion simultaneously with the substrate in this manner, cost reduction can be achieved. In addition, a convex portion is formed in the display area portion in the form of a dot at the same time when the substrate is manufactured. This convex portion may be formed between adjacent pixels.

Conventionally, beads of resin or glass have been sprayed on the display area in order to regulate the liquid crystal layer to a predetermined thickness. It is effective to form protrusions on the substrates 11 and 12 instead of the beads. That is, the substrates 11 and 12 are formed of a resin, and the resin is pressed to form a convex portion. Since the thickness of the liquid crystal layer is defined by the convex portions, it is unnecessary to disperse the beads. In the above embodiment, the convex portions functioning as the sealing resin and the beads are formed. However, the present invention is not limited to this.

For example, the liquid crystal portion (pixel portion) may be dug down (recessed portion) by press working or the like while leaving the portion where the convex portion such as the conventional sealing resin is formed as it is. Note that the formation of the unevenness includes a method of forming the unevenness by forming a flat substrate first and then pressing by reheating, in addition to forming the unevenness simultaneously with the substrate.

Alternatively, a mosaic color filter may be formed by directly coloring the substrate. Dyes, pigments, and the like are applied to the substrate using a technique such as ink jet printing, and are allowed to penetrate. After infiltration, dried at high temperature,
The surface may be covered with a resin such as a UV resin or an inorganic material such as silicon oxide or nitrogen oxide. In addition, a color filter is formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique of coating and developing a film with a spinner, or the like. Similarly, a black matrix (BM) may be directly formed by using a technique other than a color filter by coloring in a black color, a dark color, or a color complementary to a modulating light. Alternatively, a concave portion may be formed on the substrate surface so as to correspond to the pixel, and a color filter, a BM, or a TFT may be embedded in the concave portion. In particular, it is preferable to coat the surface with an acrylic resin. This configuration also has an advantage that the pixel electrode surface and the like are flattened and the alignment treatment of liquid crystal molecules is improved.

Further, the pixel electrode or the counter electrode may be directly formed by making the resin on the substrate surface conductive with a conductive polymer or the like. More specifically, a configuration in which a hole is formed in a substrate and an electronic component such as a capacitor is inserted into the hole is also exemplified. The advantage that the substrate can be formed thin is exhibited.

Also, by cutting the surface of the substrate,
A pattern may be freely formed. Further, the sealing opening of the liquid crystal may be sealed by dissolving the resin of the substrates 11 and 12. Further, the peripheral portion of the substrate may be melted instead of the sealing resin to replace the sealing resin, or may be used as reinforcement of the sealing resin. In other words, a peripheral portion of the substrate is melted and sealed in order to form a sealing resin and further prevent the ingress of moisture from the outside.

Further, since the substrate is made of resin, drilling is easy. Therefore, it is effective to make a hole, fill the hole with a conductive resin or the like, and make the front and back of the substrate conductive. This is because the substrate can be used as a multilayer circuit substrate or a double-sided substrate. Also, a conductive pin or the like may be inserted instead of the conductive resin. In an extreme case, it may be configured such that terminals of electronic components such as a capacitor can be inserted. Further, a circuit wiring, a capacitor, a coil, or a resistor may be formed in a thin film on the substrate. That is, the substrates 11 and 12 themselves may be multilayer wiring substrates. Multilayering is achieved by bonding thin substrates together. One or more substrates (films) to be bonded may be colored.

Further, the substrate itself can be colored by adding a dye or a pigment to the substrate material, or a filter can be formed. Also, the production number can be formed simultaneously with the production of the substrate. Further, by coloring only the portion other than the display area, malfunction can be prevented from being caused by irradiating the stacked IC chips with light. Also, half of the display area of the substrate can be colored differently. This is a plastic plate processing technology (injection processing,
Compression processing). Also,
By using a similar processing technique, half of the display area can be made to have a different liquid crystal layer thickness. Further, the display portion and the circuit portion can be formed simultaneously. It is also easy to change the substrate thickness between the display area and the driver mounting area.

Further, finely, the thickness of the liquid crystal in the central portion and the peripheral portion of one pixel can be changed. Further, a micro lens or a diffraction grating may be formed directly on the substrate so as to correspond to a pixel or a display region. In addition, irregularities that are sufficiently finer than the pixel size can be formed to improve or improve the visual range. Any shape processing, fine processing technology, etc. can be realized by the stamper technology for forming micro lenses developed by OMRON Corporation.

On the substrates 11 and 12, striped electrodes (not shown) are formed. An antireflection film (AIR coat) is formed on the surface of the substrate that comes into contact with air. When a polarizing plate or the like is not attached to the substrates 11 and 12, an antireflection film (AIR coat) is formed directly on the substrates 11 and 12. When another constituent material such as a polarizing plate (polarizing film) is attached, an antireflection film (AIR coat) is formed on the surface of the constituent material. In addition, a conductive film such as a film having a hydrophilic group, a conductive polymer film, or a metal film is coated to prevent or suppress the adhesion of dust to the surface of the polarizing plate. May be applied or vapor-deposited.

The polarizing plate is not limited to a linearly polarized light, but may be an elliptically polarized light. Further, a plurality of polarizing plates may be bonded together, or a combination of a polarizing plate and a retardation plate may be used.

The main material constituting the polarizing film is TAC film (triacetyl cellulose film)
Is optimal. This is because the TAC film has excellent optical properties, surface smoothness, and processability. For the production of a TAC film, it is optimal to produce it by a solution casting film forming technique.

The configuration in which the AIR coat is formed by a dielectric single layer film or a multilayer film is exemplified. Others 1.35-
A resin having a low refractive index of 1.45 may be applied. For example, a fluorine-based acrylic resin is exemplified. In particular, those having a refractive index of 1.37 or more and 1.42 or less have good characteristics.

The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide visible light wavelength band, and is called a multi-coat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and is called a V coat. The multi-coat and the V-coat are properly used depending on the purpose of the liquid crystal display panel. The number of layers is not limited to two or more, and may be one.

[0065] if multi coat aluminum oxide (Al ₂ O ₃₎ is an optical film thickness nd = λ / 4, zirconium (ZrO ₂₎ a nd1 = λ / 2, magnesium fluoride (MgF ₂₎ nd1 = It is formed by laminating λ / 4. Usually, a thin film is formed with λ of 520 nm or a value near 520 nm. In the case of V coat, silicon monoxide (S
iO) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4. It is formed by lamination. Since SiO has an absorption band on the blue side, it is better to use Y ₂ O ₃ when modulating blue light. In addition, Y ₂ O ₃ is more preferable from the viewpoint of stability of the substance. Further, a SiO ₂ thin film may be used. Of course, AIR using a resin with a low refractive index
It may be a coat. For example, an acrylic resin such as fluorine is exemplified. It is preferable to use an ultraviolet curing type.

In order to prevent the liquid crystal display panel from being charged with static electricity, it is preferable to apply a hydrophilic resin to the surface of the light guide plate such as a front light or the like, or the surface of the display panel 21 or the like. In addition, embossing may be performed on the surface of the substrate or the light guide plate of the front light to prevent surface reflection.

The stripe-shaped electrode is a general term for having a certain length, and is not necessarily limited to a rectangular shape. In the actual liquid crystal display panel of the present invention, the stripe-shaped electrodes are generally rectangular combinations. Therefore, it is needless to say that the stripe shape may have some arc portions, curved surfaces, deformed portions, or deformed portions. Further, the pixel electrodes arranged in a matrix are also short-shaped, so that they are striped electrodes.

As described above, the display panel of the present invention will be described by exemplifying a simple matrix type liquid crystal display panel or a display device for ease of explanation. But the material,
The configuration and the like can be applied to an active matrix type liquid crystal display panel, an organic (inorganic) EL display panel, a PLZT display panel, and a fluorescent display panel.

In FIG. 1, a segment driver (S) is mounted on the display panel 21 by chip-on-glass (COG) technology.
EG-IC) 14 and common driver (COM-I)
C) 15 are loaded. For data wiring, metal wiring such as chromium, aluminum, and silver is used. This is because a wiring having a small wiring width and a low resistance can be obtained. The wiring is made of a material constituting the reflection film of the pixel, and is preferably formed simultaneously with the reflection film. This is because the process can be simplified.

The present invention is not limited to the COG technology, but may be configured such that the above-described driver IC is mounted on the chip-on-film (COF) technology and connected to the signal lines of the display panel 21. In addition, the drive IC may be separately formed with a power supply IC and may have a three-chip configuration.

A color filter is formed or formed on the lower or upper layer of the striped electrode. Further, in order to prevent a reduction in contrast due to color mixing of color filters or light leakage from between pixels, it is preferable to form a black matrix (hereinafter, referred to as BM) made of black resin or chrome between the color filters. The color filters are formed so as to correspond to the three primary colors of red (R), green (G), blue (B) or cyan (C), magenta (M), and yellow (Y) so as to correspond to each pixel. . The planar layout includes a mosaic arrangement, a delta arrangement, and a stripe arrangement.

The color filter may be a color filter formed of a dielectric multilayer film or a color filter formed of a hologram, in addition to a color filter formed of a resin dyed with gelatin or acryl. Alternatively, a selective reflection type color filter composed of a cholesteric liquid crystal layer may be used.
Alternatively, the liquid crystal layer itself may be substituted by directly coloring it. For example, in the case of a PD liquid crystal, a configuration in which a resin is colored and a configuration in which a dye is dispersed in the liquid crystal are exemplified. Further, the liquid crystal layer may be used in the guest-host mode.

The color filter is not limited to three colors, but may be two colors, a single color, or four or more colors. For example, six colors of red (R), green (G), blue (B), cyan (C), yellow (Y), and magenta (M) may be used. The color filter is not limited to the transmission type, but may be formed of a dielectric multilayer film and may be of a reflection type. Further, a simple reflecting mirror may be used.

When a color filter is formed using a dielectric multilayer film, an optical multilayer film is formed below or above the striped electrodes to form a color filter. A color filter made of a dielectric multilayer film is manufactured by laminating a dielectric thin film having a low refractive index and a dielectric thin film having a high refractive index in multiple layers so as to have a certain range of spectral characteristics.

FIG. 1 exemplifies a simple matrix type liquid crystal display panel, but is not limited to this.
The present invention can also be applied to an active matrix type liquid crystal display panel. For example, "a color filter made of a dielectric multilayer film is formed below or on a stripe-shaped electrode" is described as a color filter made of a dielectric multilayer film below or above a pixel electrode, or above or below a counter electrode. A dielectric multilayer film color filter) is formed. "

The black matrix (BM) is used mainly for preventing light leakage between electrodes (striped electrodes and pixel electrodes). In BM, an insulating film (not shown) is formed between electrode stripe electrodes, and chromium (Cr) is formed thereon.
It may be formed of a metal thin film such as, for example, or may be formed of a resin obtained by adding carbon or the like to an acrylic resin. In addition, black metals such as hexavalent chromium, paints, thin films or thick films or members having fine irregularities formed on the surface, or light diffusion materials such as titanium oxide, aluminum oxide, magnesium oxide, and opal glass may be used. Further, the light modulation layer may be colored with a dye or a pigment which has a complementary color to the light modulated by the light modulation layer even if the color is not dark or black. Further, a hologram or a diffraction grating may be used.

For controlling the thickness of the liquid crystal layer, black glass beads or black glass fibers, or black resin beads or black resin fibers are used. In particular, black glass beads or black glass fibers are preferable because they have very high light absorption and are hard, so that a small number of particles are scattered in the liquid crystal layer.

Pixel electrodes such as stripe electrodes are made of copper,
It is composed of a metal material such as silver or aluminum (Al). In particular, in the case of a reflection type, it is preferable to use silver because of its high reflectance. In particular, it is preferable to form a metal multilayer. In this case, the uppermost layer is made of silver. The adhesion can be improved, and the reflectance can be increased.
In the case of a transmission type, the transmission type is made of a transparent conductive material such as ITO. In the case of the transflective type, an opening is formed at the center of the metal film or the like. Further, by controlling the thickness of the laminated layer of aluminum or the like, a semi-transmissive film having an arbitrary transmittance or reflectance can be easily obtained.

In the case of the semi-transmission type, the transmittance of the semi-transmission film is 1
It is preferable that the content be 0% or more and 30% or less. Alternatively, a semi-transmissive film may be formed as a whole by forming one or many holes in the reflective film. It is to be noted that the insulating film formed on the ITO is formed by sputtering twice or more to prevent generation of pinholes. The reflection film or the semi-transmissive film may be a dielectric interference film (dielectric multilayer film) formed by laminating dielectric films in multiple layers. As an example, a configuration in which a transparent electrode made of ITO or the like is formed on a dielectric interference film is exemplified.

The liquid crystal material of the liquid crystal layer is TN (Twi)
liquid crystal, STN liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, guest host liquid crystal, OCB mode (optically compensated Be)
liquid crystal, smectic liquid crystal, cholesteric liquid crystal, IPS (In Plane Switch)
ing) mode liquid crystal and polymer dispersed liquid crystal (hereinafter referred to as PD liquid crystal) are used. When displaying moving images is not important, it is preferable to use a PD liquid crystal from the viewpoint of light use efficiency. When a still image is mainly displayed, a TN liquid crystal or an STN liquid crystal is preferable.

The liquid crystal layer may be of the TN type, but it should be substantially of the STN type, having at least 100 scanning electrodes, and having a liquid crystal twist angle of 180 to 360 °. Is advantageous. Especially 230-280 °
It is preferable to use The liquid crystal composition used may be a mixture of various known liquid crystal materials. If necessary, a non-liquid crystal material having a similar structure, a dye, a chiral agent, and other additives may be added and used.

In the liquid crystal cell into which the liquid crystal is injected as described above,
Further, a polarizing film, a phase difference plate, a reflection film, and the like are arranged as necessary. In particular, the present invention is suitable for performing gradation display by time-division driving of 1/100 duty or more, and is suitable for an STN type liquid crystal display device in which the twist angle of liquid crystal is about 180 to 360 °. Furthermore, among them, ST
The present invention is also suitable for a STN-type liquid crystal display device for monochrome display in which a retardation plate or a liquid crystal cell for compensation is laminated on an N-type liquid crystal cell, or a liquid crystal display device for performing multi-color display by coloring the same.

The polarizing plate is exemplified by a resin film in which iodine or the like is added to polyvinyl alcohol (PVA) resin. Since the polarizing plates of the pair of polarization splitting units perform polarization splitting by absorbing a polarized light component in a direction different from the specific polarization axis direction of the incident light, the light use efficiency is relatively poor. Therefore, a polarized component of the incident light in a direction different from the specific polarization axis direction (reflective polariz)
(er: reflective polarizer), a reflective polarizer that performs polarization separation by reflecting light may be used. According to this structure, the use efficiency of light is increased by the reflective polarizer, and a brighter display can be performed than in the above-described example using the polarizing plate.

In addition to such a polarizing plate and a reflective polarizer, the polarization separating means of the present invention uses, for example, a combination of a cholesteric liquid crystal layer and a (1/4) λ plate, or the Brewster angle. It is also possible to use a hologram, a hologram, a polarization beam splitter (PBS), or the like that separates reflected polarized light and transmitted polarized light.

One or a plurality of phase films (phase plates, phase rotating means, phase difference plates, phase difference films) are disposed between the substrates 11 and 12 and a polarizing plate (not shown). It is preferable to use polycarbonate as the phase film. The phase film generates a phase difference between the incident light and the output light, and contributes to efficient light modulation.

In addition, as the phase film, an organic resin plate such as a polyester resin, a PVA resin, a polysulfone resin, a vinyl chloride resin, a Zeonex resin, an acrylic resin, and a polystyrene resin, or an organic resin film may be used. In addition, a crystal such as quartz may be used.
The phase difference of one phase plate is 50 nm or more and 350 in one axis direction.
nm or less, and more preferably 80 nm or more and 220 nm or less.

A part or the whole of the phase film may be colored, or a part or the whole may have a diffusion function. Further, the surface may be embossed or an anti-reflection film may be formed for anti-reflection. Also,
In places that are not valid for image display or where there is no problem,
It is preferable to form a light-shielding film or a light-absorbing film so as to tighten the black level of a displayed image or to exert an effect of improving contrast by preventing halation. Alternatively, microlenses may be formed in a semi-cylindrical or matrix shape by forming irregularities on the surface of the phase film. The microlenses are arranged so as to correspond to one pixel electrode or three primary color pixels, respectively.

The function of the phase film may be imparted to a color filter. For example, a phase difference can be generated by rolling at the time of forming a color filter, or by causing a phase difference in a certain direction by photopolymerization. Alternatively, a phase difference may be provided by applying or forming a resin on the side facing the liquid crystal layer and photopolymerizing the resin. With this configuration, there is no need to configure or dispose the phase film outside the substrate, so that the configuration of the liquid crystal display panel is simplified and cost reduction can be expected.
Needless to say, the above items may be applied to the polarizing plate. Note that a backlight is arranged on the back surface of the liquid crystal display device 21. Further, a front light may be arranged on the front. Of course, a light source such as a fluorescent tube, an LED, an organic or inorganic EL, or a light guide plate may be combined. In addition, we confine outside light (sunlight) with light guide plate,
It may be used as illumination light. Further, a transparent touch switch may be provided on the surface of the display panel.

As shown in FIG. 1, a COM driver (COM-
IC, scanning driver) 15 and SEG driver (SEG-
IC, signal driver) 14 are mounted. The COM driver outputs a selection voltage. Generally, the COM driver means a scan driver of a simple matrix type liquid crystal display panel, and is often called a gate driver in an active matrix type liquid crystal display panel.

However, the present specification is not limited to either one. The SEG driver outputs a video signal. Generally, the SEG driver means a signal driver of a simple matrix type liquid crystal display panel, and is often called a source driver in an active matrix type liquid crystal display panel. However, in this specification, it is not limited to either one.

As described above, the display panel of the present invention will be described by exemplifying a simple matrix type liquid crystal display panel or a display device for ease of explanation. But the material,
The configuration and the like can be applied to an active matrix type liquid crystal display panel, an organic (inorganic) EL display panel, a PLZT display panel, and a fluorescent display panel.

It is preferable that the SEG driver 14 incorporates a memory in the SEG-IC from the viewpoint of reducing power consumption. Of course, an external system in which the memory is formed in the controller may be used.

In order to perform large-capacity display by the STN method, line-sequential multiplex driving has been conventionally performed. In this method, each row electrode is sequentially selected one by one, and a column electrode is selected corresponding to a pattern to be displayed.
The display of one screen is completed by selecting all the electrodes.

In the line sequential driving method, it is known that a problem called a frame response occurs as the display capacity increases. In the line sequential driving method, a relatively large voltage is applied to the pixel when selected and a relatively small voltage is applied when not selected. Generally, this voltage ratio increases as the number of row lines increases (as the duty becomes higher). Therefore, when the voltage ratio is small, the liquid crystal responding to the effective voltage value responds to the applied waveform.

That is, the frame response is a phenomenon in which the off-state transmittance increases because the amplitude of the selection pulse is large, and the on-state transmittance decreases because the selection pulse period is long, resulting in a decrease in contrast. is there.

It is known to increase the frame frequency in order to suppress the occurrence of the frame response, thereby shortening the period of the selection pulse. However, this has a serious drawback. That is, when the frame frequency is increased, the frequency spectrum of the applied waveform is increased, which causes non-uniform display and increases power consumption. Also, there is a limit on the upper limit of the frame frequency to prevent the selection pulse width from becoming too narrow.

In order to solve this problem without increasing the frequency spectrum, the present invention employs a plurality of row electrodes (selection electrodes).
Are selected at the same time. This method can simultaneously select a plurality of row electrodes and independently control the display pattern in the column direction, and can shorten the frame period while keeping the selection width constant. That is,
High-contrast display with suppressed frame response is possible.

In the multiple line simultaneous selection method, a constant voltage pulse train is applied to each of the simultaneously applied row electrodes in order to independently control the column display pattern. In the driving method of simultaneously selecting a plurality of lines, a voltage pulse is applied to a plurality of row electrodes at the same time.Therefore, in order to simultaneously and independently control a display pattern in a column direction, each row electrode has a polarity. Different pulse voltages need to be applied. This set of simultaneously applied voltage pulses is referred to as a selection pulse vector. A pulse having a polarity is applied to the row electrode several times, and an effective voltage corresponding to ON / OFF is applied to each pixel in total.

A group of selection pulse voltages applied to each row electrode selected simultaneously within one address period can be represented as a matrix of L rows and K columns (hereinafter referred to as a selection matrix (A)).
Since the selection pulse voltage series corresponding to each row electrode can be expressed as a group of vectors orthogonal to each other within one address period, a matrix including these as column elements is an orthogonal matrix. That is,
Each row vector in the matrix is orthogonal to each other.

At this time, the number L of rows corresponds to the number of simultaneous selections, and each row corresponds to each line. For example, L
The element of the first row of the selection matrix (A) corresponds to the first line of the book simultaneous selection lines. Then, the selection pulse is applied in the order of the element in the first column and the element in the second column. In this specification, in the description of the selection matrix (A), 1 means a positive selection pulse, and -1 means a negative selection pulse. A voltage level corresponding to each column element of the matrix and the column display pattern is applied to the column electrodes. That is, the column electrode voltage sequence is determined by the matrix that determines the row electrode voltage sequence and the display pattern.

Voltage waveform applied to column electrode (see FIG. 2)
Is determined as follows. FIG. 3 is an explanatory diagram showing the concept. A case where a 4-by-4 Hadamard matrix is used as a selection matrix will be described as an example. The display data at the column electrode i and the column electrode j is shown in FIG.
Assume that it is as shown in FIG. The column display pattern is represented as a vector (d) as shown in FIG.
Here, when the column element is -1, on display is shown, and 1 indicates off display.

Assuming that row electrode voltages are sequentially applied to the row electrodes in the order of the columns of the matrix, the column electrode voltage level is as shown in FIG.
The waveform becomes like a vector v shown in FIG.
(C). In FIG. 3C, the vertical and horizontal axes are arbitrary units.

In the case of partial line selection, in order to suppress the frame response of the liquid crystal display element, it is preferable to apply a voltage by dispersing the selection pulse within one display cycle. Specifically, for example, after applying the first element of the vector v to the first simultaneously selected row electrode group (hereinafter, referred to as a subgroup), the second simultaneously selected row electrode The first element of the vector v for the electrode group is applied, and the same sequence is performed thereafter.

Therefore, the voltage pulse sequence actually applied to the column electrodes depends on how the voltage pulses are dispersed in one display cycle, and what kind of selection matrix is applied to the simultaneously selected row electrode groups. It is determined by whether (A) is selected.

According to the present invention, the frequency component is prevented from becoming too large when the image display device is driven by the simultaneous selection method for a plurality of rows, and is particularly remarkable when gradation display by frame rate control is performed. The occurrence of flicker can be suppressed. In addition, it is preferable to appropriately invert the polarity of the drive signal because the frequency component can be easily controlled. In the present invention, inversion can be performed at a cycle that is an integral multiple of a repeating unit. Further, in the present invention, since the cycle of the repeating unit is short, the degree of freedom of the inversion timing is increased.

Basically, positive and negative alternating signals are applied to the liquid crystal layer for each field. The reason why the positive or negative voltage is applied for each field in this manner is to suppress the deterioration by applying an AC voltage to the liquid crystal. However, a simple matrix type liquid crystal display panel often employs nH inversion driving for inverting the polarity of a signal applied for each of a plurality of scanning lines, instead of applying an inverted signal for each field. n indicates the number of each set to be inverted. For example, 11H inversion means inverting the signal polarity from the segment driver for every 11 scanning lines. There is no concept of a field in the nH inversion drive.

MLS driving with four simultaneously selected lines (hereinafter referred to as MLS driving)
MLS4), when the number of scanning lines is N, M =
It is preferable that the relationship between N / 16 (where M is an integer rounded down to the decimal point) and n in the nH inversion drive satisfy the following relationship.

M-1 ≦ n ≦ M + 5 (Equation 1) Further, it is particularly preferable to satisfy the following relationship.

M + 1 ≦ n ≦ M + 3 (Equation 2) By satisfying the above relationship, flicker hardly occurs. The effect is particularly remarkable when the frame rate (the number of times of rewriting the screen per second) is 50 or less.

In the MLS4 drive, the driver IC on the SEG side is used.
Outputs five levels of voltage. Now, this voltage is + V
2, + V1, V0, -V1, and -V2. The voltage on the SEG side is called an SEG voltage. These voltages are created by multiplying (multiplying) the reference voltage by a DCDC converter or the like.

It is known that a liquid crystal such as an STN liquid crystal has a temperature-dependent characteristic (temperature characteristic). In order to adjust the contrast change due to the temperature characteristic, a non-linear element such as a thermistor or a posistor is added to a reference voltage generating circuit or the like, and the change due to the temperature characteristic is adjusted by the thermistor or the like to create an analog reference voltage. . This reference voltage is integer-multiplied by a DCDC converter or the like to generate an SEG voltage.

In the present invention, various shift processes are performed to suppress the occurrence of flicker. Hereinafter, a driving method and the like of the present invention will be described with reference to the drawings.
Note that for the sake of simplicity, L = 4 (C selected at the same time)
The number of selected OM signal lines is four, that is, MLS4 drive is described.) However, the present invention is not limited to this, and L may be 2 or 4 or more.

The present invention is different from the MLS drive generally called. Therefore, it is not a conventional MLS drive. As described with reference to FIG. 5, this is because driving other than MLS driving is realized. It goes without saying that a conventional MLS drive may be realized as the drive method. In this specification, for ease of explanation, FIG.
Will be described as the MLS4 for the moment.

In the MLS4, one frame is composed of four fields (see FIG. 4). Scanning is performed four times from the top to the bottom of the screen. In the MLS4, four common signal lines are simultaneously selected for scanning. In the frame rate control (FRC), one gradation is expressed by a plurality of frames. For example, in FIG. 4, one gradation is displayed in six frames. In addition, the length of a frame is represented by a denominator in the representation of one gradation, and the number of frames to be turned on is represented by a numerator. For example, in FIG. 4, since one is on in six frames, it is expressed as 1/6. Hereinafter, the shift processing will be described in detail with reference to the drawings.

As described above, as one of the gray scale display methods, there is a frame rate control method (FRC) in which a plurality of frames are used and a column voltage is controlled for each frame to perform a gray scale expression. Hereinafter, FRC will be described first.

FIG. 73 (a) shows an example in which the first gradation out of eight gradations is expressed.
This can be displayed by displaying the frame. However, there is a problem that flicker occurs when the number of gradations is increased by this method. Therefore, there is a method of suppressing flicker by shifting the timing of ON and OFF for each pixel and adjusting the ratio of the ON pixel and the OFF pixel to the number of gradations spatially. FIG. 73B shows a pattern that realizes this.

In this method, for example, when expressing the Mth gray level among the N gray levels, the first row turns on the M columns in order from the first column, and turns off the next (N−M) columns. On and off are repeated at this rate until the last row. In the second row, the data in the first row is shifted by a certain value L and displayed in order to disperse the on / off pixels. Hereinafter, the display is shifted by L for each line. The shift amount L at this time is defined as a line shift. This makes it possible to spatially disperse the ON / OFF.

Further, the on / off state is temporally dispersed. 1
The data in the first column of the second frame is shifted and displayed by a certain value F in the same manner as the line shift with respect to the data column in the first column of the frame. The shift amount F at this time is defined as a frame shift.

Similarly, in the third and subsequent frames, a pattern shifted by F from the first data row of the previous frame is displayed. The second and subsequent columns of each frame are displayed with a line shift similarly to the first frame. FIG. 73B is an example in which the first gradation of eight gradations is expressed using the line shift L (= 1) and the frame shift (= 3).

Although the description is made here with 7 rows and 7 columns,
On a large screen, these 7 rows and 7 columns may be arranged vertically and horizontally to spread them. In all frames, the proportion of ON pixels is the same. Looking at a certain pixel, for example, 173 pixels, OFF / OFF / ON /
It is off-off-off-off and expresses one of eight gradations.

In the case of performing gradation expression by FRC (Frame Rate Control), when the number of display gradations increases, there occurs a gradation in which the ratio of the number of times of on to the number of times of off becomes small, so that flicker is likely to occur. There is a method of reducing flicker by increasing the frame rate, but power consumption increases.

For example, while gradation is expressed by 7 frames in 256-color display, 15 frames are required in 4096-color display. To simply make the flicker level the same, the frame rate must be approximately doubled. Must.
On the other hand, the power supply of mobile terminals such as mobile phones is limited, and it is required to reduce power consumption. Further, a circuit for preventing flicker needs to be simple in view of a demand for a narrower frame of the display device and cost reduction.

As described above, the conventional simple matrix liquid crystal display panel driving method includes FRC (frame rate control). Also known are APT, IAPT, and power swing method. When 1/6 is expressed by the FRC driving method, it is expressed as shown in FIG. Further, in the MLS4, it is expressed as shown in FIG. FIG. 5B shows a conventional MLS drive.

However, in the present invention, the ON position is shifted between fields as shown in FIG. Therefore, 4
The effective value obtained by adding the two fields is not the effective value of the on-voltage. The MLS 4 has an effective value obtained by adding four fields becomes an ON voltage or an OFF voltage (the sum of products becomes a predetermined effective value). In FIG. 5C, there is only one-fourth of the ON voltage in the first to fourth frames. That is, the sum of products is different from 1F to 1F, and the effective value is not the ON voltage or the OFF voltage.

However, in the present invention shown in FIG. 5C, when the 1/6 gradation expression is executed for one cycle, the ON voltage is performed once and the OFF voltage is performed five times, and the APT shown in FIG. The same effective value is applied to the liquid crystal layer. Therefore, a predetermined effective value is applied as a whole (entire 1/6 gradation), and a desired gradation expression can be realized.

In the present invention, the ON position is shifted for each frame as shown in FIG. 6A, and shifted for each field as shown in FIG. 6B. In the present invention, since the shift method is positive in the left direction, the frame shift amount in FIG. 6A is -2, the field shift 1 in FIG. 6B is -2, the field shift 2 is -4, Field shift 3 is expressed as -6.

Further, as shown in FIG.
Four line shifts of 4 can be performed. The line shift is expressed based on the state position one line before. In the case of FIG. 7, the line shift 1 is expressed as -1, the line shift 2 is expressed as -1, the line shift 3 is expressed as -1, and the line shift 4 is expressed as -2. By performing the line shift of FIG. 7, flicker is greatly reduced. In the MLS4, arithmetic processing is performed four rows at a time, but in the present invention, shift processing is performed one row at a time.

The shift processing is performed separately for red (R), green (G), and blue (B). This is called an RGB shift. This RGB shift is based on the R position. Therefore,
In FIG. 8, the G shift is expressed as -1, and the B shift is expressed as -3. In FIG. 7, if the line shift 1 is set to 0, the line shift 2 is set to 0, the line shift 3 is set to 0, and the line shift 4 is set to -1, the anti-flicker measure shown in FIG. 9 can be performed.
Since flicker can be suppressed even at a low frame rate, low power consumption can be achieved.

The frame rate control (FRC) is a method of expressing gradation by using a plurality of frames and controlling a column voltage for each frame. However, there is a problem that flicker occurs when the number of gradations is increased by this method. Therefore, there is a method of suppressing flicker by shifting the timing of ON and OFF for each pixel and adjusting the ratio of the ON pixel and the OFF pixel to the number of gradations spatially.

FIG. 59 shows a pattern which realizes this. In this method, for example, when expressing the Mth gray level of the N gray levels, the first row turns on the M columns in order from the first column,
The next (N-M) column is turned off, and on and off are repeated at this ratio until the last column. In the second row, the data in the first row is shifted by a certain value L and displayed in order to disperse the on / off pixels. Hereinafter, the display is shifted by L for each line. The shift amount L at this time is defined as a line shift. This makes it possible to spatially disperse the ON / OFF. Next, the on / off state is temporally dispersed. The embodiment of FIG. 59 shifts four rows simultaneously and again by the same amount.
This is an example in which each row is shifted by one dot.

With respect to the first data string of the first frame,
The data in the first column of the second frame is displayed after being shifted by a certain value F, similarly to the line shift. The shift amount F at this time is defined as a frame shift. Similarly, in the third and subsequent frames, a pattern shifted by F from the first data row of the previous frame is displayed. The second and subsequent columns of each frame are displayed with a line shift similarly to the first frame.

FIG. 72 is a functional block diagram according to the first embodiment of the present invention. According to the present invention, the grayscale register of the grayscale data shift circuit 211 for outputting FRC data is supplied with a horizontal synchronization signal (HD) and / or a vertical synchronization signal (V).
D), and a gradation control circuit 106 for selecting a gradation register output by an input video signal (DATA).

[0133] Multi-Line-Selecti
In the on method (hereinafter, referred to as MLS), an input unit S and an orthogonal function H generated by the orthogonal function ROM 113 are subjected to an H × S matrix operation by a calculator 711 as shown in FIG.

The output of the segment signal line is changed in accordance with the value obtained as the result of the H × S operation, and on / off display is performed by the voltage applied between the common signal line and the segment signal.
The number of columns of the orthogonal function H is the number of common signal lines, and has a value of 1 or −1 when a common signal is selected, and has a value of 0 when not selected.

Therefore, in the case of simultaneous selection of N rows, the orthogonal function is 1
Since the row has N 1s or −1s, at least N row data of the input signal S is required for the calculation of H × S.
As a result, the input signals are for the number of simultaneously selected common signal lines N rows,
Input at the same time.

The input video signal of the gradation selection circuit 202 shown in FIG. 72 is simultaneously inputted to N rows, and if all the N rows have the same gradation, the same gradation register output is selected. The reason why N rows are input simultaneously is to reduce the power consumption by lowering the main clock. Of course, the processing may be performed serially for each dot.

FIG. 70 shows a gradation selection circuit 202 according to the present invention.
Of FIG. In FIG. 70, white circles indicate ON-state pixels, and oblique lines or black circles indicate OFF-state pixels.
The horizontal direction is called a column. The vertical direction is called a line.
Note that the following embodiment is an explanation of the shift processing, so that ON may be replaced with a black circle and OFF may be replaced with a white circle. The same applies to the other drawings.

In FIG. 70, the 4-line simultaneous selection method is used,
The first gradation in the gradation is displayed on the entire screen. Since the four lines are selected simultaneously, the same on / off pattern is set for each of the four lines, and the pattern is shifted for each set of four lines having different input times. FIG. 59 shows a wider view.

By adjusting the shift amount for each four lines (line shift) and the shift amount for each frame (frame shift) by this method, the frame shift is set to 3 or 5 and the line shift is set to 3 or 5 in 8-gradation display. If set to any one, flicker can be eliminated at a frame frequency of 120 Hz.

If ± V2 occurs among the five segment output values, the image quality tends to deteriorate. For example ± V2 and V
When an image is displayed only with c, flicker due to interference with a 50 Hz fluorescent lamp is likely to occur.

In the gradation display method of the present invention, by taking the orthogonal function as shown in FIG. 69, when the entire screen has the same gradation, the on / off data is on for all four rows or is off for all four rows. Therefore, the calculation result of the orthogonal function is 2 or -2 for any shift amount.

In general, the result of the operation is 4, 2, 0, -2,-
There are five ways of 4; 4 is the voltage value V2 (= 2 × V1), 2
Is applied to the segment signal line as V1, 0 is Vc, -2 is -V1, and -4 is -V2. Therefore, in the embodiment of FIG. 70, ± V2 does not occur, and display with little deterioration in image quality is possible. Further, there is no need to add a circuit that does not generate ± V2, and the circuit scale can be reduced accordingly.

FIG. 68 is a diagram showing an FR according to another embodiment of the present invention.
9 shows an image pattern at C. 70 is different from FIG. 70 in that it has at least two types of line shifts, and can take different values as the line shift A3 and the line shift B4. In the case of simultaneous selection of four lines, a value to be shifted every four lines can be individually set.

In the case of the above configuration, the ON pixels are arranged obliquely and regularly in FIG. 70 by making the values of 3 and 4 different from each other. The more random, the smaller the occurrence of flicker even if the frame rate is reduced.

Also in the embodiment of FIG. 68, the four lines take the same on / off data. Therefore, V2 does not occur (when the screen is in a uniform display state such as a halftone white raster). Since the line shift has two types of A and B, a register for holding the two types of line shift values and a circuit for determining which of A and B to execute are added, which leads to a slight increase in circuit scale. The frame rate can be lower than in FIG.

FIG. 67 is a block diagram showing a gradation process according to another embodiment of the present invention. The difference from FIG. 72 is that a RAM is provided which holds the shift amount of at least one of the even rows and the odd rows in the N rows. Further, a shift amount holding RAM 651 composed of a RAM for holding the shift amounts of the line shift and the frame shift is provided. It is to have a microcomputer 652 for rewriting the RAM 651.

Thus, the controller 104 uses the horizontal synchronizing signal and the vertical synchronizing signal to store the shift amount holding RA.
Any one of the shift amount data is received from the M651, and based on this data, the gradation data shift circuit 21
Shift the register in 1. With this configuration, different register outputs can be obtained for even-numbered rows and odd-numbered rows in the set of N rows.

FIG. 66 shows another embodiment of the present invention. In this example as well, the four-row simultaneous selection method of N = 4 is used, and the first gradation out of eight gradations is displayed. In the first and second embodiments, the shift is performed every four rows. In this embodiment, in addition to the shift performed every four rows, different on / off data is obtained in even and odd rows among the four rows. . In FIG. 5, even lines are shifted with respect to odd lines, and this is referred to as even line shift 51.

In an 8-gradation display, if the even-numbered line shift is set to any one of 1 to 4, the frame shift is set to 3 or 5, and the line shift is set to 1, 2, 5, or 6, even at a frame frequency of 80 Hz. The effect that flicker did not occur was obtained.

When four gradations are displayed, the even line shift may be set to 2 or 3, the frame shift may be set to 1, and the line shift may be set to 1 to 3. The four-gradation display is obtained by taking four of the eight-gradation displays, and there are commonly used gradations, but it has been found that the optimum shift amount changes depending on the number of gradations. Therefore, as shown in FIG. 65, the value of the shift amount holding RAM 651 can be changed according to the number of display gradations, and the optimum shift is performed according to the number of display gradations.

It was also found that the optimum line shift and the shift amount in the set for every N rows differed depending on the frame frequency. For example, comparing the case where the frame rate is 80 Hz and the case where the frame rate is 120 Hz, the optimal line shift and the like differ by two or three shift amounts. Therefore, similarly to the number of gray scales, if the frame frequency is less than 70, 70
The microcomputer 652 may be used when the frequency is 120 Hz or more and less than 160 Hz, or when the frequency is 160 Hz or more.
Thus, the value of the shift amount holding RAM can be changed. That is, the shift amount and the like are changed in a range of at least two or more frame frequencies. Note that the shift amount may be changed stepwise or may be changed continuously.

Further, it is preferable that the amount of frame shift be made different depending on the response speed of the liquid crystal material. The microcomputer 652 can change the value of the shift amount holding RAM when the liquid crystal response speed is 150 msec or more and 150 msec or less. The response speed is obtained by adding the rise time and the fall time at normal temperature.
The method for measuring the response speed is determined in the liquid crystal field.

In this case, since it is uniquely determined by the liquid crystal material to be selected, it is often unnecessary to perform software control of the microcomputer 652 or the like. That is, a fixed shift amount may be fixed by a liquid crystal material. What is important is that there is an optimum shift amount depending on the response speed of the liquid crystal material, and it is important to select this optimum shift amount.

What needs to be changed by software is temperature dependency. As the temperature of the liquid crystal material increases, the viscosity decreases and the response time increases. It is also said that it is generally proportional to the square of the changed temperature. Therefore, the temperature of the liquid crystal display panel is measured by the temperature sensor, and the shift amount is changed by the microcomputer 652 or the like according to the measured temperature. The shift amount may be changed stepwise or continuously.

The above-described matter of changing the shift amount depending on the temperature dependency, the frame rate, and the like also applies to other shift methods and types. For example, all shift methods such as a field shift and an RGB shift are used.

In the description, ML for simultaneously selecting four rows
Although S4 has been described as an example, the present invention is not limited to this. For example, MLS8 for simultaneously selecting eight rows, MLS7 for calculating one row as a virtual row, and MLS2 for simultaneously selecting two rows. It goes without saying that the MLS method may be used. Needless to say, these items also apply to other embodiments.

When gradation expression is performed by FRC, gradation expression is performed based on the difference in average luminance of pixels in several frames. When used as a liquid crystal display device, the degree of occurrence of flicker changes depending on the response speed of the liquid crystal. In particular, when the response speed is in the range of 50 msec to 120 msec, the ON frame and the OFF frame clearly change. Therefore, vertical streaks due to interference with other gradations are likely to appear.

In particular, interference with other gradations affects all pixels on the segment line where the interference has occurred, and the image quality is more significantly reduced than flicker. Therefore, a changeover switch 653 is provided outside the gradation control block in FIG.
A response speed of 50 to less than 120 msec, a response speed of 120 to less than 300 msec,
The microcomputer 652 is configured to rewrite the value of the shift amount holding RAM 651 so as to have a different shift amount in the case of 00 msec or less.

For example, in the case of line shift, the response speed 13
For a liquid crystal of 0 to 300 ms, 1 or 2 is preferable, and for a liquid crystal of 50 to 120 ms, 3 or 4 is preferable. For a liquid crystal of 120 to 300 ms, 2 to 3 or 5 is preferable. This makes it possible to display an image with an optimum shift amount with little interference and flicker according to the response speed of the panel to be displayed.

In addition, as a method for shifting on / off in four rows, the methods shown in FIGS. 63, 62, and 61 can be considered.
FIG. 63 shows a method of rewriting the value of the shift amount holding RAM 651 in the case of an odd-numbered column and shifting the odd-numbered column in the case of an odd-numbered column. In FIG. 62, it is described as 2-3 line shift for shifting a few rows. FIG. 61 shows an example of 3-4 line shift for shifting three or four rows.

In FIG. 62, instead of two or three columns, one and four columns may be shifted (1-4 line shift). In FIG. 61, even if the first and second columns are shifted, (1-
The same effect can be obtained. A shift method effective for flicker differs depending on the values of the line shift 3 and the frame shift 4. It is necessary to combine adjacent pixels so that they have different on / off data.

In any of these methods, when the same gradation is displayed on the entire surface of the data of four rows, the shift ratio is such that the on / off ratio becomes 4: 0, 2/2, or 0/4. This is the method. In the case of this combination, when the orthogonal function of FIG. 69 is used, scanning is performed only with the voltage of ± V1 as a result of the MLS operation. Therefore, the display can be performed without generating the potential of ± V2, and the FR that can display the low frame frequency can be used.
This is a C gradation display method.

Further, for random arrangement in a frame,
A circuit for detecting the number of sets for each N rows is provided, and the value of the shift amount holding RAM 651 is rewritten according to the number of sets for each N rows, thereby changing the shift amount of the row to be shifted within the set for each N rows. There is a way to make it happen.

For example, as shown in FIG. 60, there is a method of changing the amount of even-numbered line shift every four rows. In the example of FIG. 60, the shift amount is 3 for odd-numbered blocks, and the shift amount is 5 for even-numbered blocks. The ON pattern shifted within N rows as compared with FIG.
Although it is possible to take a completely different shift amount in each block, the number of registers for storing the shift amount increases, and the circuit scale increases.

In practical use, the pattern of the shift amount is 2 to 4 in consideration of the effect of reducing flicker and the circuit scale.
Is desirable. In FIG. 60, the even line shift has been described.
A similar effect can be obtained with 3-4, 1-4, and 2-3 line shifts.

Hereinafter, a field shift in which grayscale data is shifted to a subfield in MLS driving will be described. The present invention also relates to a driving method in which flicker hardly occurs even at a low frame rate by performing a shift process. Note that the field shift deviates from the concept of the MLS drive. Therefore, although not MLS driving, description will be made as one type of MLS for ease of description.

The field shift is a driving method for driving a display panel in which one frame is composed of L subframes by a driving method for simultaneously selecting a plurality of (L) scanning electrodes. The gray scale display method is FRC, and a gray scale register for storing a gray scale pattern indicating on / off of each gray scale level, a gray scale control circuit for performing a shift operation on the gray scale pattern of the gray scale register, and A gradation selection circuit provided for the signal line. The gradation control circuit performs a shift operation on the gradation pattern of the gradation register for each frame in synchronization with the vertical synchronization signal, and performs a shift operation on a line basis in synchronization with the horizontal synchronization signal. Also performs a gray scale display by performing a shift operation process.

In the MLS4, as shown in FIG.
To the fourth subframe (subfield). A gradation display in such an MLS driving method will be described. As one of the gradation display methods, there is a frame modulation method (FRC) that performs gradation display by controlling on / off for each frame using a plurality of frames.

FIG. 92 shows an example of a frame modulation method in the case of eight gradation display. In the case of eight gradations, as shown in FIG. 92, gradations are displayed in eight gradation patterns from 0/7 to 7/7 by using on / off of seven frames. White circles on, a black circle represents a frame of off. Since gradation display is performed using a gradation pattern of seven frames, it is called 7FRC.

However, since 0/7 is all off, basically no FRC processing is required. Also, 7/7
Is basically on, so basically no FRC processing is required. However, it is described for ease of explanation. Therefore, it is unnecessary when realizing an actual hardware configuration. The above description is the same in other embodiments.

To realize the gray scale display by the frame modulation method by the MLS driving method, for example, in the case of 1/7 gray scale display, the frame shift is performed as shown in FIG.
In the first to fourth sub-frames, gradation display is performed using the same gradation pattern shown.

In the case of performing the gray scale display by the frame modulation method (FRC), when the number of display gray scales increases, a gray scale in which the ratio of the number of times of on to the number of times of off becomes small occurs, so that flicker is easily generated. There is a method of reducing flicker by increasing the frame rate, but power consumption increases. For example, while 256-color display can display gradations in 7 frames, 4096-color display requires 15 frames, and the frame rate must be approximately doubled to simply keep the same flicker level. .

On the other hand, power consumption of mobile terminals such as mobile phones is limited, and it is required to reduce power consumption. Further, a circuit for preventing flicker needs to be simple in view of a demand for a narrower frame of the display device and cost reduction.

In the field shift, the shift amount is determined based on the position of the first field. In the embodiment of 1/7 gradation shown in FIG. 75, the shift of the second field is 2, and the shift of the third field is 3
The shift amount of the field is 1, and the shift amount of the fourth field is 5. Therefore, the shift amount of the field shift in FIG. 75 can be expressed as (2, 1, 5).

FIG. 75 shows an MLS having four subfields.
4. It is needless to say that the present invention is not limited to the MLS 4 but can also be applied to the MLS 2 that performs two field processes as shown in FIG.
In FIG. 76, the shift amount of the second field is 2.

FIG. 75 shows that the interval of the shift amount is not unique in each field. In order to prevent interference with other colors or gradations, it is preferable to make the shift amount regular as shown in FIG. FIG. 77 shows that the shift amount of the second field is 2, the shift amount of the third field is 4, and the shift amount of the fourth field is 6. That is, the shift change rate (interval) is 2 in each field. The shift amount of the field shift in FIG. 77 can be expressed as (2, 4, 6).

FIG. 77 shows a case where the interval between the shift amounts of the field shift is two. As another regularity, the method shown in FIG. 78 is also effective for flicker suppression. FIG. 78 shows an example in which the even field has a predetermined shift amount with respect to the odd field.

The shift amount of the even field (the second field and the fourth field) is 4 with respect to the odd field (the first field and the third field). Of course, this relationship may be reversed. In the embodiment of FIG. 78, the shift amount can be represented as (4, 0, 4).

In the above embodiment, the number of molecules for gradation expression is 1 (for example, 1/7 in FIG. 78). However, as a matter of course, even if the number of molecules is 2 or more as shown in FIG. Field shift can be performed. The field shift in FIG. 79 can be expressed as (2, 4, 6) with a gradation of 2/7.

FIG. 80 shows the case of the MLS 8 in which the number of simultaneous selections is eight. The shift amount of the second field is 2, and the shift amount of the third field is
The shift amount of the field is 1, the shift amount of the fourth field is 5, the shift amount of the fifth field is 0, the shift amount of the sixth field is 2, and the shift amount of the seventh field is 1 And the shift amount of the eighth field is 0. Therefore, the shift amount is (2, 1, 5,
0, 2, 1, 0).

FIG. 81A shows a フ ィ ー ル ド gradation field shift. The shift amount is (1, 2, 3). FIG. 81
(B) is a field shift of 1/12 gradation. The shift amount is (2, 4, 6). As described above, the field shift can be determined for each gradation. However, it is preferable that the shift amount be the same between the displayed gray scales because of the problem of interference with other gray scales and slight deviation of the effective value. For example, in the 1/4 gradation field shift in FIG. 81A, the shift amount is (1, 2, 3).
In this case, the shift amount of the field shift of the 1/12 gradation in FIG. 81B is also (1, 2, 3).

FIG. 91 shows an embodiment in which the field shift of each gradation is the same. FRC of 16 gradations (15F
RC). The full gradation expression is shown in FIG. Of the gradations in FIG. 1/12, No. 1 1/6, No. 3 4
1/4 of FIG.

The shift amounts of the gradation shift patterns of FIGS. 91 (a), (b) and (c) are all (5, 0, 5).
The expression for shift 5 in (c) may be difficult to understand.
Because the denominator is 4. The shift amount is counted in the right direction, and returns to the left end when counted to the right end. Therefore, FIG.
1 (c).

The shift amount is the same for each gradation. If the shift of 1/12 in the second field is 5,
All gradations are set to 5. If it is 3 in the third field, it means that it is 3 for all gradations.

As described above, when the number of simultaneously selected scanning lines is L, if the (L-1) shift amounts for each sub-frame are set to the same value at each gradation level, even if the shift amount between sub-frames is the same. It has been found that even if the tone pattern changes, flicker can be suppressed without causing display unevenness due to a shift in the effective value voltage applied to the liquid crystal.

In particular, it is most preferable that the shift amount be 5 in FIG. As can be understood from FIG. 91 (a), it is preferable that the shift position of the even field is shifted by the odd field in the next field. Therefore, the on-data position follows the even-numbered and odd-numbered positions in synchronization with the field.

For example, in FIG. 91 (a), in the first frame, there is ON data at six column positions of the even field. In the next second frame shown in FIG. 91 (b), the odd field has ON data at 6 column positions, and the even field has ON data at 11 column positions. In the third frame of FIG. 91 (c), the even field is shifted by 5 columns as compared with (b), and there is ON data at the position of 3 columns from the left. In FIG. 91 (d), the odd field has ON data at three column positions, and the even field has ON data at eight column positions.

As a result of the evaluation, the shift amount of the field shift is (5, 0, 5) or (5, 5, 5) or (5, 5, 5).
5,5), the best image display could be realized without interference with other gradations, and no flicker occurred even when the frame rate was lowered.

The gradation display shown in FIG. 58 has 16 gradations (4096).
When driving a liquid crystal display panel of (color) display, the least common multiple of the number of frames forming a gradation pattern representing ON / OFF of each gradation level is 24. The shift amount for each frame at each gradation level is set to 5, and the (L-1) shift amounts for each subframe having the same value at each gradation level are set to 5 or 0. 2,3,4,6 which is a divisor of 24
Displaying 16 gradations using 8, 12 frames gives 15
Since the number of frames is smaller than in the case of frames, generation of flicker can be suppressed even at a lower frame frequency.

The shift amount for each frame that can be set in each FRC is 2 FRC: 1 (, 3, 5,...), 3 FRC:
1,2 (, 4,5, ...), 4FRC: 1,3 (,
5,...), 6 FRC: 1, 5, 8 FRC: 1, 3,
5, 7, 12 FRC: 1, 5, 7, 11, so that the shift amount for each frame can be commonly set for each gradation level of either 1 or 5, but the shift amount for each frame is 1 In this case, a gradation flow is likely to occur. If the same value is set, 5 is optimal. In addition, when the shift amount for each sub-frame having the same value at each gradation level is set to 5 or 0, interference between the gradations is reduced even in 16-gradation (4096 colors) display, and even when the frame frequency is reduced to 60 Hz. And flicker can be suppressed.

As described above, when the number of simultaneously selected scanning lines is L, if the (L-1) shift amounts for each sub-frame are set to the same value at each gradation level, even if the shift amount is between sub-frames, It has been found that even if the tone pattern changes, flicker can be suppressed without causing display unevenness due to a shift in the effective value voltage applied to the liquid crystal.

At each gradation level of RED, GREEN, and BLUE, the (L-1) shift amount of each subframe having the same value of the shift amount of each frame of the gradation pattern and the shift amount of each line is variable. The effect of suppressing flicker is high. For example, with respect to the RED gradation pattern, GREEN shifts by one and BLUE shifts by three. As described above, even with the same gradation level, RED, GREE
By shifting the gradation pattern of N and BLUE,
Flicker can be suppressed.

The above items can be applied not only to the gradation display of FIG. 59 but also to the gradation display of FIG. Of course, the present invention can be applied to other gradation displays. For example, when driving a liquid crystal display panel displaying 16 gradations (4096 colors), the gradation pattern representing the on / off of each gradation level is expressed in units of 15 frames (0/15, 1/15,..., 1).
5/15).

The shift amount for each frame is set to the same value among 1, 2, 4, 7, 8, 11, 13, and 14 for each gradation level, and (L) for each subframe having the same value for each gradation level. -1) The shift amount is set to the same value as the shift amount for each frame having the same value at each gradation level or to 0. When the shift amount is set in this manner, 16 gradations (40
96 colors), the interference between the gradations is reduced, and even if the frame frequency is reduced to 80 Hz, flicker can be suppressed.

FIG. 58 shows the case of 16 gradation display (4096 colors), and the least common divisor is 24. That is, the denominator is composed of 12 or 8 and its divisor. Therefore, one cycle in which all gradations are expressed is as short as 24. Therefore, there is a feature that interference between gradations is small even when the field shift is performed.

Generally, 4096 colors are 256 (512)
Color) color display can be realized. This can be realized by selecting 8 gradations out of 16 gradations. If R and G select 8 gradations and B selects 4 gradations, 256 colors will be obtained.

The selection of eight gradations is performed by selecting No. in FIG. 0 of 0 /
1, No. 1/12, No. 1 1/4, No. 4 5
1/3, No. No. 8; 2/3 of 10, N
o. 11/3/4, No. 11 14, 11/12, No. 14 1
1/1 of 5 may be used.

The selection is made as described above, and N gradations are displayed for eight gradations.
o. 0 to No. FIG. 92 shows an arrangement of 7. Using this gradation pattern, 256 (512) colors can be expressed. The feature of this 256-color display method is that the maximum denominator of the gradation display is 12 (the least common multiple is 12). Therefore, the least common multiple in FIG. 58 is し て compared to 24 (12/24). A pattern whose denominator is 12 and its divisor is selected from the pattern of FIG.
By performing the color gradation display, it is possible to suppress the occurrence of flicker when performing the field shift.

2,3,4,6,8,1 which is a divisor of 24
When 16 gradations are displayed using two frames, the number of frames is smaller than in the case of 15 frames, so that flicker can be suppressed even at a lower frame frequency. Further, when 8 gray levels are displayed using 12 common divisors, the occurrence of flicker can be further suppressed as compared with the case of 16 gray levels.

As a 256-color (512-color) FRC expression, a method of implementing 7-FRC shown in FIG. 92 is also conceivable. In the 7FRC, since the total denominator is 7 at the maximum, the cycle is short, and the occurrence of flicker can be further suppressed as compared with the denominator of 12 in FIG.

The gradation pattern shown in FIG. 58 and the gradation pattern (7FRC) shown in FIG. 92 are formed in an IC chip.
A method using the gradation pattern shown in FIG. 58 for 6 gradations and using the gradation pattern shown in FIG. 92 for 8 gradations can be considered.
Further, a gradation pattern of 15 FRC may be formed and used for 16 gradation display. As described above, by performing the gradation display using the gradation pattern that is optimal (probably the denominator is minimized) according to the number of gradation displays, the occurrence of flicker is suppressed and the frame frequency can be reduced. Become. Therefore, low power consumption can be realized. Note that the reduction of the frame frequency includes both measures of reducing the frame rate and reducing the main frequency used for the circuit operation.

There is a method of switching the gradation pattern, in which the user switches directly or indirectly (such as voice input) by pressing a user button arranged on the mobile phone or operating a touch panel. Further, a method may be used in which the microcomputer automatically determines the number of colors of the input image and switches the number. The above is also applied to other embodiments.

The above-described field shift is performed according to FIG.
The processing is performed in the field direction as indicated by the arrow. Another method of field shift is shown in FIG. Hereinafter, the field shift shown in FIG. 82 and the like will be described.

FIG. 82 shows an embodiment of 7FRC. The gray scale pattern 1/7 is illustrated. Data processing is performed as shown by the arrow. In the case of 7FRC, there are 28 ON / OFF data (4 fields × 4 frames) (FIG. 82). This data is processed sequentially. In FIG. 82, when seven frames are completed, one on and six off are expressed.

FIG. 82 may be somewhat harder to understand than FIG. In order to facilitate understanding, it is sufficient to consider 28 pieces of ON / OFF data connected in series. It may be considered that the 28 pieces of on or off data connected in series are processed with the number of fields of 4 as a delimiter. FIG.
In FIG. 8, four breaks are indicated by dotted lines. A range separated by a dotted line is one frame period. Simply 1,
Numbers indicating frames 2, 3,... 7 are described.

Therefore, the field shift shown in FIG. 82 has the concept of a field but has no concept of a frame (it has little relation). That is, once the processing of 7FRC is completed, ON is applied once and OFF is applied six times to the pixel.

In the field shift shown in FIG. 82, when all the four fields of the conventional first frame are on, the elements that turn on (white circles) and the elements that turn off (black circles) are equally spaced. Therefore, the frame response of the liquid crystal is at regular intervals, and it is easy to suppress the occurrence of flicker. In other words, it is preferable that the white circles and the black circles have the same interval as much as possible.

FIG. 83 shows the case of 2/7 in 7FRC. After the first white circle, three black circles are arranged, and then white circles are arranged. Also, two black circles are arranged, and then a white circle is arranged. Thereafter, this pattern is a repeated pattern. In this pattern, since white circles and black circles are arranged at substantially equal intervals, the frame response of the liquid crystal can be reduced. Of course, white circles may be arranged in one and four rows. Alternatively, the white circles may be fixed in one row, and may be arranged alternately in four rows and five rows.

In the embodiment of FIG. 83, white circles are arranged at equal intervals. However, the present invention is not limited to this.
5, white circles may be arranged at unequal intervals as shown in FIG. This is because the occurrence of flicker due to interference may be reduced by arranging at unequal intervals due to interference of other gradations.

Although the embodiments of FIGS. 82 and 83 are expressed as MLS drive, this field shift is not MLS drive. There is no concept of a field. There are only four counter fields. What is important is the number of frames x the number of fields representing the gradation. As a matter of course, there is no concept that an ON voltage or an OFF voltage is applied to a pixel in one frame. There is only a concept that an ON voltage is applied or an OFF voltage is applied in the entire frame × field. Here, in order to facilitate the description, the description is merely made as MLS.

FIG. 82 and the like show the case of 8 gradations of 7FRC. In the field shift for performing the data output in the horizontal direction as shown in FIG. 82 or the like, it is necessary (or preferable) to make the denominators of all the gradation data coincide. This is because interference and the like can be suppressed. In the case of 16 gradations, it is 15 FRC, and in the case of 32 gradations, it is 31 FRC. That is, the FRC of the gradation number -1
And This is because the ON / OFF data string can be expressed by the number of gradations -1.

FIG. 86 shows the case of MLS2. The total length is 14 data in 2 fields × 7 FRC. There are two breaks. FIG. 87 shows the case of MLS8 in which the number of simultaneously selected common electrodes is eight. 8 fields x
7FRC = 56 data strings. There are eight breaks. In any case, the field shift in FIG. 82 can correspond to all MLS driving.

FIG. 88 shows the case of 15 FRC.
(A) shows a 1/15 gradation, and FIG. 88 (b) shows a 3/1 gradation.
This is shown as 5 gradations. FIG. 89 shows a gradation of 4/15, and white circles are arranged so as to be as evenly spaced as possible. The term "equal intervals" means that the difference between the maximum interval and the minimum interval is 2 or less.

FIG. 93 shows an embodiment in which shift processing is combined. Also, 7FRC is taken as an example. Figure 93
(A) is 1/7 gradation, FIG. 93 (b) is 2/7 gradation, FIG.
3 (c) shows 3/7 gradation. FIG. 93
(A1), (b1), and (c1) are the processing of the first one section (A
). In the case of MLS4, one segment is 4 fields × 7 frames = 28. Similarly, FIGS. 93 (a2), (b2), and (c2) show the next one-part processing (indicated by B), and FIGS. 93 (a3), (b3), and (c).
3) shows a third one-division process (indicated by C). Also, FIGS. 93 (a4), (b4), and (c4) show the last one-part processing (indicated by D).

The number of divisions is four, that is, A, B, C, and D. However, the number of divisions is not limited to four, and may be four or more, or two or three. The delimiter is A
→ B → C → D → A → B → C →

The feature of FIG. 93 is that the on-data position is shifted according to the break. Also, the shift position employs the method described with reference to FIG. Therefore, the details are as described in FIG.

By performing the shift pattern shown in FIG. 91 for each break as shown in FIG. 93, randomization of the on-data position can be realized more. Therefore, interference between gray scales hardly occurs, and the frame rate can be reduced.

The flicker countermeasure process is performed by combining all or one or more of the above shift processes. The data shift (shift processing in FIGS. 6 to 10) for suppressing the occurrence of flicker even at a low frame rate is performed by the gradation data shift processing circuit 111. The operation of the gradation data processing circuit will be described later in detail.

FIG. 10 is a circuit block diagram of the liquid crystal display device of the present invention. In the present invention, at least two or more oscillators 101 are provided. The oscillator 101 includes one that oscillates independently and one that outputs a specific frequency by adding another circuit such as a crystal. Further, a configuration in which oscillation is performed to a predetermined value by an external resistor is also included. vice versa,
A configuration in which an external capacitor performs CR oscillation by a resistance inside the IC is also included. It also includes a plurality of clocks supplied from a device such as a microcomputer arranged outside. In this case, it may be difficult to provide two oscillators 201. However, a plurality of oscillators according to the present invention means that two or more clocks can be input, and therefore, even if there are not two oscillators, they are included in the scope of the present invention. Note that the number of the oscillators 101 is not limited to two. There may be three or more.

FIG. 43 shows one external capacitor C1;
A plurality of frequencies are oscillated by two external resistors R1 and R2. Note that the capacitors and resistors are driver ICs.
It is needless to say that the semiconductor chip may be constituted by a pattern. This is realized by attaching a capacitor C1 and resistors R1 and R2 to terminals S1 to S4 of the semiconductor chip as shown in FIG.

A specific semiconductor circuit has the structure shown in FIG. It is composed of three inverters 421 and a switch SW1 composed of an analog switch. Switch S
The output frequency of the terminals OSC1 to OSC4 changes according to the turning on and off of W1.

The switching circuit 102 shown in FIG. 10 is specifically an analog switch. The switching circuit 102 also includes SW1 shown in FIG. 42 from the viewpoint of selecting a frequency. The switching circuit 102 selects and outputs one clock for a plurality of input clocks. Note that the switch in the switching circuit 102 may be a mechanical switch such as a relay. Further, the oscillation frequency may be changed depending on the temperature. Alternatively, the lip switch may be manually switched. If one input clock can be changed to a plurality of frequencies by a microcomputer or the like, the switching circuit 10
2 is not necessary. Such a change by the microcomputer is also included in the concept of the switching circuit 102.

The display device of the present invention includes at least a plurality of oscillators 101. As an example, the oscillator 101a oscillates at a clock of 160 kHz, and the oscillator 101b oscillates at a clock of 100 kHz. Here, for the sake of simplicity, the clock 100 kHz has a frame rate of 10
0 Hz (the number of times that the liquid crystal display panel can be rewritten
00 times) and a clock of 160 kHz
Can realize a frame rate of 160 Hz (160 times of rewriting the liquid crystal display panel per second). The output of the oscillator 101 is input to the switching circuit 102. The switching circuit 102 is a switch, and the oscillator 101
One of the clocks a and 101b is selected and transmitted to the frequency dividing circuit 103. It is preferable that the oscillation frequencies of the oscillator 101a and the oscillator 101b be different from each other within a range of 15% or more and 30 or less.

The frequency dividing circuit 103 sets the inputted clock to 1
The frequency is divided into / 1, 1/2, 1/4, and 1/8.
That is, the output clock from the frequency dividing circuit is
Either one of a and 101b is output as it is, or the frequency is divided (see FIG. 24). Therefore, any one of the eight frequencies can be selected.

The reason why a plurality of oscillators 101 are prepared is to appropriately cope with a moving image and a still image or / and an 8-color display of 4096 colors and 256 colors. Generally, the frame rate is set high for moving images, and low for still images. When a multi-color display of 4096 colors is performed, the influence of interference between gradations becomes large in the STN liquid crystal panel, and when the expression color is reduced to eight colors, the interference is reduced. Therefore, the frame rate may be low.

If the frame rate is increased, the power consumption of the display device naturally increases. Therefore, it is desirable to use the frame rate as low as possible in order to reduce power consumption. The frame rate type values are as shown in FIG. Therefore, even with one liquid crystal display device, it is preferable to switch the frame rate between when displaying 256 colors and when displaying a moving image. For example, with a liquid crystal panel that responds 250 msec, 8
When performing color display, the frame rate is 30 or more and 40H
z or less, and the power consumption is reduced as much as possible. In the case of displaying a moving image, the frequency is increased to a range of 100 to 140 Hz to prevent splicing from occurring. Accordingly, both a moving image and a still image can be displayed with good image quality on one liquid crystal display panel. Note that the shift processing described with reference to FIGS. 6 to 9 and the like may be changed for moving images and still images. A moving image has a shift process optimal for a moving image, and a still image has a shift process optimal for a still image.

As described above, in order to change the number of display colors and the frame rate between a moving image and a still image, if one frequency is divided and used, a good image display cannot be realized. However, if at least two or more oscillators 101a and 101b are provided as shown in FIG. 10, the frame rate shown in FIG. 24 can be realized by combining with a frequency dividing circuit. That is, the circuit can be operated with many clocks, the power consumption is small, and the liquid crystal display panel can be driven at the optimum frame rate.

In the present invention, the frame rate is determined by the oscillator 1
One-thousandth of the oscillation frequency (clock) of 01 is set to the frame rate. Therefore, if the clock is 160 KHz, the frame rate is 160 at 1/1.
Hz. As shown in FIG. 24, 160 kHz and 100 KH
If two clocks of z are used (if two oscillators are used), the frame rate can be changed favorably.

The switching of the operation is exemplified by a method in which a switching switch such as a key switch is separately provided, and the frame rate is switched by the user pressing the key switch or the like. When the microcomputer inputs image data to the internal memory of the segment IC 14, when the microcomputer inputs image data of 4096 colors (4 bits for R, G, B colors) and 256 colors (3 bits for R, G colors, 3 bi)
(T, 2 bits for B color), the data storage state in the memory is different (or the operation of the microcomputer is different).
The frame rate is switched by judging the different state. That is, when the microcomputer performs an operation of storing the image data of 4096 colors in the built-in memory of the segment IC 14, a command to store the data in 4096 colors is transferred to the drive IC 14. By the transferred command, the frequency divider 103 and the like operate simultaneously, and the frequency divider 1
From 03, a clock of 100 kHz to 120 kHz is output.

Similarly, when there are 256 colors, the method of storing data in the memory is switched to 256 colors by a command from the microcomputer. For 256 colors, the frequency divider 10
3 outputs a clock of 80 to 100 kHz. In the case of a moving image, a flag (description) indicating that the image is a moving image is written in packet data of an image transmitted to a mobile phone (this display panel is used as a display panel of the mobile phone). The microcomputer detects (decodes) this flag and determines that the moving image is a moving image, and changes the output clock from the frequency dividing circuit 103 to 140 kHz to 160 kHz.

In the case of eight-color display, one of the oscillators 101b is used.
The oscillation frequency of 60 kHz is reduced to 1 /
4, and outputs a clock of 30 to 45 kHz. Therefore, in this 30 to 45 kHz, the frame rate is 3
It becomes 0 to 45 kHz. If the frequency is reduced in this way, the power consumption can be reduced almost in proportion. For example, an eight-color display is sufficient for a menu screen that is always displayed on a liquid crystal display panel of a mobile phone. Therefore, the effect of reducing power in eight-color display is high. According to the present invention, the operation clock of the entire circuit can be freely reduced by a command, and the frame rate can be reduced. Therefore, an ultra-low power consumption module can be configured as a whole.

The controller 104 has an input command decoder function, an external I / F function, and a control function such as a memory. The memory 105 is a built-in memory created inside the segment driver, and is a one-screen SRAM memory. As an example, 1-bit data is formed by eight MOS transistors, and the data bus is a bidirectional bus.

In the MLS4 drive, because of the calculation processing, it is necessary to perform calculation using data of four pixel rows. for that reason,
The data bus is configured to output data for four rows simultaneously. In addition, the semiconductor process is the
You are using a layering process. In order to simplify the data bus, the pixel data may be read four times consecutively for each row and the MLS operation may be performed. Of course, the reading operation is not limited to one row, and the reading operation may be performed serially for each pixel. In the MLS 8, data is read every eight rows.

The data from the memory is sent to the gradation MLS control circuit 106, where the MLS operation is performed. The calculation result is sent to the segment (SEG) driver circuit 14.
Although shown here independently of the SEG driver 14, actually, the SEG driver 14
S control circuit 106, controller 104, memory 105
It is constituted as one. Here, it is merely separated for ease of explanation. Of course, the controller 104
The memory 105 may be separated from the segment driver 14 to be a separate chip.

As a result of various studies, the ML of the FRC system was
Regarding the S4 drive, there is an important relationship between the response time R (msec) of the liquid crystal and the frame rate F (Hz). The response time R (msec) of the liquid crystal is 20 ° C. to 25 ° C.
It is the sum of the rise time and fall time of the liquid crystal at ° C. The frame rate F (Hz) is the number of times F that the entire screen is rewritten per second. The number of scanning lines of the display panel is L (Lduty). In the FRC process, any or all of the processes described with reference to FIGS. 6 to 9 are performed. However, the shift processing is not necessary for the 8-color display.

In eight-color display, it is optimal that the relationship between R, F, and L satisfies the following relationship.

150 ≦ (LR) / F ≦ 2500 (Equation 3) More preferably, the following relationship is satisfied.

250 ≦ (LR) / F ≦ 1500 (Equation 4) In the case of a 256-color display still image, it is preferable that the relationship among R, F, and L satisfy the following relationship.

80 ≦ (LR) / F ≦ 800 (Equation 5) More preferably, the following relationship should be satisfied.

100 ≦ (L · R) / F ≦ 600 (Equation 6) In the case of a 4096-color display still image, it is preferable that the relationship between R, F and L satisfy the following relationship.

100 ≦ (L · R) / F ≦ 700 (Equation 7) More preferably, the following relationship is satisfied.

120 ≦ (L · R) / F ≦ 600 (Equation 8) When displaying a moving image, it is preferable that the relationship between R, F and L satisfy the following relationship.

80 ≦ (L · R) / F ≦ 500 (Equation 9) More preferably, the following relationship is preferably satisfied.

100 ≦ (L · R) / F ≦ 400 (Equation 10) In the display device (cellular phone or the like) of the present invention, the value of the above-described mathematical expression is set by a setting command or by automatic switching by a microcomputer such as a user switch. It is configured to be able to. Therefore, an optimal image display can be realized at an optimal frame rate depending on the number of display colors and the display state.

The output of the frequency dividing circuit 103 is output from the COM driver circuit 15, controller 104, memory 105, gradation ML
It is provided to the S control circuit 106 and the like. In FIG. 107, S
Although the EG driver circuit 14 is provided separately, as described above, the controller 104, the built-in memory 105,
The gray scale MLS control circuit 106 and the SEG driver circuit are implemented on a single chip to achieve low power consumption.
Further, the power supply circuit is separately integrated and mounted. Of course, it may be built in the segment driver 14. The memory 105 can hold display data for one screen or more, and can perform bidirectional input / output (data writing and reading can be performed simultaneously). The controller also includes a command decoder, a data swap circuit, and the like.

Therefore, the segment driver determines whether the data is 256 colors or 409
You can know whether it is 6 colors or 8 colors. Therefore, if the command from the microcomputer is decoded and the switching circuit 102 and the frequency dividing circuit 103 are controlled, the change can be made automatically. Therefore, the user can view the image in an optimal state without worrying about the display color.

In particular, when it is desired to switch the frame rate depending on the display color, a user button may be arranged on a device such as a mobile phone so that the display color and the like can be switched using the button or the like.

FIG. 26 is a plan view of a mobile phone as an example of the information terminal device. An antenna 261, a numeric keypad 265, and the like are attached to the housing 262. 261 is a display color switching key. FIG. 27 shows an internal circuit block of a mobile phone or the like. The circuit mainly includes blocks such as an up-converter 275 and a down-converter 274, a block of the demultiplexer 271 and a LO buffer 276.

When the key 266 is pressed once, the display color is in the eight-color mode, when the same key 266 is pressed, the background color is in the 256-color mode, and when the key 266 is pressed further, the display color is in the 4096-color mode. The key is a toggle switch that changes the display color mode each time the key is pressed. Note that a change key for the display color may be separately provided. in this case,
The number of keys 266 is three (or more).

The key 266 may be another mechanical switch such as a slide switch in addition to the push switch, or may be switched by voice recognition or the like. For example, by inputting voice into 4096 colors to the receiver 264 and inputting high-quality display and voice into the receiver 264, the display color displayed on the display screen 107 of the liquid crystal display panel is changed. This can be easily achieved by employing current speech recognition technology. For example, the user voice-inputs "256 color mode" or "low display color mode" to the receiver. Then, the receiving terminal performs the voice analysis and switches to the commanded display mode.

The display color can be switched by an electrical switch.
A touch panel that is selected by touching the menu displayed in 7 may be used. The switching may be performed by the number of times the switch is pressed, or may be switched by rotation or direction like a click ball.

Although 266 is a display color switching key, it may be a key for switching a frame rate. Further, a key for switching between a moving image and a still image may be used. A plurality of requirements such as a moving image, a still image, and a frame rate may be simultaneously switched. Further, the frame rate may be configured to be gradually (continuously) changed as the holding is continued. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Also, a plurality of capacitors are formed on the semiconductor chip,
This may be realized by selecting one or more capacitors and connecting them in parallel in a circuit.

At the time of switching, the reference voltage or the bias ratio may be automatically switched by microcomputer control or the like, or may be controlled so that a specific menu display can be displayed. In addition, switching using a mouse or the like, a display screen of the liquid crystal display device 21 is a touch panel,
In addition, a configuration may be adopted in which switching can be performed by displaying a menu and pressing a specific portion.

The technical idea of switching the frame rate depending on the display color and the like is not limited to a mobile phone, but is widely applied to devices having a display screen such as a palmtop computer, a notebook computer, a desktop computer, and a mobile watch. Can be applied. Further, the present invention is not limited to a liquid crystal display device (liquid crystal display panel), and can be applied to an organic EL panel, a TFT panel, a PLZT panel, and a CRT.

If information such as the frame rate is described in the format to be transmitted, the frame rate and the like can be automatically changed by decoding or detecting the described data. In particular,
It is preferable to describe whether the transmitted image is a moving image or a still image. In the case of a moving image, it is preferable to describe the number of frames per second of the moving image. Further, it is preferable that the model number of the mobile phone is described in the transmission packet. In this specification, the description will be made as a transmission packet, but it need not be a packet. In other words, any data may be used as long as the data described in FIGS. 25 and 34 is described in the data to be transmitted or transmitted.

FIG. 25 shows a transmission format sent to a portable telephone or the like. Transmission includes both data to be received and data to be transmitted. In other words, the mobile phone may transmit the voice from the handset or the image captured by the CCD camera attached to the mobile phone to another mobile phone. Therefore, items related to the transmission format and the like described in FIGS. 25 and 34 are applied to both transmission and reception.

Generally, data is digitized and transmitted in a packet format in a mobile phone or the like. As shown in FIG. 25A, for example, an 11-bit or 7-bit marker is described before and after in a packet. Next, a 16-bit header is described as an example. A packet number and the like are described in the header. In the data area, 8-bit data indicating color number data and 8-bit data indicating a frame rate are described. These examples are shown in FIGS. Further, it is preferable to describe the distinction between a still image and a moving image in the number of display colors. Also, mobile phone model name,
It is desirable that the contents of the image data to be transmitted / received (natural images of a person or the like, a menu screen) and the like be described in the packet of FIG. The model that has received the data decodes the data, and when the data is its own (corresponding model number), automatically changes the display color, frame rate, etc. according to the described contents. Further, the described contents may be displayed in the display area 107 of the liquid crystal display device 21. The user looks at the description contents (display color, recommended frame rate) on the screen 107 and operates keys or the like to manually change to an optimal display state.

As an example, in FIG. 25 (b), the numerical value 3 is described as an example with a frame rate of 60 Hz, but the present invention is not limited to this and indicates a certain range such as 40-60 Hz. There may be. Further, the model of the mobile phone may be described in the data area. This is because the performance differs depending on the model, and it is necessary to change the frame rate. It is also preferable to describe information such as whether the image is a cartoon or an advertisement (CM). Also, information such as the viewing fee is described in the packet. Information such as a packet length may be described. The user confirms the viewing fee and determines whether to receive the information. It is also preferable to describe data indicating whether or not the image data has been subjected to error diffusion processing.

The frame rate is related to the power consumption of the panel module. That is, as the frame rate is increased, the power consumption increases almost in proportion. For mobile phones and the like, it is necessary to reduce power consumption from the viewpoint of elongating standby time. On the other hand, in the case of an STN panel or the like, it is necessary to increase the denominator of FRC (the number of bits of the gradation register) in order to increase the display color (increase the number of gradations). However, it is difficult to increase power consumption due to the problem of power consumption.

In order to solve this problem, the present invention employs a configuration in which the apparent number of gradations is increased by error diffusion processing. The error diffusion processing is a technique for increasing the number of gradations by a technique such as area gradation.

For example, if the panel has 16 gradations, 4
096 colors (16 × 16 × 16) can be displayed. RGB is 4 bits (12 bits in total). 4096 panels
It has only color performance. Therefore, in order to display 65K colors, error diffusion processing of input data (R, B: 5 bits, G: 6 bits, a total of 16 bits) is performed, converted into each of 4 bits of RGB, and applied to the liquid crystal panel. I do. In the case of full color (RGB: 8 bits each), RGB data is converted into each 4 bits and output to the liquid crystal display panel. Note that the output is not limited to 4096 colors, and the output may be 65,000 colors.

As an example of the dither method, there is a method described in FIG. As shown in FIG. 54, the original image is divided into a coarse mesh of 4 dots vertically and 4 dots horizontally,
A binarization operation is performed for each of the divided blocks. Here, for each block, for a square rectangular area composed of 4 × 4 pixel sets, the luminance of each pixel set in this rectangular area is calculated by a 4 × 4 “dither matrix” prepared in advance as shown in FIG.
If the number written in the corresponding part of the table is smaller than the corresponding luminance in the corresponding part of the table, the white (luminance 2
55), it is replaced with black (luminance 0). This is 2
In the case of a value, it may be applied to multiple values. The dither matrix includes Bayer type, halftone type, Scr
ew type, Screw deformation type, halftone emphasis type, Dot C
There is an on-center type, and any of these may be used, but for a liquid crystal display panel, a halftone emphasizing type is optimal.

In the present invention, the SEG driver 14 has an image memory (built-in memory) for one screen. Therefore, when the display image is a still image, there is no need to input data from outside, and it is only necessary to access the built-in memory 105. This is because external data input requires driving power for driving external wiring, while internal memory has a small wiring capacity inside the chip and can be almost ignored. Therefore, power consumption can be reduced in a configuration having a built-in memory.

The configuration having the built-in memory 105 for one screen may be not only the SEG driver 14 but also a source driver of a TFT liquid crystal display panel. In other words, the present invention is not limited to a simple matrix type liquid crystal display panel,
The present invention can also be applied to an active matrix type liquid crystal display panel. Further, the present invention can be applied to other display panels or devices such as an EL display panel. It is configured to transfer a command from the controller of the SEG driver 14 to the COM driver 15 and control the COM driver 15.

Further, the liquid crystal display device of the present invention has a SEG
An error diffusion processing controller 281 is provided in addition to the driver 14. Here, for ease of explanation, the SEG driver 14 has a built-in image memory 105 for one screen for displaying 4096 colors, and the error diffusion processing controller 281 shown in FIG. RB: 5 bits, G: 6 bits, 1/16 of the screen
The description will be made assuming that the memory has a size of 1/2 of the size.

If the error diffusion processing controller 281 has a memory of full color (RGB: 8 bits each), it goes without saying that full color display can be realized by the error diffusion processing.

The error diffusion processing means a general processing method that adopts the concept of area gray scale and can display more display colors on the entire screen with less gray scale expression. This technology has been established as a technology for displaying an image on a printer. The present invention is novel in that a chip or a circuit for performing an error diffusion process is provided separately from a chip or a circuit (such as a segment driver) having a memory for holding still image data. The operation data subjected to the error diffusion processing by the error diffusion processing controller 281 is stored in the still image memory 105.
And the data is held in the memory 105.

Note that error diffusion is a technique for performing calculations by introducing the concept of area gradation in consideration of the gradation and color of the peripheral portion of a pixel so that the gradation can be seen with a small number of gradations. Means the general. In addition to those introduced in display devices such as CRTs, those used in image processing of color printers are also error diffusion techniques. In addition, it goes without saying that the concept of error diffusion includes dither processing. Needless to say, a combination of error diffusion and dither processing may be used. In this specification, a method of realizing multi-gray scale display with a smaller number of gray scales by dispersing input image data and the like to peripheral pixels is referred to as error diffusion. That is, the error diffusion referred to in this specification includes a broader content than the error diffusion processing generally called.

As shown in FIG. 28, a segment (SEG)
The driver 14 (corresponding to a source driver in an active matrix liquid crystal display panel such as a TFT) has two I / Fs. One is a 12-bit input,
The other is a 16-bit input (24 bits in the case of full color. The system is not limited to two systems, but may be three systems such as 12 bits, 16 bits, and 24 bits).

Accordingly, in the case of 4096 colors, image data is directly input to the SEG driver 14 from a microcomputer or a computer. In the case of 65K color, 1 is sent to the SEG driver 14 via the error diffusion controller 281.
Two-bit data is input. Of course, the configuration may be such that 12-bit data can be passed through the error diffusion processing controller 281 and applied to the SEG driver 14.

Normally, the voltage amplitude of the segment signal applied to the liquid crystal display panel 21 needs to be about ± 5 (V) or more, so a withstand voltage near a constant 10 (V) is required. Therefore, it is difficult to miniaturize the semiconductor process rules. As an example, the maximum withstand voltage of the SEG driver using the 0.35 μm process is 8.5 (V).

However, if the process rules cannot be miniaturized, the cell size of the built-in memory also increases. For this reason, the memory size of the chip increases and the cost increases. As an example, a 40 mm ² only memory size is 128 × 160 dots in 4096 colors. The memory occupies 1/2 to 2/3 of the chip area. Due to the memory size problem, the internal memory of the SEG driver 14 is limited, and the number of display colors cannot be increased. This means that the bit size of each pixel of the built-in memory cannot be increased. This is because the memory size increases and the chip size increases.

In the error diffusion processing, the size of image data for one pixel is large, and the large image data is converted into short image data by processing (error diffusion processing). Therefore, it is extremely inefficient to secure the memory necessary for the operation for all the pixels in the chip.

On the other hand, error diffusion controller 281
Is composed of an arithmetic memory 293 and an arithmetic circuit 291 for performing an error diffusion process, as shown in FIG. In other words, it is composed of only a logic circuit (in some cases, a power supply circuit such as DCDC may be formed). Therefore, the circuit constituting the controller 281 need only be a logic gate. This is because an output stage requiring a withstand voltage is not required. That is, controller 2
81 does not require a high breakdown voltage. Therefore, a semiconductor process with a fine rule can be used.

As an example, a 0.25 μm process with a withstand voltage of 3.3 V is used. 0.25μm process and 0.35μ
In the m process, the standard cell size is 2
Times different. In other words, a memory manufactured at 0.35 μm can be manufactured with a half area by the 0.25 μm process.
Alternatively, a 0.18 μm rule with a withstand voltage of 1.8 V may be used.

The result data calculated by the error diffusion controller 281 is transferred to the segment driver 14, and the data is stored in the memory 105. At this time, the input / output format shown in FIG. 35 is used. As described above, since the error diffusion controller 281 can use the fine rule, the chip size can be reduced. Also, at least 1
Since the operation memory 293 for the rows is sufficient, the memory size of the error diffusion controller 281 can be extremely small and the chip can be reduced.

Note that the controller 281 may hold full-screen image data, and this data may be read out and subjected to a color reduction process such as an error diffusion process.
The data is transferred to the internal memory of the segment driver 14 by performing the color reduction processing. For the segment driver, only a required minimum still image memory such as eight colors or 256 colors is prepared.

It is desirable that the user can independently switch whether to perform dithering or error diffusion processing. For example, it is a push button switch or a touch panel provided on a mobile phone. Also,
You may comprise so that it may be switched indirectly by audio | voice input etc. Alternatively, the switching may be performed by the microcomputer.

Image data may be transferred after being subjected to dither or error diffusion processing. If dither processing is further performed on the dither-processed image, dot unevenness will appear. Even if the image subjected to the dither processing is subjected to the error diffusion processing, the image quality hardly deteriorates. Therefore, controller 2
It is desirable that the process of 81 is an error diffusion process.

Data input / output is also 256 colors of 8 gradation display for each color.
In order to realize (512) colors and 4096 colors of 16 gradations with one IC chip 14, it is necessary to consider the input / output format of image data. 1 for 256 colors
Pixel data is 8 bits (1 byte) because R is 3 bits, G is 3 bits, and B is 2 bits, for a total of 8 bits. However, in the case of 4096 colors,
Since each color of R, G, and B is 4 bits, the total is 12 bits. Therefore, the state is a halfway state of 1.5 bytes.

In the present invention, to cope with this, 4096
In color, two input / output formats shown in FIGS. 35A and 35B can be realized. One or both of the two input / output formats can be implemented. Of course, for 256 colors, 1-byte (8-bit) input / output is realized.

Generally, data input / output can be selected from an 8-bit format and a 16-bit format. In addition, 86 system or 68 system can be selected. FIG. 35 shows an input / output format for 16 bits.

FIG. 35A shows an input in 16-bit units. At this time, the first four bits are blank. By inputting and outputting data in this manner, the relationship between the 16-bit address and the pixel data can be easily understood. However, since there is a blank, the transfer efficiency of data input / output decreases.

In FIG. 35B, input / output is basically performed in units of 8 bits. Address 00H is R, G, address 01H
Are B and R. Such input / output makes the relationship between the address and the pixel data complicated, but the data input / output transfer efficiency is significantly improved.

In the present invention, one of the formats shown in FIGS. 35A and 35B can be switched by an initialization command from the MPU.

Error diffusion processing controller 281 of the present invention
Has a function of transferring the data transmitted after error diffusion processing to the built-in memory 105 of the segment driver 14 through the error diffusion processing controller 281 as it is. Whether or not to pass through is determined by decoding the data content of the packet in FIG. 25 and automatically performing processing. Or MPU (microcomputer), CP
This is performed by command processing from a U (personal computer).

The error diffusion controller preferably has two or more built-in memories for 1/20 to 1/4 rows of the screen area. This is to realize the optimal error diffusion processing in consideration of the absorption of the data input / output timing difference and the rows before and after performing the error diffusion processing. Also,
This is because the weighting process is performed in consideration of not only the error diffusion process but also image data of peripheral pixels. Also, it is for performing dither processing.

In this specification, the controller 281 is a circuit for performing an error diffusion process for ease of explanation, but the present invention is not limited to this. That is, the size (the number of bits) of the input image data of one pixel is shortened by calculation to be transferred to the built-in memory 105 such as the segment driver 14. Also, the built-in memory 105
The image data is read out from the device and subjected to a reverse error diffusion process or the like and output. There are various methods other than error diffusion processing for reducing the number of bits of image data. For example,
The above-described image data weighting process is exemplified, and the dither process is exemplified.

In the error diffusion processing, one row of image data is error-diffused to the next row and processed, and this processing is sequentially performed on the next row. May be one line. Therefore, in the following embodiments, the memory size is described as a plurality of rows, but this is applied to input / output timing control in order to apply to other than error diffusion processing as described above, or to increase versatility. It is to utilize. Therefore, the present invention does not limit the memory size to a plurality of rows.

As an example of image data, when the screen size of the liquid crystal display panel is 128 dots (RGB) in width and 160 dots in height, a memory having a size of 8 rows or more and 40 rows or less is formed. The memory size increases as the accuracy of error diffusion processing or the like is improved (the versatility is increased). In particular, the size should be increased as the number of display colors increases.

In the present invention, as a result of studying the image evaluation, it was concluded that the following conditions were preferably satisfied. That is, the number of bits is M (for example, 40
In the case of 96 colors, since RGB is 4 bits each, M = 12)
The number of bits of the RGB sum of the input data to be subjected to error diffusion or the like is set to N (for example, in the case of 65K color, RB: 5 bits each, G is 6 bits, so N = 5 + 5 + 6 = 1)
6), when the number of rows of the memory of the error diffusion processing controller 281 is L, it is preferable to set the following range.

N / M × 4 ≦ L ≦ N / M × 32 (Equation 11) More preferably, the following condition should be satisfied.

N / M × 8 ≦ L ≦ N / M × 16 (Equation 12) As shown in FIG.
Represents a plurality of the operation memory 293 of the above formula (29
3a, 293b) are provided. In FIG. 30, one memory 293a is a memory for performing arithmetic processing,
The other memory 293b is a memory for writing data.

Conversely, in the case of image data output (transmission), one memory 293b is a memory for performing arithmetic processing, and the other memory 293a is a memory for writing data.

For example, memory 293a is provided with a microcomputer (M
PU), the switch SA1 is closed, and the image data is written. On the other hand, SB2 is closed, and the memory 293b is transferred to the arithmetic circuit 291 to perform error diffusion processing and the like. The calculation result is transferred to a built-in memory 105 such as a segment (SEG) driver IC 14. The transferred data is stored in the built-in memory 105.

In the next phase, the switch SA2 is closed and the image data is written in the memory 293b, and the switch SB1 is closed and the data in the memory 293a is processed. The calculated image data is transferred to a built-in memory such as the SEG driver IC 14. That is,
Data writing and arithmetic processing are performed alternately on the memories 293a and 293b.

As described above, when performing error diffusion processing of image data by general sequential processing, it is not necessary to switch the memory 293 and it is not necessary to provide a memory for a plurality of rows. Needless to say. When the memory 293 for a plurality of rows is provided, there is an advantage that the processing can be performed by dividing the screen. Also, store the data once and transfer the image data once (for multiple lines)
There is also an advantage that can be.

The transfer of image data is performed by dividing the screen. For example, when the screen size is 160 lines and the memories 293a and 293b have 16 lines, the screen is divided into ten.
Therefore, the arithmetic processing is performed for every 16 rows. Then, when the calculation processing for the first 16 rows is completed, the data is transferred to the built-in memory 105, and the calculation processing for the next 16 rows is performed. The calculated result is sent to the memory 105. Therefore, 10
When the first calculation processing is completed, the error diffusion processing for one screen is completed. Since the transfer is performed ten times in this way, the efficiency is higher than when the operation result is transferred line by line. Further, low power consumption can be achieved.

The SEG driver 14 has a built-in memory 105
Is read, and an image is displayed on the display screen of the liquid crystal display device 21. If the image is a still image, the error diffusion controller 281 completes error diffusion processing and the like, and if the data is transferred to the built-in memory 105, the error diffusion controller 281 does not need to operate any further. for that reason,
The clock to the DCDC converter 201 is automatically stopped, the power supply circuit of itself is lowered, and a sleep state is set.
Switching between the sleep state and the operation state may be performed by command control from the microcomputer.

When there is new image data, the microcomputer transfers a command to the controller 281, and the error diffusion controller 281 and the like apply a clock to the DCDC converter to start up its own power supply, and wait for image data input. Become. When a command to end the image data is received from the microcomputer, the microcomputer enters a sleep state.

As described above, the error diffusion controller 2
81 switches between the sleep state and the operation state, and in the case of a still image, only one screen of arithmetic processing is performed, so that low power consumption can be realized. In addition, since only a small memory 281 required for calculation is built in, the chip size is small. When the calculation results are sequentially transferred to the built-in memory 105 in synchronization with each other, it is needless to say that the calculation results can be constituted by one row or less of the calculation memory 293.

Although two memories 293 are used in FIG. 30, the present invention is not limited to this.
As shown in FIG. 1, three or more memories 293a, 293b,
293c. The memory 293 is sequentially selected and used.

As described above, according to the present invention, the output data from the original image data holding means such as a microcomputer is subjected to the color reduction processing by the error diffusion processing controller, and the image memory section of the segment driver 14 having a smaller capacity than the original image data holding section. And an image data information storage device.
The information is reduced (color-reduced) compared to the RAM for storing the original original image, and is written to the RAM of the segment driver.

At this time, if the lower bits are simply cut off, an outline is generated due to gradation drop. In order to solve this problem, the arithmetic unit 291 of the error diffusion processing controller 281 performs color reduction processing (gradation number reduction processing, for example, changing 8 bits to 6 bits) by a so-called dither method or error diffusion method. Thus, by dispersing the gradation spatially, a contour line accompanying gradation drop is prevented. This process is effective for both moving images and still images. In particular, in the case of a still image, the controller 281 performs processing for one screen and stops after transferring to the internal memory of the segment driver 14. Thereafter, since only the segment driver 14 operates, the effect of reducing power consumption is great.

That is, the image memory 105a and the driver section 292 are integrated with the segment driver to form a one-chip IC.
In the case of a still image, an image can be displayed only by accessing from the built-in memory for which the arithmetic processing has been completed, so that the effect of reducing power consumption becomes remarkable.

In the controller 281, a gamma processing unit of a look-up table system may be formed in the controller 281 in addition to the arithmetic unit 291. Of course, gamma changing means other than the lookup table may be used. For example, a method of converting one image data into gamma-processed image data by a logic such as a decoder circuit is exemplified.

As shown in FIG. 40, the lookup table is configured so that it can be rewritten externally.
That is, data indicating a gamma curve corresponding to the display device (which can be converted into a gamma curve) is input to the position area of the memory 293 using an RS232C bus, a three-wire bus, an IIC bus, or the like. Input is performed by reading data from the ROM in the microcomputer when the controller is started and transmitting the data. Further, gamma data may be described in a transmission format such as that shown in FIGS. 25 and 34, decoded, and the like, and written to the memory 293.

By configuring the gamma curve data so that it can be rewritten from the outside as described above, it is possible to support a wide variety of display devices even if the controller hardware is the same. Further, appropriate gamma characteristics can be realized depending on the content of the display image (the content of an image such as naturalization of a bright shore, a person, a movie, etc .; image quality or atmosphere such as classic or popular). Also,
By describing the optimum gamma data for the transmission image data in the transmission format along with the transmission image data, the best image display can be realized.

The controller 281 has a RAM for displaying eight colors.
(RGB: 1 bit each) is preferably formed. Eight-color display is frequently used for menu screens and the like, and is also frequently used for standby screens of mobile phones and the like. Therefore, there are many opportunities (time) for performing the 8-color display. Therefore, reducing the power consumption of the eight-color display is an essential technology for a device such as a mobile phone that requires low power consumption.

To reduce the power consumption during the eight-color display, an eight-color display is used.
In color display, the built-in RA formed in the segment driver 14 is used.
The data is read from M and an image is displayed. Therefore, there is no need to sequentially transmit data from the controller 281 and low power consumption can be realized.

[0311] The segment driver implements PWM driving and additionally has a function capable of implementing 7FRC or 3FRC. From the controller,
Successively, the 4-bit data of each color is transferred to the segment driver 14.
And these 4 bits are applied to the liquid crystal by PWM driving. With 4 bits, the liquid crystal display panel 21 displays 4096 colors. Also, when 3FRC is performed together, the data is increased by 2 bits. That is, by executing the 4-bit PWM data of each color four times at 3FRC, a 6-bit display of each color (about 260,000 colors) can be realized.

Further, in the case of 7FRC, since 3 bits are increased, 4 bits of 15 PWM (8 + 4 + 2 + 1) are increased by 3 bits, so that about 2 million colors can be displayed. Therefore, PWM can express only 16 gradations, but 3
By combining with FRC or 7FRC, 26
It can be realized by switching between multi-color display and 2 million color display.

The calculation of the PWM is performed in the controller 281. The result of the MLS operation finally has five voltage values. This voltage value is weighted (V2 is 2, V1
Are added, Vc is 0, MV1 is -1, and MV2 is -2). The result is the magnitude of the absolute value V2 and its sign (±), and the magnitude of the absolute value V1 is its sign (±). This data is transferred to the segment driver 14, and this data is
Latch and hold for a minute. The segment driver reads the latched data and applies it to the liquid crystal display panel.

By transferring the calculation result to the segment driver 14, a complicated calculation can be performed by the controller 281 that can use the fine rule. Therefore, there is almost no need to form a logic circuit in the segment driver 14 which requires a withstand voltage and cannot be manufactured according to the fine rules. Therefore, low cost and low power consumption can be realized.

The transmitted image data often does not have an appropriate gamma characteristic on the display panel of the receiving terminal display device. For example, there is a gamma characteristic of the 2.2 power of the CRT. The received terminal (for example, a terminal having a liquid crystal display panel) converts (corrects) a gamma curve appropriate for the display panel. The number of bits of the image data increases due to the gamma conversion. For example, 8-bit data becomes 10 bits. That is, proper gamma processing is performed, and the number of bits increases. However, since appropriate color reduction processing is performed by processing such as error diffusion, it is only necessary to temporarily hold this data even if the number of bits increases. This is because the number of bits can be appropriately reduced by dithering or error diffusion processing. Therefore, good image display can be realized.

Of course, the power does not increase because the gamma processing unit is stopped during a still image. Although the receiving terminal performs the gamma processing and the like, it goes without saying that the receiving terminal preferably performs the inverse gamma processing and transmits the data. This inverse gamma processing can also be easily realized by a look-up table method or the like.

[0317] Also, processing of different gradation numbers may be performed in RGB. Basically, by increasing G and decreasing B, the image quality is improved even with the same memory capacity. For example,
G: 5 bits, R: 4 bits, B: 3 bits. This method can eliminate the feeling of roughness even in a display panel with rough pixels because there are many G gradation levels that are highly sensitive to human eyes, especially when compared to spatially dispersed methods such as the dither method and the error diffusion method. Can be.

Further, the controller 281 may be provided with a circuit processing unit for suppressing flicker by using a frame rate control (FRC) method. The FRC circuit has a large circuit scale. Since the controller can be manufactured according to the fine rules, it can be integrated sufficiently with the controller even if the circuit scale is large.

Although the above embodiments have been described on the premise of a liquid crystal display panel, a light-emitting display such as an organic or inorganic EL, a fluorescent display, a PLZT display, and a display using a digital micromirror device (DMD). However, it is needless to say that the effect of reducing the calling power at the time of the still image can be equally exhibited.

FIG. 34 shows the contents of the transmission packet as in FIG. Image processing method (type of error diffusion processing, dither processing, etc., type of weighting function and its data,
Information such as a gamma coefficient) and a model number may be described in a format to be transmitted. Also,
The image data is data captured by CCD or JPEG
Data, its resolution, MPEG data, BIT
Information such as MAP data is described. By decoding or detecting the described data, it becomes possible to change the state of the received data to an optimum state with a cellular phone or the like that has been automatically received.

Of course, as described with reference to FIG. 25, it is preferable to describe whether the transmitted image is a moving image or a still image. In the case of a moving image, it is preferable to describe the number of frames per second of the moving image. It is also preferable to describe information such as the number of reproduced frames / second recommended by the receiving terminal.

The above items are the same even when the transmission packet is a transmission. In this specification, a transmission packet will be described, but it need not be a packet. In other words, any data may be used as long as the data described in FIGS. 25 and 34 is described in the data to be transmitted or transmitted.

FIG. 34 shows an example of a transmission format of data transmitted or transmitted to a portable telephone or the like.
Transmission includes both data to be received and data to be transmitted. In other words, the mobile phone may transmit the voice from the handset or the image captured by the CCD camera attached to the mobile phone to another mobile phone.

It is preferable that the error diffusion processing controller 281 add a function of performing inverse error diffusion processing on the data that has been subjected to the error processing and sending the data back to the original data and then performing the error diffusion processing again. The presence or absence of the error diffusion processing is described in the packet data of FIG. In addition, data necessary for inverse error diffusion processing such as a processing method and a format of error diffusion (including a method such as dithering) is also provided. Other items are the same as those in FIG.

The reason why the inverse error diffusion processing is performed is that the error diffusion processing can also realize the correction of the gamma curve in the course of the processing. In some cases, the gamma curve of the liquid crystal display device that receives the data and the transmitted gamma curve do not adapt. The transmitted data may be image data on which processing such as error diffusion has already been performed.

In order to cope with this situation, reverse error diffusion processing is performed to convert the data into original data so that there is no influence of gamma curve correction. Thereafter, the received liquid crystal display device performs an error diffusion process, and performs an error diffusion process or the like so that a gamma curve optimal for the received liquid crystal display panel is obtained and an optimal error diffusion process is performed. In particular, when the display device that receives data is an STN liquid crystal display device that performs FRC processing, the luminance difference between the gradations is not linear. It is desirable for such an STN liquid crystal display device to perform gamma processing according to each gradation.

Generally, as shown in FIG. 36, the image data of the display screen 107 is transmitted at the upper left of the screen (from the number 1 in the direction of the arrow). Therefore, the image data is shown in FIG.
In the forward direction (DATA1, DATA2, D
ATA3...). The error diffusion processing is also performed from left to right as shown in FIG. As an example of the error diffusion process, the image data A in FIG. 37 is 7/16 for the left image data, 3/16 for the lower left image data, 5/16 for the lower image data, and 1 for the lower right image data. The data is distributed every / 16.

Therefore, in order to perform the inverse error diffusion processing, it is necessary to perform image processing opposite to that of FIG. 36 as shown in FIG. As shown in FIG. 38, image processing is performed in the arrow direction from the Nth line (N, N-1, N-2,...).
1). Contrary to FIG. 37, focusing on one pixel data, FIG.
Processing needs to be performed as shown in FIG.

However, if the image data is transmitted as shown in FIG. 34B, the reverse processing cannot be performed as shown in FIG. Therefore, as a transmission format, data is transmitted in reverse as shown in FIG.
An, DATAn-1,...). The description of whether or not this is the reverse data transmission is described in the packet format of FIG. The receiving apparatus detects this description and performs inverse error diffusion (including dithering and the like).

Although data is transmitted in reverse in FIG. 38, if the controller 281 or the like has a fixed-capacity memory (see FIGS. 30 and 31), reverse error diffusion processing is also performed in the forward direction. Can be implemented. For example, the method shown in FIG. In FIG. 41, the display screens are A, B, C,
And the like into multiple blocks. One divided block is input (held) to each memory of FIGS. The stored data (for example, FIG. 107
A block) is processed in the opposite direction in blocks 1, 2, 3, and 4. Needless to say, in FIG. 41, the data of the retained block is four rows, but the present invention is not limited to this, and it may be two rows, three rows, or five or more rows.
In particular, since the dithering method performs block processing such as 4 × 4 as shown in FIG. 54, the processing method in FIG. 41 is convenient. Also, in dithering, it is often unnecessary to perform processing in the reverse order from the opposite row in the block.

FIG. 10 is a circuit block diagram of the present invention.
The gray scale MLS circuit 106 shown in FIG. 10 is a circuit that performs gray scale control by MLS calculation and frame rate control (FRC). The FRC processing is realized by the data from the memory 105 and the gradation control circuit.

FIG. 12A shows an example of a seed function. There are many kinds of orthogonal functions. In the MLS 4 for simultaneously selecting four rows of common signal lines, a 4 × 4 matrix seed function is used. As the orthogonal function, a function in which -1 is included in each row is used (in the opposite expression, 1 is included in each row). In the case where there is a row including two -1's, the use of an orthogonal function in which all of the rows are 1 increases flicker. The occurrence of flicker becomes large from the segment IC because V2 (MV2)
This is probably because the rate at which the voltage is output increases. Therefore, it is preferable to adopt an orthogonal function in which one -1 is included in each row (in an opposite expression, 1 is included one by one). Note that the signs of -1 and 1 such as -1 and 1 are also valid in the opposite sense in terms of logic.
Therefore, it goes without saying that in the following description, the sign may be reversed. Only the description is focused on the positive for ease of explanation.

As shown in FIG. 12B, when the orthogonal function is 1, the common voltage aV is applied. V is a reference voltage, and a is a bias ratio. Orthogonal function 1 is replaced by logical H (positive). Also, the orthogonal function -1 is a logical L
(Negative).

For the bias ratio a, the ideal bias ratio is determined from the number of rows of the display panel. In theory, it would be 6.5 or decimal point. However, since the voltage is created by multiplying the reference voltage in the circuit, it cannot be realized unless it is an integer. Therefore, when the ideal bias ratio is 6.5, the bias ratio a = 6
Or it needs to be 7. At this time, it is preferable to adopt an integer value larger than the ideal bias ratio for the bias ratio. This is because as the bias ratio increases, the amplitude value of the segment signal decreases, and the occurrence of flicker is suppressed. That is, the bias ratio 7 is adopted. Further, from the viewpoint of the circuit, the circuit scale can be reduced when the bias ratio is an even number. Therefore, the bias ratio is 8 rather than 7.
Is better. That is, an even value larger than the ideal bias ratio is adopted as the bias ratio a. At this time, the on / off ratio at the employed bias ratio is set to be 1.067 or more. 1.067 is n = 2 where the number of rows is １ ／ of VGA
This is the on / off ratio in the case of 40. If the ON / OFF ratio is lower than this, the image quality is greatly deteriorated.

As will be described later, in the case of the 8-gradation display, the hierarchical data corresponding to the image data DATA (2: 0) is 1 bi.
t (on or off) is selected and B shown in FIG.
[3: 0]. The B data consisting of 4 bits for 4 rows is represented by an orthogonal function H and each bit shown in FIG.
The logical operation shown in (c) is performed.

As shown in FIG. 13, the image data is ON data 1 means -V voltage, which corresponds to logic 1. Conversely, OFF data 0 means V voltage, and corresponds to logic 0. FIG. 12C shows the output on the common side, and FIG. 12 corresponds to the output on the segment side. For example, when the segment side is -V voltage and the common side is aV, a high voltage is applied to the liquid crystal layer (selected ON voltage is applied).

FIG. 11 shows the gradation MLS circuit 106 shown in FIG.
It is a block diagram of. The gradation data shift circuit 111 has gradation data including at least a plurality of registers. This gradation data is shown in FIG. The output value of the gradation data shift circuit 111 is compared with 3-bit data of DATA [2: 0] to determine on / off. DAT
In A [2: 0], four rows are simultaneously selected in the MLS of four rows, or four rows are simultaneously read, or one row is sequentially read out of the four rows. Four rows are collected, and the output of the gradation selection circuit is 4-bit B [3: 0].

Although the MLS 4 is shown as an example for ease of explanation, the present invention is not limited to this, and an eight-row simultaneous selection (MLS 8) may be used. Further, simultaneous selection of seven rows (MLS7) may be used. MLS4
Therefore, four rows are collected, and the output of the gradation selection circuit is 4
It was a bit. However, in the case of MLS8, eight rows are collected, and the output of the gradation selection circuit is 8 bits. Therefore, the present invention is not applied only to the MLS4, but may be applied to other driving methods for a liquid crystal display panel or the like.

The HSEL [1: 0] signal shown in FIG.
It is a bit selection signal, and selects each row of the orthogonal function of FIG. 14A with 2 bits. The orthogonal function is stored in ROM in the segment driver 14 and transferred to the common driver 15 every 1H (or the orthogonal function stored in the common driver is selected). Preferably, the orthogonal function is stored only on the segment driver side. This is because the hardware scale is reduced.

Generally, as shown in FIG. 6B, one frame is composed of four fields. The orthogonal function in FIG. 14A is made different for each field. In the first field, the first row of the orthogonal function is selected and used to perform an MLS operation with DATA. In the second field, the orthogonal function 2
The line is selected and the MLS operation is performed in the same manner. In the third field, the third line of the orthogonal function is selected and the MLS operation is performed, and in the fourth field, the fourth line of the orthogonal function is selected and the MLS operation is performed. Note that, here, it is described that the MLS operation is performed, but this is for ease of explanation. Actually, it is not a MLS operation but a simple decoder circuit.

Each row 1H [3: 0] of the orthogonal function is output from the orthogonal relation ROM 113 in response to the row selection signal HSEL [1: 0]. It is preferable that the selection order of each row be variable. This is because, depending on the type of the image, a better result such as a reduction in splicing can be obtained by replacing the row of the orthogonal function to be selected.

The data IH [3: 0] of each row is input to the inversion processing circuit 114. The inversion processing circuit 114 performs data inversion processing. Reverse processing is normally white (NW)
Mode and a normally black (NB) mode (NW / NB) and an alternating signal PM. Note that P
M is a signal polarity switching signal for nH inversion driving.

In the present invention, switching between NW and NB is realized by inverting the sign of only one of the orthogonal function in the segment and the common driver. The AC conversion is performed by simultaneously inverting the signs of the orthogonal functions of both the segment and the common driver. As described above, by realizing AC by inverting the sign of the orthogonal function, the hardware scale can be reduced. This is because, compared to the method of inverting the sign of the image data, it can be realized only by inverting the data of 4 × 4 = 16 of the orthogonal function.

In practice, the orthogonal function is stored in the ROM only in the segment driver IC 14, and is sequentially transferred to the common driver IC 15 from the segment driver IC. Therefore, the orthogonal function is not stored in the ROM in the common driver IC 15. By employing the sequential transfer method in this way, the hardware scale can be reduced. The orthogonal function may be configured to be transmitted from outside the driver chip into the chip using a three-wire bus, an IIC bus, RS232C, or the like.
Alternatively, a configuration may be adopted in which a large number of orthogonal function rows of four or more are stored in a ROM in a segment chip, and any of the rows can be selected.

In the configuration in which the orthogonal function is transferred from the segment driver, the switching of the NW / NB is performed by transferring the inverted sign of the orthogonal function from the segment driver IC to the common driver IC. AC drive such as nH inversion inverts the sign of the orthogonal function of the segment driver IC and transfers the orthogonal function of the inverted sign to the common driver IC. Needless to say, the orthogonal functions obtained by inverting the signs of the four rows shown in FIG. 12A are stored in a ROM, and any one of 4 + 4 = 8 orthogonal functions is selected and transferred. Good. In this case, the hardware for inverting the sign and transferring is not necessary. Therefore, the driver operation becomes clear.

In the present invention, as shown in FIG. 14B, the voltage applied to the liquid crystal layer is negative when PM = 0, and positive when PM = 1. In the present invention, as shown in FIG. 14C, when NW / NB is 0, NB (normally black mode) is set, and when NW / NB is 1,
NW (normally white). Therefore, N
The output of the orthogonal function H [3: 0] is as shown in FIG. 14D due to the signals of W / NB and PM.

The MLS circuit 115 outputs B [3: 0] and H
[3: 0] is calculated. The operation is performed on each bit.
That is, B

[0] and H

[0], B [1] and H [1], B
The calculation is performed using [2] and H [2], and B [3] and H [3]. The operation logic is shown in FIG. The result is Q [3: 0]. As is clear from the logic of FIG.
It becomes X-NOR logic.

The addition circuit 116 counts the number of “1” bits of Q [3: 0]. The result of the count is S [2:
0]. This conversion table is shown in FIG. However, in actual hardware, it is realized by a decoder circuit instead of an addition circuit. Based on the value of the output S [2: 0] of the addition circuit 116, the voltage selection circuit 117 turns on the corresponding switch and outputs this voltage to the segment signal line. FIG.
15 corresponds to S [2: 0] in FIG. That is, the voltage is selected based on the value of S.

In the above description, for ease of explanation,
It has been described that the MLS operation is performed by the gradation MLS control circuit 106 and the result is totaled by the addition circuit 116, but the actual circuit does not perform such processing. The MLS circuit and the addition circuit are integrally formed. Specifically 1
And one decoder circuit. By using a decoder circuit in this manner, the circuit scale can be reduced. Therefore, neither the MLS operation nor the addition processing is performed. Logically, it is composed of a simple combination circuit. Further, in order to minimize the scale of the gate circuit, the image data is inverted and input in advance.

In the case of MLS4, the voltage values are V2, V1,
VC, MV1, and MV2. The relationship between the five values is | V1 | = | MV1 |, | V2 | = |
MV2 |, V2 = 2 × V1, and MV2 = 2 × MV1.

The above processing is performed in one horizontal scanning period (1H). Note that four common signal lines are simultaneously selected in one horizontal scanning period (1H). Therefore, the present invention provides 1H
At least four clocks. That is, the main clock is four times 1H.

A driving circuit (driver) of the display device of the present invention
Is more specifically shown in FIG. That is, the signal processing circuit 202 shown by the dotted line in FIG. 11 is configured for each segment signal line shown in FIG.

In the circuit block of the present invention, only one of R, G and B processing circuits is shown for ease of explanation. That is, the circuit scale of the color display device is about three times. In the description of the present specification, description will be made as a monochrome display, and color processing such as R, G, B, etc. will not be mentioned. However, it is not limited to this. Also,
In the case of two-color display, it is twice as large as in the case of black and white, and in the case of six-color display, it is six times.

As shown in FIG. 20, the gradation data wiring 2 from the gradation data shift circuit 111 is connected to the segment IC 14.
03 is wired in the lateral direction of the segment chip 14. The gradation data shift circuit 111 is a control circuit 2
01. Further, power is supplied from a power supply circuit 104 including a DCDC converter (such as a charge pump). The signal processing circuit 202 includes the gradation data wiring 2
03 are sequentially connected for each gradation. The output of the signal processing circuit 202 is applied to a buffer circuit 204 and further output to a segment signal line 206. Also, V3
(MV3) A voltage or the like is applied to the common signal line 205 by the common driver 15.

As an example of the gradation register, a configuration shown in FIG. 17 is exemplified. In this configuration, the maximum number of registers is 13
It is. Since the tone number 0 is always off and is off, there is no need to provide a tone register, but it is described for ease of explanation. Similarly, since the tone number 15 is always on and is on, there is no need to provide a tone register, but it is described for ease of explanation.

Tone No. 0 is represented by 0/1 and the gradation N
o. 1 is represented by 1/13, and gradation No. 2 is indicated by 1/7, and gradation No. 3 is represented by 1/5, and the gradation No. 4 is represented by 1/4, and gradation No. 5 is represented by 1/3, and the gradation No. 5 6 is indicated by 2/5, and the gradation No. 7 is indicated by 6/13, and gradation No. 7 is indicated. 8 is indicated by 7/13, and gradation No.
9 is indicated by 3/5, and gradation No. 9 10 is indicated by 2/3, and the gradation No. 11 is indicated by 3/4, and gradation No. 12
Is represented by 4/5, and gradation No. 13 is indicated by 6/7,
Tone No. 14 is indicated by 12/13, and the gradation No. Fifteen
Is shown as 1/1.

FIG. 18 shows an adjacent data difference of the gradation data shown in FIG. The gradation difference is an ideal value (1/15
= 0.667), which falls within the range of 20%. Therefore, good 16 gradations can be displayed without gradation skipping. Further, since the maximum number of frames of the gradation is 13, it is short compared to 15, so that flicker hardly occurs.

The gradation data wiring 203 is connected to the signal processing circuit 20.
2 is input. Further, the image data DATA [3: 0] is input to the signal processing circuit 202, and the output of the gradation data wiring 203 corresponding to this data is selected.

As shown in FIG. 0/1 of 0
The inverted pattern of gradation No. is 1/1 of gradation 15 and gradation No.
The inversion pattern of 1/13 of gradation 1 is 12/13 of gradation 14, and gradation pattern No. 1 is 13/13. The inversion pattern of 1/7 of 2 is gradation 13
Of the gray scale No. The inversion pattern of 1/5 of gradation 3 is 4/5 of gradation 12, and gradation No. The inverted pattern of 1/4 of gradation 4 is 3/4 of gradation 11, and gradation No. The inversion pattern of 1/3 of gradation 5 is 2/3 of gradation 10, and gradation No. Inverted pattern of 2/5 of gradation 6 has 3/5 of gradation 9, and gradation No. The inverted pattern of 6/13 of 7 is 7/13 of gradation 8. That is, the bits of each register are in a mirror relationship. That is, the gradation No. 0 to No. 7 indicates that the gradation No. 7 is inverted. No. 15 to No. It becomes 8. Therefore, the gradation No. 0 to No. 7 pairs or gradation N
o. No. 15 to No. If there is one of the eight sets, the other can be restored. The present invention makes use of this point and uses the gradation No. 8 to No. 15 is omitted.

As shown in FIG. 20, the gradation data shift circuit 111 supplies the gradation data wiring 2 to the segment IC 14.
03 is wired in the lateral direction of the chip 14. In the case of the data shown in FIG. 0 is one, and gradation No. 1 is 13 lines, gradation No. 2 is 7 lines, gradation No. 3 is 5 lines, gradation No. 4 is four lines, gradation No. 5
Are three, gradation No. No. 6 is 5 lines, gradation No. 7, there are 13 lines, so the total is 51 lines (however, gradation No. 0 can be omitted). Since this is the case of one color, in the case of RGB, the number is 153, which is tripled. If the configuration in which the registers are in a mirror relationship is not adopted, it is twice as large as 30.
The number is zero or more, and the gradation data wiring alone occupies a considerable area of the chip.

The frame rate control method (FR
When displaying in C), as the number of gradations increases, the data length (denominator) for displaying gradations, that is, the number of frames, increases.
Therefore, flicker is likely to occur. Therefore, in order to suppress the occurrence of flicker, it is preferable that the grayscale register be configured to be short.

In order to achieve this object, according to the present invention, as shown in FIG. 58, the length of the gradation register may be basically constituted by 8 and 12 and their common divisor. In the above-described embodiment, the maximum denominator is 13, but FIG.
In the embodiment, the maximum denominator is 12, which is small. Further, in FIG. 58, the least common multiple is also reduced to 24, and the period in which all gradations are expressed (the period in which all gradations (16 gradations) return to the start position) is shortened to 24.

With this configuration, occurrence of splicing and flicker is extremely reduced. Also, 8
In the case of gradation display, a denominator having a denominator of 12 or a common divisor thereof is adopted. In the present invention, the 8-gradation display selects and uses a part of the gradation data pattern of the 16-gradation display.

In the 8-gradation display, the gradation register No. 0
Is 0/1, No. No. 1 is 1/12, No. 2 is 1/4, N
o. No. 3 is 1/3, No. No. 4 is 1/2, No. 5 is 2 /
3, No. No. 6 is 3/4, No. 7 is 11/12, No.
8 is 1/1 (one is omitted). In this case, the cycle for expressing all the gradations in one way is 12, and
short. Therefore, even if the field shift of the present invention is performed, the occurrence of flicker due to the resolution is small. This is also an advantage.

In the 16-gradation display of FIG. 58, the difference in brightness between the gradations is also substantially equal. The largest denominator is 12
And the occurrence of flicker is small. This is not a mere design matter, but is a matter invented after image display and deep consideration. Note that in FIG. 0 and N
o. Although 15 is illustrated for ease of explanation, it is needless to say that a circuit can be configured without any particular configuration.

In FIG. 58, the gradation register No. 0 is 0
/ 1, No. No. 1 is 1/12, No. No. 2 is 1/8, No.
No. 3 is 1/6, No. No. 4 is 1/4, No. 5 is 1/3, N
o. No. 6 is 3/8, No. 7 is 5/12; 8 is 1 /
2, No. 9 is 7/12; No. 10 is 2/3, No.
No. 11 is 3/4, No. No. 12 is 5/6, No. 13 is 7 /
8, no. No. 14 is 11/12, No. 15 is 1/1. In particular, no. Since 1/2 of 8 is a pattern that is repeatedly turned on and off, there is no flicker at all.

Further, since the maximum length of the denominator of the gradation is 12, the common divisor of 12 is large (4, 3, 2, 6, etc.), but most of the gradation data (No. 1, 3, 4, 5). , 7,8,9.
10, 11, 12, 14) are repeated in 12 frames. Therefore, interference between gray levels hardly occurs. Also,
Splicing is unlikely to occur even with videos. No. of gradation register 2, No. 6, no. The data length of 13 or the like is also 8, and the common divisor of 4 is also 4 or 2, which coincides with the common divisor of 12. Therefore, the configuration in which 1/12 and 1/8 are combined hardly causes interference or the like.

[0368] No. No. 8 has a meaning adopted since it is a pattern in which flicker does not occur. There is a meaning that there is no “jump” between the gradations even in the gradation data without the mirror configuration of No. 6. No. When the tone pattern is arranged at the mirror position of No. 6, 7 from 5/12. 9 (If there is no 1/2 of No. 8, the next
9) is too far apart ("jump" occurs).

However, this gradation pattern is not necessarily limited in FIG. 58. For example, no. 1 in 2
/ 7 is No. No. 13 has 1/7 inserted (replaced configuration); 5/8 is placed at the mirror position of 6, and N
o. 7/5/12 or No. 7 A configuration in which 7/12 of 9 is deleted may be employed. In addition, No. 3 and No. 1 in 4
5 and the like may be arranged.

The gradation pattern shown in FIG. 58 has sufficient gradation display performance. Also, if necessary, perform error diffusion processing,
It is also possible to correct gradation jumps and make the gamma characteristic linear. Further, the number of gray scales can be increased by adopting the area gray scale display of error diffusion, which is preferable.

The gradation data shift circuit 111 is controlled by the control circuit 201, and is supplied with power from a power supply circuit 104 including a DCDC converter and a charge pump. As shown in FIG. 21, the signal processing circuit 202 is sequentially connected with a gradation data wiring 203 for each gradation.
The output of the signal processing circuit 202 is
Is applied to Each voltage (V2,
V1), a high-impedance circuit is configured to prevent the generation of a through current flowing when switching.

FIG. 21 shows the signal processing circuit 202 in more detail. The gradation data wiring 203 is input to the signal processing circuit 202 provided for each segment signal line, one by one for each gradation. On the other hand, the image data DATA [479: 0] (the data is 4 bits of 16 gradations and the number of pixels in one row is 120 pixels, that is, 4 × 120 = 480) is read out row by row. Then, the data is supplied to the signal processing circuit in units of 4 bits. The gradation data wiring 20 corresponding to the value of this image data
3 is selected, and the selected data (1 or 0) and the orthogonal function are calculated.

As shown in FIG. 19, since the configuration of mirror inversion is adopted, the circuit configuration of FIG. 22 is used to restore data. The number of the switch S is selected by the lower three bits of the image data D [3: 0]. Since it is the lower three bits, it takes a value of 0-7. Therefore, the switch S0
-S7 can be selected. The selected data is X
-Applied to terminal a of NOR. On the other hand, the most significant bit D3 of the data is applied to the terminal b of the EX-NOR. If D3 is 1, the data at terminal a is inverted. That is, the data related to the mirror is output to the terminal c. If D3 is 0, it is not inverted. By adopting such a configuration, mirror inversion can be realized. Therefore, about half of the gradation register can be omitted. Therefore, the number of gradation wirings 203 can be significantly reduced. If the data of the gradation register is transferred at double speed, the number of wirings 203 can be further reduced to １ ／.

The output c of the EX-NOR in FIG. 22 becomes the output of the signal processing circuit 202 in FIG. 20, and these processes are repeated four times in the case of MLS4.
[3: 0]. Of course, in MLS2, B [1:
0] and B [7: 0] in the MLS8.

Even with the gradation pattern of FIG. 19, the gradation display performance is sufficient. Also, if necessary, perform error diffusion processing,
It is also possible to correct gradation jumps and make the gamma characteristic linear. Further, the number of gray scales can be increased by adopting the area gray scale display of error diffusion, which is preferable.

Note that it is important to reduce the amplitude values of the voltages V3 and MV3 output from the common driver IC15. This is because the withstand voltage of the driver IC 15 can be reduced, and the generation of unnecessary radiation can be reduced. In order to lower the voltage output from the common driver IC 15, a dummy pulse is superimposed on the signal output from the segment driver 14. The dummy pulse has a width of 1/8 to 1/16 of 1H, and the voltage amplitude is V2 or MV.
2. Whether to use V2 or MV2 is determined according to the voltages output from the four common driver ICs. 4
When three of the three selection voltages are V3, the dummy pulse is MV2. When three of the four selection voltages are MV3, the dummy pulse is V2. This is so that a larger effective value can be applied.

The dummy pulse is applied to each signal line at the same voltage value, the same pulse width, and the same timing. By adjusting the voltage value and pulse width of the dummy pulse, the effective voltage applied to the liquid crystal changes. The timing of applying the dummy pulse is an arbitrary position in one horizontal scanning period.

Thus, the dummy pulse is applied to each signal line.
If the same voltage value, the same pulse width, and the same timing are applied, when a dummy pulse is applied, no potential difference occurs between the signal lines, so that interference due to stray capacitance coupling formed between the signal lines is eliminated, and the vertical streak and The occurrence of display unevenness can be reduced. Also, since the signal voltage is apparently increased in frequency, the display quality is improved. Further, since the amplitude value of the voltage output from the common driver IC can be low, the withstand voltage of the common driver IC can be reduced.

In the case of MLS4, the voltage values are V2, V1,
VC, MV1, and MV2. The relationship between the five values is | V1 | = | MV1 |, | V2 | = |
MV2 |, V2 = 2 × V1, and MV2 = 2 × MV1. Hereinafter, the power supply circuit of the present invention will be described with reference to FIG.

FIG. 44 shows a power supply circuit such as a display device of the present invention. In FIG. 20, etc., 201 corresponds. However, V3 and MV3 are not generated in the segment driver IC 14, but V2 voltage is applied to the common driver IC1.
5 is applied. It is preferable to generate a V3 voltage or the like in the common driver IC 15 from the applied V2 voltage or the like. This is because the V3 (MV3) voltage or the like is higher than the withstand voltage of the segment driver 14. If it is configured to be generated by the segment driver IC 14, the withstand voltage of the segment driver IC also needs to be manufactured by the withstand voltage process of the common driver IC. Then, the chip size becomes very large.

The input power supply voltage of this power supply circuit is VCC
(First input potential), only VSS (second input potential), and a single power supply input. Horizontal scanning period (1H)
A latch pulse LP composed of a pulse generated every time is input. The latch pulse has a frequency of + 10%,-
It is configured so that it can be changed within the range of 10%. In addition, it is configured so that the frequency can be changed to twice or half. This is because if the latch pulse is 1H, horizontal lines may be generated every four rows on the display screen of the display panel 21.

The clock forming circuit is basically necessary for the charge pump circuit based on the clock signal (LP signal) and forms several clock signals having different timings. VCC and VSS are used as power supplies.

The primary boosting circuit 441 generates a primary voltage based on the VCC and VSS voltages, and this primary voltage is input to the next electronic regulator 442. Electronic volume 442
Has a function of changing the voltage in at least 32 steps. Preferably, it is configured to be able to change in 64 or more steps. The voltage of the electronic regulator 442 becomes the reference voltage VC.

The electronic volume circuit is more specifically shown in FIG.
Circuit configuration. Electronic volume circuit is TAP1, TA
The voltage between P2 is divided by a resistor to generate a voltage VC0 to be input to a VC generation circuit. VEV-T
Between AP1, between TAP1-TAP2, TAP2-TAP3
External resistors R1, R2, and R3 are connected between them, and TAP1-
A voltage is applied to the built-in resistor between TAP2 and a voltage VC0 obtained by dividing the voltage by a switch is obtained. Switch SW is CMO
It is composed of S transistors.

The positive-direction secondary booster circuit 443 generates a voltage V2 obtained by boosting VSS twice in the positive direction based on the voltage VC of the electronic regulator 442 by a charge pump operation. Similarly, the tertiary booster circuit 444 generates a voltage V3 that is boosted three, four, and five times in the positive direction based on the V2 voltage and the VC voltage by a charge pump operation. Switching between 3, 4, and 5 times can be changed by a command.

[0386] The negative-direction double boosting circuit 445 is provided with VC and V3
MV3, which is a voltage boosted twice in the negative direction based on the reference voltage, is generated by the charge pump operation. 1/2 step-down circuit 446
V1 and VC- are voltages obtained by dividing the voltage between V2 and VC into two equal parts.
MV1 which is a voltage obtained by dividing the interval between (MV2) into two equal parts is generated by the charge pump operation. Alternatively, it is generated by resistance or transistor voltage division.

VC is used as it is for central potential VC.
MV2 corresponding to VSS is used as it is. Thus, a voltage for driving the liquid crystal display device can be generated. In this power supply circuit, the output voltages V3 and MV3, V2 and MV
2. V1 and MV1 are symmetric with respect to VC. In addition,
The half circuit 445 employs a circuit configuration as shown in FIG. That is, voltage outputs such as V2, V1, MV1, and MV2 require a constant current output and are output via the operational amplifier 451. Since VC is the center voltage, the operational amplifier 451 may not be necessary. Further, since the voltages V3 and MV3 are used on the common scanning side, the output current is also small, so that the operational amplifier 4
There is no need to go through 51. Of course, the operational amplifier 451
It is needless to say that may be configured.

The half circuit 445 is shown in more detail in FIG.
5 is configured. V generated by electronic volume circuit
C0 is amplified by an operational amplifier to generate a VC voltage. The operational amplifier is composed of a main operational amplifier PVC for discharging current and a sub operational amplifier PVCS for pulling in. The differential input transistors for pulling in are left and right asymmetrical so that the discharging and pulling-in do not cause penetration, and an offset is provided. The asymmetric ratio is 0.5% or more and 5% or less. Especially, it is preferable to set it to 1% or more and 3% or less.

The amplification is connected to a resistor so that VC = 2VC0. Note that the resistance value R1 between VSS and VC and V
The resistance value between R and C2 is equal to R2. Ideally R
It is preferable that 1 = R2, but at least the deviation of the ratio needs to be 2% or less.

The V1 and MV1 operational amplifiers are also composed of discharge and pull-in operational amplifiers. V1 discharges, and MV1 pulls in as a main amplifier.
Discharge and retraction change the input voltage so that no penetration occurs. Input voltage difference between main and sub is 2/2
00 × V2. This input voltage difference is set to be at least 1/200 × V2 and not more than 10/200 × V2, more preferably at least 1/200 × V2 and not more than 6/200 × V2.
Make sure that:

Although FIGS. 44 and 45 are more specific, they will be complicated to understand the contents of the following description.

In FIG. 47, the 1/2 voltage dividing means 445 is shown as a resistor 472, but the invention is not limited to this. For example, the voltages V1, MV1, etc. may be generated by the voltage division of a plurality of MOS transistors, or may be generated by a charge pump circuit. Further, as shown in FIG. 51, it may be generated by a (MOS) transistor, a resistor, a volume, or the like. Further, a large number of ladder resistors are arranged as shown in FIG.
A configuration in which the voltage division ratio is changed by selecting with SW, or a configuration in which a large number of MOS transistors are controlled and selected by a switch arranged at an arbitrary position to change the voltage division ratio may be employed.

As can be seen from FIG. 44, the voltage required for driving the liquid crystal is based on the output of the electronic regulator 442, and this voltage is multiplied to generate the required voltage.
However, the highest voltage V used in the common driver IC
3. There is a problem in the generation of MV3. Common driver IC
There is a problem that the breakdown voltage exceeds 15 withstand voltages. Of course, the V2 and MV2 voltages used in the segment driver IC 14 also pose a problem. However, here, for ease of explanation, the voltages V3 and MV3 used for the common driver IC are used.
This will be described as an example. Accordingly, V2 and MV2 of the segment driver IC need only correspond according to V3 and MV3, and the description is omitted.

The common driver IC 15 has a withstand voltage of V3-
(−MV3). For example, if the withstand voltage of the common driver IC 15 is 18 (V), V3 = 9
(V), MV3 = −9 (V). However, when adjusting the electronic volume by contrast adjustment, temperature compensation, or the like, the voltage exceeds this withstand voltage. In particular, the voltage required to obtain a predetermined transmittance becomes higher as the temperature of the STN liquid crystal becomes lower. If the breakdown voltage is exceeded, the common driver IC will be destroyed.

The conventional driver IC is an electronic volume 442
There was no measure other than limiting the maximum step value of the microcomputer. However, if the limitation is made simply by the step value, a large margin is required in spite of the problem only at a low temperature. If the margin is increased, it is necessary to adopt a semiconductor device having a high withstand voltage as a semiconductor process for manufacturing the driver. A device with a high withstand voltage has a large process rule and a large chip size.

To cope with this problem, the output voltage from the reference voltage generation circuit is applied to the maximum voltage generation circuit (not shown) and the electronic regulator 442. The maximum voltage generating circuit is composed of a charge pump circuit, and the common driver IC 15
Is produced (actually, a voltage smaller than the MAX voltage by a predetermined value). This voltage is temperature compensated by a thermistor or a feedback circuit.
Not affected by ambient temperature.

On the other hand, the electronic regulator 442 changes the step according to the command, and changes the output voltage. The changed voltage is applied to the third booster circuit 4 as described with reference to FIG.
44, V3 and MV3 are created by the negative direction double boosting circuit 446.

Now, assume that the output voltage of the maximum voltage generating circuit is Vm, and the output voltage of the booster circuit 444 is Vb. This Vm
And Vb are compared by a comparator. It has a certain hysteresis and a certain delay due to a capacitor circuit formed inside the comparator. Therefore, when Vb exceeds Vm, an H level voltage is output. When Vb does not exceed Vm, an L level voltage is output. Further, once the voltage exceeds Vm, the voltage does not become the L level voltage unless the predetermined voltage becomes lower than the Vm voltage. This is because the operation of the display device becomes unstable when the level is frequently switched to the H or L level.

When the electronic volume control circuit receives the input of the H level voltage, the electronic volume control circuit performs control so that the step value of the electronic volume does not increase. Therefore, even if the user operates the electronic regulator for contrast adjustment and brightness adjustment, the final output voltage Vb of the electronic regulator does not increase. Therefore, the common driver IC does not exceed the withstand voltage.

A temperature sensor (not shown) may be separately provided, and control may be performed so that the step value of the electronic regulator 442 does not change with the output of this temperature sensor. What is important is that a predetermined voltage indicating withstand voltage is separately formed, compared with a drive voltage (V3) of the liquid crystal display panel, and the like, and a reference voltage changing means such as an electronic regulator is controlled based on a result of the comparison.

Although the above description is for a common driver IC, the same applies to a segment driver IC. If V3 of the common driver IC 15 is read back as V2 voltage of the segment driver IC 14, the described circuit configuration or method can be applied.

As previously described, ideally V1
And MV1 have the same absolute value, and V2 and MV2 have the same absolute value. V2 = V1 × 2, and MV2 = MV1
× 2. However, such a setting makes crosstalk more likely to occur.

To prevent this, when the image is in the NB mode (when the display panel is in the NB mode), it is preferable that the value of V2 is smaller than V1 × 2 by 0% or more and 5% or less. More preferably, it should be smaller by 0.5% or more and 3% or less (V1 × 2> V
2).

Conversely, when the image is in the NW mode (the display panel), the value of V2 should be larger than V1 × 2 by 0% to 5%. More preferably 0.5% or more and 3%
It is better to increase the value below (V1 × 2 <V2).

With this range, crosstalk is less likely to occur in the displayed image, and good image display can be realized. This is considered to be related to the fact that the image becomes darker when V2 is set smaller in the NB mode, so that the occurrence of crosstalk is less noticeable even if the value slightly deviates from the ideal value.

For consideration of the reason or the variable range, the reflection type STN liquid crystal display panel of the NB mode is shown in FIG.
A black window was displayed as shown in Fig. The central portion C of the screen is a portion of 0% luminance (black), and the periphery (portions A and B) is a reflection (or transmission) portion of 50% luminance. Originally, the portions A and B should have the same 50% luminance. However, the portion A is actually affected by the central portion C, and the portion B is
(The transmittance may increase depending on the liquid crystal mode or the like). FIG. 49 is a graph of the change ratio of the transmittance.

The vertical axis of FIG. 49 indicates the transmission ratio,
% Indicates a case where the transmittance (reflectance) of the portion A and the portion B is the same. Therefore, when the portion B becomes dark, the ratio is indicated by-. The horizontal axis is V2 voltage and V
It is a ratio of one voltage (V2 / V1). However, V2 = −
MV2, V1 = −MV1. Ideally (theoretically), V2 / V1 is 2.

In this state, the ratio of V1 to V2 is changed and plotted on a graph.
In the display in the B) mode, it seems that the transmittance does not change most when V2 / V1 is 1.975. Expressed as a percentage, it is about 1.5%. What does not seem to be
This is because it differs depending on the size of the window and the like.
In addition, in practice, the evaluation was not performed only on the window screen, but a large number of natural images were displayed and the state of the crosstalk was comprehensively determined. Therefore, FIG.
May be understood as a conceptual diagram for explanation. Therefore, the transmission ratio in the graph 49 does not mean only the transmission measured by the measuring instrument.

In any case, in the NB mode, V2
When / V1 is smaller than 2, no draw such as crosstalk occurs (it is difficult to see), and a good image display can be realized. The ratio is about -5%, and the ideal state exists at the center between -5% and 0% or between -3% and 0%. That is, in the NB mode, the value of V2 may be smaller than V1 × 2 by 0% or more and 5% or less.
More preferably, it should be smaller by 0.5% or more and 3% or less (V1 × 2> V2). As can be seen from the graph of FIG. 87, there is a tendency that the transmission ratio curve becomes sharply sharp from a transmission ratio of about −3%. Transmission ratio is 3% for actual images
When the length of the image exceeds the limit, many vertical streaks are generated in the natural image, and the image tends to be significantly deteriorated. 3% of the transmission ratio is 100 /
3 = 33, and the resolution exceeds 30. It is said that it is enough for current televisions to be able to display 32 gradations. Therefore, if the difference is not more than about 3%, it is presumed that the determination is difficult. For this reason, V falls within the range where the transmission ratio is -3%.
It is appropriate to accommodate the 2 / V1 ratio.

[0410] Conversely, when the image is in the normally white (NW) mode (display panel), NB is set as shown in FIG.
A completely opposite relationship to the mode was obtained. Therefore, NW
In the mode, the value of V2 is 0% or more with respect to V1 × 2.
% Or less. More preferably, it should be larger by 0.5% or more and 3% or less (V1 × 2 <V2). By setting the value in this range, crosstalk hardly occurs in the display image, and a favorable relationship can be obtained.

The problem is that the ratio of V2 / V1 differs depending on the liquid crystal mode, the liquid crystal material, the ambient temperature or the displayed image. Talking about the display image, in the case of eight-color display, even if the ratio of V2 / V1 is relatively deviated from 2, the influence of crosstalk and the like is less likely. However, 409
In the case of a six-color natural image, it is easy to receive. Therefore, it is preferable to change the ratio of V2 / V1 depending on the ambient temperature, the number of display colors, and the like.

The present invention is configured so that the ratio of V2 / V1 can be changed in eight stages by external command control. FIG. 50 is a circuit diagram thereof. Voltage control unit 501
Changes the voltage dividing ratio of the voltage dividing circuit 503 to V2 / V1
Is changed. As an example of the voltage control unit 502, there is a volume configuration shown in FIG. The control target is not limited to the resistance, but may be a current value,
It may be a voltage value. Here, in order to facilitate understanding, a description will be given on the assumption that the control target is a resistance value. Also, V2 / V1
It is preferable that the minimum value can be changed in steps of about 0.5% or about 1%. Also,
It is preferable that the IC chip is configured so that the number of steps can be changed from 4 steps to 16 steps.

[0413] The voltage dividing circuit section 503 is a volume that can be switched in predetermined steps as shown in Fig. 50B. That is, by switching the tap, the voltage of V2 or V1 is changed, and as a result, the ratio of V2 / V1 is changed. The tap position can be changed by an external command. More specifically, as shown in FIG. 52, an analog switch (ASW) is arranged at a predetermined position of the voltage dividing resistor R, and an arbitrary analog switch (ASW) is turned on / off by a 3-bit command (D0, D1, D2). What is necessary is just to comprise so that it can be performed.

When (D2, D1, D0) is 0, the decoder 521 selects the terminal G0 and sets the analog switch ASW0.
Turn on. When (D2, D1, D0) is 1, the decoder 521 selects the terminal G1, and the analog switch ASW
Turn 1 on. When (D2, D1, D0) is 2, the decoder 521 selects the terminal G2, and the analog switch AS
Turn on W2. The same applies hereinafter.

In the present invention, the voltage division ratio V2 / V1 is switched by a command, but the invention is not limited to this. For example, a liquid crystal display panel is manufactured by selecting either NB or NW from the time of manufacturing the module. That is, one panel is not used in the NW mode or used in the NB mode (or rarely). Therefore, if the liquid crystal display panel is in the NB mode, V2 /
The ratio of V1 may be set lower by 0.5% to 3%.
That is, the ratio of V2 / V1 may be set to be smaller than 2. If the value of V2 / V1 is fixed, the voltage control circuit 501 is not necessary, and the voltage dividing circuit 5
03 does not need to adopt the configuration shown in FIG.

In the case where V2 / V1 is fixed, the resistance values R1 and R2 in FIG. 84 may be fixed. FIG.
In this case, the size of the MOS transistor or the channel width W and channel length L of the transistor may be designed to predetermined values.

Also, as shown in FIG. 53, there is a method of changing with a mask pattern. In FIG. 53, reference numeral 532 denotes a ladder resistor (resistance wire) connected in series. A contact portion (connection point) 531 is formed at a connection point of the ladder resistor 532. On the other hand, a metal wiring 533 is arranged in parallel with the ladder resistor 532. The contact portion 531 of the metal wiring 533 and the contact portion 5 of the ladder resistor 532
31 with a connection line 534, V2 and V2
The ratio of 1 can be changed. That is, V1 is applied to the metal wiring 533.
A voltage is output.

In the configuration of FIG. 53, the connection line 53 is
4, and the ratio between V2 and V1 is fixed. In addition, by switching the connection points, V2 / V1
Can be changed. Therefore, it is possible to change the connection between the contact portions 531a and 531b in the NW mode and to connect the contact holes 531c and 531d in the NB mode. Therefore, the driver chip can be manufactured for the NW mode and the NB mode with only one mask change.

As shown in FIG. 50, if a command from an MPU or the like is decoded and an external switching means 502 for controlling the voltage control section 501 is provided, the V2 / V1 ratio control is very simple. Also. If the NW / NB switching means is provided, it is easy to switch between the NW mode and the NB mode.

Another problem is that the viscosity of the liquid crystal changes depending on the temperature, and the responsiveness changes. Therefore, the appropriate ratio of V2 / V1 differs depending on the temperature of the liquid crystal display panel. As a result of the examination, as the temperature becomes higher, V2 / V
It is better to make the ratio of 1 closer to the ideal value of 2. In order to cope with this problem, a temperature sensor may be separately provided and the voltage division ratio (V2 / V2) may be controlled in consideration of the output result of the temperature sensor.

[0421] The voltage dividing circuit 503 and the like include not only a mechanical configuration but also all electrical configurations using analog switches. In addition, a mechanical relay, a configuration in which the voltage dividing ratio is changed by changing the resistance value by light irradiation, a configuration in which the voltage dividing ratio is changed by applying a voltage, and the like may be used.
This is because the purpose is to change the ratio of V2 / V1 by some means. Although the above embodiment is for the case of MLS4, other MLS driving, for example, MLS6, MLS
Even in the case of 8 or the like, since the relationship such as V2 / V1 occurs, it goes without saying that the contents of the present invention can be applied.

The common driver IC outputs the selection voltage V3 or the reverse polarity MV3 voltage. This V
The brightness of the screen may be adjusted by adjusting the 3 (MV3) voltage. The variable range of V3 is in the range of ± 10%, more preferably ± 5%. Further, adjustment of only V3 is easy, and the adjustment circuit can be simplified.

Although the reference numeral 451 is an operational amplifier, the present invention is not limited to this, and it is needless to say that an operational amplifier is not particularly necessary when the output current is small.

The drive circuit and drive I of the present invention described above
If a display panel or a display device is configured by employing C (driver) or a driving method, a display device with low power consumption, high image quality, and small size and light weight can be configured.

The display device of the present invention can be used in a transmission type, a reflection type or a transflective type. In the case of a reflection type or the like, illumination means is required when the surroundings are dark. A self-luminous element such as an LED, an organic EL, or a fluorescent tube is used as the lighting means. In particular, it is desirable to use a white LED because it is lit by a direct current (voltage) and is compact.

The light guide plate may be either a backlight system or a front light system. The material may be any transparent resin material such as acrylic and polycarbonate. Further, an inorganic material such as a glass plate may be used.

A white LED (light) as a light emitting element
Nitto Chemical Co., Ltd. sells a GaN-based blue LED chip surface coated with a YAG (yttrium-aluminum-garnet) -based phosphor. In addition, Sumitomo Electric Industries, Ltd.
We are developing a white LED in which a layer that emits yellow light is provided in a blue LED element manufactured using a ZnSe material.

The light emitting element is not limited to a white LED. For example, when displaying an image in a field sequential manner, one or more LEDs of R, G, and B light emission may be used. Also, R, G, B
LEDs are arranged densely or in parallel, and these three LEs
A configuration in which D is turned on in a field sequential manner in synchronization with the display on the display panel may be employed. In this case, LED
It is preferable to dispose a light diffusion plate on the light emission side of the light emitting device. By disposing the light diffusion plate, the occurrence of color unevenness is eliminated.

In the present invention, the segment driver IC
14 and 15 have been described as being made of a silicon chip, but the invention is not limited thereto. May be used. Drivers are COF, T
What is necessary is just to connect to a striped electrode using AB, COP, COG technology.

The light modulating layer of the display device of the present invention is not limited to the liquid crystal alone, but is a 9/6 layer having a thickness of about 100 microns.
It may be 5/35 PLZT or 6/65/35 PLZT. Further, a light modulating layer to which a phosphor is added, a liquid crystal to which a polymer ball, a metal ball, or the like is added may be used. Further, fine balls may be colored in black and white.

The transparent electrode such as the striped electrode has been described as ITO. However, the present invention is not limited to this. For example, a transparent electrode such as SnO ₂ , indium, or indium oxide may be used. Further, a thin film of a thin metal film such as gold may be employed. Further, an organic conductive film, an ultrafine particle-dispersed ink, or a transparent conductive coating agent “Syntron” commercialized by TORAY may be used.

In the embodiment of the present invention, TF is used for each pixel electrode.
It has been described as an active matrix type in which switching elements such as T, MIM, and thin film diode (TFD) are arranged. The active matrix type and the dot matrix type include not only a liquid crystal display panel, but also a micro mirror and a DMD (DLP) developed by TI which displays an image by changing the angle.

A switching element such as a TFT has one
The number of pixels is not limited to one, and a plurality of pixels may be connected. Further, it is preferable that the TFT adopts an LDD (low doping drain) structure.

Although the FRC control method, the switching of the frame rate, and the like have been described based on the STN binary liquid crystal, the present invention can be applied to a TFT multi-valued liquid crystal. Generally, a TFT liquid crystal is a multi-value output signal line driver (corresponding to the SEG driver 14).
A driver with 56 gradations is not suitable for a portable liquid crystal in terms of power and circuit configuration, and a method of displaying multiple gradations with a driver having fewer 8 gradations or 16 gradations and frame rate control is adopted. Can be Even in this case, if the frame rate is made variable in accordance with the number of colors, that is, the number of gradations, the degree of freedom of switching between high image quality and low power can be obtained as in STN.

The technical idea of each embodiment of the present invention is that a liquid crystal display panel, an EL display panel, an LED display panel, an FE
The present invention can be applied to a D (field emission display) display panel and a PDP. Further, the present invention is not limited to the active matrix type, but may be a simple matrix type. Even in the simple matrix type, the intersection points have pixels (electrodes) and can be regarded as a dot matrix type display panel. Of course, the reflection type of the simple matrix panel is also within the technical scope of the present invention. Others
It goes without saying that the present invention can be applied to a display panel that displays simple symbols, characters, symbols, and the like such as eight segments. These segment electrodes are also one of the pixel electrodes.

It is needless to say that the technical idea of the present invention can be applied to a plasma addressed display panel. In addition, the technical idea of the present invention can be applied to an optical writing type display panel, a thermal writing type display panel, and a laser writing type display panel having no specific pixels. Also, a projection type display device using these can be constructed.

The modes of the display panel (described without distinguishing between the mode and the mode) include the STN mode, the ECB mode, the DAP mode, the TN mode, in addition to the PD mode.
(Anti) ferroelectric liquid crystal mode, DSM (dynamic scattering mode),
The present invention can be applied to a vertical alignment mode, a guest host mode, a homeotropic mode, a smectic mode, a cholesteric mode, and the like.

The display panel / display device of the present invention is not limited to a PD liquid crystal display panel / PD liquid crystal display device, but includes a TN liquid crystal, an STN liquid crystal, a cholesteric liquid crystal, a DA
P liquid crystal, ECB liquid crystal mode, IPS method, ferroelectric liquid crystal,
Other liquid crystals such as antiferroelectric and OCB may be used. Other, P
A system such as LZT, electrochromism, electroluminescence, LED display, EL display, plasma display (PDP), and plasma addressing may be used.

The technical ideas described in the embodiments of the present invention include a video camera, a liquid crystal projector, a three-dimensional television, a projection television, a viewfinder, a monitor of a portable telephone, a PHS, a portable information terminal and its monitor, a digital camera and its monitor, Electrophotographic systems, head-mounted displays, direct-view monitor displays, notebook personal computers, video cameras, electronic still cameras, monitors for automatic teller machines, public telephones, videophones, personal computers, liquid crystal watches and their display devices, home appliances It goes without saying that the present invention can be applied or applied to a liquid crystal display monitor, a pocket game machine and its monitor, a backlight for a display panel, and the like.

[0440]

The display panel, display device, etc. of the present invention exhibit characteristic effects according to the respective configurations such as high image quality, low power consumption, low cost, and high luminance.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of a liquid crystal display device of the present invention.

FIG. 2 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 3 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 4 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 5 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 6 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 7 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 8 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 9 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 10 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 11 is an explanatory view of a liquid crystal display device of the present invention.

FIG. 12 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 13 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 14 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 15 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 16 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 17 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 18 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 19 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 20 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 21 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 22 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 23 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 24 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 25 is an explanatory diagram of a data transmission method according to the present invention.

FIG. 26 is an explanatory diagram of the information terminal device of the present invention.

FIG. 27 is an explanatory diagram of an information terminal device of the present invention.

FIG. 28 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 29 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 30 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 31 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 32 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 33 is an explanatory view of a liquid crystal display device of the present invention.

FIG. 34 is an explanatory diagram of a data transmission method according to the present invention.

FIG. 35 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 36 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 37 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 38 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 39 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 40 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 41 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 42 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 43 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 44 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 45 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 46 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 47 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 48 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 49 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 50 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 51 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 52 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 53 is an explanatory diagram of a liquid crystal display device of the present invention.

FIG. 54 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 55 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 56 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 57 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 58 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 59 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 60 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 61 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 62 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 63 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 64 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 65 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 66 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 67 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 68 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 69 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 70 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 71 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 72 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 73 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 74 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 75 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 76 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 77 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 78 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 79 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 80 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 81 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 82 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 83 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 84 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 85 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 86 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 87 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 88 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 89 is an explanatory diagram of a driving method of the liquid crystal display device of the present invention.

FIG. 90 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 91 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 92 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

FIG. 93 is an explanatory diagram of a driving method of a liquid crystal display device of the present invention.

[Explanation of symbols]

11, 12 Substrate 14 Segment driver (SEGIC, SEG drive circuit) 15 Common driver (COMIC, COM drive circuit) 21 Liquid crystal display panel (light modulation means, image display device) 101 Oscillator 102 Switching circuit 103 Divider circuit 104 Controller 105 Built-in Memory 106 Tone MLS control circuit 107 Display area (pixel forming part) 111 Tone data shift circuit 112 Tone select circuit 113 Orthogonal function ROM 114 Inversion processing circuit 115 MLS circuit 116 Addition circuit 117 Voltage select circuit 201 Power supply 202 Signal processing circuit 203 Gradation data wiring 204 Buffer 205 Common (COM) signal line (gate signal line) 206 Segment (SEG) signal line (source signal line) 261 Antenna 262 Housing 263 Speaker 264 Sound receiver 265ー 266 Display color switching key 271 Deplexer 273 LNA 274 Down converter 275 Up converter 276 LO buffer 277 PA pre-driver 278 PA 281 Error diffusion (dither) controller 291 Operation circuit 292 Processing circuit 293 Operation memory 321 Base board 322 Auxiliary board 323 Auxiliary board 421 Inverter 441 Primary booster circuit 442 Electronic volume circuit 443 Secondary booster circuit 444 Tertiary booster circuit 445 1/2 circuit 446 Negative double circuit 451 Operational amplifier 472 Voltage dividing resistor 501 Voltage control section 502 External switching means 503 Voltage dividing means 521 Decoder 531 Contact part 532 Resistance wiring 533 Metal wiring 534 Connection line 561 Pixel 562 Convex part (concavo-convex part) 571 Light transmitting part 572 Reflecting part 711 Operation Department

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G09G 3/20 641 G09G 3/20 641H 641A 641C 660 660U 660V (72) Inventor Atsuhiro Yamano Kazuma, Osaka Pref. 1006, Kadoma Matsushita Electric Industrial Co., Ltd. FA51 FA56 5C080 AA06 AA10 BB05 CC03 DD06 DD26 DD27 EE29 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06 KK02 KK07 KK20 KK43 KK49 KK50 KK52

Claims (16)

[Claims] 1. A driving method for driving a simple liquid crystal display panel in which one frame is composed of L sub-frames by a multi-line select (MLS) driving method for simultaneously selecting a plurality of (L) scanning electrodes. In performing gradation display by a frame modulation method, gradation patterns representing ON / OFF of each gradation level are held in series for four fields, and the held data is sequentially processed to calculate voltage data. A method for driving a liquid crystal display panel, wherein the converted voltage data is sequentially applied to segment signal lines of the liquid crystal display panel. 2. A driving method for driving a simple liquid crystal display panel in which one frame is composed of L sub-frames by a multi-line select (MLS) driving method for simultaneously selecting a plurality of (L) scanning electrodes. And when performing gradation display by a frame modulation method, comprising a temperature detecting means of a liquid crystal display panel, holding gradation patterns representing on / off of each gradation level for 4 fields in series, Changes shift processing according to the output result of the temperature detecting means, sequentially converts the held data into voltage data by performing arithmetic processing, and sequentially converts the converted voltage data to segment signal lines of the liquid crystal display panel. A method for driving a liquid crystal display panel, characterized by applying a voltage. 3. A driving method for driving a simple liquid crystal display panel in which one frame is composed of L sub-frames by a multi-line select (MLS) driving method for simultaneously selecting a plurality of (L) scanning electrodes. And when performing a gray scale display by a frame modulation method, a shift amount switching unit is provided, and a gray scale pattern representing ON / OFF of each gray scale level is held in series for four fields, and a shift amount of the held data is provided. Changing the shift processing by the switching means, sequentially performing the arithmetic processing on the held data, converting the data into voltage data, and sequentially applying the converted voltage data to the segment signal lines of the liquid crystal display panel. Characteristic liquid crystal display panel driving method. 4. A driving method for driving a simple liquid crystal display panel in which one frame is composed of L sub-frames by a multi-line select (MLS) driving method for simultaneously selecting a plurality of (L) scanning electrodes. In performing the gradation display by the frame modulation method, a gradation pattern shift processing circuit is provided, and the gradation patterns representing on / off of each gradation level are held in series for four fields, and the serial holding is performed. The shift processing circuit performs a shift process using the gradation data for the four fields as a set, and the shift process is at least a plurality of patterns. The held data is sequentially processed to calculate voltage data. A method for driving a liquid crystal display panel, wherein the converted voltage data is sequentially applied to segment signal lines of the liquid crystal display panel. 5. A driving method for driving a simple liquid crystal display panel in which one frame is composed of L sub-frames by a multi-line select (MLS) driving method for simultaneously selecting a plurality of (L) scanning electrodes. And performing gradation display by a frame modulation method, including a gradation pattern shift processing circuit, and holding, in series, four fields of gradation patterns representing ON / OFF of each gradation level, The difference between the maximum interval value and the minimum interval value of the ON data and the OFF data is 2 or less, and the held data is sequentially subjected to arithmetic processing to be converted into voltage data. A method for driving a liquid crystal display panel, wherein the voltage is sequentially applied to segment signal lines of the liquid crystal display panel. 6. A driving method for driving a simple liquid crystal display panel in which one frame is composed of L sub-frames by a multi-line select (MLS) driving method for simultaneously selecting a plurality of (L) scanning electrodes. In order to perform gradation display by the frame modulation method, a red gradation pattern shift processing circuit, a blue gradation pattern shift processing circuit, and a green gradation pattern processing circuit are provided, and each gradation level is turned on / off. Are held in series for four fields, the difference between the maximum interval value and the minimum interval value of the interval between the ON data and the OFF data of the held data is 2 or less, and the held data is The arithmetic processing is sequentially performed to convert the voltage data into voltage data, and the converted voltage data is sequentially applied to the segment signal lines of the liquid crystal display panel. Method of driving a liquid crystal display device comprising the color green, that is changing in blue. 7. The gradation pattern is 7FRC, 15FRC,
2. The method according to claim 1, which is one of 31 FRC.
A method for driving a liquid crystal display device according to any one of claims 1 to 6. 8. It comprises first gradation data expressing 16 gradations by frame control, and second gradation data expressing 8 gradations by frame rate control. In the case of 16 gradation display, A liquid crystal display device that displays an image with first gradation data and displays an image with second gradation data in the case of 8-gradation display. 9. It has gradation data for expressing 16 gradations by frame control, and the length of each element of the gradation data is constituted by the least common divisor of 24. In the case of 16 gradation display, , Use each element of the gradation data indicated by the common divisor of 12 and the length of the common divisor of 8. In the case of 8 gradation display, use each element of the gradation data indicated by the length of the common divisor of 12 A liquid crystal display device characterized by the above-mentioned. 10. A data having an image display unit, an image memory for at least one screen, a controller IC having a function of performing an MLS operation, and a data memory holding data received from the controller for at least one horizontal scanning period. A driver IC; and a scanning driver IC, wherein the controller IC stores the data of the image memory in ML.
S operation, calculates the voltage value of the operation result, its polarity, and its time, the data driver receives the voltage value, its polarity, and its time calculated by the controller IC, and based on the value, the segment signal line A liquid crystal display device, wherein a voltage is applied to the liquid crystal display. 11. A segment driver having a built-in memory for realizing at least one screen of eight-color display, a common driver, and a controller having at least an image memory for realizing a multi-gradation display more than the built-in memory of the segment driver. The controller performs a first operation of performing error diffusion processing or dither processing on the input image data, and a second operation of transferring the image data subjected to error diffusion processing or dither processing to the internal memory. A liquid crystal display device characterized by being implemented. 12. A segment driver for driving a segment signal line, a common driver for driving a common signal line, a controller having an image memory for at least one screen, and operating means. A first operation of performing an error diffusion process or a dither process on the image data obtained by performing an error diffusion process or a dither process, and a second operation of transferring the image data subjected to the error diffusion process or the dither process to the internal memory. A liquid crystal display device capable of switching whether to perform a diffusion process or a dither process. 13. A segment driver having a function of displaying a plurality of gray scales by frame rate control, a function of displaying 16 or more gray scales by pulse width modulation, a common driver, and a built-in memory for at least one screen. A first operation for performing error diffusion processing or dither processing on the input image data, and a second operation for converting the error diffusion processing or dithered image data into pulse width modulated data. 2. A liquid crystal display device which performs the operation of 2. 14. The liquid crystal display device according to claim 13, wherein only a built-in memory and a segment driver operate during a still image. 15. The liquid crystal display device according to claim 13, wherein a frame rate is higher in a moving image than in a still image. 16. An information display device comprising: the liquid crystal display device according to claim 10; a down converter; an up converter; a receiver; and a speaker.