JP2002124644A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily achieve a high integration and non-defective product ratio. SOLUTION: A conductive plug 24 is formed of a polysilicon. A dielectric capacitor 25 is formed, by sequentially laminating a silicide film 31, diffused barrier film 32, lower electrode 28, dielectric film 29 and upper electrode 30 from a substrate side on the plug 24. Thus, material diffusion will no occur in the plug 24 and the electrode 28, even in crystallizing step of the dielectric at a high heat treating temperature, and a ferroelectric characteristics of the film 29 becomes proper. When the electrode 28 is formed of Ir of an Ir/IrO2, an SBT is used as the film 29, so that Ir precipitates in, for example, 6-inch wafer which is suppressed to 100 pieces or fewer, and the nondefective rate of an integrated FeRAM of 256 kbits can be set to 90% or higher. A polarization inverting charge amount is set to 10 μC/cm2 or larger, and decision which does not produce errors can be made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a selective transistor,
A capacitor comprising a conductive plug, a silicide film containing a metal element and a diffusion barrier film, and further comprising a lower electrode, a dielectric film and an upper electrode electrically connected to the select transistor via the diffusion barrier film. And a method of manufacturing the same.

[0002]

2. Description of the Related Art Ferroelectrics have many functions such as spontaneous polarization, high dielectric constant, electro-optic effect, piezoelectric effect and pyroelectric effect, so that they have been applied to a wide range of devices. For example, utilizing its pyroelectricity to an infrared linear array sensor, its piezoelectricity to an ultrasonic sensor, its electro-optic effect to a waveguide type optical modulator, and its high dielectric properties DRAM (Dynamic Random Access
Memory) and MMIC (monolithic / microwave integrated circuit)
And various other applications. Above all, with the progress of thin film formation technology in recent years, development of a ferroelectric nonvolatile memory (hereinafter abbreviated as FeRAM) which operates at high density and at high speed has been actively developed in combination with semiconductor memory technology.

The above-mentioned FeRAM is a conventional EPROM (ultraviolet erasable read only memory) or an EEPROM (electrically erasable writable R / W) because of its high-speed writing / reading, low voltage operation, and high repetition durability of writing / reading.
OM) and flash memory (batch erase type memory) as well as SRAM (static RAM) and DR
As a memory that can replace the AM, research and development for practical use are actively performed.

Conventionally, as a ferroelectric material used for a ferroelectric capacitor, Pb (Zr _1-x , Ti _x ) which is an oxide ferroelectric is used.
O ₃ (PZT), SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O _{12 and the} like have been studied, and Pt, Pt / Ta, Pt / T
A noble metal material such as i or a composite electrode of the above noble metal material and an adhesion layer has been used for studying the characteristics of a ferroelectric thin film. In particular, low-voltage operation at 3 V or less is possible, and
Reliability characteristics for stable operation as ferroelectric memory
A SrBi ₂ Ta ₂ O ₉ material exhibiting excellent characteristics (eg, fatigue characteristics, imprint characteristics, temperature characteristics, etc.) can be said to be the most suitable material for FeRAM.

However, in order to exhibit good ferroelectric properties in the SrBi ₂ Ta ₂ O ₉ material, a high heat treatment process at 600 ° C. to 800 ° C. in an oxygen atmosphere is essential.

Incidentally, in order to realize the integration of megabits or more using the above-mentioned ferroelectric capacitor and the process for forming the same, a stack type structure is indispensable as a device structure.

FIG. 7 shows a configuration of a conventional dielectric storage element having a stack type structure. In FIG. 7, a selection transistor 1 and a dielectric capacitor 2 are electrically connected by a conductive plug 3 made of polysilicon. The selection transistor 1 includes a gate electrode 5 formed on a silicon substrate 4 and source / drain regions 6 located on both sides thereof. The conductive plug 3 is buried in a hole penetrating the first interlayer insulating film 7 covering the select transistor 1. The dielectric capacitor 2 is formed by laminating a lower electrode 8, a dielectric thin film 9, and an upper electrode 10, and the lower electrode 8 is directly connected to the conductive plug 3.

A second interlayer insulating film 11 is formed on the first interlayer insulating film 7 and the dielectric capacitor 2,
The upper electrode 10 of the dielectric capacitor 2 is connected via a contact hole to a lead electrode 12 formed on the second interlayer insulating film 11. Further, the source region 6a of the select transistor 1 is connected to the extraction electrode 13 via contact holes provided in the first interlayer insulating film 7 and the second interlayer insulating film 11. The LOCOS film 14 separates each element.

Consider a case where Pt is used as the lower electrode 8 electrically connected to the conductive plug 3 made of polysilicon in the above-mentioned stack type structure. When Pt is directly formed on polysilicon, the ferroelectric capacitor process causes a silicidation reaction between Pt and polysilicon, which causes deterioration of ferroelectric characteristics. Therefore, a diffusion barrier film such as TiN is required between Pt and polysilicon.

When TiN is used as a diffusion barrier, it is known that during the crystallization heat treatment of the ferroelectric film, TiN is oxidized by oxygen gas that has permeated the grain boundaries of the Pt film. Proceedings of the Lectures of the Joint Lectures on Applied Physics 28p-V-6 (pp.500) ". Furthermore, as described in the above-mentioned “Preprints of the 43rd Joint Lecture Meeting on Applied Physics in the Spring of 1996, 28p-V-7 (pp.500)”, stress changes caused by volume expansion accompanying oxidation of TiN were also reported. Pt / TiN to mitigate
There is a problem that peeling or Pt hillocks are generated upward at the interface.

As described above, as the structure of the lower electrode 8, when Pt is used, silicidation of Pt or Pt /
In the case where TiN is used, contact failure occurs due to generation of hillocks due to oxidation of TiN, and it is difficult to realize the above-mentioned stacked structure.

On the other hand, Ir, PtRh, Ru or an oxide thereof (Ir) is used as the lower electrode 8 of the ferroelectric film.
O ₂ , PtRhO _x , RuO ₂ ) and the like have begun to be studied from the viewpoint of their excellent barrier properties and compatibility with the oxide dielectric formed on the top. In particular, regarding Ir or IrO ₂ ,
In the literature "App1.Phys.Lett.vo1.65 (1994) pp.1522-1524" and "Jpn.J.Appl.Phys.vol.33 (1994) pp.5207-5210", Ir / IrO ₂ / poly It has been reported that the fatigue properties of PZT formed on silicon or Pt / IrO ₂ / polysilicon electrodes are significantly improved. It is described that the reason is due to the barrier property of the IrO ₂ film against ferroelectric constituent elements such as Pb.

However, in the structure of Ir / IrO ₂ / polysilicon or Pt / IrO ₂ / polysilicon, in the process of forming the IrO ₂ film and the ferroelectric film,
A contact failure problem occurs due to oxidation of polysilicon at the interface between rO ₂ and polysilicon.

As a method of solving the above-mentioned problem of the reaction between Ir and IrO ₂ and polysilicon, as a method of applying TiN as a barrier metal to the oxide electrode IrO ₂ , IrO ₂ / Ir / TiN / T is used.
i The lower electrode is reported in “Proceedings of the 43rd Joint Lecture on Applied Physics in the Spring of 1996, 28p-V-4 (pp.499)”. In this case, a high dielectric SrTiO ₃ film was formed on the silicon substrate having a low resistance by ion implantation, and the contact was examined. As a result, it was confirmed that an ohmic contact was taken, and the high dielectric property was confirmed. Also said that a product equivalent to Pt was obtained.

The above IrO ₂ / Ir / TiN / Ti structure is used for an SrTiO ₃ film which is a high dielectric material.
In a process at a relatively low temperature of 0 ° C. to 450 ° C., the electrical characteristics of the capacitor are not deteriorated due to the hillock and the deterioration of the flatness. Therefore, it can be said that the stacked structure using a high dielectric capacitor is promising.

However, in the ferroelectric crystallization process, even when PZT is formed, an oxygen atmosphere at 600 ° C. or higher is required, and SrBi ₂ Ta ₂ O ₉ requires 60 ° C.
A high heat treatment temperature in an oxygen atmosphere of 0 ° C. to 800 ° C. is required. At such a high temperature, Ir /
In the TiN structure, hillocks are generated due to film stress caused by oxidation of TiN.

In order to solve the above problem, a silicide layer is provided on the conductive plug, and on the silicide,
Ta _x Si as a diffusion barrier film _1-x N _y or Hf _x Si _1-x N _y
And a structure in which Ir and IrO ₂ lower electrodes are sequentially formed on the diffusion barrier film has been proposed. In the case of this structure, material diffusion between the conductive plug and the lower electrode does not occur even in the process of crystallization of the dielectric, and good ferroelectric characteristics formed on the lower electrode are obtained. ing.

[0018]

[SUMMARY OF THE INVENTION However, above conventional conductive on the plug is provided a silicide _{layer, Ta x Si 1-x N} y or Hf as a diffusion barrier layer on the silicide
_x Si _1-x N _y is provided, and Ir,
The structure in which the IrO ₂ lower electrode is sequentially formed has the following problems. That is, Ir or IrO ₂ / Ir
When a dielectric is formed on the lower electrode, a precipitate composed of Ir oxide is generated depending on the crystallization conditions of the dielectric. Then, the precipitate short-circuits the lower electrode and the upper electrode of the capacitor to increase the leakage current of the capacitor, and as a result, lowers the capacity and increases the operating current.

In addition, the step due to the Ir precipitate may cause a wiring defect in a subsequent wiring step. Therefore, in order to suppress the generation of Ir precipitates and improve the yield of the megabit class dielectric storage element, it is essential to identify strict crystallization conditions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of easily realizing a high degree of integration and a good product ratio, and a method of manufacturing the same.

[0021]

In order to achieve the above object, a first aspect of the present invention is to provide a capacitor having an upper electrode / dielectric film and a lower electrode, wherein the lower electrode is located below the lower electrode and a select transistor is provided. A conductive plug electrically connected to the conductive plug, a diffusion barrier film between the conductive plug and the lower electrode to prevent a diffusion reaction between the conductive plug and the lower electrode, and the conductive plug A semiconductor device provided with a silicide film containing a metal element between the diffusion barrier film, wherein the metal element of the silicide film is IV
-Group A (Ti, Zr, Hf), Group VA (V, Nb, Ta), VI-A
Group (Cr, Mo, W) and group VIII (Ru, Os, Co, Rh, Ir,
Ni, Pd, Pt), at least one element selected from at least one group of:
A is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Ru, Os, Co,
B is Zr, Hf, V, Nb, Ta, Cr, Mo, W, Ru, O, and any one element selected from Rh, Ir, Ni, Pd, and Pt.
As any one element selected from s, Co, Rh, Ir, Ni, Pd and Pt, A _x Si _1-x N _y , A _x Al _1-x N _y and B
N _z (0.2 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1), and the lower electrode is formed of an Ir film or an Ir film and an IrO ₂ film. consists of a multilayer film including, the conductive plug is formed of a polysilicon, the dielectric _{film, Bi 4 Ti 3 O 12,} SrBi 2 (Ta x,
Nb _1-x ) ₂ O ₉ (0 ≦ x <1), BaBi ₂ Nb ₂ O ₉ , BaBi ₂ Ta
₂ O ₉ , PbBi ₂ Ta ₂ O ₉ , PbBi ₂ Nb ₂ O ₉ , PbBi ₄ Ti
₄ O ₁₅ , SrBi ₄ Ti ₄ O ₁₅ , BaBi ₄ Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti
₅ O ₁₈ , Ba ₂ Bi ₄ Ta ₅ O ₁₈ , Pb ₂ Bi ₄ Ti ₅ O ₁₈ , Na _0.5 B
_{i 4.5 Ti 4 O 15, K} 0.5 Bi 4.5 Ti 4 O 15, (SrBi 2 (Ta x,
Nb _1-x ) ₂ O ₉ ) _y · (Bi ₃ TiTaO ₉ ) _1-y (0 ≦ x <1,0.6)
Bi-based layered perovskite ferroelectric material containing ≦ y <1; (Pb _1-x , La _x ) (Zr _1-y , Ti _y ) O ₃ (0 ≦ x <0.2,
It is constituted by using any one of a Pb-based perovskite ferroelectric material containing 0.48 ≦ y <1) and a perovskite high-dielectric material containing SrTiO ₃ and (Ba, Sr) TiO _3. It is characterized by having.

According to the above construction, the Ir film or IrO ₂ / Ir film is used as the lower electrode of the capacitor, preventing the oxygen by a high temperature at the time of crystallization of the dielectric film is diffused into the diffusion barrier layer This prevents the volume expansion of the diffusion barrier film and the occurrence of contact failure due to oxidation. Furthermore, the diffusion barrier film used Ta _x Si _1-x N _y film and the like as the diffusion of silicon or Ti or the like to the lower electrode can be prevented from silicide film and the conductive plug. In addition, the silicide film is provided between the diffusion barrier film and the conductive plug, thereby preventing the formation of a reaction layer that occurs when the diffusion barrier film is formed directly on the conductive plug, and having an adhesion strength. And hillocks are reduced.

Further, as the dielectric film, a perovskite ferroelectric material such as SBT or a perovskite high dielectric material is used. Therefore, when an Ir film or an Ir / IrO ₂ film is used as the lower electrode, the crystallization temperature of the dielectric film is set to 625 ° C. or more and 67 ° C.
If the temperature is set to 5 ° C. or lower, for example, Ir on a 6-inch wafer
The generation of precipitates consisting of oxides of the above is suppressed to 100 or less. Therefore, the non-defective rate of a 20 mm ² chip in which 256,000 FeRAMs are integrated becomes 90% or more. In addition, since the amount of domain-inverted charges is 10 μC / cm ² or more, in the 256-kbit integrated FeRAM, the read margin of the sense amplifier is sufficient, and erroneous determination is prevented.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the dielectric film is
It is characterized in that it is formed at a crystallization temperature of not less than ° C and not more than 675 ° C.

According to the above configuration, the dielectric film constituting the capacitor is formed at 625 ° C. using a perovskite ferroelectric material such as SBT or a perovskite high dielectric material.
It is formed at a crystallization temperature of not less than 675 ° C. Therefore, an Ir film or Ir / IrO _{2 is used} as the lower electrode.
If a film is used, for example, I on a 6 inch wafer
r Precipitation is suppressed to 100 or less. Therefore, 20 mm ² integrated with 256,000 FeRAMs
Of non-defective chips becomes 90% or more. In addition, since the amount of domain-inverted charges is 10 μC / cm ² or more, in the 256-kbit integrated FeRAM, the read margin of the sense amplifier is sufficient, and erroneous determination is prevented.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the crystallization time for forming the dielectric film may be reduced to 30.
It is desirable that the time be equal to or longer than 900 minutes.

According to the above configuration, the dielectric film is 625
When formed at a crystallization temperature of not less than 100 ° C. and not more than 675 ° C., for example, the generation of Ir precipitates on a 6-inch wafer is reliably suppressed to 100 or less, and the amount of domain-inverted charges is surely increased to 10 μC / cm ² or more. Become.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a cross-sectional view of a main part showing a basic configuration of a dielectric storage element as a semiconductor device according to the present embodiment. This dielectric storage element is
It has a select transistor 22 formed thereon, a first interlayer insulating film 23 formed on the select transistor 22, and a conductive plug 24 embedded in a contact hole penetrating the first interlayer insulating film 23. ing. The conductive plug 24 is formed of polysilicon, and electrically connects the drain region 26b of the select transistor 22 and the dielectric capacitor 25. 26a
Is a source region of the selection transistor 22, and 27 is a gate electrode of the selection transistor 22.

A second interlayer insulating film 33 is formed on the first interlayer insulating film 23 and the dielectric capacitor 25, and the upper electrode 30 of the dielectric capacitor 25 is formed on the second interlayer insulating film 33. To the extracted lead electrode 34 via a contact hole. Further, the source region 26a of the select transistor 22 is
In addition, it is connected to the extraction electrode 35 via a contact hole provided in the second interlayer insulating film 33. The Locos film 36 separates each element.

The dielectric capacitor 25 has a lower electrode 28, a dielectric film 29 and an upper electrode 30 which are sequentially laminated. Dielectric capacitor 25 according to the present embodiment
The lower electrode 28 is formed of Ir or IrO ₂ . Further, the dielectric capacitor 25 is connected to the lower electrode 2.
8 and a conductive plug 24, which include a silicide film 31 and a diffusion barrier film 32 which are sequentially stacked from the lower side.

[0031] The diffusion barrier film 32 is for preventing diffusion between the conductive plug 24 and the lower electrode _{28, A x Si 1-x} N y, A x Al 1-x N y or BN _z (0.2
≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z <1). The above "A" is Ti, Zr, Hf, V, Nb, Ta, Cr, M
O, W, Ru, Os, Co, Rh, Ir, Ni, Pd, and Pt. "B"
Are Zr, Hf, V, Nb, Ta, Cr, Mo, W, Ru, Os, Co, Rh,
Any one element selected from the group consisting of Ir, Ni, Pd and Pt.

The metal constituting the silicide film 31 is as follows.
Group IV-A (Ti, Zr, Hf), Group VA (V, Nb, Ta), VI-
Group A (Cr, Mo, W) and Group VIII (Ru, Os, Co, Rh, Ir,
At least one element selected from at least one group of (Ni, Pd, Pt).

Hereinafter, the dielectric memory element having the above configuration will be described. The Ir film or the IrO ₂ / Ir film constituting the lower electrode 28 is made of a dielectric film 29 formed thereon.
The high temperature at the time of the crystallization process, oxygen is prevented from being diffused to the diffusion barrier layer _{(e.g., Ta x Si 1-x N} y film) 32. Therefore, Ta oxidative _x Si _1-x N
It is possible to prevent the volume expansion of the _y film and the occurrence of contact failure. The lower due Ir or IrO ₂ electrode 2
8, and the use of the diffusion barrier film 32 having the above configuration is also partially described in the conventional dielectric storage element.

The diffusion barrier film (for example, Ta _x SI _1-x N)
_{The y} film 32 functions as a diffusion barrier between the silicide film (for example, titanium silicide film) 31 and the conductive plug (polysilicon) 24 and the lower electrode (Ir film or IrO ₂ / Ir film) 28. In other words, by Ta _x Si _1-x N _y film is to prevent the element such as silicon or Ti is diffused into the lower electrode 28.

The diffusion barrier film 32 of Ta _x S
When an i _1-x N _y film is formed directly on polysilicon, Ta _x
The detailed interface analysis revealed the fact that a very small reaction layer may be formed at the interface between the Si _1-x N _y film and the polysilicon. When such a reaction layer is formed, the contact resistance between the lower electrode 28 and the conductive plug 24 increases after the dielectric crystallization process, and the current-voltage characteristics may become non-ohmic. The non-ohmicity of the current-voltage characteristics often causes problems such as delay in high-speed operation and difficulty in obtaining a signal S / N ratio in a memory operation of a dielectric. However, by providing the silicide film 31 between the diffusion barrier film 32 and the conductive plug 24, the above-described formation of the reaction layer is prevented. Furthermore, the presence of the silicide film 31, conductive plugs (polysilicon) 24 and the diffusion barrier film (Ta _x Si
The adhesion strength with the ( _{1-xN y} ) film 32 increases, which contributes to the reduction of hillocks.

On the other hand, when an Ir film or an IrO ₂ / Ir film is used for the lower electrode 28 of the dielectric capacitor 25, there are the following problems. That is, the lower electrode 28
After the formation, when a heat treatment process for forming a dielectric film is performed, a precipitate composed of an oxide of Ir is generated in the dielectric film. Then, the Ir precipitate is deposited on the dielectric capacitor 25.
In this case, the lower electrode 28 and the upper electrode 30 are short-circuited to increase the leakage current of the dielectric capacitor 25, and as a result, the capacitance is reduced and the operating current is increased. Also,
The step due to the Ir precipitate causes a wiring failure in a subsequent wiring process.

For example, consider a 256 kbit integrated ferroelectric memory (hereinafter, simply referred to as an integrated FeRAM). When the chip area in which 256,000 cells are integrated is 20 mm ² , it is necessary to suppress the number of precipitates to 200 mm ² or less in order to increase the yield rate to 90% or more. Assuming a 6-inch wafer, its area is about 17,
600mm ² next, 17,600mm ² / 200mm ² = 88
It is essential that the number of Ir precipitates in the wafer surface, that is, the number of Ir precipitates be reduced to 100 or less.

This Ir precipitate is closely related to the crystallization conditions of the dielectric material. FIG. 2 shows the crystallization temperature of Ir / TaSiN / Ti of SrBi ₂ Ta ₂ O ₉ (hereinafter abbreviated as SBT), which is one of the dielectric materials used in the present embodiment.
Relationship with Ir precipitates generated on silicide, and
It is a figure which shows the relationship with the polarization inversion charge amount of the said SBT at the crystallization temperature. The method of manufacturing the SBT will be described later in detail, but the SBT is formed by a spin coating method, and the baking time per layer is 30 minutes. Then, the above-described film formation and baking are repeated for four layers. Thus, the total crystallization time is 120 minutes and the crystallization atmosphere is oxygen.

The polarization inversion charge amount is one of the important parameters when driving the FeRAM, and if this value is too low, the sense amplifier is not required to determine “0” and “1”. Since the reading margin cannot be secured, an error occurs in the determination. 2 as in the example above
In the case of an integrated FeRAM of 56 k bits, an amount of domain-inverted charges of 10 μC / cm ² or more is required to make a determination without an error. As can be seen from FIG. 2, the generation of Ir precipitates on the 6-inch wafer was reduced by 100%.
The crystallization temperature must be suppressed to 675 ° C. or lower to suppress the number to less than or equal to the number, and the crystallization temperature must be set to 625 ° C. or higher to keep the polarization inversion charge amount to 10 μC / cm ² or more.

FIG. 3 shows the relationship between the crystallization time of the SBT and Ir precipitates generated on Ir / TaSiN / Ti silicide, and the relationship between the polarization inversion charge amount of the SBT and the SBT during the crystallization time. It is a figure showing a relation. The sintering temperature of the SBT is 625 ° C., four layers are repeated in the same manner as described above, and the crystallization atmosphere is oxygen.

As can be seen from FIG. 3, when the sintering temperature of the SBT is 625 ° C., the IBT on the 6-inch wafer is
rTo suppress the generation of precipitates to 100 or less, the total crystallization time must be 900 minutes or less (225 minutes per layer), and in order to make the polarization inversion charge amount 10 μC / cm ² or more, The total crystallization time needs to be 120 minutes or more (30 minutes per layer).

FIG. 4 shows the SBT as in the case of FIG.
FIG. 4 is a diagram showing the relationship between the crystallization time of Ir and the precipitates of Ir generated on Ir / TaSiN / Ti silicide, and the relationship between the polarization inversion charge amount of the SBT and the crystallization time. However, the sintering temperature of the SBT is 675 ° C., and four layers are repeated in the same manner as in the above case. The crystallization atmosphere is oxygen.

As can be seen from FIG. 4, when the sintering temperature of the SBT is 675 ° C., the IBT on the 6-inch wafer is
rTo suppress the generation of precipitates to 100 or less, the total crystallization time needs to be 120 minutes or less (30 minutes per layer), and in order to make the polarization inversion charge amount 10 μC / cm ² or more, It must be 30 minutes or longer (7.5 minutes per layer).

In the method of manufacturing the SBT, the film formation and the baking by the spin coating method are repeated by four layers, but the number of repetitions is not limited to four. The point is that the number of times of repetitive firing times the crystallization time = the total crystallization time only needs to be within a range in which the generation of the Ir precipitate as described above can be suppressed.

Further, in this embodiment, using the SBT as the dielectric film 29 formed on the lower electrode _{28, Bi 4 Ti 3 O 12} , SrBi 2 (Ta x, Nb 1-x) ₂ O ₉ (0 ≦
x <1), BaBi ₂ Nb ₂ O ₉ , BaBi ₂ Ta ₂ O ₉ , PbBi ₂ Ta ₂ O
₉ , PbBi ₂ Nb ₂ O ₉ , PbBi ₄ Ti ₄ O ₁₅ , SrBi ₄ Ti ₄ O ₁₅ ,
BaBi ₄ Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ , Ba ₂ Bi ₄ Ta
₅ O ₁₈ , Pb ₂ Bi ₄ Ti ₅ O ₁₈ , Na _0.5 Bi _4.5 Ti ₄ O ₁₅ , K _{0.5
Bi 4.5 Ti 4 O 15, (} SrBi 2 (Ta x, Nb 1-x) 2 O 9) y · (Bi 3 T
Bi-based layered perovskite ferroelectric materials such as iTaO ₉ ) _1-y (0 ≦ x <1,0.6 ≦ y <1), (Pb _1-x La _x ) (Zr _1-y ,
Py perovskite ferroelectric materials such as Ti _y ) O ₃ (0 ≦ x <0.2, 0.48 ≦ y <1), SrTiO ₃ , (Ba, Sr) Ti
Even if a perovskite-type high dielectric material such as O ₃ is used, the same tendency as in the present embodiment can be obtained.

These dielectric films can be formed by known methods, for example, a spin coating method used in the present embodiment, a reactive evaporation method, an EB (electron beam) evaporation method, a sputtering method, a laser ablation method, or a chemical vapor deposition method. It can be formed by selecting a method such as a method (MOCVD method). The atmosphere at the time of forming the dielectric film is not limited to the oxygen atmosphere, and similar results can be obtained by using a nitrogen atmosphere, an argon atmosphere, or a mixed atmosphere containing at least one of oxygen, nitrogen, and argon. can get.

The upper electrode 30 provided on the dielectric film 29 can be formed of the same material as the lower electrode 28 by a similar method in addition to a single-layer structure such as a Pt film. The substrate used for the dielectric storage element in the present embodiment is not particularly limited as long as it can be used as a substrate for a normal semiconductor device, an integrated circuit, or the like, but a silicon substrate is preferable.

The dielectric storage element according to the present embodiment is
An integrated circuit can be formed by mounting a dielectric material on a wafer for an integrated circuit as a part of the structure of a dielectric device or a semiconductor device. For example, an MFMIS-FET (Metal Ferroelectric) is formed by applying a dielectric material to a capacitor portion of a nonvolatile memory or a gate electrode of an FET (field effect transistor) and forming a gate insulating film and a source / drain region in combination. Met
al Insulator Semiconductor FET), MFS-FET
(Metal Ferroelectric Semiconductor FET), MI
It can also be used as an S-FET (Metal Insulator Semiconductor FET).

FIG. 5 is a sectional view showing a method of manufacturing the dielectric memory element shown in FIG. Hereinafter, a method of manufacturing the dielectric memory element according to the present embodiment will be described with reference to FIG.

First, as shown in FIG. 5A, a LOCOS film 36 having a thickness of about 500 nm is formed on the surface of the silicon substrate 21 to perform element isolation. Then, using known methods,
The select transistor 22 including the gate electrode 27 and the source / drain region 26 is formed. Thereafter, a first silicon oxide film as a first interlayer insulating film 23 is formed to a thickness of about 500 nm by CVD (chemical vapor deposition),
Subsequently, the select transistor 22 is formed on the first interlayer insulating film 23.
A contact hole 37 having a diameter of about 0.6 μm communicating with the drain region 26b is formed.

Next, as shown in FIG. 5B, after the polysilicon is buried in the contact hole 37 by the CVD method, the surface is flattened by the CMP (chemical mechanical polishing) method, and the conductive plug 24 is formed. To form Next, the surface of the conductive plug 24 is wet-treated with hydrofluoric acid in order to suppress the formation of a natural oxide film on the polysilicon forming the conductive plug 24.

Thereafter, the conductive plug 24 and the first interlayer insulating film are formed by DC (direct current) magnetron sputtering.
(Silicon oxide film) 1 nm to 30 nm of Ti film 31a on 23
(Preferably 5 nm to 25 nm). here,
If the thickness of the Ti film 31a is 1 nm or less, it is difficult to obtain a good contact. If the thickness is 30 nm or more, the surface of the Ti film 31a becomes rough after dielectric crystallization annealing.

Thereafter, on the Ti film 31a, a T _x Si _1-x N _y (0.2 ≦ x ≦ 1, 0 ≦ y ≦) as the diffusion barrier film 32 is formed by DC reactive magnetron sputtering.
1) A film having a thickness of 50 nm to 150 nm (preferably 80 nm to 120 n)
m). Here, the film thickness of the Ta _x Si _1-x N _y is in the case of 50nm or less, it is difficult to serve as a diffusion barrier layer. On the other hand, when the thickness is 150 nm or more, the thickness of the entire capacitor is increased, which impairs the precision of fine processing. In this embodiment, the conditions for forming the above-mentioned Ta _x Si _1-x N _y film are Ta / Si =
Using a 10/3 alloy target and setting the substrate temperature to 500 ° C
The sputtering power was 2 kW, the sputtering gas pressure was 0.7 Pa, and the Ar / N ₂ flow ratio was 3/2.

[0054] The diffusion barrier film _{(Ta x Si 1-x N} y film) 32
Is formed in an atmosphere of pure nitrogen at 500 ° C. to 800 ° C.
A heat treatment is performed for 1 hour at a temperature of 600C (preferably 600C). By this heat treatment, the Ti film 31a formed below the diffusion barrier film 32 reacts with the polysilicon of the conductive plug 24 to form a silicide film 31 (about 2 nm to 60 nm in thickness). Here, if the temperature of the heat treatment is 500 ° C. or less, sufficient silicide cannot be formed. Further, when the temperature of the heat treatment is 800 ° C. or higher, if the time of the heating step is one hour, the reaction with polysilicon excessively proceeds, which causes the surface roughness of silicide. Moreover,
To Ta _x Si _1-x N _y film diffusion barrier film 32 which may exert a bad Hohibiki. The heat treatment was performed in a pure nitrogen atmosphere.
The same effect can be obtained by using another gas such as krypton or helium.

Further, as described above, the diffusion barrier film 32 formed of the Ta _x Si ₁ -xN _y film was confirmed to have an amorphous structure by X-ray diffraction analysis. further,
According to Auger electron spectroscopy, the composition ratio was Ta _0.85 Si.
It was confirmed to be _0.15 N _0.41 . The diffusion barrier film after heat treatment in a pure nitrogen atmosphere _{(Ta x Si 1-x N} y
As a result of measuring the resistivity of the film 32, 100 μΩcm to 20
It was found to be within the range of 00 μΩcm. Here, "x" in the composition Ta _x Si _1-x N _y of the diffusion barrier film 32
If x <0.2, the Si component is too large and the resistivity becomes extremely high, which is not suitable as a device.
Therefore, the range of 0.2 ≦ x ≦ 1 is suitable.

Subsequently, a DC voltage is applied on the diffusion barrier film 32.
The Ir film as the lower electrode 28 is formed to a thickness of about 50 nm to 300 nm (preferably 100 nm to 2 nm) by magnetron sputtering.
(00 nm). Here, the film thickness of Ir is 50 nm.
In the following cases, oxygen in the atmosphere permeates the Ir film during the ferroelectric crystallization annealing, and hillocks are generated due to the volume expansion of the Ta _x Si _{1 -x} N _y film which is the diffusion barrier film 32. On the other hand, when the thickness is 300 nm or more, the thickness of the entire dielectric capacitor portion is eventually increased, which causes problems such as a problem in fine processing accuracy and a problem that processing cannot be performed with an existing resist film thickness. The Ir film used in the present embodiment was formed under the following conditions: a DC power of 0.5 kW, a substrate temperature of 500 ° C., and a gas pressure of 0.6 Pa.

Next, SrBi ₂ Ta as a dielectric film 29 is formed on the lower electrode (Ir film) 28 by a spin-on method.
₂ O ₉ (SBT) is formed. The method for forming the SBT film is as follows.
This is performed as follows. First, a precursor solution in which the elements constituting the SBT are dispersed in a solvent is formed, and the precursor solution is applied at 3000 rpm using a spinner. Then, after drying in the air at 150 ° C. for 10 minutes, calcination is performed in the air at 400 ° C. for 30 minutes. Then, crystallization is performed at 650 ° C. for 60 minutes. By repeating these steps four times, SB
A T film is formed with a thickness of 120 nm to form the dielectric film 29.
No hillocks or peeling were observed in the dielectric film 29 formed of the SBT film in this manner, and no reaction was observed in each layer even in cross-sectional observation with a scanning electron microscope (SEM).

Next, on the dielectric film (SBT film) 29,
An upper electrode 30 having a thickness of 100 nm is formed of Pt by DC magnetron sputtering.

Next, as shown in FIG. 5C, the upper electrode (Pt) 30 is patterned into a size of 1 μm to 3 μm square by a dry etching method using Cl ₂ . Further, the dielectric film (SBT film) 29 under the upper electrode 30 is
Patterned into a desired shape by a dry etching method using ₂ F ₆ and Ar. Subsequently, the lower electrode (Ir) 28 below the dielectric layer 29, the diffusion barrier film (Ta _x Si _1-x N
_y film) 32 and silicide film 31 are made of Cl ₂ and C ₂ F ₆
Is processed into a desired shape by a dry etching method using. Thus, a dielectric capacitor 25 is formed in which the silicide film 31, the diffusion barrier film 32, the lower electrode 28, the dielectric film 29, and the upper electrode 30 are sequentially stacked from the substrate side.

Thereafter, as shown in FIG.
The CV is formed on the interlayer insulating film 23 and the dielectric capacitor 25.
Using method D, a second silicon oxide film as the second interlayer insulating film 33 is formed. Thereafter, a contact hole is formed in the second interlayer insulating film 33 on the upper electrode 30, and a lead electrode 34 connected to the upper electrode 30 is formed of aluminum using a DC magnetron sputtering method. Next, contact holes are formed in the first interlayer insulating film 23 and the second interlayer insulating film 33 on the source region 26a of the select transistor 22, and a lead electrode 35 connected to the source region 26a is formed of aluminum. Thus,
A dielectric storage element as shown in FIG. 1 is formed.

The extraction electrode 34 from the upper electrode (Pt) 30 of the dielectric capacitor 25 formed as described above.
A hysteresis curve as shown in FIG. 6 was obtained by applying a triangular waveform voltage between the gate electrode and the extraction electrode 35 from the source region 26a. The electric field strength of the applied triangular wave is 150 kV / cm, and the frequency is 75 kV / cm.
Hz. According to FIG. 6, the ferroelectric characteristics of the dielectric capacitor 25 were such that the polarization-reversed charge amount ΔQ was 12 μC / cm ² and the coercive electric field Ec was 35 kV / cm. The leakage current density when applying +3 V is 8 × 10 ⁻⁸ A / cm ² , and the withstand voltage is 1
It was 0 V or more. From these results, ferroelectric characteristics large enough to be used as a ferroelectric capacitor were obtained, and since the symmetry of the hysteresis curve was not broken, the silicon substrate 21 and the lower electrode (Ir) 28 It can be seen that the contact with is sufficiently obtained.

Although the present embodiment has been described by taking a 256 kbit integrated FeRAM as an example, the present invention can be similarly applied to a megabit class (1 megabit to 256 megabit) integrated FeRAM or DRAM.

As described above, in the present embodiment, the conductive plug 24 constituting the dielectric storage element is formed of polysilicon. Further, the dielectric capacitor 25 electrically connected to the drain region 26b of the select transistor 22 via the conductive plug 24 is formed by sequentially forming a silicide film 31, a diffusion barrier film 32, a lower electrode 28, and a dielectric film 29 from the substrate side. And the upper electrode 30 are sequentially laminated. Thus, the silicide film 31 is provided on the conductive plug 24, and the diffusion barrier film 32 is provided on the silicide film 31. Therefore, 500 ° C. to 8
Even in the process of crystallization of the dielectric at a high heat treatment temperature in an oxygen atmosphere of 00 ° C., material diffusion between the conductive plug 24 and the lower electrode 28 does not occur, and the lower electrode 2
The ferroelectric material formed in No. 8 has good characteristics.

At this time, the lower electrode 28 is formed of Ir or Ir / IrO ₂ from the viewpoint of excellent barrier properties and compatibility with the oxide dielectric formed on the upper portion. In the embodiment, SB is used as the dielectric film 29.
T is used. As shown in FIG. 2, the SBT is formed by setting the crystallization temperature to 625 ° C. or more and 675 ° C. or less, for example, Ir in a 6-inch wafer.
The generation of precipitates can be suppressed to 100 or less, and the amount of domain-inverted charges can be increased to 10 μC / cm ² or more. Here, the SB
When the crystallization temperature of T is 625 ° C., the total crystallization time may be set to 120 minutes or more and 900 minutes or less as shown in FIG. The crystallization temperature of the SBT is 675 ° C.
In the case of, as shown in FIG.
The time may be longer than or equal to 120 minutes.

That is, according to the present embodiment, for example, the generation of Ir precipitates on a 6-inch wafer can be suppressed to 100 or less, so that 256,000 cells are integrated in a 256 kbit integrated FeRAM. 90% non-defective rate when the chip area is 20 mm ²
That is all. Further, since the amount of the domain-inverted charges can be increased to 10 μC / cm ² or more,
In a bit-integrated FeRAM, a sufficient read margin in the sense amplifier can be secured. Therefore, it is possible to make a determination without error.

The metal constituting the silicide film 31 is a group IV-A (Ti, Zr, Hf), a group VA (V, Nb, Ta), V
Groups IA (Cr, Mo, W) and VIII (Ru, Os, Co, Rh, I
(r, Ni, Pd, Pt) at least one element selected from at least one group.

The diffusion barrier film 32 is made of A _x Si
_1-x N _y , A _x Al _1-x N _y and BN _z (0.2 ≦ x ≦ 1,0 ≦ y
≦ 1,0 ≦ z <1), and
"A" is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo,
W, Ru, Os, Co, Rh, Ir, Ni, Pd, and Pt are any one element selected from the group, and "B" is Zr,
Hf, V, Nb, Ta, Cr, Mo, W, Ru, Os, Co, Rh, Ir, Ni,
It is any one element selected from the group consisting of Pd and Pt.

The dielectric film 29 is made of S
Similar effects can be obtained by using any one of the above-mentioned Bi-based layered perovskite-type ferroelectric material, Pb-based perovskite-type ferroelectric material, and perovskite-type high-dielectric material in addition to BT. Can be

[0069]

As is clear from the above, the semiconductor device of the first invention uses an Ir film or an IrO ₂ / Ir film as the lower electrode of the capacitor, so that the oxygen is generated by the high temperature during the crystallization of the dielectric film. Can be prevented from diffusing to the diffusion barrier film immediately below the lower electrode, and the expansion of the diffusion barrier film due to oxidation and the occurrence of contact failure can be prevented. _{Further, Ta x Si 1-x N} y as the diffusion barrier film
Since a film or the like is used, diffusion of silicon, Ti, or the like from the silicide film and the conductive plug adjacent immediately below the diffusion barrier film to the lower electrode can be prevented. Further, since the silicide film is provided between the diffusion barrier film and the conductive plug, it is possible to prevent the formation of a reaction layer that occurs when the diffusion barrier film is formed directly on the conductive plug, and to reduce the adhesion strength. Hillock can be reduced by increasing.

Further, since a perovskite-type ferroelectric material such as SBT or a perovskite-type high-dielectric material is used as the dielectric film of the capacitor, an Ir film or an Ir / IrO ₂ film is used as the lower electrode. If the crystallization temperature of the dielectric film is 625 ° C. or more and 675 ° C. or less, for example, the generation of Ir precipitates on a 6-inch wafer is suppressed to 100 or less, and the amount of domain-inverted charges is reduced to 10 μC / cm ² or more. it can. Therefore, 256,00
The non-defective product rate in the case where zero FeRAM is integrated on a 20 mm ² chip can be 90% or more. Further, in the 256-kbit integrated FeRAM, the read margin in the sense amplifier can be made sufficient to prevent erroneous determination.

That is, according to the present invention, it is possible to easily improve the non-defective rate of the dielectric memory device highly integrated in the megabit class.

Further, the method of manufacturing a semiconductor device according to the second aspect of the present invention is directed to a method of manufacturing a semiconductor device according to the first aspect of the present invention, wherein the dielectric film is made of a perovskite ferroelectric material such as the SBT or a perovskite high dielectric material. At 625 ° C. or higher and 6
Since the film is formed at a crystallization temperature of 75 ° C. or less, when an Ir film or an Ir / IrO ₂ film is used as the lower electrode, for example, generation of Ir precipitates on a 6-inch wafer is suppressed to 100 or less, and polarization inversion charge is reduced. The amount can be 10 μC / cm ² or more. Therefore, 256,000 FeRAM
90% non-defective product rate when integrated on a 20 mm ² chip
More than that. Further, the integrated Fe of 256 kbits described above is used.
In the RAM, a reading margin in the sense amplifier can be made sufficient to prevent erroneous determination.

Further, in the method of manufacturing a semiconductor device according to the second aspect of the present invention, the crystallization time at the time of forming the dielectric film is reduced to 30.
And 900 minutes or less, the dielectric film is
In the case of forming at a crystallization temperature of 5 ° C. or more and 675 ° C. or less, for example, the generation of Ir precipitates on a 6-inch wafer is reliably suppressed to 100 or less, and the polarization inversion charge amount is reliably reduced to 10 μC / cm ² or more. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a dielectric storage element as a semiconductor device according to the present invention.

FIG. 2 is a diagram showing the relationship between the crystallization temperature of SBT and the amount of Ir precipitates and polarization inversion charges.

FIG. 3 is a graph showing the relationship between the crystallization time and the amount of Ir precipitates and the amount of domain-inverted charges in an SBT having a firing temperature of 625 ° C.

FIG. 4 is a diagram showing the relationship between the crystallization time and the amount of Ir precipitates and the amount of domain-inverted charges in an SBT having a firing temperature of 675 ° C.

FIG. 5 is a sectional view illustrating the method for manufacturing the dielectric memory element illustrated in FIG.

FIG. 6 is a diagram showing applied voltage / polarization characteristics in the dielectric storage element shown in FIG.

FIG. 7 is a cross-sectional view of a conventional dielectric storage element having a stack type structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 ... Substrate, 22 ... Selection transistor, 23 ... 1st interlayer insulation film, 24 ... Conductive plug, 25 ... Dielectric capacitor, 26a ... Source region, 26b ... Drain region, 27 ... Gate electrode, 28 ... Lower electrode, 29 ... dielectric film, 30 ... upper electrode, 31 ... silicide film, 32 ... diffusion barrier film, 33 ... second interlayer insulating film, 34, 35 ... lead-out electrode, 36 ... locos film, 37 ... contact hole.

Continued on the front page F term (reference) 5F001 AA17 AD12 5F083 AD21 FR02 FR05 FR07 GA09 GA25 JA15 JA17 JA35 JA38 JA39 JA40 JA43 MA05 MA06 MA17 NA02 PR22 PR23 PR33 5F101 BA62 BD02

Claims (4)

[Claims] 1. A semiconductor device comprising an upper electrode, a dielectric film and a lower electrode.
Located below and above the lower electrode of the capacitor
Conductivity for electrically connecting the lower electrode to the selection transistor
Between the conductive plug and the conductive plug and the lower electrode.
To prevent diffusion reaction between the conductive plug and the lower electrode
A diffusion barrier film, the conductive plug and the diffusion barrier film;
Semiconductor with silicide film containing metal element in between
An apparatus, wherein the metal element of the silicide film is a group IV-A (Ti, Zr, H
f), VA group (V, Nb, Ta), VI-A group (Cr, Mo, W),
And VIII group (Ru, Os, Co, Rh, Ir, Ni, Pd, Pt)
At least one selected from at least one group
The diffusion barrier film is characterized in that A represents Ti, Zr, Hf, V, Nb, Ta, C
From r, Mo, W, Ru, Os, Co, Rh, Ir, Ni, Pd and Pt
Let B be Zr, Hf, V, N
b, Ta, Cr, Mo, W, Ru, Os, Co, Rh, Ir, Ni, Pd and
As one element selected from Pt, A_xSi_1-x
N_y, A_xAl_1-xN_yAnd BN_z(0.2 ≦ x ≦ 1,0 ≦ y
≦ 1,0 ≦ z <1)
The lower electrode is made of an Ir film or an Ir film and IrO_TwoIncluding membrane
The conductive plug is formed of polysilicon, and the dielectric film is formed of Bi._FourTi_ThreeO₁₂, SrBi_Two(Ta_x, Nb_1-x)
_TwoO₉(0 ≦ x <1), BaBi_TwoNb_TwoO₉, BaBi_TwoTa_TwoO₉, Pb
Bi_TwoTa_TwoO₉, PbBi_TwoNb_TwoO₉, PbBi_FourTi_FourO_Fifteen, SrBi_Four
Ti_FourO_Fifteen, BaBi_FourTi_FourO_Fifteen, Sr_TwoBi_FourTi_FiveO₁₈, Ba_TwoBi_Four
Ta_FiveO₁₈, Pb_TwoBi_FourTi_FiveO₁₈, Na_0.5Bi_4.5Ti_FourO_Fifteen, K
_0.5Bi_4.5Ti_FourO_Fifteen, (SrBi_Two(Ta_x, Nb _1-x)_TwoO₉)_y・ (Bi
_ThreeTiTaO₉)_1-yBi including (0 ≦ x <1,0.6 ≦ y <1)
Layered perovskite ferroelectric material, (Pb_1-x, La_x)
(Zr_1-y, Ti_y) O_Three(0 ≦ x <0.2, 0.48 ≦ y <1)
Containing Pb-based perovskite ferroelectric material, SrTiO_Three,
(Ba, Sr) TiO_ThreePerovskite-type high dielectric material containing
Be constructed using any one of the dielectric materials
A semiconductor device characterized by the above-mentioned. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is formed at a crystallization temperature of 625 ° C. or more and 675 ° C. or less. . 3. The method for manufacturing a semiconductor device according to claim 2, wherein a crystallization time during the formation of the dielectric film is 30 minutes or more and 900 minutes or less. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the crystallization atmosphere at the time of forming the dielectric film is an oxygen atmosphere, a nitrogen atmosphere, an argon atmosphere, or an oxygen, nitrogen, and argon atmosphere. Wherein the mixed atmosphere contains at least one of the following.