JP2002122889A - Electrooptical device and projection type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the light resistance and to display a high quality image on an electrooptical device such as a liquid crystal device. SOLUTION: On a TFT array substrate (10) of the electrooptical device, scanning lines (3a), data lines (6a), TFTs (30) connected to the lines (3a) and the lines (6a), pixel electrodes (9a) connected to the TFTs (30), top side light shielding films (300 and 6a) that are arranged in a grid shape on the top side of the plural TFTs and determine the nonopening region of the pixels and a bottom side light shielding film (11a) which is arranged in the bottom side of the plural TFTs in a grid shape. By looking at an image display region in a planar manner, the forming region of the film (11a) is located within the forming region of the top side light shielding films and the channel region of the TFT is located within the crossing region of the film (11a).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an electro-optical device of an active matrix drive system, and particularly to a thin film transistor for pixel switching (Thin Film Tran).
(hereinafter, appropriately referred to as a TFT) in a laminated structure on a substrate.

[0002]

2. Description of the Related Art In an electro-optical device of a TFT active matrix drive type, when incident light is applied to a channel region of a pixel switching TFT provided in each pixel, a current is generated by excitation by light, and the characteristics of the TFT are reduced. Change. In particular, in the case of an electro-optical device for a light valve of a projector, since the intensity of incident light is high, it is important to shield the TFT channel region and its peripheral region from incident light. Therefore, conventionally, the channel region and its peripheral region are shielded from light by a light-shielding film that defines an opening region of each pixel provided on the opposite substrate, or by a data line that passes over the TFT and is made of a metal film such as Al. It is configured to be. Japanese Patent Application Laid-Open No. 9-33944 discloses a-Si (amorphous silicon) having a large refractive index.
There is disclosed a technique for reducing light incident on a channel region by using a light-shielding film formed from a thin film. Further, a light-shielding film made of, for example, a refractory metal may be provided on the TFT array substrate at a position facing the pixel switching TFT (that is, below the TFT). If a light-shielding film is also provided below the TFT as described above, the back surface reflection from the TFT array substrate side or another electro-optical device when a plurality of electro-optical devices are combined via a prism or the like to constitute one optical system is used. Projection light that penetrates the prism or the like from the electro-optical device can be prevented from being incident on the TFT of the electro-optical device.

[0003]

However, the above-described various light-shielding techniques have the following problems.

That is, according to the technique of forming a light-shielding film on a counter substrate or a TFT array substrate, the space between the light-shielding film and the channel region is three-dimensionally viewed, for example, as a liquid crystal layer, an electrode, or an interlayer insulating film. And so on, so that the light obliquely incident between them is not sufficiently shielded. In particular, in a small electro-optical device used as a light valve of a projector, the incident light is a light beam obtained by focusing light from a light source with a lens, and includes a component that is obliquely incident and cannot be ignored. Insufficient blocking of such oblique incident light poses a practical problem.

In addition, light that has entered the electro-optical device from a region without the light-shielding film is exposed to the inner surface of the light-shielding film or the data line (that is, the data line).
After the light is reflected by the surface facing the channel region), the reflected light or the multiple reflected light further reflected by the light-shielding film or the inner surface of the data line may eventually reach the channel region of the TFT. is there. Further, according to the technique of shielding light with data lines, the data lines are formed in a stripe shape extending perpendicular to the scanning lines when viewed two-dimensionally, and the adverse effect of the capacitive coupling between the data lines and the channel region is negligible. Since it is necessary to arrange a thick interlayer insulating film between them, it is basically difficult to sufficiently shield light.

According to the technique described in Japanese Patent Application Laid-Open No. 9-33944, an a-Si film is formed on a gate line, so that the adverse effect of capacitive coupling between a gate electrode and an a-Si film is reduced. It is necessary to stack a relatively thick interlayer insulating film between them. As a result, the laminated structure is complicated and enlarged due to the additionally formed a-Si film, interlayer insulating film, and the like, and it is also difficult to sufficiently shield obliquely incident light and internally reflected light. In particular, as the electro-optical device has been improved in definition or the pixel pitch has been reduced to meet the general demand for higher quality of display images in recent years, according to the conventional various light shielding techniques described above, sufficient light shielding has been achieved. It is more difficult to perform the process, and there is a problem that flicker or the like occurs due to a change in the transistor characteristics of the TFT, and the quality of a displayed image is reduced.

Incidentally, in order to improve such light resistance,
It is thought that the area for forming the light-shielding film may be expanded, but if the area for forming the light-shielding film is expanded, it is fundamentally necessary to increase the aperture ratio of each pixel in order to improve the brightness of the display image. The problem that it becomes difficult arises.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an electro-optical device which is excellent in light resistance, has a relatively high aperture ratio of each pixel, and can display a high-quality image. As an issue.

[0009]

According to another aspect of the present invention, there is provided an electro-optical device comprising: a pair of substrates; an electro-optical material sandwiched between the pair of substrates;
A plurality of pixel electrodes arranged in a matrix, a thin film transistor electrically connected to the pixel electrode, and an upper light-shielding film arranged in a cross shape over the thin film transistor on the one substrate; A lower light-shielding film which is arranged in a cross shape below the thin film transistor on the substrate, and which is formed inside the formation region of the upper light-shielding film, and a region where an intersection region of the upper light-shielding film and the lower intersection region overlap each other; And a junction of a channel region of the thin film transistor formed therein.

According to the electro-optical device of the present invention, the electro-optical device is defined by the upper light-shielding film arranged in a cross shape above the thin film transistor. Therefore, the upper light-shielding film can effectively prevent light from leaking and lowering the contrast ratio. Here, an upper light-shielding film arranged in a cross shape exists above the thin film transistor, and below the thin film transistor,
There is a lower light-shielding film arranged in a cross shape, and the formation region of the lower light-shielding film is located within the formation region of the upper light-shielding film when viewed in plan in the image display region. At least the junction of the channel region of the thin film transistor (the junction between the channel region and the source region or the drain region including the N− region, the N + region, the P− region, and the P + region) is located within the intersection region of the lower light-shielding film. Located in.

Therefore, when strong incident light is incident as in the case of a projector, the thin film transistor is shielded by the upper light-shielding film from not only the component perpendicular to the substrate but also the component oblique to the substrate in the incident light. it can. Further, when a plurality of electro-optical devices are used in combination as a light valve, such as a back-reflected light or a double-plate type projector, return light such as light that penetrates the synthetic optical system from another light valve is shielded from the lower side. Light can be blocked by the film. In particular, the incident light incident from the side of the upper light-shielding film is reflected by the surface of the lower light-shielding film on the side facing the upper light-shielding film, thereby causing internal reflected light and multiple reflected light to occur. In this configuration, the lower light-shielding film is hidden behind the upper light-shielding film, which can be effectively prevented.

In addition, according to a study by the present inventors,
It has been found that when light enters the junction of the channel region in the thin film transistor, light leak occurs most sensitively. Therefore, as in the present invention, the crossing area of the cross-shaped light-shielding film having the best overall light-shielding property with respect to incident light that is obliquely incident vertically and horizontally in the image display area (that is, the incident light hardly hits). Further, by locating the junction of the channel region of the thin film transistor, a configuration in which light leakage hardly occurs when light enters can be obtained. In addition, such light shielding from above and below of the thin film transistor can be performed relatively close to the thin film transistor as compared with a case where a light shielding film provided on a traditional counter substrate is used. In addition, it is possible to improve the light-shielding performance while preventing the formation region of the light-shielding film from being enlarged (that is, without unnecessarily narrowing the non-opening region of each pixel).

As a result, there is provided an electro-optical device in which the aperture ratio of each pixel is high, the characteristic deterioration due to light leakage of the thin film transistor is reduced due to the high light resistance, and the contrast ratio is high and a high quality image can be displayed. Is achieved.

In one aspect of the electro-optical device according to the present invention, the upper light-shielding film is arranged in a lattice so as to define a non-opening region of a pixel, and the lower light-shielding film is arranged in a lattice. And

According to this aspect, the non-opening region of each pixel corresponding to each pixel electrode is defined by the upper light-shielding film arranged in a cross shape above the thin film transistor. And
In the lower light-shielding film, each stripe portion forming a lattice in the vertical and horizontal directions is formed narrower (one size smaller) than the upper light-shielding film. Therefore, higher light shielding performance can be improved.

Further, in the above aspect, the upper light-shielding film comprises:
One electrode includes at least one of a storage capacitor electrically connected to the pixel electrode and a data line electrically connected to the thin film transistor.

According to this aspect, since one of the capacitor electrodes constituting the storage capacitor and the data line can be used also as the upper light-shielding film, it is advantageous in simplifying the laminated structure.

The upper light-shielding film is composed of a data line and a capacitor line which intersect each other in a lattice pattern.
At least a junction of the channel region of the thin film transistor is located. Therefore, the junction of the channel region of the thin film transistor should be located in the region where the data line and the capacitance line, which have the best overall light-shielding properties for light obliquely incident vertically and horizontally, intersect with each other. By
A structure in which light leakage hardly occurs in the thin film transistor can be obtained.

Further, in the above aspect, the semiconductor layer of the thin film transistor is formed in a region where the region of the data line and the region of the lower light-shielding film overlap.

According to this aspect, since the entire semiconductor layer of the thin film transistor can be shielded from light, the occurrence of light leakage from the thin film transistor can be further reduced.

In the above aspect, the upper light-shielding film may include:
A plurality of first light shielding films extending in the first direction, an insulating film formed on the first light shielding film, and a plurality of second light shielding films formed on the insulating film and intersecting in the first direction. It is characterized by having been done.

According to this aspect, the upper light-shielding film is formed in a lattice shape from the first light-shielding film and the second light-shielding film that intersect with each other,
A junction of at least a channel region of the thin film transistor is located in the intersection region. Therefore, the junction of the channel region of the thin film transistor is formed in the region where the first light-shielding film and the second light-shielding film, which have the best overall light-shielding properties for light obliquely incident vertically and horizontally, intersect. , A configuration in which light leakage hardly occurs in the thin film transistor can be obtained.

Further, in the above aspect, the first light-shielding film includes:
One electrode is at least one capacitance electrode of a storage capacitor electrically connected to the pixel electrode, and the second light-shielding film is a data line electrically connected to the thin film transistor. I do.

According to this aspect, since one of the capacitor electrodes constituting the storage capacitor and the data line can be used also as the upper light-shielding film, it is advantageous in simplifying the laminated structure.

In another aspect of the electro-optical device according to the present invention, at least one of the upper light-shielding film and the lower light-shielding film comprises a plurality of light-shielding portions arranged in a cross shape in a region of the thin-film transistor. And

In order to reduce the occurrence of light leakage of the thin film transistor, it is sufficient that at least the junction of the channel region of the thin film transistor is shielded from light, and a cross-shaped light shielding portion may be formed for each thin film transistor.

In the above aspect, a scanning line electrically connected to the thin film transistor is formed in a region of the lower light-shielding film.

At this time, the scanning line may be made of polysilicon, amorphous silicon, a silicon film such as a single crystal silicon film, or polycide or silicide.

With this configuration, incident light and return light are guided like an optical fiber by, for example, a silicon film such as polysilicon, amorphous silicon, or a single crystal silicon film, or a scanning line made of polycide or silicide. The situation where the light reaches the channel region of the thin film transistor can be effectively prevented.

Further, in the above aspect, the scanning line is formed in the upper light-shielding film.

According to this aspect, since the scanning lines can be formed along the upper light-shielding film, the aperture ratio can be improved.

In another aspect of the electro-optical device according to the present invention, the semiconductor layer of the thin-film transistor includes a high-concentration region in which a channel and a high-concentration impurity are doped, and a low-concentration region between the channel and the high-concentration region. And a low-concentration region in which impurities are doped. The low-concentration region is formed in a region where an intersection region of the upper light-shielding film and an intersection region of the lower light-shielding film overlap.

According to this aspect, even in the thin film transistor having the LDD structure, occurrence of light leakage of the thin film transistor can be reduced.

In another aspect of the electro-optical device of the present invention, an edge of the lower light-shielding film in a cross section perpendicular to the one substrate is at least 10 degrees inside an edge of the upper light-shielding film opposed to the edge. It is characterized by being retreated.

According to this aspect, the edge of the lower light-shielding film in a cross section perpendicular to the substrate is receded inward by 10 degrees or more from the edge of the upper light-shielding film facing the edge, so that the direction perpendicular to the substrate is If the angle of incident light obliquely incident on the basis of 10 degrees or less, the incident light passing through the upper light-shielding film is reflected by the surface of the lower light-shielding film facing the upper light-shielding film. Generation of internally reflected light and multiple reflected light can be effectively prevented. In particular, in the case of an electro-optical device for general projector use, since oblique light exceeding 10 degrees hardly exists, it is effective to set the angle to 10 degrees or less.

On the other hand, by setting the angle at which the lower light-shielding film recedes does not extremely exceed 10 degrees, the lower light-shielding film of the upper light-shielding film is included in the return light passing by the lower light-shielding film. The amount of light reflected from the surface facing the film to become internally reflected light or multiple reflected light can be appropriately suppressed.

In another aspect of the electro-optical device according to the present invention, the other substrate facing the substrate is provided with an opposing light-shielding film located inside a region where the upper light-shielding film is formed. I do.

According to this aspect, in a configuration in which an electro-optical material such as liquid crystal is sandwiched between a substrate on which a thin film transistor or the like is formed and a counter substrate, another light shielding film is provided on the counter substrate side. ing. The other light-shielding film is located in the upper light-shielding film formation region when viewed in a plan view. Therefore, the other light-shielding film does not have a function defined by the opening region of each pixel, but faces unnecessary incident light. By blocking light on the substrate side, it is possible to prevent the temperature of the electro-optical device from rising. Further, by blocking unnecessary incident light to a certain extent on the counter substrate side, the incident light portion including components that become internal reflection or multiple reflection light can be reduced, so that the deterioration of the characteristics of the thin film transistor can be finally reduced more reliably.

In order to solve the above-mentioned problems, a projection type display device according to the present invention includes a light source, a light valve as the first electro-optical device of the present invention, and a device for guiding light generated from the light source to the light valve. And a projection optical member for projecting light modulated by the light valve.

According to this aspect, since the occurrence of light leakage of the thin film transistor in the electro-optical device can be prevented, a high-quality image can be projected.

The thin film transistor according to the present invention may be of a so-called top gate type in which a gate electrode formed of a part of a scanning line is located above a channel region, or may be a gate electrode formed of a part of a scanning line. May be a so-called bottom gate type located on the lower side. Further, the interlayer position of the pixel electrode may be above or below the scanning line on the substrate.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0043]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the electro-optical device according to the invention is applied to a liquid crystal device.

(First Embodiment) First, the configuration of an electro-optical device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 3 is a sectional view taken along line AA ′ of FIG. In FIG. 3, the scale of each layer and each member is different so that each layer and each member have a size that can be recognized in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to the present embodiment are formed by a pixel electrode 9a and a TFT 30 for controlling the switching of the pixel electrode 9a. The data line 6a to which the image signal is supplied is connected to the TFT
It is electrically connected to 30 sources. Data line 6a
, Sn to be written may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. The scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning line 3a is provided at a predetermined timing.
The scanning signals G1, G2,..., Gm are applied to a in a pulse-wise manner in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are connected to a counter electrode (described later) formed on a counter substrate (described later). For a fixed period of time. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the transmittance for the incident light decreases according to the voltage applied in each pixel unit. In the normally black mode, the light enters according to the voltage applied in each pixel unit. Light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole. here,
In order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a '), and the data line 6a and the scanning line 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a, respectively.

Further, the scanning line 3a is arranged so as to face the channel region 1a 'indicated by the hatched region in the semiconductor layer 1a, which rises to the right in the figure, and the scanning line 3a functions as a gate electrode (particularly, In the present embodiment, the scanning line 3a
Is formed wide in a portion to be the gate electrode). In this manner, at the intersections of the scanning lines 3a and the data lines 6a, the scanning lines 3a and
A pixel switching TFT 30 is provided in which a is opposed to each other as a gate electrode.

As shown in FIGS. 2 and 3, in this embodiment, particularly, the storage capacitor 70 is a relay layer as a pixel potential side capacitor electrode connected to the high-concentration drain region 1 e (and the pixel electrode 9 a) of the TFT 30. 71 a and a part of the capacitance line 300 as a fixed-potential-side capacitance electrode are formed to be opposed to each other with a dielectric film 75 interposed therebetween. Capacity line 3
00 denotes a first film 72 made of a conductive polysilicon film or the like.
And a second layer made of a metal silicide film or the like containing a high melting point metal.
The film 73 is formed of a multilayer film formed by lamination.

When viewed in plan, the capacitance line 300 is the scanning line 3a.
The portion overlapping the TFT 30 protrudes vertically in FIG. The data lines 6a extending in the vertical direction in FIG. 2 and the capacitance lines 300 extending in the horizontal direction in FIG. 2 are formed so as to intersect with each other. An example of a lattice-shaped upper light-shielding film is formed when viewed.

On the other hand, T on the TFT array substrate 10
Below the FT 30, a lower light-shielding film 11a is provided in a lattice shape.

In this embodiment, in particular, the lattice-shaped upper light-shielding film (capacitance line 300 and data line 6a) defines a non-opening region of the pixel. The formation region of the lattice-shaped lower light-shielding film 11a is also located in the formation region of the lattice-shaped upper light-shielding film (that is, formed to be slightly smaller than the lower light-shielding film 11a).
Are formed narrower than the widths of the capacitance line 300 and the data line 6a). Then, the channel region 1 of the TFT 30
a, including the junction with the low-concentration source region 1b and the low-concentration drain region 1c (that is, the LDD region), is within the intersection region of such a lattice-shaped lower light-shielding film 11a (accordingly, (In the crossing region of the upper light-shielding film).

The second film 7 forming a part of these upper light shielding films
3 and the lower light shielding film 11a are, for example, Ti, Cr,
It is composed of a single metal, an alloy, a metal silicide, a polysilicide, or a laminate of any of these, including at least one of metals such as W, Ta, Mo, Pb, and Al. In the present embodiment, particularly, the capacitance line 300 has a multilayer structure, and the first film 72 is a conductive polysilicon film.
The film 73 does not need to be formed from a conductive material, but if not only the first film 72 but also the second film 73 is formed from a conductive film, the resistance of the capacitance line 300 can be further reduced. In any case, at least one of the first film 72 and the second film 73 constituting the capacitance line 300 is formed of a light shielding film so as to constitute an upper light shielding film.

The dielectric film 75 disposed between the relay layer 71a as the capacitance electrode and the capacitance line 300 is, for example, a relatively thin HTO film having a thickness of about 5 to 200 nm, LT
It is composed of a silicon oxide film such as an O film, a silicon nitride film, a nitrided oxide film or the like, or a laminated film thereof. From the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained.

The first film 72 forming the capacitance line 300 is made of, for example, a polysilicon film having a thickness of about 50 nm or a silicon film made of amorphous or single crystal, and the second film 73 is made of, for example, about 150 nm. It is made of a tungsten silicide film. Thus, the first film 72 disposed on the side in contact with the dielectric film 75 is formed of a silicon film, and the relay layer 71a in contact with the dielectric film 75 is formed of a polysilicon film or a silicon film made of amorphous or single crystal. With this configuration, the deterioration of the dielectric film 75 can be prevented. For example, if a configuration is adopted in which a metal silicide film is brought into contact with the dielectric film 75, a metal such as a heavy metal enters the dielectric film 75, and the performance of the dielectric film 75 is deteriorated. Furthermore, such a capacitance line 300
Is formed on the dielectric film 75, without performing a photoresist process after the formation of the dielectric film 75, the capacitance line 30 is formed.
If 0 is formed, the quality of the dielectric film 75 can be improved, so that the dielectric film 75 can be formed thin, and the storage capacitance 70 can be finally increased.

As shown in FIGS. 2 and 3, the data line 6a
Is connected to a relay layer 71b for relay connection via a contact hole 81. The relay layer 71b is further connected via a contact hole 82 to the high-concentration source region 1d in the semiconductor layer 1a made of, for example, a polysilicon film. Is electrically connected to The relay layer 71b is formed simultaneously from the same film as the relay layer 71a.

The capacitance line 300 extends from the image display area where the pixel electrode 9a is arranged to the periphery thereof, is electrically connected to a constant potential source, and has a fixed potential. As the constant potential source, a scanning line driving circuit (described later) for supplying a scanning signal for driving the TFT 30 to the scanning line 3a or a data line driving circuit for controlling a sampling circuit for supplying an image signal to the data line 6a. It may be a constant potential source such as a positive power supply or a negative power supply supplied to (described later) or a constant potential supplied to a counter electrode of a counter substrate.

The lower light-shielding film 11a provided below the TFT 30 also has a capacitance line 300 to prevent the potential fluctuation from adversely affecting the TFT 30.
Similarly to the above, it is preferable to extend from the image display area to the periphery and connect to the constant potential source.

As shown in FIGS. 2 and 3, the pixel electrode 9a is electrically connected to the high-concentration drain region 1e of the semiconductor layer 1a through the contact holes 83 and 85 by relaying the relay layer 71a. It is connected. That is,
In this embodiment, the relay layer 71a functions as a pixel potential side capacitor electrode of the storage capacitor 70, and the pixel electrode 9a serves as a TFT.
It performs both the function of relay connection to 30. Further, the relay layer 71a and the relay layer 71b are made of the same conductive film (for example, a silicon film made of polysilicon, amorphous silicon, and single crystal silicon). Thus, the relay layer 71a
And 71b as relay layers, even if the interlayer distance is as long as, for example, about 1000 nm to 2000 nm, two or more series having relatively small diameters can be connected while avoiding technical difficulty of connecting them with one contact hole. A good contact hole can provide a good connection between the two, the pixel aperture ratio can be increased, and it also helps to prevent etching penetration when the contact hole is opened.

As shown in FIGS. 2 and 3, the electro-optical device includes a transparent TFT array substrate 10 and a transparent opposing substrate 20 disposed opposite to the TFT array substrate. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

The TFT array substrate 10 has a lattice-shaped groove 10cv dug in a plan view (indicated by a hatched area at the lower right in FIG. 2). Scanning line 3a, data line 6
a, wiring and elements such as the TFT 30 are embedded in the trench 10cv. As a result, the step between the region where the wiring, the element, and the like are present and the region where the wiring, the element, and the like are not present is reduced, and ultimately, image defects such as defective alignment of the liquid crystal due to the step can be reduced.

As shown in FIG. 3, the TFT array substrate 10
Is provided with a pixel electrode 9a, and above it,
Alignment film 16 that has been subjected to a predetermined alignment treatment such as a rubbing treatment
Is provided. The pixel electrode 9a is made of, for example, ITO (In
It consists of a transparent conductive thin film such as a dium tin oxide film. The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

The opposing substrate 20 may be provided with a lattice-shaped or stripe-shaped light-shielding film. By adopting such a configuration, incident light from the counter substrate 20 side together with the capacitor line 300 and the data line 6a constituting the upper light-shielding film as described above is transmitted from the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region. 1c can be more reliably prevented from entering. Further, such a light-shielding film on the counter substrate 20 side functions to prevent a temperature rise of the electro-optical device by forming at least a surface to be irradiated with incident light with a highly reflective film. The light-shielding film on the side of the counter substrate 20 is preferably formed so as to be located inside the upper light-shielding film including the capacitor line 300 and the data line 6a in plan view. Thus, the light-shielding film on the counter substrate 20 side can achieve such effects of light-shielding and temperature rise prevention without lowering the aperture ratio of each pixel.

The space between the TFT array substrate 10 and the opposing substrate 20 having the pixel electrode 9a and the opposing electrode 21 arranged in such a manner as to face each other is provided in a space surrounded by a sealing material described later. Liquid crystal, which is an example of an electro-optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 holds the alignment film 1 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is taken by 6 and 22. Liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is used for bonding the TFT array substrate 10 and the opposing substrate 20 around them.
For example, it is an adhesive made of a photo-curing resin or a thermosetting resin, and a gap material such as glass fiber or glass beads for mixing the two substrates at a predetermined distance is mixed.

Further, a base insulating film 12 is provided below the pixel switching TFT 30. Base insulating film 1
2 has a function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, and is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 can be roughened during polishing or stains remaining after cleaning. T for pixel switching
It has a function of preventing deterioration of the characteristics of the FT 30.

In FIG. 3, a TF for pixel switching is used.
T30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', an insulating thin film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, a high-concentration source region 1d of the semiconductor layer 1a, and a high-concentration source region. It has a concentration drain region 1e.

On the scanning line 3a, a high concentration source region 1d
A first interlayer insulating film 41 is formed in which a contact hole 82 leading to the contact hole 83 and a contact hole 83 leading to the high concentration drain region 1e are opened.

The relay layers 71a and 71b, the dielectric film 75, and the capacitor line 300 are formed on the first interlayer insulating film 41, and the contact holes 81 and the conductive holes 71a and 71b are formed on these relay layers 71a and 71b, respectively. The second interlayer insulating film 42 in which the contact holes 85 are respectively formed is formed.

In this embodiment, the first interlayer insulating film 41
Is carried out at 1000 ° C. to form a polysilicon film (or a silicon layer made of amorphous silicon or single crystal silicon) constituting the semiconductor layer 1a or the scanning line 3a.
May be activated. On the other hand, the second
By not sintering the interlayer insulating film 42, stress generated near the interface of the capacitance line 300 may be reduced.

A data line 6a is formed on the second interlayer insulating film 42, and a third interlayer insulating film 4 having a contact hole 85 connected to the relay layer 71a is formed thereon.
3 are formed. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 configured as described above. The alignment film 16 is provided on the pixel electrode 9a.

According to the present embodiment configured as described above, the channel region 1 of the TFT 30 is arranged from the counter substrate 20 side.
When the incident light attempts to enter a ′ and its vicinity, the light is shielded by the lattice-shaped upper light-shielding film including the data line 6a and the capacitance line 300 (particularly, the second film 73). On the other hand, TFT
From the array substrate 10 side, the channel region 1 of the TFT 30
When return light attempts to enter a ′ and its vicinity, the light is blocked by the lower light-shielding film 11a (particularly, a plurality of electro-optical devices are combined via a prism or the like in a multiple-plate type color display projector or the like). When two optical systems are configured, the return light composed of the projected light portion penetrating through the prism or the like from another electro-optical device is effective because it is strong.)

For example, like a light shielding film on the opposing substrate 20,
TFT3 for oblique incident light, internally reflected light, multiple reflected light, etc.
If the light is shielded at an interlayer distance from 0, the light shielding effect is low. In contrast, in the present embodiment, the light is shielded by the capacitance line 300, the data line 6a, and the lower light-shielding film 11a which can be arranged so that the interlayer distance to the semiconductor layer 1a is relatively small. Deterioration hardly occurs, and extremely high light resistance can be obtained in the electro-optical device.

Next, with reference to FIGS. 4 to 15, light-shielding in this embodiment will be further described. here,
FIG. 4 is a schematic plan view illustrating the upper light-shielding film and the lower light-shielding film in the image display area, which are extracted and enlarged. FIG. 5 is a schematic plan view illustrating the vicinity of the channel region of the TFT 30 in an enlarged manner. FIG. 6 to 9 are characteristic diagrams showing the relationship between the gate voltage and the drain current when the channel width W of the TFT is changed, and FIG. 10 is a characteristic diagram showing the relationship between the channel width W and the drain current. It is. FIGS. 11 to 13 are characteristic diagrams showing the relationship between the gate voltage and the drain current when the channel width W in the TFT is fixed and the channel length L1 or the LDD length L2 is changed. 14 and FIG.
FIG. 5 is a schematic cross-sectional view showing a state of light shielding by an upper light-shielding film and a lower light-shielding film in a BB ′ section of FIG. 4.

As shown in FIG. 4, in the present embodiment, the non-opening region of each pixel is mainly composed of the capacitor line 300 and the portion where the capacitor line 300 is interrupted for forming the contact holes 81 and 82. It is defined by the upper light-shielding film composed of the data line 6a. Therefore, the upper light-shielding film can effectively prevent the light leakage from occurring and lowering the contrast ratio. Here, an upper light-shielding film exists above the TFT 30, a lower light-shielding film 11a arranged in a lattice exists below the TFT 30, and a formation region of the lower light-shielding film 11a is
It is located in the formation region of the upper light shielding film.

Further, as shown in FIG. 5, the junction JC of the channel region of the TFT 30 is located in the intersection region CR of the lower light-shielding film 11a shown in FIG.

Therefore, according to the present embodiment, when strong incident light is incident as in a projector, not only the component perpendicular to the TFT array substrate 10 but also the oblique component of the incident light, the TFT 30 (especially , Its junction JC) can be shielded from light by the upper light-shielding film. On the other hand, return light can be reliably shielded by the lower light shielding film 11a.

In addition, according to the study by the present inventors,
It has been found that light leaks most sensitively when light enters the junction JC of the channel region 1a 'of the TFT 30. This point will be described with reference to FIGS.

That is, it has an LDD structure (provided that the channel length L1 shown in FIG. 5 is 5 μm and the LDD length L2 is 1.
A TFT 30 is prepared and (1) a state in which the drain voltage is set to 10 V and no light is irradiated, (2) a state in which the drain voltage is set to 4 V and light is not irradiated, and (3) Here, the relationship between the gate voltage and the drain current is examined here for a total of four states: a state in which the drain voltage is set to 10 V and light is irradiated, and (4) a state in which the drain voltage is set to 4 V and light is irradiated. .
The result of setting the channel width W to 5 μm is as shown in FIG. 6 (in FIG. 6, the characteristic curves corresponding to the above four states are indicated by C1, C2, C3 and C4), The result of setting the channel width W to 20 μm is as shown in FIG. 7 (in FIG. 7, the characteristic curves corresponding to the above four states are indicated by C1, C2, C3, and C4), and the channel width W The result of setting W to 50 μm is as shown in FIG. 8 (in FIG. 8, the characteristic curves corresponding to the above four states are indicated by C1, C2, C3 and C4), and the channel width W is The result of 100 μm is as shown in FIG. 9 (in FIG. 9, characteristic curves corresponding to the above four states are indicated by C1, C2, C3 and C4). Further, based on these results, the relationship between the channel width W and the current in the two states of irradiating light out of the above four states is as shown in FIG. 10 (in FIG. 10, the drain voltage was set to 10 V). characteristic curve in the case is shown in L _10, characteristic curve in the case of setting the drain voltage to 4V is represented by L _04). FIG. 10 shows a current value (here, this is referred to as a light leakage current) during light irradiation when the drain voltage is between -8 and -5 V.

FIGS. 11 to 13 show that the channel width W = 15.
FIG. 11 shows the relationship between the gate voltage and the drain current of the TFT 30 with the channel length L1 = 4 μm.
m and the LDD length L2 = 1.5 μm, and in FIG.
Channel length L1 = 2 μm and LDD length L2 = 1.5 μm
In FIG. 13, the channel length L1 = 2 μm and LD
D length L2 = 1.0 μm. 11 to FIG.
Characteristic curves corresponding to the above four states are respectively shown in FIG.
1, C2, C3 and C4. 6 to 9
In comparison with the gate voltages 5 to 5 shown in FIGS.
The reason why the drain current at 15 V is different is that the metal material used for the source electrode is different, that is, the contact resistance between the source electrode and the high-concentration source region is high. This is irrelevant to the light leakage current that is the gist of the present application.

When comparing FIG. 11 and FIG. 12, there is almost no difference in the light leakage current. That is, it is considered that even if the channel length L1 (see FIG. 5) is changed, the light leak current hardly changes. Further, comparing FIG. 16 and FIG. 17, there is almost no difference in the light leakage current, and the LDD length L2 (see FIG. 5)
It is considered that there is almost no change in the light leakage current even if is changed.

It can be seen from FIGS. 6 to 13 that the amount of light leakage significantly changes when the channel width W is changed even when various conditions such as the amount of light to be irradiated, the channel length L1 and the LDD length L2 are fixed. I understand. Then, it can be determined that the photocurrent is generated at the junction JC of the channel region 1a 'shown in FIG. That is, it is determined that the light leakage current can be effectively reduced by reducing the light applied to the junction JC.

Therefore, in the present embodiment, the lattice-shaped lower light-shielding film 11a, which is hardly incident light in the image display area, is used.
The junction JC (see FIG. 5) of the channel region 1a 'of the TFT 30 is located in the intersection region CR (see FIG. 4). Therefore, a configuration in which light leakage hardly occurs for incident light can be efficiently obtained. In addition, by shielding the TFT 30 from above and below in close proximity to the TFT 30, it is possible to avoid unnecessarily expanding the formation region of the light-shielding film (that is, to unnecessarily narrow the non-opening region of each pixel). Without light), and the light-shielding performance can be improved.

Further, in this embodiment, as shown in FIG. 4, the formation region of the lower light-shielding film 11a is located in the upper light-shielding film, that is, the formation region of the capacitor line 300 and the data line 6a. The incident light incident from the side of the film is reflected on the upper surface of the lower light-shielding film 11a, thereby effectively preventing the occurrence of internal reflected light and multiple reflected light. This point will be further described with reference to FIGS.

As shown in FIG. 14, in the present embodiment, preferably, the lower light-shielding film 11a in the BB 'section of FIG.
Of the capacitor line 300, which forms the upper light-shielding film, is 1
It recedes inward by more than 0 degrees. That is, in the present embodiment, the laminated structure is preferably designed such that the receding angle Δθ of the lower light-shielding film 11a shown in FIGS. 14 and 15 is 10 degrees or more.

Therefore, in FIG. 14, if the angle of the incident light LT1 obliquely incident on the TFT array substrate 10 is 10 degrees or less, the incident light LT1 passing by the side of the capacitance line 300
However, the reflection on the upper surface of the lower light-shielding film 11a can effectively prevent the generation of internal reflected light and multiple reflected light. In particular, in the case of an electro-optical device for general projector use, the incident light LT1 obliquely incident at more than 10 degrees.
Is almost nonexistent, so that the receding angle Δθ is 10
It is effective to increase the degree. However, if the oblique incident light LT1 of up to about 15 degrees exists so as to be negligible due to the specifications and design of the apparatus, the lower side is set so that the receding angle Δθ becomes 15 degrees or more accordingly. The light shielding film 11a may be configured.

On the other hand, as shown in FIG.
By setting the receding angle Δθ of 1a not exceeding 10 degrees, the return light LT passing by the side of the lower light-shielding film 11a.
2, the internal reflected light L reflected by the lower surface of the capacitance line 300
It is possible to moderately suppress the light amount of the portion that becomes the T3 and the multiple reflection light LT4. By forming the lower light-shielding film 11a one size smaller than the upper light-shielding film as in the present embodiment, the return light LT2 passing by the side of the lower light-shielding film 11a is reflected by the inner surface of the upper light-shielding film. However, since the light intensity of the return light LT2 is much lower than that of the incident light LT1, the internal reflection light LT3 and the multiple reflection light LT caused by the return light LT2 are obtained.
4 can be much smaller than those caused by the incident light LT1. Accordingly, although the internal reflection light LT3 and the multiple reflection light LT4 due to the return light LT2 are slightly generated, the configuration of the present embodiment for minimizing the generation of the internal reflection light and the multiple reflection light due to the incident light LT1 reduces the light leakage. It is very advantageous in practice.

In addition, in the present embodiment described above, the scanning line 3a made of a light-guiding polysilicon film is located within the formation region of the lower light-shielding film 11a along the scanning line 3a. I have. Therefore, incident light and return light enter the inside of the scanning line 3a made of a polysilicon film (or at least a film containing silicon) and pass through the inside of the scanning line 3a (light is guided like an optical fiber). TFT3
The situation that reaches the zero channel region 1a 'and its vicinity can be prevented.

As a result, according to the present embodiment, deterioration of characteristics due to light leakage of the pixel switching TFT 30 can be reduced by increasing the light resistance while increasing the aperture ratio of each pixel, and finally the contrast ratio is high, and the brightness is high. High-quality image display becomes possible.

In the embodiment described above, by stacking a large number of conductive layers as shown in FIG. 3, the data line on the ground under the pixel electrode 9a (ie, the surface of the third interlayer insulating film 43) is formed. The occurrence of a step in the area along the scanning line 6a and the scanning line 3a is mitigated by digging a groove 10cv in the TFT array substrate 10, but instead or additionally, the base insulating film 12, the first interlayer insulating Film 41, second interlayer insulating film 4
Second, a flattening process may be performed by digging a groove in the third interlayer insulating film 43 and burying the wiring such as the data line 6a or the TFT 30 or the like, or the third interlayer insulating film 43 or the second interlayer insulating film 42. The step on the upper surface of the
lishing) process, or by polishing organic S
The flattening treatment may be performed by using OG to form a flat surface.

In the embodiment described above, the pixel switching TFT 30 preferably has the LDD structure as shown in FIG. 3, but does not implant impurities into the low-concentration source region 1b and the low-concentration drain region 1c. An impurity may be implanted at a high concentration using an offset structure, or using a gate electrode composed of a part of the scanning line 3a as a mask.
A self-aligned TFT that forms high-concentration source and drain regions in a self-aligned manner may be used. In the present embodiment, the gate switching TFT 30 has a single gate structure in which only one gate electrode is disposed between the high-concentration source region 1d and the high-concentration drain region 1e, but two or more gate electrodes are provided between them. It may be arranged. In this way, the TF is more than dual gate or triple gate.
When T is formed, a leak current at a junction between the channel and the source / drain region can be prevented, and a current at the time of off can be reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG.
It is a top view of an upper light shielding film or a lower light shielding film.

In the first embodiment, the upper light shielding film is constituted by the data line 6a and the capacitance line 300. In the second embodiment, however, the independent upper light shielding film 100 is formed between the storage capacitor 70 and the thin film transistor 30. are doing. The upper light-shielding film 100 is formed in a cross-shaped island shape. A high-concentration source region 1d and a relay layer 7
1b, a contact hole 81 between the relay layer 71b and the data line 6a, a high-concentration drain region 1e, a relay layer 71a and a contact hole 83 are formed.

The upper light-shielding film 100 overlaps the channel region 1a of the semiconductor layer 1a, the low-concentration source region 1b, the low-concentration drain region 1c, a part of the high-concentration source region 1d, and a part of the high-concentration drain region 1e. It is formed as follows.

The upper light-shielding film 100 is formed in two layers, like the capacitance line 300 of the first embodiment. The upper side is a light-shielding layer, and the lower side, which faces the thin film transistor 30, is a light-absorbing layer. It is composed of In this case, the storage capacitor 70 may be configured in the same manner as in the first embodiment, or may be a light transmissive material. Alternatively, the capacitance line 300 of the storage capacitor 70 may be a light-shielding layer, and the upper light-shielding film 100 may be a light-absorbing layer only.

The cross-shaped island-shaped light-shielding film may be formed as the lower light-shielding film 11a. The configuration is the same as in the first embodiment.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIG. 17 and FIG. Note that FIG.
FIG. 18 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20, and FIG. 18 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 18, on the TFT array substrate 10, a sealing material 52 is provided along the edge thereof, and in parallel with the inside thereof, a light shielding as a frame defining the periphery of the image display area 10a is provided. A film 53 is provided. In a region outside the sealing material 52, a data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10. A scanning line driving circuit 1 for driving a scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing.
04 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area 10a. Further, on one remaining side of the TFT array substrate 10, the scanning line driving circuits 10 provided on both sides of the image display area 10a are provided.
A plurality of wirings 105 are provided to connect the four wirings. In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided. Then, as shown in FIG. 18, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 17 is fixed to the TFT array substrate 10 by the sealing material 52.

On the TFT array substrate 10, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of Data line 6a
A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.

In each of the embodiments described above with reference to FIGS. 1 to 18, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, the TN mode, V
A (Vertically Aligned) mode, PDLC (Polymer D
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as an ispersed liquid crystal (mode) or a normally white mode / normally black mode.

(Application Example of Electro-Optical Device) The electro-optical device in each of the embodiments described above can be applied to a projector. A projector using the above-described electro-optical device as a light valve will be described. FIG. 19 is a plan view showing the configuration of this projector. As shown in the figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is applied to three mirrors 1106 arranged inside.
And two dichroic mirrors 1108
The light is separated into three primary colors of GB and guided to light valves 100R, 100G, and 100B corresponding to the respective primary colors. Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the electro-optical device according to the above-described embodiment, and the primary colors of R, G, and B supplied from a processing circuit (not shown) that inputs an image signal. Each is driven by a signal. In addition, the light of B color is used for other R color and G light.
Since the optical path is longer than that of the color, the light is guided through a relay lens system 1121 including an input lens 1122, a relay lens 1123, and an output lens 1124 in order to prevent the loss.

Now, the light valves 100R, 100G,
The lights modulated by 100B respectively enter dichroic prism 1112 from three directions. And
In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, after the images of each color are combined, a color image is projected on the screen 1120 by the projection lens 1114.

Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 1108, it is not necessary to provide a color filter as described above. The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 1112, whereas the transmitted images of the light valve 100G are projected as they are.
Is inverted left and right with respect to the display image by the light valve 100G.

In each of the embodiments, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 in a predetermined region facing the pixel electrode 9a together with the protective film. In this way, the electro-optical device in each embodiment can be applied to a direct-view or reflective color electro-optical device other than the projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

The present invention is not limited to the above-described embodiment, but can be appropriately modified without departing from the spirit or spirit of the invention which can be read from the claims and the entire specification. The electro-optical device and the manufacturing method thereof are also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wires, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the first embodiment.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a plan view of a pixel on a TFT array substrate, showing an upper light-shielding film and a lower light-shielding film in the first embodiment.

FIG. 5 is an enlarged schematic plan view showing the vicinity of a channel region of the TFT according to the first embodiment.

FIG. 6 is a characteristic diagram (part 1) illustrating a relationship between a gate voltage and a current when a channel width W in a TFT is changed.

FIG. 7 is a characteristic diagram (part 2) illustrating a relationship between a gate voltage and a drain current when a channel width W of a TFT is changed.

FIG. 8 is a characteristic diagram (part 3) illustrating a relationship between a gate voltage and a drain current when a channel width W in a TFT is changed.

FIG. 9 is a characteristic diagram (part 4) illustrating a relationship between a gate voltage and a drain current when a channel width W in a TFT is changed.

FIG. 10 is a characteristic diagram showing a relationship between a channel width W and a current.

FIG. 11 is a characteristic diagram (part 1) illustrating a relationship between a gate voltage and a drain current when the channel width W in the TFT is fixed and the channel length L1 or the LDD length L2 is changed.

FIG. 12 is a characteristic diagram (part 2) illustrating a relationship between a gate voltage and a drain current when the channel width W in the TFT is fixed and the channel length L1 or the LDD length L2 is changed.

FIG. 13 is a characteristic diagram (part 3) illustrating a relationship between a gate voltage and a drain current when the channel width W in the TFT is fixed and the channel length L1 or the LDD length L2 is changed.

FIG. 14 is a schematic cross-sectional view (part 1) showing a state of light shielding by the upper light-shielding film and the lower light-shielding film in the BB 'section of FIG.

FIG. 15 is a schematic cross-sectional view (part 2) showing a state of light shielding by the upper light-shielding film and the lower light-shielding film in the BB 'section of FIG.

FIG. 16 is a plan view of an upper light-shielding film or a lower light-shielding film in a second embodiment of the present invention.

FIG. 17 is a plan view of the TFT array substrate in the electro-optical device according to the embodiment together with the components formed thereon as viewed from the counter substrate side.

18 is a sectional view taken along the line H-H 'of FIG.

FIG. 19 is a configuration diagram of a projector.

[Description of Signs] 1a Semiconductor layer 1a 'Channel region 1b Low concentration source region 1c Low concentration drain region 1d High concentration source region 1e High concentration drain region 2 Insulating thin film 3a Scanning line 6a Data line 9a: Pixel electrode 10: TFT array substrate 10cv: Groove 11a: Lower light-shielding film 12: Base insulating film 16: Alignment film 20: Counter substrate 21: Counter electrode 22: Alignment film 30: TFT 50: Liquid crystal layer 70: Storage capacitor 71a ... relay layer 71b ... relay layer 72 ... first film of capacitance line 73 ... second film of capacitance line 75 ... dielectric film 81, 82, 83, 85 ... contact hole 300 ... capacitance line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H088 EA12 EA13 EA14 EA15 EA16 HA08 HA14 2H092 GA21 GA24 GA28 GA30 GA42 GA43 GA44 JA24 JA45 JB21 JB22 JB31 JB51 JB61 JB63 JB64 JB68 KA10 NA07 5C058 AA09 AB04 AB06 AB06 AB06 AB06

Claims (13)

[Claims] 1. A pair of substrates, an electro-optical material sandwiched between the pair of substrates, a plurality of pixel electrodes arranged in a matrix on the one substrate, and electrically connected to the pixel electrodes. A thin film transistor, an upper light-shielding film arranged in a cross shape above the thin film transistor on the one substrate, and a formation region of the upper light-shielding film arranged in a cross shape below the thin film transistor on the one substrate. A lower light-shielding film formed on the inner side; and a junction of a channel region of the thin film transistor formed in a region where an intersection region of the upper light-shielding film and the lower intersection region overlap each other. Electro-optical device. 2. The electro-optical device according to claim 1, wherein the upper light-shielding film is arranged in a lattice so as to define a non-opening region of a pixel, and the lower light-shielding film is arranged in a lattice. apparatus. 3. The upper light-shielding film includes at least one capacitance electrode of a storage capacitor whose one electrode is electrically connected to the pixel electrode, and a data line electrically connected to the thin film transistor. 3. The electro-optical device according to claim 2, wherein 4. The electro-optical device according to claim 3, wherein a semiconductor layer of the thin film transistor is formed in a region where a region of the data line and a region of the lower light-shielding film overlap. 5. The upper light-shielding film includes a plurality of first light-shielding films extending in a first direction, an insulating film formed on the first light-shielding film, and a first direction formed on the insulating film. 3. The electro-optical device according to claim 2, comprising a plurality of second light-shielding films intersecting with each other. 6. The first light-shielding film is at least one capacitance electrode of a storage capacitor whose one electrode is electrically connected to the pixel electrode, and the second light-shielding film is electrically connected to the thin-film transistor. 6. The electro-optical device according to claim 5, wherein the data line is connected to the data line. 7. The electro-optical device according to claim 1, wherein at least one of the upper light-shielding film and the lower light-shielding film includes a plurality of light-shielding portions arranged in a cross shape in a region of the thin film transistor. . 8. The electro-optical device according to claim 2, wherein a scanning line electrically connected to the thin film transistor is formed in a region of the lower light shielding film. 9. The electro-optical device according to claim 8, wherein the scanning line is formed in the upper light shielding film. 10. The semiconductor layer of the thin film transistor,
A high-concentration region in which a channel and a high concentration of impurities are doped; and a low-concentration region in which a low concentration of impurities is doped between the channel and the high-concentration region. 2. The electro-optical device according to claim 1, wherein the intersection area of the film and the intersection area of the lower light-shielding film overlap each other. 11. An edge of the lower light-shielding film in a cross section perpendicular to the one substrate is receded inward by 10 degrees or more from an edge of the upper light-shielding film opposed to the edge. The electro-optical device according to claim 1. 12. The electro-optical device according to claim 1, wherein an opposing light-shielding film located inside a region where the upper light-shielding film is formed is provided on the other substrate opposite to the substrate. 13. A light valve comprising the electro-optical device according to claim 1, a light guide member for guiding light generated from the light source to the light valve, and modulation by the light valve. And a projection optical member for projecting the projected light.