JP2002110988A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a high-frequency high power MOS transistor of smaller parasitic capacitance in the drain region and a smaller chip size, having superior heat radiation. SOLUTION: The high-frequency high power MOS transistor is formed, using a silicon epitaxial layer on an SOI substrate, and the source or drain region is bump-connected to a circuit board on a chip main surface using a connection electrode separately provided on the source or drain region. Thus a deep P+ diffusion layer, which is used conventionally for grounding of a source region on the rear surface of a substrate is not required, resulting in a semiconductor device with a reduced chip size and superior heat radiation. If the thickness of a silicon epitaxial layer on the SOI substrate is so set that a chip of a drain junction void layer expanding from the bottom surface of the drain region toward the SOI substrate side reaches the SOI substrate surface, a drain junction capacitance at a part directly under the drain region is reduced, for significantly improving high-frequency characteristics of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to a field effect transistor for high frequency and large power.

[0002]

2. Description of the Related Art In a conventional field effect transistor for high frequency and high power, two comb electrodes are arranged so as to face each other, and a gate electrode and a drain region of the field effect transistor are divided into a number of segments. Are connected in parallel with each other to avoid non-uniform flow of channel current due to gate resistance or the like.

As described above, if a large number of field effect transistors having relatively small gate widths are connected in parallel using two opposing comb electrodes, the field effect for high frequency and high power operation with high efficiency can be obtained. A transistor can be obtained.

Next, the structure of a conventional high-frequency, high-power field-effect transistor will be described with reference to FIGS. FIG. 5 is a plan view of a MOS transistor having two opposing comb electrodes.

The MOS transistor shown in FIG. 5 has a comb-shaped gate electrode 16 for connecting a plurality of gate electrodes 1 in parallel,
It comprises a comb-shaped drain electrode 5 for connecting a plurality of drain regions 6 (see FIG. 6) in parallel, and a connection electrode 4 on a source region grounded on the lower surface of the semiconductor chip.

In FIG. 5, the gate electrode 1 is formed by patterning a pair of adjacent gate electrodes.
One set of gate electrodes is connected to the electrode 1 through the contact hole.
Strictly speaking, the electrode 16 is hardly called a comb-shaped electrode because it is connected to the electrode 6, but in this specification, the electrode 16 is also referred to as a comb-shaped electrode including the case where the electrodes 16 are combined as described above.

Next, the cross-sectional structure of a conventional high-frequency, high-power MOS transistor will be described in detail with reference to FIG. FIG. 6 is a sectional view taken along line AA of FIG.

[0008] cross-sectional structure of a conventional MOS transistor for high frequency high power shown in FIG. 6, on the P ⁺ silicon substrate 11 P ^-
A silicon epitaxial layer 10, an N ⁺ drain region 6 formed by ion implantation and diffusion into the P ^- silicon epitaxial layer 10, and a low impurity concentration N-type extended drain region extended from the N ⁺ drain region 6 7
, N ⁺ source region 8 and deep P ⁺ formed on the source side.
The diffusion layer 9, the gate electrode 1 formed on the gate insulating film 2, the interlayer insulating film 3 covering the surface thereof, the source electrode 4 for grounding the N ⁺ source region 8, and the N ⁺ drain region 6 are arranged in parallel. And a comb-shaped drain electrode 5 connected to the drain electrode 5.

Here, the N-type extended drain region 7 having a low impurity concentration serves to increase the breakdown voltage between the drain and source of the MOS transistor, and the deep P ⁺ diffusion layer 9 extends until it reaches the P ⁺ silicon substrate 11. Deeply diffused, the N ⁺ source region 8 and the P ⁺ silicon substrate 11 are electrically connected via the source electrode 4 on the surface. Normal P ⁺ silicon substrate 1
1 is grounded, so that the N ⁺ source region 8 of the conventional high-frequency high-power MOS transistor is configured to be grounded on the back surface of the P ⁺ silicon substrate 11.

In this case, the parasitic inductance can be reduced and the efficiency of high-frequency operation can be improved as compared with the case where the source electrode is taken out from the surface of the silicon substrate and grounded on the surface of the silicon substrate using bonding wires. .

However, if this structure is used, the drain junction capacitance between the N ⁺ drain region 6 and the N type extended drain region 7 and the P ⁻ silicon epitaxial layer 10 becomes a parasitic capacitance. In order to improve the characteristics, the drain junction capacitance must be reduced.

Conventionally, as a countermeasure for reducing the drain junction capacitance, there has been proposed a method of providing a buried insulating film 19 immediately below a drain region as shown in FIG. But,
A sufficient thickness of the insulating film 19 necessary for reducing the drain junction capacitance without lowering the crystal quality of the P ^- silicon epitaxial layer 10 necessary for forming a good MOS transistor is formed by a deep P ⁺ diffusion layer. It is extremely difficult to selectively bury them with a high yield during 9.

Although high power operation of a MOS transistor inevitably involves a large amount of heat generation, since a silicon oxide film generally has a low thermal conductivity, heat generated intensively on the drain side is generated on a P ⁺ silicon substrate. It becomes difficult to radiate heat to the lower part of the MOS transistor 11, which adversely affects the operation and reliability of the MOS transistor.

[0014]

As described above, N ⁺
In a conventional semiconductor device including a high-frequency high-power MOS transistor in which a source region is grounded on the back surface of a silicon substrate via a source electrode on the surface and a deep P ⁺ diffusion layer, the parasitic capacitance of the drain region is low. To be big
There has been a problem that high frequency characteristics cannot be significantly improved. Further, since it is necessary to form deep P ⁺ diffusion layers connected to a large number of N ⁺ source regions, there is a problem that the chip area of the semiconductor device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made of a semiconductor comprising a high-frequency, high-power MOS transistor having a smaller parasitic capacitance of a drain region, a better heat dissipation, and a smaller chip area than conventional ones. It is intended to provide a device.

[0016]

According to the present invention, there is provided a semiconductor device comprising:
A MOS transistor for high frequency and high power was formed using an epitaxial silicon single crystal layer on an SOI (Silicon On Sapphire) substrate, and the connection between the source or drain region and the circuit substrate was individually provided on the source or drain region. A first feature is that bump connection is made on the surface of the MOS transistor chip via a connection electrode.

With this configuration, a deep P ⁺ diffusion layer for electrically connecting the source or drain region to the back surface of the chip is not required, so that the chip area is reduced and a semiconductor device having excellent heat dissipation is provided. be able to.

Further, the thickness of the epitaxial silicon single crystal layer on the SOI substrate of the semiconductor device of the present invention is the above MO
A second feature is that the tip of the drain junction depletion layer spreading from the bottom surface of the drain region to the surface of the SOI substrate reaches the surface of the SOI substrate in the operating state of the S transistor. By doing so, the drain junction capacitance immediately below the drain region is eliminated, and the high-frequency characteristics of the semiconductor device can be significantly improved.

Specifically, the semiconductor device of the present invention comprises a semiconductor layer formed on an insulating substrate, a plurality of source and drain regions formed on the semiconductor layer, and a plurality of source and drain regions formed on the semiconductor layer. A plurality of source and drain regions and the gate electrode, wherein the plurality of source and drain regions and the gate electrode are parallel to each other in a longitudinal direction,
It forms a row of field effect transistors arranged in order along the direction perpendicular to the longitudinal direction, and a source region and a drain region located between the row of field effect transistors are between adjacent field effect transistors. The gate electrodes of the field-effect transistors in a row, which are shared with each other, are connected in parallel by first comb-shaped electrodes, respectively.
The source region of the row of field effect transistors is
Are connected in parallel by the comb-shaped electrodes, and the drain region of the one-line field-effect transistor is connected to a wiring substrate facing the main surface of the semiconductor device via a connection electrode formed on the drain region. It is characterized by being individually connected.

Preferably, the drain regions of the row of field-effect transistors are connected in parallel by second comb-shaped electrodes, respectively, and the source region of the row of field-effect transistors is formed on the source region. The semiconductor device is directly and individually connected to the wiring substrate facing the main surface of the semiconductor device via the connection electrode. Preferably, the drain region includes an extended drain region with a low impurity concentration extended toward the gate electrode.

Preferably, the semiconductor layer has a thickness d.
Where d1 ≦ d ≦ d1 + d, where d1 is the depth of the drain region, and d2 is the thickness of the drain junction depletion layer when the drain bias of the field effect transistor is applied.
2 is set.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment. In the first embodiment, a structure of a high-frequency, high-power semiconductor device including a MOS transistor will be described.

The high-frequency high-power MOS transistor according to the first embodiment shown in FIG. 1 has an insulator substrate (SOI substrate) 14 made of a single crystal such as sapphire, and is epitaxially grown on the insulator substrate 14. Semiconductor layer 13 made of P ⁻ silicon, N ⁺ drain region 6 formed in semiconductor layer 13, and low impurity concentration formed on both sides of N ⁺ drain region 6 along the surface of semiconductor layer 13. and N-type extended drain region 7, and N ⁺ source regions 8 formed in the semiconductor layer 13 via the gate insulating film 2 is formed between the extended drain region 7 and the N ⁺ source regions 8 on the semiconductor layer 13 Gate electrode 1, insulating film 3 covering the surface of semiconductor layer 13, source electrode 4 and drain electrode 5 formed on insulating film 3 through contact holes.
And an interlayer insulating film 15 formed so as to cover it,
It comprises a connection electrode 17 connected to the source electrode 4 via a contact hole.

The MO for high frequency and high power configured as described above
The S transistor chip is connected to a circuit board (not shown) using the connection electrode 17 with its main surface facing down.
For example, if a solder bump or the like is formed on the connection electrode 17 and connected to a pad having high heat dissipation provided on the circuit board, high mounting efficiency can be obtained, and at the same time, high performance can be obtained because no parasitic inductance is generated in the connection portion. In addition, since heat can be radiated directly from the surface of the semiconductor layer 13 close to the heat source toward the circuit board, a highly reliable semiconductor device can be obtained.

At this time, the drain electrode 5 is, for example, as shown in FIG.
It is sufficient to form a pattern as a comb-shaped electrode as shown in FIG. The connection between the connection electrode 17 and the circuit board is not necessarily limited to the solder bump,
The connection can be made using ball bonding or a via plug having excellent thermal conductivity. Further, since all the electrodes required for the operation of the MOS transistor are taken out from the main surface side of the MOS transistor chip, the deep P ⁺ diffusion layer 9 shown in FIGS. 6 and 7 becomes unnecessary, and the chip area is reduced as compared with the conventional case. can do.

Next, the structure of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment. In the second embodiment, another structure of a high-frequency, high-power semiconductor device including a MOS transistor will be described.

The high-frequency, high-power MOS transistor according to the second embodiment shown in FIG. 2 is the same as the first embodiment except for the connection structure between the source electrode 4 and the drain electrode 5, so that the same portion is used. The same reference numerals are given and the description is omitted. In the second embodiment, unlike the first embodiment, a connection electrode 18 used for connection to a circuit board (not shown) is formed on the drain electrode 5.

The high-frequency high-power MO configured as described above
The S transistor chip is connected to the circuit board using the connection electrode 18 with its main surface facing down. For example, if solder bumps are formed on the connection electrodes 18 and connected to pads having high heat dissipation provided on the circuit board, high mounting efficiency can be obtained, and at the same time, high performance is achieved because no parasitic inductance is generated at the connection portions. In addition, since heat can be directly radiated to the circuit board from the surface of the drain region 6 that generates heat particularly intensively in the MOS transistor, a highly reliable semiconductor device having excellent heat radiation properties can be obtained.

At this time, the source electrode 4 may be formed in a pattern in the same manner as, for example, the comb-like electrode 5 shown in FIG. The connection between the connection electrode 18 and the circuit board shown in FIG. 2 is not necessarily limited to the solder bump, and ball bonding, a via plug having excellent thermal conductivity, or the like can be used. Also in the second embodiment, since all the electrodes required for the operation of the MOS transistor are taken out from the main surface of the MOS transistor chip, the deep P ⁺ diffusion layer 9 shown in FIG. Therefore, the chip area can be reduced.

Next, the structure of the semiconductor device according to the third embodiment will be described with reference to FIG. FIG. 3 is a partially enlarged cross-sectional view for explaining the effect of reducing the drain junction capacitance. In the partially enlarged sectional view shown in FIG.
The N ⁺ drain region 6 formed in the 3, the drain junction depletion layer 20 extending outside from the N-type extended drain region 7 of low impurity concentration formed on both sides of the N ⁺ drain region 6 is shown. Other configurations are the same as those of the first and second embodiments shown in FIGS. 1 and 2, and therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted.

FIG. 4 shows the conventional semiconductor device shown in FIG. 6 in which a drain depletion layer 20 is added in a region corresponding to FIG. 3 for comparison with the third embodiment. The drain junction capacitance based on the drain depletion layer 20 is proportional to the drain junction area and inversely proportional to the thickness of the drain depletion layer 20. Therefore, as shown in FIG. 3, if the material constant and drain bias of the MOS transistor are set such that the tip of the drain depletion layer contacts the insulating substrate 14 such as sapphire, the effective drain depletion layer at the contact portion is set. Can be regarded as infinite, the junction capacitance at the bottom surface of the N ⁺ drain region 6 becomes zero.

As an example, the length of the N ⁺ drain region 6 is 2.5 μm, and the length of the N-type extended drain region 7 is 0.5 μm.
m, the drain junction capacitance of the MOS transistor shown in FIG. 3 is (0.5 ×
2) Since (0.5 × 2 + 2.5) = 1 / 3.5 times, the semiconductor device for high frequency and high power of the present invention can achieve a significant improvement in performance.

In the sectional structure shown in FIG. 3, if the thickness of the semiconductor layer 13 made of P ^- silicon is d, the thickness of the N ⁺ drain region 6 is d1, and the thickness of the depletion layer 20 is d2, the depletion layer D = d1 + d2 in a state where the tip of 20 has just reached the interface with the insulator substrate 14. However, the present invention is not limited to this case, and the MO is set so that the condition of d1 ≦ d ≦ d1 + d2 holds.
The same effect can be obtained even if the material constant and the bias condition of the S transistor are set.

Note that d <d1 may be satisfied if attention is paid only to the parasitic capacitance of the N ⁺ drain region 6, but under this condition, a low impurity formed to increase the withstand voltage between the drain and source of the MOS transistor. The electric field distribution in the vicinity of the N-type extended drain region 7 of the concentration changes, so that it is not possible to maintain a high drain withstand voltage required for a high-power semiconductor device. However, for applications of MOS transistors that do not require such a high drain breakdown voltage,
As d <d1, a larger drain parasitic capacitance reduction effect can be obtained.

The present invention is not limited to the above embodiment. In the first to third embodiments described above, the high-frequency high-power semiconductor device including a MOS transistor has been described, but the subject of the present invention is not necessarily limited to the MOS transistor. The present invention can be similarly applied to a field effect transistor composed of a MESFET. In addition, various modifications can be made without departing from the spirit of the present invention.

[0036]

As described above, according to the semiconductor device of the present invention, the parasitic capacitance of the drain region is smaller than that of the prior art,
In addition, it is possible to provide a high-frequency, high-power semiconductor device with a small chip area and excellent heat dissipation.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a drain parasitic capacitance reducing effect of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a state of generation of a drain depletion layer in a conventional semiconductor device.

FIG. 5 is a plan view showing a comb-like electrode pattern in a conventional semiconductor device.

FIG. 6 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

FIG. 7 is a sectional view showing another structure of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate electrode 2 ... Gate insulating film 3 ... Insulating film 4 ... Source electrode 5 ... Drain electrode 6 ... N ⁺ drain region 7 ... N-type extended drain region 8 ... N ⁺ source region 9 ... Deep P ⁺ diffusion layer 10 ... P ^- silicon epitaxial layer 11 ... P ⁺ silicon substrate 13 ... P ^- semiconductor layer 14 ... insulator substrate 15 ... interlayer insulation film 16 ... comb-shaped gate electrode 17, 18 ... connecting electrode 19 ... buried insulating film 20 ... drain depletion made of silicon layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F102 FA02 GB01 GC01 GD01 GJ10 GL03 GS09 5F110 AA02 AA04 AA30 BB12 CC02 DD04 EE24 EE37 GG02 GG12 GG42 HM04 HM12 HM15 HM17 HM19

Claims (4)

[Claims] A semiconductor layer formed on an insulating substrate; a plurality of source and drain regions formed in the semiconductor layer; and a gate insulating film interposed between the plurality of source and drain regions. A plurality of source and drain regions and the gate electrode are arranged in a longitudinal direction parallel to each other and sequentially along a direction perpendicular to the longitudinal direction. A source region and a drain region located between the one row of field effect transistors are shared between adjacent field effect transistors, and a gate electrode of the one row of field effect transistors is formed. Is the first
Are connected in parallel with each other by a comb-shaped electrode.
Are connected in parallel by the comb-shaped electrodes, and the drain region of the one-line field-effect transistor is connected to a wiring substrate facing the main surface of the semiconductor device via a connection electrode formed on the drain region. A semiconductor device which is individually connected. 2. The drain region of the one-row field-effect transistor is connected in parallel by a second comb-like electrode, and the source region of the one-row field-effect transistor is formed on the source region. Through the connection electrode,
2. The semiconductor device according to claim 1, wherein the semiconductor device is directly and individually connected to a wiring board facing a main surface of the semiconductor device. 3. The semiconductor device according to claim 1, wherein the drain region includes an extended drain region with a low impurity concentration extended toward the gate electrode. 4. The thickness d of the semiconductor layer is d1 ≦ d ≦, where d1 is the depth of the drain region and d2 is the thickness of a drain junction depletion layer when a drain bias is applied to the field effect transistor. The semiconductor device according to claim 1, wherein the value is set in a range of d1 + d2.