JP2002110889A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide packaging technique which reduces earth inductance and has excellent high-frequency characteristics. SOLUTION: This semiconductor device is constituted by electrically connecting a semiconductor chip mounted in a semiconductor chip mount area of a tab and a lead which is arranged as an external terminal at the periphery of the tab and exposed to outside the seal; and a bonding area of the tab and a pad for the power circuit of the semiconductor chip are electrically connected, part of the tab is exposed to outside the sealing body, and the exposed part of the tab is used as an external terminal for the semiconductor device. The exposed part of the tab is used as the external terminal for an earth power source, so a transmission line is made shorter than that of a conventional semiconductor device which uses a lead as an external terminal and its sectional area increases, so low inductance and low impedance can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique effective when applied to improvement of high frequency characteristics of a semiconductor device.

[0002]

2. Description of the Related Art Since a semiconductor device is relatively easy to manufacture and inexpensive, an SOP type semiconductor device is covered with a sealing body using a resin, and a lead extending from the sealing body is used as an external terminal. Semiconductor devices of SOJ type, QFP type and the like are widely used.

In these semiconductor devices of the QFP type and the like, the leads serving as external terminals of the semiconductor device extend from the side surfaces of the sealing body. Necessary around. Therefore, in order to reduce the area of the connection region around the semiconductor device and reduce the size of the electronic device, the bottom surface of the lead is exposed from the sealing body at the outer peripheral portion of the bottom surface of the sealing body, and the external terminals of the semiconductor device are A bottom terminal type semiconductor device was considered. As a bottom terminal type semiconductor device, QFN (Quad Flat Nonlead)
2. Description of the Related Art Semiconductor devices of a semiconductor device type or an SON (Small Outline Nonlead) type are known. Such a bottom terminal type semiconductor device is disclosed in, for example, JP-A-63-296252 or JP-A-9-162327.

A lead frame is used for assembling a semiconductor device such as the QFP type or the QFN type described above. A semiconductor chip is fixed to a tab with a resin or silver paste, and the pads of the semiconductor chip are bonded to the leads. They are electrically connected by wires. After this bonding, the semiconductor chip, the tab, and the bonding wire are sealed with a sealing body made of, for example, an epoxy resin, the dam bar and the tie bar are cut, each lead is separated mechanically and electrically, and the separated lead is The semiconductor device is completed by molding into a shape.

[0005]

In a semiconductor device, as typified by mobile communication such as a mobile phone, a rapid increase in the amount of information to be transmitted requires maintenance of a high-speed communication network. Higher speeds have been promoted, and semiconductor devices for processing such high-frequency signals are required to have improved high-frequency RF characteristics. For this reason, in a semiconductor device equipped with a semiconductor chip for processing a high-frequency signal, it is required that the packaging technology also has a structure that makes use of the high-frequency characteristics in the lead and the like serving as a transmission system between the semiconductor chip and the mounting substrate. Therefore, it is necessary to reduce the ground inductance.

An object of the present invention is to provide a packaging technique which reduces ground inductance and has good high frequency characteristics. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

In a semiconductor device in which a semiconductor chip mounted in a semiconductor chip mounting area of a tab and leads which are arranged around the tab and are exposed outside a sealing body and serve as external terminals are electrically connected, the bonding of the tab is performed. The region is electrically connected to a power supply circuit pad of the semiconductor chip, a part of the tab is exposed outside the sealing body, and the exposed part of the tab is used as a power supply external terminal of the semiconductor device.

In a semiconductor device in which a semiconductor chip mounted on a semiconductor chip mounting region of a tab and leads which are disposed around the tab and are exposed outside a sealing body and serve as external terminals are electrically connected, Electrically connecting the bonding area and the pad for ground power of the semiconductor chip, exposing the bottom surface of the tab from the bottom surface of the sealing body,
The exposed bottom surface of the tab is used as a ground power supply external terminal of the semiconductor device.

Further, in a method of manufacturing a semiconductor device for electrically connecting a semiconductor chip mounted on a semiconductor chip mounting area of a tab to a lead which is arranged around the tab and is exposed outside a sealing body and serves as an external terminal. Mounting a semiconductor chip in a semiconductor chip mounting region of a tab, bonding a pad of the semiconductor chip to a lead, bonding a ground power supply pad of the semiconductor chip to a bonding region of the tab, and Exposing the bottom surface of the tab to form a sealing body.

(Operation) Since the exposed portion of the tab is used as an external terminal for ground power, the transmission path is shortened and the cross-sectional area is increased as compared with a conventional semiconductor device using a lead as an external terminal. In addition, low inductance and low impedance can be achieved. Note that some conventional semiconductor devices have a tab on which a semiconductor chip is mounted exposed from a sealing body. However, these semiconductor devices only use the tab as a heat radiating plate. Only the characteristics are considered, but the high frequency characteristics are not considered.

[0012]

Embodiments of the present invention will be described below. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view showing a QFP type semiconductor device according to an embodiment of the present invention through a sealing body, taken along the line aa in FIG. FIG. 2 shows a vertical cross-sectional view as a substrate mounted state.

In the semiconductor device of the present embodiment, a semiconductor chip 1 in which a predetermined element is formed on a semiconductor substrate such as single crystal silicon is placed on a semiconductor chip mounting area 3a of a tub 3 by a bonding agent 2 such as resin or silver paste. The pads 1 a of the semiconductor chip 1 are fixed and the inner ends of the inner leads 4 a of the leads 4 are electrically connected by bonding wires 5. Ground pad 1a of power supply circuit of semiconductor chip 1
Is connected to the grounding lead 4, and the grounding pad 1 a and the bonding area 3 b of the tub 3 are connected in parallel by a bonding wire 5.

The semiconductor chip 1, the tab 3, the inner lead 4a of the lead 4, and the bonding wire 5 are part of the bottom surface of the tab 3 by a sealing body 6 using a sealing resin in which a filler is mixed into an epoxy resin, for example. Is exposed and sealed. The outer leads 4b of the leads 4 are exposed from the side surfaces of the sealing body 6, and the outer ends of the outer leads 4b are connected and fixed to the wiring board in a mounted state.

In the wiring board, the wiring layer 7 is formed on the surface or inside of a substrate 8 formed of a plate-like insulating material such as glass epoxy or mullite ceramic, and the wiring layer 7 formed on the uppermost layer is partially formed. The connection terminal 7a is connected to an outer lead 4b, which is an external terminal of the semiconductor device. In the mounted state, the connection terminal 7a is connected to the outer lead 4b.
And are connected by solder 9 as a bonding agent. And
In the semiconductor device of the present embodiment, the exposed portion of tab 3 exposed from sealing body 6 is used as an external terminal for ground power supply of the semiconductor device, and the bottom surface is joined to connection terminal 7b of wiring layer 7 at the ground potential. The connection is made by a solder 9 which is an agent.

As described above, since the exposed portion of the tab 3 is used as an external terminal for ground power, the transmission path is shortened and the cross-sectional area is reduced as compared with the conventional semiconductor device using the lead 4 as an external terminal. Because of the increase, it is possible to reduce the inductance and resistance of the ground transmission path,
It is possible to reduce the impedance by shortening the bonding wires. Thereby, the isolation characteristics are improved, and the RF characteristics are significantly improved.

Further, since the exposed portion of the tub 3 is used as an external terminal for the ground power supply, if only the problem of power supply is considered, the ground pad 1a of the power supply circuit of the semiconductor chip 1 is considered.
Need not be connected to the ground lead Vcc. However, the ground lead Vcc connected to the ground pad 1a
Is arranged adjacent to the input / output leads RFin and RFout of the high-frequency signal, whereby there is an advantage that the high-frequency signal can be stabilized. In addition, by providing the grounding lead Vcc, compatibility with the pin arrangement of the conventional semiconductor device can be provided. If these advantages are not required, it is possible to adopt a configuration in which the ground lead Vcc and the semiconductor chip 1 are not bonded and connected, and a configuration in which the number of pins is reduced without providing the ground lead Vcc. .

The resin of the sealing body 6 and the metal of the tab 3 or the lead 4 have different coefficients of thermal expansion. Even if the coefficient of thermal expansion is adjusted by using a filler or the like, the transient characteristics of thermal contraction / expansion cannot be changed, and the speed of contraction / expansion differs due to this difference. Then, a shift occurs at the interface between the resin and the metal. Since such a deviation increases as the distance from the center of the semiconductor device increases, in the bonding region 3b located at the periphery of the tub 3, the shearing stress acts on the bonding wire 5 due to the deviation, the bonding wire 5 comes off, and the conduction is interrupted. May be lost. Such a disconnection is not limited to the problem of power supply. For example, when a ground line provided adjacent to a high-frequency signal line is disconnected, the transmitted high-frequency signal is affected.

To prevent such a disconnection, FIG.
FIG. 4 is a partial plan view, and FIG. 4 is a longitudinal sectional view taken along line aa in FIG. 3, and a hole or a slit is formed between the bonding region of the shrinkable tub and the semiconductor chip mounting region. It is effective to provide a separating unit 10 as follows. Since the semiconductor chip mounting region 3a and the bonding region 3b are separated by the separating portion 10, the thermal stress in the semiconductor chip mounting region 3a is hardly transmitted to the bonding region 3b. In addition, the resin positioned above and below the tab 3 is integrated by the resin filled in the separation portion 10, and the bonding region 3b behaves together with the nearby resin. Since the generated displacement is small, a large shear stress is not applied to the bonding wire 5.

FIG. 5 is a plan view showing a modification of the embodiment of the present invention through a sealing body. In this example,
The grounding lead 4 is directly connected to the tab to be integrated. Therefore, bonding with the semiconductor chip 1 can be performed with one bonding wire. In this case, since the inner lead 4a is close to the tab 3, it may be difficult to raise the bonding area 3b. In such a case, it is possible to provide a notch in the tab 3 as shown in a partial plan view in FIG.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described. The semiconductor device of the present embodiment
A plurality of sets of tabs and leads integrated with a tie bar or a dam bar are continuously formed in a plurality of sets of tabs and leads used for individual semiconductor devices, and each lead frame is used. F
A plurality of signal leads 4 are arranged around the entire periphery of the tab 3 on which the semiconductor chip 1 is mounted, and are made of e-Ni-based alloy or Cu-based alloy. The tab 3 is provided between the leads 4. The tab 3 is supported on the frame by the tab suspension lead 11.

Then, the semiconductor chips 1 are fixed to the semiconductor chip mounting areas 3a of the respective tabs 3 of the lead frame with resin or silver paste.
The pad 1a electrode and the inner lead 4a are connected by a bonding wire 5, and the semiconductor chip 1 is mounted on a lead frame. Semiconductor chip 1 and inner lead 4
At the time of bonding with a, the ground power supply pad 1a of the semiconductor chip 1 and the bonding area 3b of the tub 3 are bonded.

Next, the semiconductor chip 1, the tab 3, the lead 4, and the bonding wire 5 are accommodated in a mold cavity in a lead frame on which the semiconductor chip 1 is mounted. 6 is formed. At this time, since the lower surface of the tab 3 is in close contact with the mold, the bottom surface of the tab 3 is exposed on the bottom surface of the sealing body 6 without attaching the sealing resin. Thereafter, the tie bar or the dam bar is cut, separated into individual semiconductor devices, and the outer lead 4b is formed into a gull wing or the like.

(Embodiment 2) FIG. 7 is a plan view showing a QFN type semiconductor device according to another embodiment of the present invention through a sealing body, taken along line aa in FIG. FIG. 8 shows the vertical cross-sectional view as a substrate mounted state.

In the semiconductor device of the present embodiment, a semiconductor chip 1 in which a predetermined element is formed on a semiconductor substrate such as single crystal silicon is placed on a semiconductor chip mounting area 3a of a tub 3 by a bonding agent 2 such as resin or silver paste. The pads 1 a of the semiconductor chip 1 are fixed and the inner ends of the inner leads 4 a of the leads 4 are electrically connected by bonding wires 5. Ground pad 1a of power supply circuit of semiconductor chip 1
Is connected to the grounding lead 4, and the grounding pad 1 a and the bonding area 3 b of the tub 3 are connected in parallel by a bonding wire 5.

The top surface and side surfaces of the semiconductor chip 1, the tab 3, the lead 4, and the bonding wire 5 are part of the bottom surface of the tab 3, for example, by a sealing body 6 using a sealing resin in which a filler is mixed into an epoxy resin. Then, the bottom surface of the lead 4 is exposed and sealed. In the mounted state, the bottom surface of the lead 4 is connected and fixed to the wiring board. In such a bottom terminal type semiconductor device, since a plurality of leads are provided on the bottom surface of a sealing body for sealing a semiconductor chip, when the semiconductor device is mounted on a wiring board, a connection region is formed around the semiconductor device. Since there is no need to provide, there is an advantage that the occupied area of the semiconductor device in the mounted state is reduced, and the surrounding space can be used effectively.

In the wiring board, the wiring layer 7 is formed on the surface or inside of a base 8 formed of a plate-like insulating material such as glass epoxy or mullite ceramic, and the wiring layer 7 formed on the uppermost layer is partially formed. And a connection terminal 7a with the bottom surface of the lead 4 which is an external terminal of the semiconductor device.
In the mounted state, the connection terminal 7a and the bottom surface of the lead 4 are connected by solder 9 as a bonding agent. In the semiconductor device of the present embodiment, the exposed portion of the tab 3 exposed from the sealing body 6 is used as an external terminal for ground power supply of the semiconductor device, and the bottom surface thereof is connected to the connection terminal 7b of the wiring layer 7 of the ground potential. Are connected by solder 9 as a bonding agent.

The bonding region 3b has its bottom surface removed by half etching, and a sealing body 6 is formed in this portion. This is because when the bottom surface of the bonding region 3b is exposed, the tab 3
This is to prevent the occurrence of a solder bridge in which the solder 9 connecting the lead 4 and the solder 9 connecting the adjacent leads 4 are integrated.

As described above, since the exposed portion of the tab 3 is used as an external terminal for ground power, the transmission path is shortened and the cross-sectional area is reduced as compared with the conventional semiconductor device using the lead 4 as an external terminal. Because of the increase, it is possible to reduce the inductance and resistance of the ground transmission path,
It is possible to reduce the impedance by shortening the bonding wires. Thereby, the isolation characteristics are improved, and the RF characteristics are significantly improved.

FIG. 9 shows a plan view through a sealing body, and FIG. 10 shows a vertical cross-sectional view taken along the line aa in FIG. The leads 4 are directly connected to the tabs to be integrated, and a part of the leads 4 is used as a bonding region 3b. Therefore, bonding with the semiconductor chip 1 can be performed with one bonding wire. In this case, the half space between the tab 3 and the lead 4 is half-etched. With this configuration, the above-described solder bridge is prevented and a function corresponding to the separating portion 10 of the above-described embodiment is exhibited. That is, the lead 4 is formed by the resin filled in the half-etched portion.
The resin located above the lead 4 is integrated with the lead 4 and behaves together with the resin in the vicinity, and the displacement generated between the resin and the bonding region 3b of the lead 4 is reduced. No stress is applied.

FIG. 9 is a plan view showing a transparent structure through a sealing body, and FIG. 10 is a vertical sectional view taken along the line aa in FIG. As in the example, the peripheral portion of the normal tab 3 can be implemented as the bonding region 3b. A conventional lead frame can be used as it is, and the present invention can be easily implemented.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, in the above description, the case where the invention made mainly by the present inventor is applied to a QFP type or QFN type semiconductor device, which is the field of application as the background, has been described. Not
The present invention can be widely applied to other types of surface mount semiconductor devices.

[0035]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, since the transmission path is shortened and its cross-sectional area increases, the low inductance and
There is an effect that the resistance can be reduced. (2) According to the present invention, there is an effect that the impedance can be reduced by shortening the bonding wire. (3) According to the present invention, the effects (1) and (2)
There is an effect that the isolation characteristics are improved. (4) According to the present invention, according to the effects (2) and (1),
There is an effect that the RF characteristics are significantly improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view taken along the line aa in FIG.

FIG. 3 is a partial plan view showing a separation unit of the embodiment.

FIG. 4 is a longitudinal sectional view taken along line aa in FIG.

FIG. 5 is a plan view showing a modification of the embodiment of the present invention.

FIG. 6 is a partial plan view showing a step-up portion of the present example.

FIG. 7 is a plan view showing a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a longitudinal sectional view taken along the line aa in FIG. 7;

FIG. 9 is a plan view showing a semiconductor device which is a modification of another embodiment of the present invention.

FIG. 10 is a longitudinal sectional view taken along the line aa in FIG. 9;

FIG. 11 is a longitudinal sectional view showing a modification of the semiconductor device according to the embodiment of the present invention;

FIG. 12 is a longitudinal sectional view taken along the line aa in FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Bonding agent, 3 ... Tab, 3a ... Semiconductor chip mounting area, 3b ... Bonding area, 4 ... Lead, 4a ... Inner lead, 4b ... Outer lead, 5
... bonding wire, 6 ... sealing body, 7 ... wiring layer, 8 ...
Substrate, 9 solder, 10 separation part, 11 tab suspension lead.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shun Imai 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Co., Ltd. F-term (reference) 4M109 AA01 BA01 CA21 DA04 DA10 FA00 5F044 AA01 AA11 5F067 AA00 AB02 BC13 BD00

Claims (5)

[Claims] 1. A semiconductor device in which a semiconductor chip mounted on a semiconductor chip mounting area of a tab and a lead disposed around the tab and exposed to the outside of a sealing body and serving as an external terminal are electrically connected. Electrically connecting the bonding area of the semiconductor chip to a power supply circuit pad of the semiconductor chip, exposing a part of the tab outside the sealing body, and making the exposed part of the tab a power supply external terminal of the semiconductor device. A semiconductor device characterized by the above-mentioned. 2. A semiconductor device in which a semiconductor chip mounted on a semiconductor chip mounting area of a tab and leads which are arranged around the tab and are exposed outside a sealing body and serve as external terminals are electrically connected, wherein the tab is provided. Is electrically connected to the ground power supply pad of the semiconductor chip, the bottom surface of the tab is exposed from the bottom surface of the sealing body, and the exposed bottom surface of the tab is connected to the ground power supply of the semiconductor device. A semiconductor device having external terminals. 3. The height of the bonding area of the tab is:
It is different from the height of the semiconductor chip mounting area of the tab,
3. The semiconductor device according to claim 1, wherein the height of the semiconductor device is close to a height of a pad of the semiconductor chip. 4. The semiconductor device according to claim 1, wherein a hole or a slit is provided between the bonding area of the tab and the semiconductor chip mounting area. 5. A method of manufacturing a semiconductor device for electrically connecting a semiconductor chip mounted on a semiconductor chip mounting region of a tab to a lead which is disposed around the tab and is exposed outside a sealing body and serves as an external terminal. Mounting a semiconductor chip in a semiconductor chip mounting region of the tab; bonding pads and leads of the semiconductor chip; bonding a ground power supply pad of the semiconductor chip to a bonding region of the tab; Exposing the bottom surface of the tab to form a sealing body.