JP2002100707A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2002100707A JP2002100707A JP2000288377A JP2000288377A JP2002100707A JP 2002100707 A JP2002100707 A JP 2002100707A JP 2000288377 A JP2000288377 A JP 2000288377A JP 2000288377 A JP2000288377 A JP 2000288377A JP 2002100707 A JP2002100707 A JP 2002100707A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- sealing resin
- semiconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子が搭載さ
れた基板の上面が封止樹脂で封止され、基板底面にボー
ル電極が付設されたボールグリッドアレイ（ＢＧＡ）タ
イプの半導体装置およびその製造方法に関するものであ
り、特に実装基板等への二次実装時の信頼性を高めた半
導体装置およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array (BGA) type semiconductor device in which a top surface of a substrate on which a semiconductor element is mounted is sealed with a sealing resin and ball electrodes are provided on the bottom surface of the substrate, and its manufacture. The present invention relates to a method, and more particularly, to a semiconductor device having improved reliability at the time of secondary mounting on a mounting board or the like and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】エリアアレイタイプの半導体装置とし
て、半導体素子が搭載された基板の上面が封止樹脂で封
止され、基板底面にボール電極が付設されたＢＧＡタイ
プの半導体装置がある。2. Description of the Related Art As an area array type semiconductor device, there is a BGA type semiconductor device in which an upper surface of a substrate on which a semiconductor element is mounted is sealed with a sealing resin and a ball electrode is provided on a bottom surface of the substrate.
【０００３】以下、従来の半導体装置について図面を参
照しながら説明する。図９，図１０，図１１は従来の半
導体装置として、ＢＧＡ型の半導体装置を示す図であ
り、図９は平面図、図１０は底面図、図１１は図９のＡ
−Ａ１箇所，図１０のＢ−Ｂ１箇所の断面図である。Hereinafter, a conventional semiconductor device will be described with reference to the drawings. 9, 10, and 11 are views showing a BGA type semiconductor device as a conventional semiconductor device. FIG. 9 is a plan view, FIG. 10 is a bottom view, and FIG.
FIG. 11 is a cross-sectional view taken along a line A- 1 and a line B-B 1 in FIG. 10.
【０００４】図９，図１０および図１１に示すように従
来の半導体装置は、上面に配線電極１を有し、底面にそ
の配線電極１と基板内部で電気的に接続したパッド電極
（図示せず）と、そのパッド電極上にボール電極２を有
した樹脂基板３と、樹脂基板３の上面のボンディング位
置に搭載された半導体素子４と、半導体素子４と樹脂基
板３の配線電極１とを電気的に接続した金属細線５と、
樹脂基板３の上面を封止した絶縁性の封止樹脂６とより
構成されたものである。従来の半導体装置において外形
形状としては、各側面は垂直な面を有し、全体として矩
形状をなしているものである。なおこの外形形状は製造
過程上の形状である。As shown in FIGS. 9, 10 and 11, a conventional semiconductor device has a wiring electrode 1 on an upper surface and a pad electrode (not shown) electrically connected to the wiring electrode 1 inside the substrate on a bottom surface. ), A resin substrate 3 having a ball electrode 2 on its pad electrode, a semiconductor element 4 mounted on a bonding position on the upper surface of the resin substrate 3, and a wiring electrode 1 of the semiconductor element 4 and the resin substrate 3. An electrically connected thin metal wire 5;
It is composed of an insulating sealing resin 6 which seals the upper surface of the resin substrate 3. In a conventional semiconductor device, the outer shape is such that each side surface has a vertical surface and is generally rectangular. This external shape is a shape in the manufacturing process.
【０００５】また従来の半導体装置において、樹脂基板
３に付設されたボール電極２は半田ボールであり、実装
基板への二次実装の際の高接続信頼性のために付設され
ている。またその配置においては樹脂基板３の底面に対
して格子状に配置されているものである。In the conventional semiconductor device, the ball electrode 2 provided on the resin substrate 3 is a solder ball, which is provided for high connection reliability at the time of secondary mounting on the mounting board. In this arrangement, they are arranged in a lattice with respect to the bottom surface of the resin substrate 3.
【０００６】次に従来の半導体装置の製造方法について
説明する。図１２〜図１５は従来の半導体装置の製造方
法を示す図であり、図１２（ａ）は平面図、図１２
（ｂ）は底面図であり、図１３，図１４，図１５は平面
図である。また図１４，図１５においては一部、内部構
造を透過した平面図としている。Next, a conventional method for manufacturing a semiconductor device will be described. 12 to 15 are views showing a conventional method of manufacturing a semiconductor device. FIG. 12 (a) is a plan view and FIG.
(B) is a bottom view, and FIGS. 13, 14, and 15 are plan views. 14 and 15 are plan views partially showing the internal structure.
【０００７】まず図１２（ａ），（ｂ）に示すように、
絶縁性樹脂より構成され、上面に複数の配線電極１を備
え、底面にその配線電極と基板内部で電気的に接続した
パッド電極７を備えた半導体素子搭載用の樹脂基板３を
用意する。パッド電極７は後工程でボール電極が付設さ
れる部分である。またここで用意する樹脂基板３は、１
枚の基板に複数の半導体素子を搭載し、その後で個々の
半導体装置に分割するための大型の基板を用意するもの
である。図１２中、破線で示した領域が個々の半導体装
置に分割される際の区切りラインである。また図１２
（ａ）において、各配線電極１で包囲された中央領域が
半導体素子を搭載するボンディング位置を構成するもの
である。First, as shown in FIGS. 12 (a) and 12 (b),
A resin substrate 3 for mounting a semiconductor element is prepared, which is made of an insulating resin, has a plurality of wiring electrodes 1 on an upper surface, and has pad electrodes 7 on the bottom surface which are electrically connected to the wiring electrodes inside the substrate. The pad electrode 7 is a portion where a ball electrode is attached in a later step. The resin substrate 3 prepared here is 1
A plurality of semiconductor elements are mounted on a single substrate, and then a large substrate is prepared for dividing into individual semiconductor devices. In FIG. 12, a region indicated by a broken line is a dividing line when the semiconductor device is divided into individual semiconductor devices. FIG.
2A, a central region surrounded by each wiring electrode 1 forms a bonding position for mounting a semiconductor element.
【０００８】次に図１３（ａ）に示すように、図１２に
示したような樹脂基板３を用意し、図１３（ｂ）に示す
ように、樹脂基板３の上面の各ボンディング位置に対し
て各々、半導体素子４を接着剤により接着固定して搭載
する。Next, as shown in FIG. 13A, a resin substrate 3 as shown in FIG. 12 is prepared, and as shown in FIG. Each of the semiconductor elements 4 is mounted by bonding with an adhesive.
【０００９】次に図１４（ａ）に示すように、樹脂基板
３上に搭載した半導体素子４の電極パッド（図示せず）
と樹脂基板３の上面に設けられた配線電極１とを金属細
線５により電気的に接続する。Next, as shown in FIG. 14A, electrode pads (not shown) of the semiconductor element 4 mounted on the resin substrate 3
And the wiring electrode 1 provided on the upper surface of the resin substrate 3 are electrically connected by the thin metal wires 5.
【００１０】そして図１４（ｂ）に示すように、樹脂基
板３の上面全面を封止樹脂６により封止する。この封止
樹脂６による上面封止はトランスファーモールドにより
行う。なお図１４（ｂ）においては配線電極１、半導体
素子４の各構成を透過した状態を破線で示しており、金
属細線は省略している。Then, as shown in FIG. 14B, the entire upper surface of the resin substrate 3 is sealed with a sealing resin 6. The top surface sealing with the sealing resin 6 is performed by transfer molding. In FIG. 14B, a broken line shows a state in which the components of the wiring electrode 1 and the semiconductor element 4 are transmitted, and a thin metal wire is omitted.
【００１１】そして図１５に示すように、上面が封止樹
脂６で全面封止された樹脂基板３に対して、回転ブレー
ドにより各半導体素子単位に切断することにより、個片
化された半導体装置８を得るものである。ここで得られ
た半導体装置の構造としては図９，図１０，図１１に示
した構造と同一であるため図示は省略する。Then, as shown in FIG. 15, the resin substrate 3 whose upper surface is entirely sealed with the sealing resin 6 is cut into individual semiconductor elements by a rotating blade to thereby separate the semiconductor device. 8 is obtained. The structure of the semiconductor device obtained here is the same as the structure shown in FIGS. 9, 10 and 11, and is not shown.
【００１２】ここで回転ブレードによる切断の際は、樹
脂基板３に設けた分割用の区切りラインに沿って切断す
ることにより、精度よく個片状の半導体装置を得ること
ができる。通常、この回転ブレードによる分割は、半導
体製造工程で用いられるダイシング設備によって行うも
のである。また個片に分割切断する際、基板の底面側か
ら切断する場合と、基板上面の封止樹脂６側から切断す
る場合とがある。Here, when cutting with a rotating blade, by cutting along a dividing line provided on the resin substrate 3, it is possible to obtain an individual semiconductor device with high accuracy. Usually, the division by the rotating blade is performed by a dicing facility used in a semiconductor manufacturing process. Further, when cutting into individual pieces, there are a case where the substrate is cut from the bottom surface side of the substrate and a case where it is cut from the sealing resin 6 side of the substrate upper surface.
【００１３】個片化した各半導体装置に対しては、後工
程として樹脂基板３の底面のパッド電極に半田ボールを
付設してボール電極を形成し、外部端子を構成する。For each of the individual semiconductor devices, a ball electrode is formed by attaching a solder ball to a pad electrode on the bottom surface of the resin substrate 3 as a later process to form an external terminal.
【００１４】以上のように従来は、複数個の半導体素子
を搭載可能な大型の基板を用いて、その基板に半導体素
子を搭載、電気的な接続、樹脂封止を行い、最終に一括
切断で個片に分離するという工程によりＢＧＡ型の半導
体装置を製造していた。As described above, conventionally, a large-sized substrate on which a plurality of semiconductor elements can be mounted is used, and the semiconductor elements are mounted on the substrate, electrical connection and resin sealing are performed. A BGA type semiconductor device has been manufactured by a process of separating into individual pieces.
【００１５】[0015]
【発明が解決しようとする課題】しかしながら前記従来
の半導体装置およびその製造方法では、複数個の半導体
素子を搭載可能な大型の基板を用いて、その基板に半導
体素子を搭載し、電気的な接続後、樹脂封止を行い、最
後に個片にブレード切断するという工程によりＢＧＡ型
の半導体装置を製造していたため、その製造上の特徴と
して、得られた半導体装置の外形形状が各側面が垂直な
面を有し、全体として扁平な直方体形状をなしているも
のであった。そのため半導体装置の各コーナー部分の４
箇所には角部が存在することとなる。この角部の存在に
より、半導体装置を実装基板へ実装する（二次実装）
際、ハンドリング如何によってはその角部の割れ、カケ
が発生する場合があり、二次実装時の信頼性低下が懸念
されていた。However, in the conventional semiconductor device and the method of manufacturing the same, a large-sized substrate on which a plurality of semiconductor elements can be mounted is used, and the semiconductor elements are mounted on the substrate and the electrical connection is made. After that, the BGA type semiconductor device was manufactured by a process of performing resin sealing and finally cutting blades into individual pieces, so that the outer shape of the obtained semiconductor device is such that each side surface is vertical. And had a flat rectangular parallelepiped shape as a whole. Therefore, 4
There will be corners at the locations. Due to the presence of this corner, the semiconductor device is mounted on the mounting board (secondary mounting)
At this time, depending on the handling, the corners may be cracked or chipped, and there is a concern that the reliability during secondary mounting may be reduced.
【００１６】本発明は製造効率の低下を招くことなく半
導体装置を製造するとともに、実装基板等への二次実装
時の信頼性を高めた半導体装置およびその製造方法を提
供することを目的とする。An object of the present invention is to provide a semiconductor device which manufactures a semiconductor device without lowering the manufacturing efficiency, and which has improved reliability at the time of secondary mounting on a mounting board or the like, and a method of manufacturing the same. .
【００１７】[0017]
【課題を解決するための手段】前記従来の課題を解決す
るために本発明の半導体装置は、上面に配線電極を有
し、底面に前記配線電極とその基板内部で電気的に接続
したパッド電極とを有した基板と、前記基板の上面に搭
載された半導体素子と、前記半導体素子と前記基板の前
記配線電極とを電気的に接続した接続手段と、前記基板
上の半導体素子領域を含む上面を封止した封止樹脂とよ
りなる半導体装置であって、少なくとも前記半導体装置
の各コーナー部分の４箇所の前記封止樹脂の上面部分が
その内側に曲面をなして凹んだ凹部形状を有するととも
に、前記封止樹脂の上面部分の各辺は斜辺を有している
半導体装置である。SUMMARY OF THE INVENTION In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention has a wiring electrode on an upper surface and a pad electrode electrically connected to the wiring electrode inside the substrate on a lower surface. A semiconductor element mounted on the upper surface of the substrate, a connection means for electrically connecting the semiconductor element and the wiring electrode of the substrate, and an upper surface including a semiconductor element region on the substrate A semiconductor device comprising a sealing resin that seals the semiconductor device, wherein at least four top surfaces of the sealing resin at each corner of the semiconductor device have a concave shape in which a curved surface is recessed inside. Each side of the upper surface portion of the sealing resin is a semiconductor device having an oblique side.
【００１８】具体的には、凹部形状は、その平面形状と
して円形の４分の１部分の形状をなしている半導体装置
である。More specifically, the concave shape is a semiconductor device having a planar shape of a quarter of a circle.
【００１９】また、基板底面のパッド電極にはボール電
極が設けられている半導体装置である。The present invention is a semiconductor device in which a ball electrode is provided on a pad electrode on the bottom surface of a substrate.
【００２０】前記構成の通り本発明の半導体装置は、半
導体装置の各コーナー部は凹部形状を有し、封止樹脂の
上面の各辺は斜辺を有しているので、半導体装置を実装
基板へ実装する（二次実装）際、そのコーナー部の割
れ、カケの発生を防止することができ、二次実装時の信
頼性低下を防止できるものである。特にコーナー部分の
封止樹脂の上面部分に対する衝撃による封止樹脂の割
れ、カケを防止できるものである。これにより、封止樹
脂の割れた欠片が実装基板上に残存して実装の妨げとな
ることを防止できる。As described above, in the semiconductor device of the present invention, each corner of the semiconductor device has a concave shape, and each side of the upper surface of the sealing resin has an oblique side. At the time of mounting (secondary mounting), it is possible to prevent cracks and chips from being generated at the corners, and to prevent a reduction in reliability at the time of secondary mounting. In particular, cracking and chipping of the sealing resin due to impact on the upper surface of the sealing resin at the corner portion can be prevented. Thus, it is possible to prevent the broken piece of the sealing resin from remaining on the mounting board and hindering the mounting.
【００２１】本発明の半導体装置の製造方法は、上面に
複数の配線電極を備え、底面に前記配線電極と基板内部
で電気的に接続した複数のパッド電極を備えた半導体素
子搭載用の基板を用意する工程と、前記基板の上面に対
して半導体素子を接着固定して搭載する工程と、前記基
板上に搭載した半導体素子と前記基板の上面の配線電極
とを電気的に接続する工程と、前記基板の上面領域の実
質的に全面を封止樹脂により封止する工程と、前記基板
の封止樹脂上の個々の半導体装置に分割する際の区切り
ラインの各交差点の中心点に対して凹部加工を施して封
止樹脂上に円形の凹部を形成するとともに、前記区切り
ラインに対して凹部加工を施して封止樹脂上に直線状の
凹部を形成する工程と、区切りラインおよび区切りライ
ンの各交差点に凹部形状が形成された基板に対して、前
記区切りラインで回転ブレードにより切断し、個片化し
た半導体装置を得る工程とよりなる半導体装置の製造方
法である。According to the method of manufacturing a semiconductor device of the present invention, there is provided a semiconductor device mounting substrate provided with a plurality of wiring electrodes on an upper surface and a plurality of pad electrodes on a bottom surface electrically connected to the wiring electrodes inside the substrate. Preparing, mounting and mounting the semiconductor element on the upper surface of the substrate, and electrically connecting the semiconductor element mounted on the substrate and the wiring electrode on the upper surface of the substrate, A step of sealing a substantially entire surface of the upper surface region of the substrate with a sealing resin, and a concave portion with respect to a center point of each intersection of a dividing line when dividing into individual semiconductor devices on the sealing resin of the substrate. A step of forming a circular concave portion on the sealing resin by performing processing, and forming a linear concave portion on the sealing resin by performing a concave portion processing on the partition line, and each of the partition line and the partition line. Concave at the intersection The substrate having the shape is formed, the cut with rotating blades delimited lines, a method of manufacturing a more becomes a semiconductor device and to obtain a semiconductor device singulation.
【００２２】具体的には、区切りラインおよび区切りラ
インの各交差点に凹部形状が形成された基板に対して、
前記区切りラインで回転ブレードにより切断し、個片化
した半導体装置を得る工程は、前記凹部の幅よりも小さ
い幅のブレードを用いて切断する半導体装置の製造方法
である。More specifically, for a substrate in which a concave shape is formed at each intersection of the dividing line and the dividing line,
The step of cutting the semiconductor device into individual pieces by cutting it with a rotating blade at the dividing line is a method of manufacturing a semiconductor device that uses a blade having a width smaller than the width of the concave portion.
【００２３】また、半導体装置に個片化する前に基板の
底面のパッド電極にボール電極を付設する工程を有する
半導体装置の製造方法である。Further, the present invention is a method of manufacturing a semiconductor device, comprising a step of attaching a ball electrode to a pad electrode on the bottom surface of a substrate before singulating the semiconductor device.
【００２４】また、用意する基板は１枚の基板上に複数
の半導体素子が搭載でき、個々の半導体装置に分割する
ことができる基板である半導体装置の製造方法である。Further, the present invention is a method for manufacturing a semiconductor device which is a substrate on which a plurality of semiconductor elements can be mounted on one substrate and which can be divided into individual semiconductor devices.
【００２５】前記構成の通り本発明の半導体装置の製造
方法は、複数個の半導体素子を搭載可能な大型の基板を
用いて、最終的に一括切断で個片の半導体装置に分離す
るという工程を用いた場合でも、半導体装置の各コーナ
ー部分の４箇所に対してその内側に曲面をなして凹んだ
凹部形状を有したＢＧＡ型の半導体装置を効率よく製造
できるものである。さらに直線上の凹部を切断すること
により、半導体装置が個片となった際、封止樹脂の上面
部分の各辺に斜辺を形成できるものである。As described above, the method of manufacturing a semiconductor device according to the present invention includes a step of using a large substrate on which a plurality of semiconductor elements can be mounted and finally separating the semiconductor device into individual semiconductor devices by batch cutting. Even when the semiconductor device is used, a BGA-type semiconductor device having a concave shape concaved with a curved surface inside four corner portions of the semiconductor device can be manufactured efficiently. Further, by cutting the concave portion on the straight line, when the semiconductor device is individualized, oblique sides can be formed on each side of the upper surface portion of the sealing resin.
【００２６】[0026]
【発明の実施の形態】以下、本発明の半導体装置および
その製造方法の一実施形態について、図面を参照しなが
ら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.
【００２７】まず本発明の半導体装置の一実施形態につ
いて説明する。First, one embodiment of the semiconductor device of the present invention will be described.
【００２８】本実施形態の半導体装置は基本構成とし
て、その上面に複数の半導体素子が搭載され、その上面
の全面が封止樹脂で一括封止された樹脂基板に対して、
個々の半導体装置単位に切断して形成された半導体装置
である。The semiconductor device according to the present embodiment has a basic configuration in which a plurality of semiconductor elements are mounted on the upper surface, and the entire upper surface of the resin substrate is collectively sealed with a sealing resin.
This is a semiconductor device formed by cutting into individual semiconductor device units.
【００２９】図１，図２，図３および図４は本実施形態
の半導体装置を示す図であり、図１は平面図、図２は底
面図、図３は図１のＣ−Ｃ１箇所，図２のＤ−Ｄ１箇所
の断面図、図４は図１のＥ−Ｅ１箇所，図２のＦ−Ｆ１
箇所の断面図である。FIGS. 1, 2, 3 and 4 are views showing a semiconductor device according to the present embodiment. FIG. 1 is a plan view, FIG. 2 is a bottom view, and FIG. FIG. 4 is a sectional view taken along a line D-D1 in FIG. 2, and FIG. 4 is a sectional view taken along a line E-E1 in FIG.
It is sectional drawing of a location.
【００３０】図１，図２，図３および図４に示すよう
に、本実施形態の半導体装置は、上面に配線電極１を有
し、底面にその配線電極１と基板内部で電気的に接続し
たパッド電極（図示せず）と、そのパッド電極上にボー
ル電極２を有した樹脂基板３と、樹脂基板３の上面のボ
ンディング位置に搭載された半導体素子４と、半導体素
子４と樹脂基板３の配線電極１とを電気的に接続した金
属細線５と、樹脂基板３の上面を封止したエポキシ樹脂
等の絶縁性の封止樹脂６とより構成されたものである。As shown in FIGS. 1, 2, 3 and 4, the semiconductor device of this embodiment has a wiring electrode 1 on the upper surface and is electrically connected to the wiring electrode 1 on the bottom inside the substrate. Pad electrode (not shown), a resin substrate 3 having a ball electrode 2 on the pad electrode, a semiconductor element 4 mounted on a bonding position on the upper surface of the resin substrate 3, a semiconductor element 4 and a resin substrate 3 And a thin metal wire 5 electrically connected to the wiring electrode 1 and an insulating sealing resin 6 such as an epoxy resin sealing the upper surface of the resin substrate 3.
【００３１】ここで本実施形態の半導体装置は、半導体
装置の各コーナー部分の４箇所は、その上面，下面部分
がその内側に曲面をなして凹んだ凹部形状９を有し、封
止樹脂６の上面部分の各辺は斜辺１０を有しているもの
である。また凹部形状９の具体的な形状としては、平面
形状として円形の４分の１部分の形状をなし、断面形状
として曲面を有した凹状の形状をなしている。このコー
ナー部の凹部形状９の構造により角部が除去され、かつ
曲面を有してくぼんでいるので、半導体装置を実装基板
へ実装する（二次実装）際、そのコーナー部の割れ、カ
ケの発生を防止することができ、二次実装時の信頼性低
下を防止できるものである。特に凹部形状９は曲面を有
して内側に凹んだ凹状の形状をなしているので、ベベル
形状に比べてより外部からの衝撃に対して耐性を有し、
封止樹脂６の上面部分に対する衝撃による封止樹脂６の
割れ、カケを防止できるものである。したがって封止樹
脂６の割れた欠片が実装基板上に残存して実装の妨げと
なることを防止できる。さらに封止樹脂６の上面の各辺
が曲面をなして内側に凹んだ斜辺１０を有しているた
め、各辺部分の封止樹脂の割れ、カケも防止できるもの
である。Here, in the semiconductor device of this embodiment, the four corner portions of the semiconductor device have concave portions 9 in which the upper surface and the lower surface are curved inside and are recessed. Each side of the upper surface portion has a hypotenuse 10. Further, as the specific shape of the concave shape 9, the planar shape is a circular quarter shape, and the sectional shape is a concave shape having a curved surface. Since the corner portion is removed by the structure of the concave portion 9 at the corner portion and is concave with a curved surface, when the semiconductor device is mounted on the mounting substrate (secondary mounting), the corner portion is cracked and chipped. It is possible to prevent occurrence of the occurrence and prevent a decrease in reliability at the time of secondary mounting. In particular, since the concave shape 9 has a concave shape having a curved surface and concave inward, the concave shape 9 is more resistant to external impact than a bevel shape,
It is possible to prevent cracking and chipping of the sealing resin 6 due to impact on the upper surface of the sealing resin 6. Therefore, it is possible to prevent the broken pieces of the sealing resin 6 from remaining on the mounting substrate and hindering the mounting. Further, since each side of the upper surface of the sealing resin 6 has the inclined side 10 which is curved and is depressed inward, cracking and chipping of the sealing resin on each side can be prevented.
【００３２】また本実施形態の半導体装置において、樹
脂基板３に付設されたボール電極２は半田ボールであ
り、実装基板への二次実装の際の高接続信頼性のために
付設されている。またその配置においては樹脂基板３の
底面に対して格子状に配置されているものである。In the semiconductor device of this embodiment, the ball electrode 2 provided on the resin substrate 3 is a solder ball, which is provided for high connection reliability at the time of secondary mounting on the mounting board. In this arrangement, they are arranged in a lattice with respect to the bottom surface of the resin substrate 3.
【００３３】本実施形態の半導体装置において、実施形
態では半導体装置の各コーナー部分の４箇所として、上
面側の封止樹脂６のコーナー部と、底面側の樹脂基板３
のコーナー部に内側に曲面をなして凹んだ凹部形状９を
有しているが、上面側の封止樹脂６のコーナー部にのみ
凹部形状９を形成してもよく、また底面側の樹脂基板３
のコーナー部にのみ凹部形状９を形成してもよい。In the semiconductor device of this embodiment, in the embodiment, the corner portion of the sealing resin 6 on the top surface and the resin substrate 3
Has a concave shape 9 depressed with a curved surface inward at the corner portion, but the concave shape 9 may be formed only at the corner portion of the sealing resin 6 on the upper surface side. 3
The concave shape 9 may be formed only at the corners of.
【００３４】次に本発明の半導体装置の製造方法の一実
施形態について説明する。図５〜図８は本実施形態の半
導体装置の製造方法を示す図であり、図５（ａ）は平面
図、図５（ｂ）は底面図であり、図６，図７，図８は平
面図である。また図７，図８においては一部、内部構造
を透過した平面図としている。Next, one embodiment of a method of manufacturing a semiconductor device according to the present invention will be described. 5 to 8 are views showing a method of manufacturing the semiconductor device according to the present embodiment. FIG. 5 (a) is a plan view, FIG. 5 (b) is a bottom view, and FIGS. It is a top view. 7 and 8 are plan views partially showing the internal structure.
【００３５】まず図５（ａ），（ｂ）を参照して本実施
形態で用いる樹脂基板について説明する。図５に示すよ
うに、絶縁性樹脂より構成され、上面に複数の配線電極
１を備え、底面にその配線電極と基板内部で電気的に接
続したパッド電極７を備えた半導体素子搭載用の樹脂基
板３を用意する。パッド電極７は後工程でボール電極が
付設される部分である。またここで用意する樹脂基板３
は、１枚の基板に複数の半導体素子を搭載し、その後で
個々の半導体装置に分割することができる大型の基板を
用意するものである。図５中、破線で示した領域が個々
の半導体装置に分割される際の区切りラインである。ま
た図５（ａ）において、各配線電極１で包囲された中央
領域が半導体素子を搭載するボンディング位置を構成す
るものである。First, the resin substrate used in this embodiment will be described with reference to FIGS. 5 (a) and 5 (b). As shown in FIG. 5, a semiconductor element mounting resin comprising an insulating resin, having a plurality of wiring electrodes 1 on the upper surface, and pad electrodes 7 electrically connected to the wiring electrodes on the bottom surface inside the substrate. A substrate 3 is prepared. The pad electrode 7 is a portion where a ball electrode is attached in a later step. Also, the resin substrate 3 prepared here
A large-sized substrate is prepared in which a plurality of semiconductor elements are mounted on one substrate and then divided into individual semiconductor devices. In FIG. 5, a region indicated by a broken line is a dividing line when divided into individual semiconductor devices. In FIG. 5A, a central region surrounded by each wiring electrode 1 forms a bonding position for mounting a semiconductor element.
【００３６】本実施形態の半導体装置の製造方法として
は、まず図６（ａ）に示すように、図５に示したような
樹脂基板３を用意し、図６（ｂ）に示すように、樹脂基
板３の上面の各ボンディング位置に対して各々、半導体
素子４をその上面側を上にして接着剤により接着固定し
て搭載する。また半導体素子４の基板搭載については、
基板に対してフリップチップ実装でもよい。As shown in FIG. 6A, a method of manufacturing a semiconductor device according to the present embodiment is as follows. First, a resin substrate 3 as shown in FIG. 5 is prepared, and as shown in FIG. At each bonding position on the upper surface of the resin substrate 3, the semiconductor element 4 is mounted by bonding with an adhesive with the upper surface side up. Regarding the mounting of the semiconductor element 4 on the substrate,
Flip chip mounting on the substrate may be used.
【００３７】次に図７（ａ）に示すように、樹脂基板３
上に搭載した半導体素子４の電極パッド（図示せず）と
樹脂基板３の上面に設けられた配線電極１とを金属細線
５により電気的に接続する。なお本実施形態では前述の
通り、半導体素子４をその主面を上にして基板に搭載し
た構造により、金属細線５による電気的接続手段を示し
ているが、半導体素子をフェースダウンにより基板に対
してフリップチップ実装した場合はバンプによる接続手
段となるため金属細線の使用はない。Next, as shown in FIG.
The electrode pads (not shown) of the semiconductor element 4 mounted thereon and the wiring electrodes 1 provided on the upper surface of the resin substrate 3 are electrically connected by the thin metal wires 5. In this embodiment, as described above, the semiconductor element 4 is mounted on the substrate with its main surface facing upward, and the electrical connection means using the thin metal wires 5 is shown. When flip-chip mounting is used, there is no need to use a thin metal wire because the connection means is provided by bumps.
【００３８】そして図７（ｂ）に示すように、樹脂基板
３の上面領域の全面を封止樹脂６により封止する。この
封止樹脂６による上面封止はトランスファーモールドに
より行うもので、樹脂基板３の搬送部分等のマージン領
域を除いた実質的な全面を封止するものである。なお図
７（ｂ）においては配線電極１、半導体素子４の各構成
を透過した状態を破線で示しており、金属細線は省略し
ている。Then, as shown in FIG. 7B, the entire upper surface region of the resin substrate 3 is sealed with the sealing resin 6. The upper surface sealing by the sealing resin 6 is performed by transfer molding, and seals substantially the entire surface of the resin substrate 3 excluding a margin area such as a transfer portion. In FIG. 7 (b), the broken lines show the state of transmission through the respective components of the wiring electrode 1 and the semiconductor element 4, and the thin metal wires are omitted.
【００３９】次に図８（ａ）に示すように、上面を封止
樹脂６で全面封止した樹脂基板３に対して、その樹脂基
板３の封止樹脂６上の個々の半導体装置に分割する際の
区切りラインの各交差点の中心点に凹部加工を施す。こ
の凹部加工は樹脂基板３の上面の封止樹脂６の面に対し
て行うもので、レーザー加工、エッチング加工、アッシ
ング加工により封止樹脂６を研削して円形の凹部形状を
形成するものである。図８（ａ）中、円形で示した部分
が凹部加工を施す領域である。また樹脂基板３上の区切
りラインの端部にも凹部加工を施すものである。ここで
封止樹脂６に対する凹部加工により、その厚み方向の形
状は加工精度の関係上、曲面を有した形状となる。また
図示はしていないが、樹脂基板３の底面側の個々の半導
体装置に分割する際の区切りラインの各交差点の中心点
に対しても凹部加工を施すものである。これにより封止
樹脂６側、樹脂基板３側に凹部形状を形成できる。もち
ろん前述の通り、封止樹脂６側、樹脂基板３側のいずれ
か一方の側にのみ凹部加工を施して凹部形状を形成して
もよい。さらに区切りライン上にも凹部加工を施して封
止樹脂６上に直線状の凹部形状を形成する。直線状の凹
部の断面形状としては、曲面をなして凹んだＵ字型が好
ましい。なお、封止樹脂６の面上の半導体装置ごとの区
切りラインについては、区切り目印、例えばけがき線や
凹凸を封止樹脂６上に予め形成しておいてもよいし、赤
外線で区切り領域を認識してもよい。Next, as shown in FIG. 8A, the resin substrate 3 whose upper surface is entirely sealed with the sealing resin 6 is divided into individual semiconductor devices on the sealing resin 6 of the resin substrate 3. The center point of each intersection of the dividing line is subjected to concave processing. This recess processing is performed on the surface of the sealing resin 6 on the upper surface of the resin substrate 3, and the sealing resin 6 is ground by laser processing, etching processing, and ashing processing to form a circular concave shape. . In FIG. 8A, a portion indicated by a circle is a region where the concave portion processing is performed. Also, the end of the dividing line on the resin substrate 3 is subjected to concave processing. Here, due to the processing of the concave portion on the sealing resin 6, the shape in the thickness direction becomes a shape having a curved surface due to processing accuracy. Although not shown, a concave portion is also formed on the center point of each intersection of the dividing lines when dividing into individual semiconductor devices on the bottom surface side of the resin substrate 3. Thereby, concave portions can be formed on the sealing resin 6 side and the resin substrate 3 side. Of course, as described above, only one of the sealing resin 6 side and the resin substrate 3 side may be subjected to concave processing to form a concave shape. Further, a concave portion is formed on the dividing line to form a linear concave shape on the sealing resin 6. As the cross-sectional shape of the linear concave portion, a U-shaped concave shape having a curved surface is preferable. In addition, regarding the dividing line for each semiconductor device on the surface of the sealing resin 6, a dividing mark, for example, a scribe line or unevenness may be formed on the sealing resin 6 in advance, or the dividing region may be formed by infrared rays. You may recognize.
【００４０】そして図８（ｂ）に示すように、上面が封
止樹脂６で全面封止され、凹部加工が施された樹脂基板
３に対して、回転ブレードにより分割用の区切りライン
に沿って各半導体素子単位に切断することにより、個片
化された半導体装置１１を得るものである。区切りライ
ンで回転ブレードにより切断する際は、区切りラインに
形成された直線状の凹部の中心線に対して、直線状の凹
部の幅よりも小さい幅のブレードを用いて切断すること
により、切断した後は封止樹脂６に斜辺１０を形成する
ことができる。ここで得られた半導体装置の構造として
は図１，図２，図３，図４に示した構造と同一であり、
半導体装置１１の各コーナー部分の４箇所は、その上
面，下面部分がその内側に曲面をなして凹んだ凹部形状
９を有し、封止樹脂６の上面の各辺には斜辺１０を有し
ている。各半導体装置の凹部形状９の具体的な形状とし
ては、加工工程の形状を受けて平面形状として円形の４
分の１部分の形状をなし、断面形状として曲面を有した
凹状の形状をなしている。Then, as shown in FIG. 8B, the resin substrate 3 having the upper surface entirely sealed with the sealing resin 6 and subjected to the recess processing is rotated along the dividing line by the rotating blade. The individual semiconductor devices 11 are obtained by cutting the semiconductor devices into individual pieces. When cutting with a rotating blade at the dividing line, the cutting was performed by using a blade having a width smaller than the width of the linear concave portion with respect to the center line of the linear concave portion formed in the dividing line. Thereafter, the oblique side 10 can be formed in the sealing resin 6. The structure of the semiconductor device obtained here is the same as the structure shown in FIG. 1, FIG. 2, FIG. 3, and FIG.
Four corner portions of the semiconductor device 11 have concave portions 9 whose upper and lower portions are concavely curved inside, and have oblique sides 10 on each side of the upper surface of the sealing resin 6. ing. The specific shape of the concave shape 9 of each semiconductor device is a circular 4
It has a shape of a half part and has a concave shape having a curved surface as a cross-sectional shape.
【００４１】また回転ブレードによる切断の際は、樹脂
基板３に設けた分割用の区切りラインに沿って切断する
ことにより、精度よく個片状の半導体装置を得ることが
できる。通常、この回転ブレードによる分割は、半導体
製造工程で用いられるダイシング設備によって行うもの
である。また個片に分割切断する際、基板の底面側から
切断する場合と、基板上面の封止樹脂６側から切断する
場合とがあるが、本実施形態では樹脂基板３の底面側か
ら切断している。これにより樹脂基板を安定に保持した
状態で切断できる。In the case of cutting with a rotating blade, by cutting along a dividing line provided on the resin substrate 3, a semiconductor device in the form of an individual piece can be obtained with high accuracy. Usually, the division by the rotating blade is performed by a dicing facility used in a semiconductor manufacturing process. Further, when divided into individual pieces, there are a case where cutting is performed from the bottom side of the substrate and a case where cutting is performed from the sealing resin 6 side of the upper surface of the substrate. In the present embodiment, cutting is performed from the bottom side of the resin substrate 3. I have. Thereby, the resin substrate can be cut while being stably held.
【００４２】個片化した各半導体装置に対しては、後工
程として樹脂基板３の底面のパッド電極に半田ボールを
付設してボール電極を形成し、外部端子を構成する。ま
たは樹脂基板を切断して個片化した半導体装置を形成す
る前に、樹脂基板全体に対して、樹脂基板の底面のパッ
ド電極上にボール電極を１枚の基板単位で形成すること
により効率よくボール電極を形成できる。For each of the individual semiconductor devices, a solder ball is attached to a pad electrode on the bottom surface of the resin substrate 3 to form a ball electrode as a later process, thereby forming external terminals. Or, before forming a semiconductor device which is cut into individual pieces by cutting the resin substrate, the ball electrodes are formed on the pad electrodes on the bottom surface of the resin substrate in units of one substrate with respect to the entire resin substrate, so that the efficiency is improved. A ball electrode can be formed.
【００４３】以上のように本実施形態の半導体装置の製
造方法は、複数個の半導体素子を搭載可能な大型の基板
を用いて、最終的に一括切断で個片の半導体装置に分離
するという工程を用いた場合でも、半導体装置の各コー
ナー部分の４箇所に対してその内側に曲面をなして凹ん
だ凹部形状を有したＢＧＡ型の半導体装置を効率よく製
造できるものである。As described above, the method of manufacturing a semiconductor device according to the present embodiment uses a large substrate on which a plurality of semiconductor elements can be mounted, and finally separates the semiconductor devices into individual semiconductor devices by batch cutting. Even when the semiconductor device is used, it is possible to efficiently manufacture a BGA-type semiconductor device having a concave shape in which four corner portions of the semiconductor device are concavely curved inside.
【００４４】[0044]
【発明の効果】以上、実施形態で説明した通り、本発明
の半導体装置は、半導体装置の各コーナー部の凹部形状
および封止樹脂上部の各斜辺の構造により、半導体装置
を実装基板へ実装する（二次実装）際、そのコーナー部
分の割れ、カケの発生を防止することができ、二次実装
時の信頼性低下を防止できるものである。特に基板上面
コーナー部の封止樹脂部分に対する衝撃による封止樹脂
の割れ、カケを防止できるものである。したがって半導
体装置の特にコーナー部の封止樹脂の割れを防止し、割
れた欠片が実装基板上に残存して実装の妨げとなること
を防止できる。As described above, in the semiconductor device of the present invention, the semiconductor device is mounted on the mounting substrate by the concave shape of each corner and the structure of each oblique side above the sealing resin. At the time of (secondary mounting), it is possible to prevent cracks and chips from being generated at the corners, and it is possible to prevent a reduction in reliability at the time of secondary mounting. In particular, cracking and chipping of the sealing resin due to impact on the sealing resin portion at the corner of the upper surface of the substrate can be prevented. Therefore, cracking of the sealing resin, particularly at the corners of the semiconductor device, can be prevented, and broken pieces can be prevented from remaining on the mounting substrate and hindering mounting.
【００４５】また本発明の半導体装置の製造方法は、複
数個の半導体素子を搭載可能な大型の基板を用いて、最
終的に一括ブレード切断で個片の半導体装置に分離する
という工程を用いた場合でも、半導体装置の各コーナー
部分の４箇所に対してその内側に曲面をなして凹んだ凹
部形状と封止樹脂の上部に斜辺とを有した半導体装置を
効率よく製造できるものである。The method of manufacturing a semiconductor device according to the present invention uses a step of using a large substrate on which a plurality of semiconductor elements can be mounted and finally separating the semiconductor device into individual semiconductor devices by batch blade cutting. Even in this case, it is possible to efficiently manufacture a semiconductor device having a concave shape having a concave surface with a curved surface inside each of four corner portions of the semiconductor device and an oblique side above the sealing resin.
【図１】本発明の一実施形態の半導体装置を示す平面図FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態の半導体装置を示す底面図FIG. 2 is a bottom view showing the semiconductor device according to the embodiment of the present invention;
【図３】本発明の一実施形態の半導体装置を示す断面図FIG. 3 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図４】本発明の一実施形態の半導体装置を示す断面図FIG. 4 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図５】本発明の一実施形態の半導体装置の製造方法を
示す図FIG. 5 is a diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention;
【図６】本発明の一実施形態の半導体装置の製造方法を
示す平面図FIG. 6 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
【図７】本発明の一実施形態の半導体装置の製造方法を
示す平面図FIG. 7 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
【図８】本発明の一実施形態の半導体装置の製造方法を
示す平面図FIG. 8 is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図９】従来の半導体装置を示す平面図FIG. 9 is a plan view showing a conventional semiconductor device.
【図１０】従来の半導体装置を示す底面図FIG. 10 is a bottom view showing a conventional semiconductor device.
【図１１】従来の半導体装置を示す断面図FIG. 11 is a sectional view showing a conventional semiconductor device.
【図１２】従来の半導体装置の製造方法を示す図FIG. 12 is a diagram showing a conventional method of manufacturing a semiconductor device.
【図１３】従来の半導体装置の製造方法を示す平面図FIG. 13 is a plan view showing a conventional method for manufacturing a semiconductor device.
【図１４】従来の半導体装置の製造方法を示す平面図FIG. 14 is a plan view showing a conventional method for manufacturing a semiconductor device.
【図１５】従来の半導体装置の製造方法を示す平面図FIG. 15 is a plan view showing a conventional method for manufacturing a semiconductor device.
１ 配線電極 ２ ボール電極 ３ 樹脂基板 ４ 半導体素子 ５ 金属細線 ６ 封止樹脂 ７ パッド電極 ８ 半導体装置 ９ 凹部形状 １０ 斜辺 １１ 半導体装置 DESCRIPTION OF SYMBOLS 1 Wiring electrode 2 Ball electrode 3 Resin substrate 4 Semiconductor element 5 Fine metal wire 6 Sealing resin 7 Pad electrode 8 Semiconductor device 9 Concave shape 10 Oblique side 11 Semiconductor device
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/12 ５０１ Ｈ０１Ｌ 21/78 Ｑ 23/12 Ｃ (72)発明者 南尾 匡紀 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 福田 敏行 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 野村 徹 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 Ｆターム(参考） 4M109 AA01 BA03 CA21 DA03 DA07 DB15 DB16 5F061 AA01 BA03 CA21 CB13 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 501 H01L 21/78 Q23 / 12 C (72) Inventor Masanori Minao Masayuki Takatsuki, Osaka No. 1-1, Matsushita Electronics Industrial Co., Ltd. (72) Inventor Toshiyuki Fukuda 1-1, Yukicho, Takatsuki-shi, Osaka Pref. Matsushita Electronics Industrial Co., Ltd. (72) Toru Nomura 1-1, Yukicho, Takatsuki-shi, Osaka, Japan No. Matsushita Electronics Corporation F term (reference) 4M109 AA01 BA03 CA21 DA03 DA07 DB15 DB16 5F061 AA01 BA03 CA21 CB13
Claims (7)
電極とその基板内部で電気的に接続したパッド電極とを
有した基板と、前記基板の上面に搭載された半導体素子
と、前記半導体素子と前記基板の前記配線電極とを電気
的に接続した接続手段と、前記基板上の半導体素子領域
を含む上面を封止した封止樹脂とよりなる半導体装置で
あって、少なくとも前記半導体装置の各コーナー部分の
４箇所の前記封止樹脂の上面部分がその内側に曲面をな
して凹んだ凹部形状を有するとともに、前記封止樹脂の
上面部分の各辺は斜辺を有していることを特徴とする半
導体装置。A substrate having a wiring electrode on an upper surface, a pad electrode electrically connected inside the substrate and the wiring electrode on a bottom surface; a semiconductor element mounted on an upper surface of the substrate; A semiconductor device comprising: connecting means for electrically connecting a semiconductor element and the wiring electrode of the substrate; and a sealing resin sealing an upper surface including a semiconductor element region on the substrate, wherein at least the semiconductor device The upper surface portion of the sealing resin at each of the four corner portions has a concave shape in which the upper surface portion of the sealing resin is curved inside, and each side of the upper surface portion of the sealing resin has an oblique side. Characteristic semiconductor device.
４分の１部分の形状をなしていることを特徴とする請求
項１または請求項２に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the shape of the recess is a quarter of a circular shape as a planar shape.
設けられていることを特徴とする請求項１または請求項
２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein a ball electrode is provided on the pad electrode on the bottom surface of the substrate.
記配線電極と基板内部で電気的に接続した複数のパッド
電極を備えた半導体素子搭載用の基板を用意する工程
と、前記基板の上面に対して半導体素子を接着固定して
搭載する工程と、前記基板上に搭載した半導体素子と前
記基板の上面の配線電極とを電気的に接続する工程と、
前記基板の上面領域の実質的に全面を封止樹脂により封
止する工程と、前記基板の封止樹脂上の個々の半導体装
置に分割する際の区切りラインの各交差点の中心点に対
して凹部加工を施して封止樹脂上に円形の凹部を形成す
るとともに、前記区切りラインに対して凹部加工を施し
て封止樹脂上に直線状の凹部を形成する工程と、区切り
ラインおよび区切りラインの各交差点に凹部形状が形成
された基板に対して、前記区切りラインで回転ブレード
により切断し、個片化した半導体装置を得る工程とより
なることを特徴とする半導体装置の製造方法。4. A step of preparing a substrate for mounting a semiconductor element, comprising: a plurality of wiring electrodes on an upper surface; and a plurality of pad electrodes on a bottom surface, the plurality of pad electrodes being electrically connected to the wiring electrodes inside the substrate. A step of bonding and mounting the semiconductor element on the upper surface, and a step of electrically connecting the semiconductor element mounted on the substrate and the wiring electrode on the upper surface of the substrate;
A step of sealing a substantially entire surface of the upper surface region of the substrate with a sealing resin, and a concave portion with respect to a center point of each intersection of a dividing line when dividing into individual semiconductor devices on the sealing resin of the substrate. A step of forming a circular concave portion on the sealing resin by performing processing, and forming a linear concave portion on the sealing resin by performing a concave portion processing on the partition line, and each of the partition line and the partition line. A method of manufacturing a semiconductor device, comprising: a step of cutting a substrate having a concave shape at an intersection with a rotary blade at the separation line to obtain an individual semiconductor device.
差点に凹部形状が形成された基板に対して、前記区切り
ラインで回転ブレードにより切断し、個片化した半導体
装置を得る工程は、前記凹部の幅よりも小さい幅のブレ
ードを用いて切断することを特徴とする請求項４に記載
の半導体装置の製造方法。5. The step of cutting a dividing line and a substrate having a concave shape at each intersection of the dividing line by using a rotating blade at the dividing line to obtain an individual semiconductor device, comprising the steps of: 5. The method according to claim 4, wherein the cutting is performed using a blade having a smaller width.
のパッド電極にボール電極を付設する工程を有すること
を特徴とする請求項５に記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of attaching a ball electrode to a pad electrode on the bottom surface of the substrate before dividing into individual semiconductor devices.
導体素子が搭載でき、個々の半導体装置に分割すること
ができる基板であることを特徴とする請求項５に記載の
半導体装置の製造方法。7. The semiconductor device according to claim 5, wherein the prepared substrate is a substrate on which a plurality of semiconductor elements can be mounted on one substrate and which can be divided into individual semiconductor devices. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000288377A JP2002100707A (en) | 2000-09-22 | 2000-09-22 | Semiconductor device and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000288377A JP2002100707A (en) | 2000-09-22 | 2000-09-22 | Semiconductor device and manufacturing method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002100707A true JP2002100707A (en) | 2002-04-05 |
Family
ID=18771971
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000288377A Pending JP2002100707A (en) | 2000-09-22 | 2000-09-22 | Semiconductor device and manufacturing method therefor |
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| Country | Link |
|---|---|
| JP (1) | JP2002100707A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006078071A2 (en) * | 2005-01-24 | 2006-07-27 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor chips, and semiconductor chip |
| WO2006112423A1 (en) * | 2005-04-14 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor chips, and semiconductor chip |
| JP2009170476A (en) * | 2008-01-11 | 2009-07-30 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
| JP2010040689A (en) * | 2008-08-04 | 2010-02-18 | Taiyo Yuden Co Ltd | Circuit module and method of manufacturing circuit module |
| JP2010087055A (en) * | 2008-09-30 | 2010-04-15 | Panasonic Corp | Semiconductor package and semiconductor device |
| JP2013258286A (en) * | 2012-06-12 | 2013-12-26 | Shindengen Electric Mfg Co Ltd | Semiconductor wafer, semiconductor device manufacturing method and semiconductor device |
| JP2017163063A (en) * | 2016-03-11 | 2017-09-14 | 三菱電機株式会社 | Semiconductor wafer and manufacturing method for the same |
| WO2017179326A1 (en) * | 2016-04-11 | 2017-10-19 | 株式会社村田製作所 | Module |
-
2000
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006078071A3 (en) * | 2005-01-24 | 2006-09-14 | Matsushita Electric Ind Co Ltd | Manufacturing method for semiconductor chips, and semiconductor chip |
| WO2006078071A2 (en) * | 2005-01-24 | 2006-07-27 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor chips, and semiconductor chip |
| US8383436B2 (en) | 2005-01-24 | 2013-02-26 | Panasonic Corporation | Manufacturing method for semiconductor chips, and semiconductor chip |
| US8012805B2 (en) | 2005-04-14 | 2011-09-06 | Panasonic Corporation | Manufacturing method for semiconductor chips, and semiconductor chip |
| WO2006112423A1 (en) * | 2005-04-14 | 2006-10-26 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method for semiconductor chips, and semiconductor chip |
| JP2009170476A (en) * | 2008-01-11 | 2009-07-30 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
| JP2010040689A (en) * | 2008-08-04 | 2010-02-18 | Taiyo Yuden Co Ltd | Circuit module and method of manufacturing circuit module |
| JP2010087055A (en) * | 2008-09-30 | 2010-04-15 | Panasonic Corp | Semiconductor package and semiconductor device |
| JP2013258286A (en) * | 2012-06-12 | 2013-12-26 | Shindengen Electric Mfg Co Ltd | Semiconductor wafer, semiconductor device manufacturing method and semiconductor device |
| JP2017163063A (en) * | 2016-03-11 | 2017-09-14 | 三菱電機株式会社 | Semiconductor wafer and manufacturing method for the same |
| WO2017179326A1 (en) * | 2016-04-11 | 2017-10-19 | 株式会社村田製作所 | Module |
| JPWO2017179326A1 (en) * | 2016-04-11 | 2019-02-21 | 株式会社村田製作所 | module |
| US10872853B2 (en) | 2016-04-11 | 2020-12-22 | Murata Manufacturing Co., Ltd. | Module |
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