JP2002190604A - Thin-film transistor, liquid crystal display device using the thin-film transistor and electroluminescence display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor of high reliability where factors of instability that irregularity in threshold voltage, fluctuation in the threshold voltage, in voltage-applying test at a high temperatures, etc., are eliminated. SOLUTION: This thin-film transistor 10 is provided with a semiconductor thin film 13, which has a channel region 13a, and a source region 13b and a drain region 13c, which are formed on both sides of the channel region 13a, a gate insulating film 14 formed on the semiconductor thin film 13, and a gate electrode 15 which is formed on a position, corresponding to the channel region 13a on the gate insulating film 14. The respective concentrations of impurity elements existing in an interface between the semiconductor thin film 13 and the gate insulating film 14 are at most 3×1011 atoms/cm2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a liquid crystal display and an electroluminescence display using the same. More specifically, the present invention relates to a thin film transistor in which a change in threshold voltage is suppressed, a liquid crystal display device and an electroluminescence display device using the thin film transistor.

[0002]

2. Description of the Related Art Hitherto, active matrix liquid crystal display devices in which thin film transistors as pixel switching elements are formed on a substrate have been actively developed. Such a liquid crystal display device is used as a display unit of a device such as a mobile phone and a video camera.

In recent years, thin film transistors using polycrystalline silicon (polysilicon: p-Si) having higher field-effect mobility than amorphous silicon (amorphous silicon: a-Si) have been developed. .

A polycrystalline silicon thin film transistor used in a liquid crystal display device generally has a configuration as shown in FIG. FIG. 13 is a schematic diagram showing a configuration of a conventional thin film transistor.

An undercoat film 2 for preventing diffusion of impurities is formed on a glass substrate 1, and a polycrystalline silicon film 3 obtained by crystallizing an amorphous silicon film on the undercoat film 2 by laser annealing. Are provided as semiconductor layers.

[0006] A gate insulating film 4 is deposited so as to cover the polycrystalline silicon film 3, and a gate electrode 5 is provided on the gate insulating film 4.

Further, an interlayer insulating film 6 is deposited on the gate electrode 5, and the interlayer insulating film 6 and the gate insulating film 4 are formed.
The source electrode 7 and the drain electrode 8 formed on the interlayer insulating film 6 are connected to the source region 3b and the drain region 3c of the polycrystalline silicon film 3, respectively, through the contact holes formed in the above.

[0008]

However, in the above-mentioned conventional polycrystalline silicon thin film transistor, metal impurities (particularly, Na, K) are present at the interface between the channel region 3a of the polycrystalline silicon film 3 and the gate insulating film 4. (Such as alkali metals such as B, Al, etc., and heavy metals such as Fe, Cu, etc.), which cause unstable characteristics such as the threshold voltage of the transistor being fluctuated by the electric charge of these metals. Had become.

When the channel regions of these thin film transistors having poor characteristics were examined by SIMS (Secondary Ion Mass Spectroscopy), Mo, Cr, Fe, Ca, Ba, C, Na, K, Al, and B were found. And many other impurities were detected from the interface between the channel region and the gate insulating film.

Further, when a thin film transistor having good characteristics was similarly analyzed, it was found that the above-mentioned impurities existing at the interface between the channel region and the gate insulating film were small.

From the above analysis results, in the conventional polycrystalline silicon film forming process for crystallizing an amorphous silicon film by laser annealing, metal impurities attached to the surface of the amorphous silicon film were melted during laser annealing. The polycrystalline silicon film diffuses into the silicon film and contains metal impurities in the film. In the subsequent step of forming a gate insulating film, the surface of the polycrystalline silicon film is once exposed to air, so that metal impurities attached at that time remain at the interface between the polycrystalline silicon film and the gate insulating film. I found out.

It has been found that these impurities cause a transistor characteristic defect.

In the so-called semiconductor process, in order to prevent the contamination of the above-mentioned impurities which deteriorate the characteristics,
Comprehensive efforts to remove impurities such as the use of high-purity materials and clean equipment, the cleaning of chemicals, water and gas, and the removal of impurities in the environment have been successful.
Efforts have also been made to clean the thin film transistors used in liquid crystal display devices.

However, in the liquid crystal display device, since glass is used as a substrate, a substance contained in the glass is necessarily mixed into the thin film transistor as an impurity.

In particular, contamination tends to occur via the environment or a chemical solution at a break in a manufacturing process, and therefore, many impurities exist at the interface of the thin film transistor.

A large number of thin film transistors used in a liquid crystal display device are formed on a substrate, and impurities present at the interfaces between the constituent elements of the thin film transistors cause the threshold voltage of each thin film transistor to vary. Had become.

As means for preventing the above-mentioned contamination, a method of providing an impurity diffusion preventing film on the glass surface (for example, JP-A-09-167845) and a method of removing once-attached contamination by washing or etching (for example, JP-A-63-293981, JP-A-10-1169
No. 91), a method of performing continuous processing in a clean atmosphere without exposing the interface to the atmosphere (for example, Japanese Patent Application Laid-Open No.
Many methods have been proposed.

Although all of these methods have some effect in reducing pollution and are effective means, it is actually impossible to completely remove the contamination by any means.

That is, although some impurities remain on the interface as contamination, although the amount is small, it is necessary to determine an allowable amount of these impurities.

[0020]

Means for Solving the Problems The inventors of the present invention set forth the above section.
In order to solve the problem, the semiconductor
Of impurities present at the interface between the body thin film and the gate insulating film
And the relationship between the threshold voltage of thin film transistors
In addition, the concentration of each of the impurity elements is 3 × 10 ¹¹ato
ms / cm^TwoIf it is below, reduce the amount of change in the threshold voltage
I found what I could do. And the threshold voltage
Thin film transistors with small fluctuations in
When applied as an etching element, the thin film transistor
The variation in the threshold voltage of each
Liquid crystal display device with excellent display quality
You.

That is, according to a first aspect of the present invention, there is provided a semiconductor thin film having a channel region, a source region and a drain region formed on both sides of the channel region, and a gate formed on the semiconductor thin film. An insulating film, comprising a gate electrode formed at a position corresponding to the channel region on the gate insulating film, a thin film transistor formed on a substrate, the thin film transistor on the interface between the semiconductor thin film and the gate insulating film Has at least one impurity element, and the concentration of each of the impurity elements is 3 × 10 ¹¹ atoms / c.
m ² or less.

Here, the "interface" means a region extending from the surface where the semiconductor thin film and the gate insulating film are in contact with each other to a depth of 30 °. Further, in this specification, the “interface” between the semiconductor thin film and the substrate and the “interface” between the gate insulating film and the gate electrode are also used in the same meaning.

According to a second aspect of the present invention, there is provided a thin film transistor comprising a gate electrode, a gate insulating film provided on the gate electrode, and a semiconductor thin film provided on the gate insulating film. The concentration of each impurity element present at the interface between the semiconductor thin film and the gate insulating film is:
The characteristic is not more than 3 × 10 ¹¹ atoms / cm ² .

Thus, even with a bottom gate type thin film transistor, the same effect as the thin film transistor according to the first aspect can be achieved.

According to a third aspect of the present invention, there is provided the thin film transistor according to the first aspect, wherein at least one impurity element exists at an interface between the semiconductor thin film and the substrate, and a concentration of each of the impurity elements is determined. Is 3 × 10 ¹¹ atoms
s / cm ² or less.

According to a fourth aspect of the present invention, there is provided the thin film transistor according to the first aspect, wherein an impurity diffusion preventing film is formed on the substrate, and an interface between the semiconductor thin film and the impurity diffusion preventing film is formed. Has at least one impurity element, and the concentration of each of the impurity elements is 3 × 10 ¹¹
atoms / cm ² or less.

With the above structure, the variation in the threshold voltage can be reduced, and the variation in the threshold voltage can be suppressed. Therefore, a thin film transistor having better characteristics can be provided.

According to a fifth aspect of the present invention, there is provided the thin film transistor according to the third aspect, wherein at least one impurity element is present at an interface between the gate insulating film and the gate electrode. Is 3 × 10 ¹¹ a
toms / cm ² or less.

With the above-described structure, it is possible to suppress the fluctuation of the threshold voltage of the thin film transistor in the high-temperature voltage application test (so-called BT test).

According to a sixth aspect of the present invention, there is provided the thin film transistor according to the first aspect, wherein at least one impurity element exists at an interface between the semiconductor thin film and the gate insulating film. Is 1 × 10 ⁹ a
toms / cm ² or more.

With the above structure, the manufacturing process of the thin film transistor can be simplified as much as possible, and a thin film transistor having no change in threshold voltage can be provided.

The invention according to claim 7 is the thin film transistor according to claim 1, wherein the impurity element is an alkali metal and / or an alkaline earth metal.

The invention according to claim 8 is the thin film transistor according to claim 1 and the thin film transistor according to claim 3, wherein the substrate is a glass substrate having a strain point of 650 ° C. or less. The impurity element is an element except for Si and O among elements contained in the glass substrate.

According to a ninth aspect of the present invention, in the thin film transistor according to the fifth aspect, an interlayer insulating film is formed on the gate electrode, and the source region and the source region are formed on the interlayer insulating film. A source electrode and a drain electrode connected to a drain region are formed; the substrate is a glass substrate having a strain point of 650 ° C. or lower; and the impurity element is formed of the glass substrate, the gate electrode, the source electrode, and the drain. It is an element excluding Si and O among elements contained in the electrode.

According to the above configuration, even if impurities generated from the glass substrate or the electrode material are present at the interface, the characteristics of the thin film transistor are not deteriorated.

The invention according to claim 10 is the same as the invention according to claim 8.
The thin film transistor according to the above, wherein the impurity element is:
Na, K, Ca, Mg, Ba, B, Fe, Cu and Z
and at least one element selected from the group consisting of n.

The invention according to claim 11 is the invention according to claim 9
The thin film transistor according to the above, wherein the impurity element is:
Na, K, Ca, Mg, Ba, B, Al, Mo, Cr,
It is characterized by being at least one element selected from the group consisting of Fe, Cu and Zn.

The twelfth aspect of the present invention is the first aspect of the present invention.
The thin film transistor according to the above, wherein the semiconductor thin film is
It is a polycrystalline silicon film.

The invention according to claim 13 is the first invention.
The thin film transistor according to the above, wherein the semiconductor thin film is
It is a polycrystalline silicon film obtained by laser annealing a non-single-crystal silicon film.

In the above structure, when the semiconductor thin film is a polycrystalline silicon film, in particular, a polycrystalline silicon film obtained by laser annealing a non-single-crystal silicon film, the effect of the present invention is remarkably seen. be able to. Note that the non-single-crystal silicon means amorphous silicon and microcrystalline silicon.

According to a fourteenth aspect of the present invention, the first substrate, the second substrate disposed to face the first substrate, and the first substrate and the second substrate are connected to each other. A liquid crystal display device having a liquid crystal layer interposed therebetween, wherein the thin film transistor according to claim 1 and display electrodes connected to the thin film transistor are arranged in a matrix on the first substrate. It is characterized by the following.

According to the above configuration, since the characteristics of the individual thin film transistors constituting the transistor array are good, a liquid crystal display device having excellent display quality and reliability can be obtained.

According to a fifteenth aspect of the present invention, the first substrate, the second substrate opposed to the first substrate, and the first substrate and the second substrate are connected to each other. An electroluminescent display device having an electroluminescent material sandwiched therebetween, wherein the thin film transistor according to claim 1 and display electrodes connected to the thin film transistor are arranged in a matrix on the first substrate. It is characterized by becoming.

According to the above configuration, since the characteristics of the individual thin film transistors constituting the transistor array are good, an electroluminescent display device having excellent display quality and reliability can be obtained.

[0045]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a schematic diagram showing the structure of a thin film transistor according to Embodiment 1 of the present invention. FIG. 1 (a) is a schematic plan view of the thin film transistor, and FIG. FIG. 2 is a schematic sectional view taken along line AA ′ of FIG.

As shown in FIG. 1, an impurity diffusion preventing film 12 is formed on a glass substrate 11 as an insulating substrate, and a TFT 10 is formed on the impurity diffusion preventing film 12.

The impurity diffusion preventing film 12 is an insulating film made of, for example, silicon oxide or silicon nitride, and has a high density, and therefore has an excellent blocking effect of blocking impurities such as alkali metal elements and alkaline earth elements. I have.

The TFT 10 is a top gate type thin film transistor, and includes a semiconductor thin film 13 and a gate insulating film 1.
4, a gate electrode 15, and an interlayer insulating film 16 are sequentially laminated. Further, a source electrode 17 and a drain electrode 18 are provided on the interlayer insulating film 16.

The semiconductor thin film 13 includes a channel region 13
a, a source region 13b, and a drain region 13c, and is a semiconductor layer made of polycrystalline silicon patterned in a predetermined shape.

The source region 13b and the drain region 13c are located on both sides of the channel region 13a and are doped with impurity ions such as phosphorus. On the other hand, the channel region 13a is formed so as to be located below the gate electrode 15.

The gate insulating film 14 is made of, for example, SiO ₂
And is formed above the semiconductor thin film 13.

The gate electrode 15 is made of, for example, Al-Zr
It is made of an alloy or the like, and is formed above the gate insulating film 14 at a position corresponding to the channel region 13a of the semiconductor thin film 13.

The interlayer insulating film 16 is an insulating film made of, for example, SiN _x , and is laminated above the gate electrode 15 and the gate insulating film 14.

In the interlayer insulating film 16 and the gate insulating film 14, contact holes 14a and 14b reaching the source region 13b or the drain region 13c of the semiconductor thin film 13, respectively, are formed. The electrode 18 is provided in the contact hole 1
The source region 13b and the drain region 13c are formed so as to be in contact with each other via 4a and 14b.

Next, the concentration of the impurity element existing at the interface between the constituent elements of the thin film transistor, which is a feature of the present invention, will be described.

In the TFT 10 of the present invention, the concentration of the impurity element contained in the interface between the semiconductor thin film 13 (more specifically, the channel region 13a) and the gate insulating film 14 is 3 × 10 ¹¹ atoms /
cm ² or less.

[0058] The concentration of the impurity elements present in the interface between the said diffusion preventing film semiconductor thin film 13 is configured so as to be a 3 × 10 ¹¹ atoms / cm ² or less for each element.

Here, the concentration of impurities present at the interface between the semiconductor thin film and the gate insulating film and the interface between the semiconductor thin film and the impurity diffusion preventing film is set to 3 × 10 ^{11 at.}
The technical significance of setting the value to ms / cm ² or less will be described.

The present inventors examined in detail how the concentration of the impurity element at the interface between the semiconductor thin film and the gate insulating film affects the characteristics of the thin film transistor, and obtained the experimental results shown in FIG. I got

FIG. 2 is a diagram showing the relationship between the concentration of the impurity element at the interface between the semiconductor thin film and the gate insulating film and the amount of change in the threshold voltage. Incidentally, Na, as the impurity element,
Data when B and Al are used are shown.

As can be seen from FIG. 2, the direction in which the threshold voltage is shifted differs depending on the element, and Na shifts the threshold voltage to negative, and B and Al shift to positive. Further, their fluctuation widths differ depending on the element.

As shown in FIG. 2, in order to keep the threshold voltage of the thin film transistor from fluctuating, the concentration of any of the impurity elements needs to be 3 × 10 ¹¹ atoms / cm ² or less.

Although not shown, K and Ca cause a negative shift of the threshold voltage, and Fe and Cu cause a positive shift. These elements also have an atomic quantity of 3 × 10 ¹¹ at.
It has been found that the threshold voltage is not affected when the value is set to oms / cm ² or less.

Further, the inventors of the present application examined in detail how the concentration of the impurity element at the interface between the semiconductor thin film and the impurity diffusion preventing film affects the characteristics of the thin film transistor, and as shown in FIG. Experimental results were obtained.

FIG. 3 is a diagram showing the relationship between the concentration of the impurity element at the interface between the semiconductor thin film and the impurity diffusion preventing film and the amount of change in the threshold voltage.

As is apparent from FIG. 3, a result substantially similar to the result of FIG. 2 described above is obtained. To prevent the threshold voltage of the transistor from fluctuating, the concentration of any impurity element is set to 3 × 10 ¹¹ atoms / cm ²
It can be seen that it is necessary to:

However, it has been found that the interface between the semiconductor thin film and the impurity diffusion preventing film has less influence on the threshold voltage fluctuation than the interface between the semiconductor thin film and the gate insulating film.

From the above results, the following contents can be derived. That is, the concentration of the impurity element existing at the interface between the semiconductor thin film and the gate insulating film is reduced.
By setting the value to × 10 ¹¹ atoms / cm ² or less, variation in threshold voltage can be reduced.
When the thin film transistor of the present invention is used as a switching element of a liquid crystal display device, a variation in threshold voltage between the thin film transistors can be reduced.

Further, in addition to the above structure, the concentration of each impurity element existing at the interface between the semiconductor thin film and the impurity diffusion preventing film is set to 3 × 10 ¹¹ atoms / cm ² or less, so that the The variation of the threshold voltage can be reduced, and the variation of the threshold voltage of each thin film transistor can be reduced. Further, the total concentration of the impurity element existing at the interface between the semiconductor thin film and the gate insulating film is set to 3 × 10 ¹¹ atoms / cm.
By setting it to ² or less, the above effect can be further enhanced.

Next, a method of manufacturing the thin film transistor according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5 are schematic sectional views showing the steps of manufacturing the thin film transistor according to the first embodiment of the present invention.

(1) First, as shown in FIG. 4A, on a glass substrate 11 which is an insulating substrate, a plasma CVD (Plasma-Enhanced Chemical Vapor Deposition) method is used. Thickness 100-100
Impurity diffusion preventing film 12 of about 0 nm of SiO ₂ or the like
(Impurity diffusion preventing film forming step).

(2) Next, as shown in FIG. 4B, an amorphous silicon (a-Si) film 13 ′ is formed on the impurity diffusion prevention film 12 in the same chamber of the CVD apparatus. (A-Si film forming step).

Specifically, SiH is used as a source gas.
₄ Using a mixed gas such as (silane), Ar (argon), and H ₂ (hydrogen), a film thickness of 3
An amorphous silicon thin film of 0 to 150 nm is formed.

Thus, since the surface of the impurity diffusion preventing film 12 is not exposed to the atmosphere, impurity contamination at the interface between the impurity diffusion preventing film 12 and the amorphous silicon thin film can be prevented. Specifically, the respective concentrations of Al, B, and Na could be made 3 × 10 ¹⁰ atoms / cm ² or less.

(3) Next, hydrogen in the amorphous silicon film is removed to a few at% or less by a heat treatment for 6 to 24 hours (heat treatment step).

(4) Next, as shown in FIG.
For example, the a-Si film is melt-recrystallized (polycrystallized) by laser annealing (ELA) using an excimer laser having a wavelength of 308 nm to obtain the semiconductor thin film 13 (laser annealing step).

In this ELA step, the impurity on the surface of the a-Si film was set to 3 × for any element.
Laser irradiation is performed in a state of 10 ¹¹ atoms / cm ² or less.

Examples of the method for reducing the concentration of impurities below the above concentration include a method of cleaning with a solution containing hydrofluoric acid, a method of etching the surface by reverse sputtering, and an ELA without depositing the a-Si film and exposing it to the atmosphere. And so on.

In this embodiment, the surface of the a-Si film is
By washing with an ol% dilute hydrofluoric acid aqueous solution for about 90 seconds, the impurities present on the surface of the a-Si film were etched and removed together with the natural oxide film, and then ELA was immediately performed. In this step, a step (6) described later may be performed.

(5) Next, as shown in FIG. 4D, the semiconductor thin film 13 is patterned and processed into a predetermined shape (island shape) by photolithography and etching techniques (photolithography). Process).

(6) Next, before depositing the gate insulating film, the concentration of any impurity element on the surface of the semiconductor thin film is set to 3 × 10 ¹¹ atoms / cm ² or less.

The surface of the semiconductor thin film is oxidized to form a surface oxide layer 19 having a thickness of about 1 to 5 nm (oxidation step) (FIG. 4E). If the oxide layer is thinner than 1 nm, the surface protection effect cannot be sufficiently exerted. In addition, if an oxide layer having a thickness of more than 5 nm exists, a problem may occur because the etching rate is different between the silicon thin film and the oxide layer. As a method of oxidation, a method of exposing to water in which ozone is dissolved (hereinafter, referred to as ozone water) or a method of UV
A method such as light irradiation, UV ozone treatment, or oxygen plasma treatment can be used. In particular, the method of exposing to ozone water is desirable because it does not cause any damage to the polysilicon film, a uniform oxide layer can be formed to an appropriate thickness over the entire surface of the substrate, and is a low-cost means. Further, it has an effect of removing organic substance contamination and dirt such as fine particles attached to the substrate surface. In this embodiment mode, the processing is performed by dropping ozone water on the surface of the substrate while rotating the substrate. The ozone concentration is about 5 to 25 mg / L, and the processing time is about several seconds, which is effective, but it is preferable to perform the processing for 10 seconds or more, since an oxide layer is sufficiently formed.

Next, the surface oxide layer 19 is removed by etching, and the impurities on the surface are removed (surface oxide layer removing step) (FIG. 4F).

As an etching means, dilute hydrofluoric acid was dropped while rotating the substrate in order to prevent impurities dissolved in dilute hydrofluoric acid from remaining on the polysilicon surface. By doing so, clean dilute hydrofluoric acid is always supplied onto the substrate, and old dilute hydrofluoric acid in which the oxide layer has dissolved is shaken off. The dilute hydrofluoric acid concentration was about 0.2 to 1%, and the treatment time was 30 to 60 seconds, and the impurities existing inside or on the oxide layer could be removed together with the oxide layer.

(7) Subsequently, as shown in FIG.
Immediately after the step (5), silicon oxide is applied to the semiconductor thin film 13 by using a mixed gas of, for example, TEOS (tetraethoxysilane) vapor and oxygen as a source gas by a plasma CVD method or the like. The gate insulating film 14 was formed to have a thickness of 100 nm (gate insulating film forming step).

As described above, the concentration of the impurity element existing at the interface between the semiconductor thin film and the gate insulating film is set to 3 × 10 ¹¹ a
toms / cm ² or less. Specifically, the concentration of Al is set to 3 × 10 ¹⁰ atoms / cm ² ,
Could be set to 4 × 10 ¹⁰ atoms / cm ² .

(8) Next, as shown in FIG. 5H, a gate electrode film made of, for example, an alloy of molybdenum and tungsten is formed, and the gate electrode film is patterned into an island shape by photolithography and etching. To form a gate electrode 15 (gate electrode forming step).

(9) Next, as shown in FIG.
Source / drain regions 13b and 13c are formed by generating a plasma of hydrogen-diluted phosphine (PH ₃ ) using the gate electrode 15 as a mask and performing ion doping under the conditions of an acceleration voltage of 70 kV and a dose of 10 ¹⁵ cm ⁻² ( Source / drain region forming step).

(10) Thereafter, as shown in FIG. 5 (j), for example, RTA (Rapid Thermal An
Neal) to perform local heating to activate the implanted ions (annealing step).

(11) Next, as shown in FIG. 5 (k), for example, a plasma C using TEOS as a source gas is used.
SiO ₂ is deposited on the entire surface as an interlayer insulating film 16 by VD method, then forming contact holes 14a · 14b (contact hole forming step).

(12) Next, as shown in FIG. 5 (l), for example, an aluminum alloy film is deposited as a source electrode 17 and a drain electrode 18 by sputtering, and then patterned by photolithography and etching (source / drain). Electrode forming step).

As described above, a thin film transistor is completed. The thin film transistor completed in this manner is referred to as Experimental Example 1.

Comparative Example 1 As a comparative example of the first embodiment (Experimental Example 1), the concentration of the impurity element existing at the interface between the semiconductor thin film 13 and the gate insulating film 14 is 3 × 10 ¹¹ atoms.
Thin film transistors with more than s / cm ² present were fabricated as follows.

That is, in the first embodiment, before depositing the gate insulating film 14, impurities are attached to the surface of the semiconductor thin film 13. In this comparative example, an aqueous solution of a compound containing an impurity element was prepared, and the surface of the semiconductor thin film was exposed to the aqueous solution of the impurity. By changing the impurity concentration of the aqueous solution, impurities of various atomic quantities can be attached to the surface of the semiconductor thin film. The thin film transistors manufactured in this way were Comparative Examples 1 and 2.

As the impurity element, Al was used in Comparative Example 1 and Na was used in Comparative Example 2.

<Experiment 1> The voltage / voltage of the thin film transistor (Experimental Example 1) manufactured by the manufacturing method as shown in the first embodiment and the thin film transistors of Comparative Examples 1 and 2 was measured.
The current characteristics were measured. The result is shown in FIG.

<Result 1> FIG. 6 shows Embodiment 1 of the present invention.
FIG. 9 is a diagram showing voltage / current characteristics of the thin film transistor of (Experimental Example 1) and the thin film transistors of Comparative Examples 1 and 2.

The line L1 is the TFT of the first embodiment.
(That is, the concentration of the impurity element at the interface between the semiconductor thin film and the gate insulating film is 3 × 10 ¹¹ atoms / cm ² or less.
FT).

On the other hand, the lines L2 and L3 show the characteristics of the TFTs of Comparative Examples 1 and 2 (that is, TFTs in which the concentration of the impurity element at the interface between the semiconductor thin film and the gate insulating film is higher than 3 × 10 ¹¹ atoms / cm ² ). Show.

Each of the TFTs on the lines L1 to L3
, The concentration of impurities at the interface between the channel region and the gate insulating film was measured by SIMS.
In FT, Al is 1.0 × 10 ¹² atoms / cm ² ,
In the TFT of the line L3, Na is 1.1 × 10 ^{12 at.}
ms / cm ^{2 was} detected. In the TFT of line L1, A
1 is 3 × 10 ¹⁰ atoms / cm ² , Na is 4 × 10 ¹⁰
Only atoms / cm ² were detected.

As is clear from FIG. 6, the transistor shown in line L1 has a low impurity concentration,
The rise of the V characteristic is almost at 0V.

On the other hand, in the transistor L2 shown in the line L2, Al is 1.0 × 10 ¹² atoms /
cm ^{2, the} voltage rises from around +1.5 V. In the transistor shown in line L 3, since Na is present at 1.0 × 10 ¹² atoms / cm ² , the voltage rises around -2 V. , And the threshold voltages of the transistors shown on both lines L2 and L3 have fluctuated greatly.

As described above, the thin film transistor manufactured according to the first embodiment does not change in threshold voltage and has excellent characteristics.

As described above, the concentration of impurities existing at the interface between the semiconductor thin film and the gate insulating film is preferably as low as possible, but the impurity concentration at the interface between the semiconductor thin film and the gate insulating film is set to 1 × 10 ⁹ If it is desired to lower the value to lower than atoms / cm ^2, it is necessary to manufacture the semiconductor thin film without exposing the surface thereof to the atmosphere. This requires a very complicated manufacturing process and requires expensive manufacturing equipment.

More specifically, the steps from the deposition of an amorphous silicon film on a glass substrate to the crystallization by laser and the deposition of a gate insulating film must be performed in a vacuum without exposure to the air. . Therefore, it is necessary to connect at least the amorphous silicon film deposition device, the heat treatment device, the laser annealing device, and the gate insulating film deposition device, and move the substrate between the four devices while keeping it in a vacuum. However, the amorphous silicon film deposition device, the laser annealing device and the gate insulating film deposition device,
The heat treatment apparatus is a batch type. On the other hand, the heat treatment apparatus is of a batch type, and the above four apparatuses are connected to form four steps: an amorphous silicon film deposition step, a heat treatment step, a laser annealing step, and a gate insulating film deposition step. Is very difficult to perform continuously in a vacuum.

That is, the heat treatment step is performed at a temperature of about 400 ° C., and the time required for the heat treatment step is 6 to 24 hours.
And the time required for the laser annealing step and the gate insulating film deposition step is about several tens of minutes. Thus, the throughput of each device is different,
Since the speed is determined by the device (heat treatment device) having the slowest tact, the manufacturing method is extremely inferior in productivity as a whole.

Further, since the polysilicon film is patterned after the gate insulating deposition step, the deposited film of the gate insulating film and the polysilicon film must be etched, which makes the process complicated and commensurate with it. Requires special manufacturing equipment.

For the above reason, the impurity concentration is set to 1 × 10 ⁹
If it is lower than atoms / cm ^2, considerable manufacturing cost is required, and as a result, the product price rises, which is not suitable for mass production.

On the other hand, according to the present embodiment, it is not necessary to connect the four devices and perform the four steps in a vacuum, so that the thin film transistor can be manufactured without being affected by the throughput of each device. Accordingly, a thin film transistor having no change in threshold voltage can be obtained in a short time and reliably.

Therefore, in order to obtain a thin film transistor in which the threshold voltage does not fluctuate while simplifying the manufacturing process as much as possible, the concentration of each impurity element existing between the semiconductor thin film and the gate insulating film must be 1 × 10 ⁹ a
It is preferable that the concentration be not less than toms / cm ^{2 and not} more than 3 × 10 ¹¹ atoms / cm ² .

The impurity element existing at the interface between the semiconductor thin film and the substrate or the interface between the gate insulating film and the gate electrode is also set to 1 × 10 ⁹ atoms / cm 2.
cm ² or more and 3 × 10 ¹¹ atoms / cm ² or less.

It is more preferable that the concentration of each of the impurity elements is 1 × 10 ¹⁰ atoms / cm ² or more. The reason will be described below.

The concentration of each of the impurity elements is set to 1 × 10 ¹⁰
In order to lower the density to below atoms / cm ² , it is necessary to thoroughly eliminate the source of contamination when constructing a semiconductor manufacturing line and to perform a process control for thoroughly removing impurities.

That is, it is necessary to prevent impurities from the manufacturing apparatus, the manufacturing environment, water, chemicals, and other materials.

For example, a member that does not generate impurities is used for the apparatus or the factory building, an air filter for purifying the air in the factory is used with a higher purification performance, or a pure water producing apparatus is used. Similarly, a high-performance one is used, or impurities are removed by filtering multiple times. In addition, a high-purity expensive chemical solution is purchased, and if necessary, a process for removing impurities, such as distillation or filtration, is performed. Implementing these measures requires a great deal of labor and a great deal of cost.

However, according to the present embodiment, the concentration of each of the impurity elements at the interface between the semiconductor thin film and the gate insulating film can be reduced to 1 × 10 ¹⁰ atoms / s without requiring such a large manufacturing cost. cm ² or more, 3 × 10 ¹¹ ato
ms / cm ² or less, and a thin film transistor with no change in threshold voltage can be obtained.

(Embodiment 2) In this embodiment 2, the variation in the threshold voltage of the thin film transistor in the high-temperature voltage application test (so-called BT test) is reduced by reducing impurities at the interface between the gate insulating film and the gate electrode. It aims at suppressing. This will be specifically described below.

The steps up to the deposition of the gate insulating film 14 are performed in accordance with the method of manufacturing a thin film transistor described in the first embodiment (FIGS. 4A to 4G).

Next, a step of removing surface impurities of the gate insulating film 14 is performed (impurity removing step).

In this embodiment, the first embodiment is used.
The step (6) was performed to remove impurities present on the surface of the gate insulating film 14.

As another method for removing the surface impurities of the gate insulating film 14, when forming the gate electrode, the extreme surface of the gate insulating film is etched by reverse sputtering, and then the gate electrode film is deposited. Can also.

Thereafter, the gate electrode 15 composed of, for example, a molybdenum-tungsten alloy was immediately formed (gate electrode forming step).

In this way, the concentration of the impurity element at the interface was set to 3 × 10 ¹¹ atoms / cm ² or less.

Thereafter, the steps after depositing the gate electrode film were performed according to the first embodiment, and a thin film transistor was completed. The thin film transistor completed in this manner is referred to as Experimental Example 2.

Here, the impurity concentration at the interface is set to 3 × 1
The technical significance of setting the value to 0 ¹¹ atoms / cm ² or less will be described with reference to FIG.

The present inventors studied in detail how the impurity concentration at the interface between the gate insulating film and the gate electrode affects the characteristics of the thin film transistor, and obtained the experimental results shown in FIG. Obtained.

FIG. 7 shows the result of examining the relationship between the amount of Na at the interface between the gate insulating film and the gate electrode and the amount of change in the threshold voltage by the BT test.

Thus, the concentration of the Na element was set to 3 × 10 ¹¹ a
It has been found that a thin film transistor whose threshold voltage does not fluctuate before and after the BT test can be manufactured with a sufficient margin if the thickness is set to be not more than toms / cm ² .

<Comparative Example 3> With reference to Comparative Examples 1 and 2 described in the first embodiment, a thin film transistor in which a large amount of Na exists at the interface between the gate insulating film and the gate electrode was manufactured.
This thin film transistor is referred to as Comparative Example 3.

<Experiment 2> In each of the thin film transistors of Experimental Example 2 and Comparative Example 3, the concentration of the impurity element at the interface between the gate insulating film and the gate electrode was measured by SIMS. Was detected only at 1 × 10 ¹¹ atoms / cm ^2, whereas in Comparative Example 3, Na was 2.0 × 10 ¹² atoms / cm ^2.
m ^{2 was} detected.

Therefore, a change in the characteristics was examined by performing the BT test manufactured in the above steps. FIG. 8 shows a change in thin film transistor characteristics before and after the BT test for each thin film transistor.

The test conditions were 85 ° C., applied voltage +30.
V, application time was 600 seconds. FIG. 8 (a)
Indicates that the concentration of impurities at the interface between the gate insulating film and the gate electrode is 1 × 10 ¹¹ atoms
/ Cm ² TFT).

On the other hand, FIG. 8B shows the TFT of Comparative Example 3.
(That is, the concentration of Na atoms at the interface is 2.0 × 10 ¹² a
shows a toms / cm ² of TFT) test results.

<Result 2> As is apparent from FIG.
In a thin film transistor having a high element concentration (TFT shown in FIG. 8B), the threshold voltage fluctuates by -1 V before and after the test. On the other hand, in the thin film transistor having a low impurity concentration (TFT shown in FIG. 8A), the threshold voltage did not change.

As described above, by reducing impurities at the interface between the gate insulating film and the gate electrode, fluctuations in transistor characteristics in a high-temperature voltage application test (so-called BT test) can be suppressed.

(Embodiment 3) FIG. 9 is a schematic sectional view for illustrating the configuration of a liquid crystal display device according to Embodiment 3 of the present invention. FIG. 10 is an equivalent circuit diagram of the liquid crystal display device according to Embodiment 3 of the present invention.

According to the method described in the first embodiment, a thin film transistor is formed in a matrix as a switching transistor of each pixel, and at the same time, a CMOS drive circuit for driving each pixel transistor is integrally formed. The pixel electrode 21 was formed on the thin film transistor array substrate 39, an alignment film 22 was applied, and an alignment process was performed by rubbing.

The counter electrode 24 and the color filter 2
Similarly, the alignment film 22 was applied to the counter substrate 23 on which the layer 5 was formed, and an alignment process was performed by rubbing.

A liquid crystal display device is completed by bonding both substrates, injecting a liquid crystal 26 between them, and disposing a polarizing plate 27 before and after the two substrates.

Such a liquid crystal display device is excellent in display performance because the threshold voltage of the thin film transistor as a constituent element does not vary and the threshold voltage does not change.

(Embodiment 4) FIG. 9 is a cross-sectional view for explaining a liquid crystal display device according to Embodiment 4 of the present invention. FIG. 10 is an equivalent circuit diagram of the liquid crystal display device according to the fourth embodiment.

According to the method of the second embodiment, a thin film transistor is formed as a switching transistor of each pixel in a matrix, and at the same time, a thin film transistor array substrate integrally formed with a CMOS drive circuit for driving each pixel transistor. A pixel electrode 21 was formed thereon, an alignment film 22 was applied, and an alignment process was performed by rubbing.

The counter electrode 24 and the color filter 2
Similarly, an orientation film is applied to the counter substrate 23 on which
An alignment treatment by rubbing was performed. The two substrates are attached to each other, and a liquid crystal 26 is injected between the two substrates.
By arranging 7, the liquid crystal display device is completed.

(Embodiment 5) FIG. 11 is a cross-sectional view for explaining an electroluminescent display device according to Embodiment 5 of the present invention. FIG. 12 shows Embodiment 5
FIG. 3 is an equivalent circuit diagram of the electroluminescent display device of FIG.

In accordance with the method of the first embodiment, a CMOS for driving each pixel transistor at the same time as forming a thin film transistor as a switching transistor and a current driving thin film transistor in a matrix in each pixel.
An ITO electrode is formed as a transparent electrode 49 on a thin film transistor array substrate integrally formed with a driving circuit.

Thereafter, for example, as the conductive polymer 43, for example, polyethylene dioxythiophene (PED)
T), a polydialkylfluorene derivative 44 which actually emits light is formed, and finally a cathode 45 is deposited to complete an electroluminescent display device.

The operation is as follows. First, when a display signal is applied to the signal line when a pulse signal is applied to the scanning line so that the switching transistor 50 is turned on, the driving transistor 46 is turned on and a current flows from the current supply line 47, and the electroluminescence The cell 48 emits light.

Such an electroluminescent display device has excellent display quality and reliability because the characteristics of the individual thin film transistors constituting the transistor array are good.

(Embodiment 6) FIG. 11 is a cross-sectional view for explaining an electroluminescent display device according to Embodiment 6 of the present invention. FIG. 12 shows Embodiment 6
FIG. 3 is an equivalent circuit diagram of the electroluminescent display device of FIG.

According to the method of the second embodiment, a CMOS for driving each pixel transistor at the same time as forming a thin film transistor as a switching transistor and a current driving thin film transistor in a matrix in each pixel.
An ITO electrode is formed as a transparent electrode 49 on a thin film transistor array substrate integrally formed with a driving circuit.

Thereafter, for example, as the conductive polymer 43, for example, polyethylene dioxythiophene (PED)
T), a polydialkylfluorene derivative 44 which actually emits light is formed, and finally a cathode 45 is deposited to complete an electroluminescent display device.

Although the polydialkylfluorene derivative is used as the electroluminescent material in the fifth and sixth embodiments, other organic materials, for example, other polyfluorene-based materials or polyphenylvinylene-based materials may be used. Or an inorganic material.

Further, as a method for forming the electroluminescent material, a coating method such as spin coating, a method such as vapor deposition, or a discharge forming method using an ink jet may be used.

(Other Matters) (1) In the first to sixth embodiments, examples in which the present invention is applied to an n-channel polycrystalline thin film transistor having a top gate structure have been described. However, the present invention is not limited to this. The present invention can be applied to a channel polycrystalline thin film transistor and a top gate thin film transistor.

(2) In the first to sixth embodiments, a glass substrate having a strain point of 650 ° C. or less is used as the substrate.
The glass substrate is a general-purpose substrate, and is liable to generate impurities and the like, and is likely to adversely affect the thin film transistor. However, even if the thin film transistor of the present invention is formed on the glass substrate, there is no change in the threshold voltage of the thin film transistor, which is practically effective.

[0157]

As described above, according to the structure of the present invention, the object of the present invention can be sufficiently achieved.

That is, according to the structure of the present invention, the fluctuation of the threshold voltage of the thin film transistor can be suppressed. In addition, variation in threshold voltage among a plurality of thin film transistors can be prevented.
Therefore, a thin film transistor having favorable characteristics can be stably provided with high yield. Further, it is possible to suppress a change in the threshold voltage of the thin film transistor in the high-temperature voltage application test. Therefore, the reliability of the thin film transistor can be improved. Further, according to the liquid crystal display device of the present invention, a liquid crystal display device having excellent initial characteristics and reliability can be provided. Further, according to the electroluminescent display device of the present invention, it is possible to provide an electroluminescent display device which is also excellent in initial characteristics and reliability.
From the above, the practical effect of the present invention is great.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic diagrams illustrating a structure of a thin film transistor according to Embodiment 1 of the present invention. FIG. 1A is a schematic plan view of the thin film transistor, and FIG. −
FIG. 4 is a schematic sectional view taken along line A ′.

FIG. 2 is a diagram showing the relationship between the concentration of an impurity element at the interface between a semiconductor thin film and a gate insulating film and the amount of change in threshold voltage.

FIG. 3 is a diagram showing the relationship between the concentration of an impurity element at the interface between a semiconductor thin film and an impurity diffusion preventing film and the amount of change in threshold voltage.

FIG. 4 is a schematic sectional view showing a manufacturing process of the thin film transistor according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a manufacturing step of the thin-film transistor according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating voltage / current characteristics of the thin film transistor of the first embodiment (Experimental example 1) of the present invention and the thin film transistors of Comparative examples 1 and 2.

FIG. 7 shows an interface between a gate insulating film and a gate electrode;
It is a figure which shows the relationship between the amount of Na and the fluctuation | variation amount of the threshold voltage by a BT test.

FIG. 8 is a diagram showing a relationship between a thin film transistor according to a second embodiment (Experimental example 2) of the present invention and a thin film transistor according to Comparative example 3 with a variation in threshold voltage before and after a BT test.

FIG. 9 is a schematic cross-sectional view schematically showing a liquid crystal display device according to Embodiments 3 and 4 of the present invention.

FIG. 10 is a schematic diagram for explaining an equivalent circuit of the liquid crystal display device according to the third and fourth embodiments of the present invention.

FIG. 11 is a schematic cross-sectional view schematically showing the electroluminescent display devices according to the fifth and sixth embodiments.

FIG. 12 is a schematic diagram for explaining an equivalent circuit of the electroluminescent display device according to the fifth and sixth embodiments.

13A and 13B are schematic diagrams showing the structure of a conventional thin film transistor. FIG. 13A is a schematic plan view of the thin film transistor, and FIG. It is.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 TFT 11 Glass substrate 12 Impurity diffusion prevention film 13 Semiconductor thin film 13a Channel region 13b Source region 13c Drain region 13 'Amorphous silicon (a-Si) film 14 Gate insulating film 14a / 14b Contact hole 15 Gate electrode 16 Interlayer insulating film Reference Signs List 17 source electrode 18 drain electrode 19 surface oxide layer 21 pixel electrode 22 alignment film 23 counter substrate 24 counter electrode 25 color filter 26 liquid crystal 27 polarizing plate 39 array substrate 43 conductive polymer 44 polydialkylfluorene derivative 45 cathode 46 driving transistor 47 Current supply line 48 Electroluminescence cell 49 Transparent electrode 50 Switching transistor L1, L2, L3 line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/20 H01L 29/78 618F 21/336 626C 627G 617S 617J (72) Inventor Masami Ido Kadoma City, Osaka 1006 Oaza Kadoma Matsushita Electric Industrial Co., Ltd.F-term (reference) CC02 DD02 DD13 DD14 EE06 FF02 FF07 FF30 FF36 GG02 GG13 GG25 GG31 GG32 GG34 GG45 HJ01 HJ04 HJ12 HJ23 HL06 HL23 NN02 NN24 NN35 PP01 PP03 PP04 PP10 PP29 PP31 PP35 QQ09 QQ11

Claims (15)

[Claims] A semiconductor thin film having a channel region, a source region and a drain region formed on both sides of the channel region; a gate insulating film formed on the semiconductor thin film; A thin film transistor formed on a substrate, the thin film transistor including a gate electrode formed at a position corresponding to a channel region, wherein at least one impurity element is present at an interface between the semiconductor thin film and the gate insulating film; A thin film transistor, wherein the concentration of each of the impurity elements is 3 × 10 ¹¹ atoms / cm ² or less. 2. A thin film transistor comprising: a gate electrode; a gate insulating film provided on the gate electrode; and a semiconductor thin film provided on the gate insulating film, wherein the semiconductor thin film and the gate insulating film are provided. At least one impurity element is present at an interface with the impurity element, and the concentration of each of the impurity elements is 3 × 10 ¹¹ atoms / cm ² or less. 3. The thin film transistor according to claim 1, wherein at least one impurity element exists at an interface between the semiconductor thin film and the substrate, and a concentration of each of the impurity elements is:
A thin film transistor having a resistivity of 3 × 10 ¹¹ atoms / cm ² or less. 4. The thin film transistor according to claim 1, wherein an impurity diffusion preventing film is formed on the substrate, and at least one impurity element is provided at an interface between the semiconductor thin film and the impurity diffusion preventing film. A thin film transistor, wherein the concentration of each of the impurity elements is 3 × 10 ¹¹ atoms / cm ² or less. 5. The thin film transistor according to claim 3, wherein at least one impurity element exists at an interface between the gate insulating film and the gate electrode, and a concentration of each of the impurity elements is 3 × 10 ^11. A thin film transistor having a thickness of atoms / cm ² or less. 6. The thin film transistor according to claim 1, wherein at least one impurity element exists at an interface between the semiconductor thin film and the gate insulating film, and a concentration of each of the impurity elements is 1 × 10 ^9. A thin film transistor having a thickness of atoms / cm ² or more. 7. The thin film transistor according to claim 1, wherein the impurity element is an alkali metal and / or an alkaline earth metal. 8. The thin film transistor according to claim 1, wherein the substrate is a glass substrate having a strain point of 650 ° C. or less, and the impurity elements are Si and O among elements contained in the glass substrate. A thin film transistor characterized by being an element excluding. 9. The thin film transistor according to claim 5, further comprising: an interlayer insulating film formed on the gate electrode; and a source electrode connected to the source region and the drain region on the interlayer insulating film. And a drain electrode are formed. The substrate is a glass substrate having a strain point of 650 ° C. or lower. The impurity element is an impurity element contained in the glass substrate, the gate electrode, the source electrode, and the drain electrode. A thin film transistor characterized by being an element excluding Si and O among them. 10. The thin film transistor according to claim 8, wherein the impurity element is Na, K, Ca, Mg, Ba, B,
A thin film transistor comprising at least one element selected from the group consisting of Fe, Cu, and Zn. 11. The thin film transistor according to claim 9, wherein the impurity element is Na, K, Ca, Mg, Ba, B,
A thin film transistor comprising at least one element selected from the group consisting of Al, Mo, Cr, Fe, Cu, and Zn. 12. The thin film transistor according to claim 1, wherein said semiconductor thin film is a polycrystalline silicon film. 13. The thin film transistor according to claim 1, wherein the semiconductor thin film is a polycrystalline silicon film obtained by laser annealing a non-single-crystal silicon film. 14. A first substrate, a second substrate disposed to face the first substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate. A liquid crystal display device comprising: the thin film transistor according to claim 1 and display electrodes connected to the thin film transistor arranged in a matrix on the first substrate. . 15. A first substrate, a second substrate disposed opposite to the first substrate, and an electroluminescent material sandwiched between the first substrate and the second substrate. An electroluminescent display device comprising: the thin film transistor according to claim 1 and display electrodes connected to the thin film transistor arranged in a matrix on the first substrate. Luminescence display device.