JP2002174668A - System or testing ic, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system for testing IC that allows a simulation result in an analyzing part to be analyzed in real time, allows a microprogram inputted for setting a simulation condition to be diverted to setting of an actual testing condition, and can enhance the working efficiency for worker, by making a microprogram simulator and the analyzing part hold information about a simulation for an IC test and information about the test in common. SOLUTION: In this IC testing system, an IC testing device 150 impresses a test pattern signal to a tested IC. The microprogram simulator 14 simulates an operation of the IC testing device 150. A controller 11 controls operations of the testing device 150 and the simulator 14, and stores the informations about the operations of the device and the simulator. The controller 11 controls also the one information out of the information about the testing condition and a result of the IC testing device 150, and the simulation condition and the result of the simulator 14, based on the other information out of them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test system for checking whether or not the characteristics of an IC satisfies a predetermined standard, and a storage medium.

[0002]

2. Description of the Related Art In general, semiconductor integrated circuits (ICs)
ated Circuit) and LSI (Large Scale Integrated cir)
cuit) and the like (hereinafter simply referred to as “IC”) slightly vary in the characteristics of each product when mass-produced. Therefore, an IC test system has been conventionally used as an apparatus for checking whether or not the characteristics of an IC satisfy a predetermined standard.

FIG. 5 shows a configuration example of a conventional IC test system. As shown in FIG. 5, the IC test system 100
Are the input device 110, the output device 120, and the management device 13
0, a control device 140, and an IC test device 150.

The input device 110 inputs a microprogram for simulating the operation of the IC test device 150 described later and data for specifying a test pattern signal to be applied to the IC. A keyboard, a mouse, and the like correspond to the input device. I do. The output device 120 outputs a simulation mode or an actual operation content of the IC test device 150 described later, or an IC test result, and corresponds to a display or a printer.

[0005] The management device 130 is used for the IC test system 10.
0, and outputs a control signal to the other components constituting
The entire C test system 100 is managed. The management device 130 includes a management unit 131, an analysis unit 132, hardware / register information 133, and a microprogram simulator 134.

[0006] The management unit 131 includes a management program 131a.
And manages the transmission and reception of data between the analysis unit 132 and a control device 140, which will be described later, according to the processing procedure described in the management program 13 1 a.

[0007] The analysis unit 132 has an application program 132a, and analyzes a test result by an IC test apparatus 150, which will be described later, in accordance with the processing procedure described in the application program 132a.

[0008] Microprogram simulator 134
Simulates the operation of the IC test apparatus 150. The operation of the microprogram simulator 134 will be described later. The hardware register information 133 stores information on simulation conditions and results of the microprogram simulator 134.

The control device 140 is connected to the management unit 131 and the IC test device 150, analyzes a control signal input from the management unit 131 according to the control program 141, and controls the IC test device 150 based on the analysis result. Control.

[0010] The IC test apparatus 150 is for actually inspecting the characteristics of the IC under the control of the control unit 140, and applies a predetermined test pattern signal for inspecting the electrical characteristics to the IC as a product. A pattern generator (not shown).

The IC test apparatus 150 has a storage area, and the storage area has the hardware register information 15 separately from the hardware register information 133.
1 is stored. This hardware register information 1
51 stores information on test conditions and results of the IC test apparatus 150.

Next, the operation of the IC test system 100 will be described. First, an operator inputs an I-
When data specifying a test pattern signal to be applied to C is input, the analysis unit 13 analyzes the data and outputs an analysis result to the management unit 131. The management unit 131 that has received the analysis result outputs the analysis result to the control device 140.

The control device 140 includes a control program 141
To process the analysis result of the analysis unit 132 and control the IC test apparatus 150 based on the processing result. The IC test device 150 applies a test pattern signal to the IC under the control of the control device 140, and outputs a test result, which is a response of the IC, to the control device 140.

The control device 140 outputs the result of the IC test performed by the IC test device 150 to the management unit 131. The management unit 131 having received the test result converts the test result into the analysis unit 13.
Output to 2. The analysis unit 132 analyzes the test result and outputs the analysis result to the output device 120. The actual inspection of the IC is performed according to the procedure described above.

On the other hand, the microprogram simulator 1
34 simulates the operation of the IC test apparatus 150. The operation of the microprogram simulator 134 will be described with reference to the flowchart shown in FIG. 6. First, the microprogram simulator 134 translates the microprogram input from the input device 110 into an executable instruction. The processing is performed (step S600).

Next, the microprogram simulator 1
34 changes the contents of the hardware register information 133 according to the translated microprogram (step S601). Here, when the contents of the microprogram are changed by the operator via the input device 110 (step S602; YES), the process returns to step S600 again, and the translation process is performed.

If there is no change in the microprogram (step S602; NO), the microprogram simulator 134 performs a simulating process (step S6).
03), simulate the operation of the IC test apparatus 150,
The execution result is output to the output device 120.

As described above, the microprogram simulator 134 does not need to be linked with the analysis unit 132 and the management unit 131, and can operate alone. Therefore, based on the result of the simulation processing, the operator actually performs the IC test
The operation of the microprogram can be confirmed without using the IC 50, the generated microprogram can be evaluated, and a test pattern signal to be applied to the IC can be designed.

[0019]

However, in the IC test system 100 according to the prior art as described above, the management unit 131 has two pieces of hardware register information 133.
And 151 were individually managed, and the analysis result by the microprogram simulator 134 could not be analyzed by the analysis unit 132 in real time. Further, the microprogram input for the simulation cannot be diverted as a microprogram for performing an actual test as it is, thus reducing the work efficiency of the operator.

Further, since the dedicated hardware register information 133 is set in the microprogram simulator 134 separately from the hardware register information 151 of the IC test apparatus 150, a large number of IC test systems 100 as a whole are provided. Needed storage space.

An object of the present invention is to enable a microprogram simulator and an analysis unit to share information relating to a simulation of an IC test and information relating to a test.
To enable real-time analysis of the simulation results in the analysis unit, and to enable the microprogram input for setting the simulation conditions to be used for setting the actual test conditions, thereby improving the work efficiency of the workers. It is to provide an IC test system capable of performing the above.

[0022]

The present invention has the following features in order to solve the above-mentioned problems. In the description of the following means, a configuration corresponding to the embodiment is exemplified by parentheses. In addition, reference numerals are reference numerals in the drawings described later.

According to the first aspect of the present invention, there is provided a test signal applying means for applying a test pattern signal to an IC under test based on a test program (for example, an IC test apparatus shown in FIG. 1).
0), simulation means for simulating the operation of the test signal applying means based on the simulation program (for example, the microprogram simulator 14 shown in FIG. 1), and the test signal applying means detachably connected to the management program. A management unit (for example, a management device 11 shown in FIG. 1) for managing each operation of the test signal applying unit and the simulation unit based on the information and storing information relating to the operation of each unit.
In the test system (10), the management unit manages the other information based on one of information on a simulation operation of the simulation unit and information on an operation of the test signal application unit. .

In the first aspect of the present invention, the test signal applying means applies a test pattern signal to the IC under test based on a test program. The simulation means simulates the operation of the test signal application means based on a simulation program. The management unit stores information on the operation of the test signal applying unit and the simulation unit, and manages the operation of each unit.

However, the operation of each unit and the management of the result are performed by the management unit. Thus, real-time analysis of the simulation result is possible. The management means manages simulation conditions and results of the simulation means based on the operation conditions and results of the test signal application means, and manages the operation conditions of the test signal application means based on the simulation conditions of the simulation means. Runode, the microprogram entered to set the simulation conditions, as it possible to divert the set of actual test conditions can improve the work efficiency of the worker required for IC testing.

Thus, it is not necessary to individually set these simulation conditions and results and the operating conditions and results of the test signal applying means as in the prior art. Therefore, I
The storage area of the entire C test system can be effectively used.

According to a fifth aspect of the present invention, there is provided the method according to the first aspect.
In the C test system, the management unit stores a storage area for storing information on an operation of the test signal application unit and information on a simulation operation of the simulation unit in accordance with whether or not the test signal application unit is connected. A storage area setting unit (for example, the management unit 12 shown in FIG. 1) for appropriately setting whether to use a shared storage area or an individual storage area is further provided.

According to a fifth aspect of the present invention, the management means includes a storage area setting means. The storage area setting means,
Depending on whether the test signal applying means is connected or not, whether the storage area for storing the information on the operation of the test signal applying means and the information on the simulation operation of the simulation means is a shared storage area or an individual storage area Is set appropriately.

Thus, even if the test signal applying means is not connected, the information on the operation of the test signal applying means and the information on the simulation operation of the simulation means can be individually managed in the IC test system. It has the convenience that only means can be operated alone.

The invention according to claim 6 is the invention according to claim 5,
In the C test system, the simulation means controls switching between a storage area for information related to a simulation operation set by the management means based on the simulation program and a separate storage area. It is characterized by.

According to the sixth aspect of the present invention, since the setting of whether the storage area in the management means is a shared storage area or an individual storage area is controlled by the simulation means, the test signal is applied in advance. Even when the simulation means is operated independently without connecting the means, the test signal applying means can be connected as necessary, and information on the simulation conditions of the simulation means can be fed back to the connected test signal applying means.
Therefore, the operability of the IC test system is improved, and the work efficiency of the operator can be further improved.

According to a seventh aspect of the present invention, in the IC test system according to the fifth or sixth aspect, the management means stores information on an operation of the test signal applying means and information on a simulation operation of the simulation means. When at least one of the information related to the operation of each unit is changed, the information related to the changed operation is returned in real time to the test signal applying unit and the simulation unit. It is characterized by doing.

According to the seventh aspect of the present invention, in the case where the storage area for storing the information on the operation of the test signal applying unit and the information on the simulation operation of the simulation unit is shared, the information on the operation of each unit is shared. When at least one of them is changed, the information on the changed operation is returned to the test signal applying unit and the simulation unit in real time by the management unit, so that the simulation condition is changed to the actual operation of the test signal applying unit. Can be reflected in real time.

In setting the simulation conditions by the simulation means, the actual operation conditions and results of the test signal applying means can be taken into account in real time. Therefore, the work efficiency required for the simulation process of the operator required for the IC test can be further improved.

According to an eighth aspect of the present invention, in the IC test system according to any one of the fifth to seventh aspects, the management unit includes information on an operation of the test signal applying unit and information on a simulation operation of the simulation unit. When the storage area for storing the simulation operation is not shared, information on the simulation operation is managed without referring to the management program.

In the invention according to claim 8, the management means does not refer to the management program if the storage area for storing the information on the operation of the test signal applying means and the information on the simulation operation of the simulation means are not shared. Manages information about simulation operations.

That is, when the management unit does not share a storage area for storing the information on the operation of the test signal applying unit and the information on the simulation operation of the simulation unit, a conventional simulation program is used instead of the management program. It refers to a program that individually manages only the information on the operation.

As a result, the management means can be provided with a management program of the conventional specification, so that the IC test system requires only a minimum design change to the existing IC test system of the conventional specification. And can be realized at low cost.

According to a ninth aspect of the present invention, there is provided a storage medium storing a computer-executable program for controlling an operation of an IC test system, wherein the computer for applying a test pattern signal to an IC under test is provided. An executable program code, a computer-executable program code for simulating the operation of applying the test pattern signal, and constantly managing each operation of applying the test pattern signal to the IC under test and the simulation, A computer-executable program code for storing information relating to those operations, information relating to the simulation operation, and information relating to the operation of the test pattern signal, for managing the other information based on one of the information. Computer-executable program code. And characterized by storing a program.

According to the ninth aspect of the invention, in order to control the operation of the IC test system, a test pattern signal is applied to the IC under test, the operation of applying the test pattern signal is simulated, and the test pattern is applied to the IC under test. It constantly manages the operation of signal application and simulation,
Stores information on these operations, manages the operation of test pattern signals based on information on simulation conditions out of information on simulation operations, and manages information on simulation operations based on information on application of test pattern signals To be executed by a computer.

Here, the computer that executes the program stored in the storage medium performs the same operation as the IC test system according to the first aspect. As a result, an IC test system that can improve the work efficiency of the worker and effectively use the storage area of the entire IC test system is realized.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. First, the configuration will be described. FIG. 1 shows an IC test system 10 according to the present invention.
FIG. 3 is a block diagram showing a configuration of a main part of FIG. As shown in FIG. 1, the IC test system 10 includes an input device 110, an output device 120, a management device 11, a control device 140, and an IC test device 150.

In FIG. 1, the components denoted by the same reference numerals as those in FIG. 5 are substantially the same as the components of the IC test apparatus 100, and therefore, detailed description thereof will be omitted.

As shown in FIG. 1, the management device 11 includes a management unit 12, an analysis unit 13, and a microprogram simulator 14, and includes hardware and register information 1.
5 is stored.

The management section 12 has a management program 12a, and manages each section constituting the management apparatus 11 according to a management procedure described in the management program 12a. More specifically, the management unit 12 always manages each operation of the IC test apparatus 150 and the microprogram simulator 14 described later. In addition, the management unit 12 controls the IC test apparatus 1
50 and the control device 140 are detachably connected.

The analysis unit 13 has an application program 13a, and analyzes the test results of the IC test apparatus 150 and the simulation results of the microprogram simulator 14 described later according to the analysis procedure described in the application program 13a. And
The analysis result is output to the output device 120.

The microprogram simulator 14
The operation of the IC test apparatus 150 is simulated, and a control signal for updating a part of the hardware register information 15 described later is output to the management unit 12 based on the simulation.

The hardware register information 15 is an IC
It includes information on test conditions and results of the test apparatus 150 and simulation conditions and results of the microprogram simulator 14.

The IC test system 10 has a hardware
The greatest feature is that a storage management method is adopted in which the register information 15 can be shared by the microprogram simulator 14 and the analysis unit 13.

Hereinafter, the contents of the storage management processing of the IC test system 10 will be described with reference to the flowchart shown in FIG. First, microprogram simulator 1
4 is started, the management unit 12 causes the management device 11
It is determined whether or not the control device 140 and the IC test device 150 are connected to each other (step S200).

When the control device 140 and the IC test device 150 are not connected to the management device 11 (step S20)
0; NO), the management unit 12 presents the output device 120 with a selection menu (not shown) for selecting whether to share the hardware register information 15 between the analysis unit 13 and the microprogram simulator 14. Let it. The worker
This selection menu can be selected via the input device 10 (step S201).

When the operator sets the hardware register information 15
If the user selects not to share the information on the test conditions and results and the information on the simulation conditions and results stored in the memory (step S201; NO), the analysis unit 13 and the microprogram simulator 14 use the hardware / register information. The information on the test conditions and the results stored in the storage unit 15 and the information on the simulation conditions and the results are not shared (step S202).

In this case, the management unit 12 individually manages information on test conditions and results of the analysis unit 13 and information on simulation conditions and results of the microprogram simulator 14 without referring to the management program 12a. Here, the selection in step S201 can be redone.

That is, the microprogram simulator 1
4 controls switching of whether or not the information on the simulation conditions and results of the microprogram simulator 14 and the information on the test conditions and results of the IC test apparatus 150 among the hardware and register information 15 are shared with the analysis unit 13. You can also. This switching control is performed based on a selection menu (not shown) displayed on the output device 120, and the operator can again select whether to share the hardware register information 15 or not.

On the other hand, when the operator specifies that the hardware register information 15 is shared (step S20).
1; YES) in the IC test system 10
The analysis unit 13 and the microprogram simulator 14 share the hardware / register information 15 (step S203).

That is, in this case, among the hardware register information 15 stored in the management device 11, information on the simulation conditions and results of the microprogram simulator 14 and information on the test conditions and results of the IC test device 150 are included. , Shared by the analysis unit 13 and the microprogram simulator 14.

The management unit 12 manages one of the information on the simulation condition and the result of the microprogram simulator 14 and the information on the test condition and the result of the IC test apparatus 150 and manages the other information. However, in this case, the operator can again select whether to share the hardware register information 15 or not.

On the other hand, if the control device 140 and the IC test device 150 are connected to the management device 11 (step S200; YES), the management unit 12 sends the hardware of the hardware / register information 15 to the output device 120. A selection menu (not shown) for selecting whether to share the wear information, that is, information on test conditions and simulation conditions, between the analysis unit 13 and the microprogram simulator 14 is presented. When the control device 140 and the IC test device 150 are connected to the management device 11, the register information in the hardware register information 15, that is, the test result and the Information on the simulation result is stored in the analysis unit 13 and the microprogram simulator 14.
Not shared with. The operator selects this selection menu,
Can be selected via the input device 110 (step S20
4).

When the operator selects not to share the hardware information (step S204; NO), the analysis is performed in the same manner as when the operator selects not to share the hardware register information 15 in step S202. The unit 13 and the microprogram simulator 14 do not share information on test conditions and results stored in the hardware register information 15 and information on simulation conditions and results (step S201).

In this case, the management unit 12 individually manages information on test conditions and results of the IC test apparatus 150 and information on simulation conditions and results of the microprogram simulator 14 without referring to the management program 12a. Here, the selection in step S204 can be redone.

That is, the microprogram simulator 1
The control unit 4 can control whether the hardware information in the hardware register information 15 is shared with the analysis unit 13 or not. This switching control is performed by the output device 1.
20 is performed based on a selection menu (not shown) displayed on the hardware register information 15 again.
Can be selected whether to share hardware information.

The operator registers the hardware register information 15
If it is specified that the hardware information is to be shared (step S204; YES), the analysis unit 13 and the microprogram simulator 14 in the IC test system 10 execute the hardware register information 15 in the hardware register information 15. Share the wear information (step S20)
5).

In this case, the hardware information stored in the management device 11, that is, the information on the simulation conditions of the microprogram simulator 14,
Information on the test conditions of the C test apparatus 150 is shared by the analysis unit 13 and the microprogram simulator 14.

Then, based on one of the information on the simulation conditions of the microprogram simulator 14 and the information on the test conditions of the IC test apparatus 150, the management unit 12 manages the other information.
However, also in this case, the operator can redo the selection of whether to share the hardware information in the hardware register information 15 in step S204.

Next, in accordance with the flowchart shown in FIG.
The operation of the IC test system 10 when sharing the hardware register information 15 with the IC test system 10 will be described.

First, the microprogram simulator 1
4 performs translation processing of the microprogram input via the input device 110 (step S40)
0), the program code of the microprogram is converted into a code format executable by the microprogram simulator 14, and a simulation according to the converted program code is executed.

In the simulation process, the microprogram simulator 14 generates a control signal indicating that a part (simulation condition and / or test condition) of the hardware register information 15 should be changed (step S401), and The control signal is transmitted to the management unit 12 (step S402).

The management unit 12 that has received the control signal changes a part of the hardware register information 15 according to the control signal, and sends the change result to the microprogram simulator 14, the IC test apparatus 150, and the analysis unit 13. Give feedback in real time.

Here, the analysis unit 13 always waits for a response from the management unit 12 in real time (step S).
403). When receiving the change result of the hardware register information 15 from the management unit 12 (step S403 YES), the analysis unit 13 analyzes the change result (step S404) and outputs the analysis result to the output device 120 (step S404). S405).

On the other hand, when the analysis unit 13 does not receive the change result from the management unit 12 (step S403; NO), that is, while waiting for a response from the management unit 12,
The simulation is continuously performed by the microprogram simulator 14.

Here, when a part of the hardware register information 15 is changed according to the contents of the simulation (step S406; YES), the microprogram simulator 14 sequentially generates a control signal to that effect (step S406; YES). Along with step S407), the control signal is sequentially transmitted to the management unit 12 (step S408).

On the other hand, when a part of the hardware register information 15 is not changed (step S406; NO),
The microprogram simulator 14 determines whether the microprogram has been changed by the operator via the input device 110 (step S409).

When the change of the microprogram is detected (step S409; YES), the process returns to step S40.
Returning to 0, the microprogram simulator 14 translates the changed microprogram. On the other hand, when the change of the microprogram is not detected (step S409; NO), the microprogram simulator 14 outputs the evaluation result of the microprogram to the output device 120 (step S410), and ends the simulation.

As described above, according to the IC test system 10 in the embodiment, the operation and results of the IC test device 150 and the microprogram simulator 14 are managed by the management device 11, and the IC test device 1
Simulation conditions and results of the microprogram simulator 14 are managed based on the 50 test conditions and results.
IC test equipment 150 based on the simulation conditions
Is not required, so that it is not necessary to individually set the simulation conditions and results and the test conditions and results of the IC test apparatus 150 as in the related art. Therefore, I
The storage area of the entire C test system 10 can be effectively used.

The simulation conditions and results obtained by the IC test system 10 in the above embodiment are
The information relating to the test conditions and results of the IC test apparatus 150 is analyzed by the analysis unit 13 and the microprogram simulator 1.
4, since it is possible to immediately provide feedback to the IC test apparatus 150 in real time, the number of operations of the operator required for the IC test can be reduced, and the work efficiency of the operator can be improved.

Further, the control unit 140 is different from the control unit 140 in that the control device 140 and the IC test device 150 are not connected to the control unit 12.
If the operator selects not to share the hardware / register information 15, the information on the test conditions and results of the IC test apparatus 150 and the information on the simulation conditions and results of the microprogram simulator 14 are stored in the microprogram. Since the simulator 14 and the analyzer 13 are set so as not to be shared, even if the IC test apparatus 150 is not connected, the IC test apparatus 1
The 50 test conditions and results and the simulation conditions and results of the microprogram simulator 14 are individually managed, so that only the microprogram simulator 14 can be operated independently.

Further, the microprogram simulator 1
4 switches whether or not the information on the simulation conditions and results of the microprogram simulator 14 and the information on the test conditions and results of the IC test apparatus 150 in the hardware / register information 15 are shared with the analysis unit 13. Since it has a control function, for example, even if only the simulation is performed without connecting the IC test apparatus 150 in advance, the IC test apparatus 150 is connected as necessary and the simulation is performed on the connected IC test apparatus 150. Feedback on conditions and results. Therefore, the operability of the IC test system 10 is improved,
The work efficiency of the worker can be further increased.

Further, when the hardware register information 15 is changed, the changed hardware register information 15 is sent to the analyzing unit 13, the microprogram simulator 14, and the IC testing device 150 by the management unit 12.
Since the simulation conditions are fed back in real time, the simulation conditions can be immediately reflected in the actual test conditions of the IC test apparatus 150. At the time of the simulation, information on the actual test conditions and results of the IC test apparatus 150 can be immediately taken into consideration. Therefore,
It is possible to reduce the number of operations of the operator required for the IC test, and it is possible to further improve the operation efficiency of the operator.

Further, the management unit 12 controls the IC testing device 150
If the analysis unit 13 and the microprogram simulator 14 do not share the information about the test conditions and results of the above and the information about the simulation conditions and results of the microprogram simulator 14, the management program 1
Since the simulation conditions and results are managed without referring to 2a, in this case, instead of the management program 12a,
By referring to a conventional program that individually manages only simulation conditions and results, the IC
The test system 10 can be realized at low cost by making minimal design changes to an existing conventional IC test system.

The description in the present embodiment is a preferred example of the IC test system according to the present invention, and the present invention is not limited to these.

For example, the IC test system includes (G
It is preferable to provide a UI (Graphical User Interface). With such a configuration, the selection menu can be easily specified using a pointing device such as a mouse, so that the work efficiency of the operator can be further improved.

In addition, the detailed configuration and operation of the IC test system 10 can be appropriately changed without departing from the spirit of the present invention.

[0083]

According to the first and ninth aspects of the present invention, it is possible to improve the work efficiency of the worker and to effectively utilize the storage area as a whole in the IC test system.

According to the fifth aspect of the present invention, even if the test signal applying means is not connected, the test conditions and results of the test signal applying means and the simulation conditions and results of the simulation means are individually managed. In addition, it is possible to provide a highly convenient IC test system that can operate only the simulation means independently.

According to the sixth aspect of the present invention, even if the simulation means is operated independently without connecting the test signal applying means in advance, the test signal applying means is connected and connected as necessary. Since the simulation conditions and results of the simulation means can be fed back to the test signal applying means, the operability of the IC test system can be improved, and the work efficiency of the operator can be further improved.

According to the present invention, the simulation conditions and results can be immediately reflected in the actual operation of the test signal applying means. Further, at the time of simulation by the simulation means, the actual operation result of the test signal applying means can be immediately determined. As a result, the number of operations of the operator required for the IC test can be reduced, and the working efficiency of the operator can be further improved.

According to the eighth aspect of the present invention, since the management means can be provided with a management program of the conventional specification, the IC test system can be reduced to a minimum with the existing IC test system of the conventional specification. It can be realized at low cost only by making a limited design change.

[Brief description of the drawings]

FIG. 1 is an IC test system 1 according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a main part configuration of No. 0.

FIG. 2 is a flowchart showing storage management of the IC test system 10 shown in FIG.

3 is a diagram showing a state in which a control device 140 and an IC test device 150 are removed from a management device 11 in the IC test system 10 shown in FIG.

FIG. 4 is a flowchart showing an operation of the IC test system 10 shown in FIG.

FIG. 5 is a diagram showing an IC test system 100 according to the related art.

6 is a flowchart showing an operation of the IC test system 100 shown in FIG.

[Explanation of symbols]

 10, 20, 100 IC test system 11, 130 Management device 12, 131 Management unit 12a, 131a Management program 13, 132 Analysis unit 13a, 132a Application program 14, 134 Microprogram simulator 15, 133, 151 Hardware / register information 110 Input device 120 Output device 140 Control device 141 Control program 150 IC test device

Claims (9)

[Claims] 1. A test signal applying means for applying a test pattern signal to an IC under test based on a test program, a simulation means for simulating an operation of the test signal applying means based on a simulation program, and the test signal applying means And a management unit for managing each operation of the test signal applying unit and the simulation unit based on a management program and storing information on the operation of each unit. An IC test system, wherein the management unit manages the other information based on one of information on a simulation operation of the simulation unit and information on an operation of the test signal application unit. 2. The IC test system according to claim 1, wherein the information on the simulation operation of the simulation means is a simulation result, and the information on the operation of the test signal applying means is an operation result. 3. The IC test system according to claim 1, wherein the information on the simulation operation of the simulation means is a simulation condition, and the information on the operation of the test signal applying means is an operation condition. 4. When the test signal applying means is connected, the managing means manages operating conditions of the test signal applying means based on simulation conditions of the simulation means, and the test signal applying means controls the operating conditions of the test signal applying means. 4. The method according to claim 1, wherein when not connected, the simulation conditions and the simulation results of the simulation means are managed based on the operation conditions and the operation results of the test signal applying means.
C test system. 5. The storage device according to claim 1, wherein the management unit stores information on an operation of the test signal application unit and information on a simulation operation of the simulation unit in accordance with whether or not the test signal application unit is connected. 2. The IC test system according to claim 1, further comprising storage area setting means for appropriately setting whether the storage area is a shared storage area or an individual storage area. 6. The simulation means controls switching between a storage area for information related to an operation set by the management means and a separate storage area based on the simulation program. The IC test system according to claim 5, wherein: 7. When the management unit shares a storage area for storing information relating to the operation of the test signal applying unit and information relating to the simulation operation of the simulation unit, the management unit includes information of the operation relating to each unit. 7. The IC test system according to claim 5, wherein when at least one of them is changed, information on the changed operation is returned in real time to said test signal applying means and said simulation means. 8. The management means, when not sharing a storage area for storing information on the operation of the test signal applying means and information on the simulation operation of the simulation means, without referring to the management program. 8. The IC test system according to claim 5, wherein information on a simulation operation is managed. 9. A storage medium storing a computer-executable program for controlling the operation of an IC test system, comprising: a computer-executable program code for applying a test pattern signal to an IC under test. A computer-executable program code for simulating the operation of applying the test pattern signal; and constantly managing each operation of applying the test pattern signal to the IC under test and the simulation, and storing information on those operations. Based on one of a program code executable by a computer for storing, information on the operation of the simulation, and information on an application operation of the test pattern signal, a computer for managing the other information is executable. Program that contains A storage medium characterized by being stored.