JP2002170893A5 - - Google Patents

Description

Patent application title: Nonvolatile semiconductor memory device and method of manufacturing the same

[0001]
Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same .

[0002]
[Prior Art]
The configuration of a conventional non-volatile semiconductor memory device will be described with reference to FIGS. This conventional nonvolatile semiconductor memory device is a NAND cell type EEPROM which is one of electrically programmable and erasable nonvolatile semiconductor memory devices, and the equivalent circuit of this EEPROM is shown in FIG. A cross-sectional view taken along the line A-A 'shown in FIG. 11 and shown in FIG. 11 is shown in FIG. 12, and a cross-sectional view taken along the line B-B' along the cut line shown in FIG. Show.
The NAND cell type EEPROM has a plurality of NAND cell units 40 ₁₁ , 40 ₁₂ , 40 ₂₁ and 40 ₂₂ arranged in a matrix as shown in FIG. Each NAND cell unit 40 _ij (i = 1, 2, j = 1, 2) has a plurality of memory cells MC ₁ , MC ₂ ,... MC _n . Each memory cell MC _i (i = 1,... N) is formed of a transistor having a stack structure in which the floating gate 6 and the control gate 8 are stacked on the semiconductor substrate via the insulating film 7 (FIGS. 10 and 12). reference). The plurality of memory cells MC ₁ ,..., MC _n in each NAND cell unit are connected in series so that adjacent ones share the source and drain.

[0006]
[Problems to be solved by the invention]
As described above, in the conventional nonvolatile semiconductor memory device , the memory cell is covered with a silicon nitride film, which has the following problems.
First, in the EEPROM, since the carrier of the gate insulating film 5 at the time of writing and erasing of data, as shown in FIG. 14 passes, the barrier insulating film 12 portion of the carrier is close to the gate insulating film 5, and the barrier It is trapped at the interface 82 between the insulating film 12 and the silicon oxide film 5a. As a result, carriers of the opposite polarity are induced on the surface of the diffusion layer 9, causing a problem that the parasitic resistance of the diffusion layer 9 increases and the drivability of the transistor decreases. Particularly in the NAND cell type EEPROM, since the memory cells are connected in series via the diffusion layer 9, the influence of the increase in resistance of the diffusion layer 9 is large. Further, as the memory cell is miniaturized, if the dose of the diffusion layer is reduced to reduce the short channel effect, the increase of the above-mentioned parasitic resistance becomes more remarkable, which is a large obstacle to the miniaturization. In FIG. 14, reference numeral 10 denotes a silicon oxide film formed by post-oxidation performed to recover from damage due to gate processing.
In addition, since the barrier insulating film 12 generally contains hydrogen, the hydrogen degrades the gate insulating film 5 in the vicinity of the barrier insulating film 12 , resulting in a problem that the reliability of the transistor is lowered.

[0007]
The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a nonvolatile semiconductor memory device and a method of manufacturing the same which can prevent the deterioration of the driving power and the reliability of transistors as much as possible. I assume.

[0008]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention comprises a plurality of memory cell transistors formed on a semiconductor substrate, and the plurality of memory cell transistors are formed on a gate insulating film formed on the semiconductor substrate and on the gate insulating film. A floating gate electrode, an insulating film formed thereon, and a control gate formed thereon, wherein the plurality of memory cell transistors share a diffusion layer between a source line and a bit line contact And a barrier insulating film connected in series and disposed to cover the upper surface and the side surface of the memory cell transistor, wherein the distance between the insulating film and the barrier insulating film is larger than 3 nm.

[0009]
A method of manufacturing a nonvolatile semiconductor memory device according to the present invention further includes: a plurality of memory cell transistors each having a gate insulating film and a gate electrode formed on a semiconductor substrate; and bit line contacts connected to the semiconductor substrate, In a method of manufacturing a non-volatile semiconductor memory device including a barrier insulating film disposed to cover the upper surface and the side surface of the memory cell transistor, the step of processing the gate electrode, and post oxidation is performed. The method further comprises the steps of: depositing a thick silicon oxide film on the entire surface of the semiconductor substrate; and depositing the barrier insulating film.

[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.
First Embodiment
The configuration of the first embodiment of the nonvolatile semiconductor memory device according to the present invention is shown in FIG. The nonvolatile semiconductor memory device according to the first embodiment is a transistor having a gate electrode of a structure in which floating gate 6 and control gate 8 are stacked via insulating film 7, and is used, for example, as a memory cell of EEPROM. Be In this transistor, the gate electrode is formed on the element region of the semiconductor substrate 2 via the gate insulating film 5 made of, for example, a tunnel oxide film, and becomes a source / drain in the element region of the semiconductor substrate 2 on both sides of the gate electrode. A diffusion layer 9 is provided. Further, this gate electrode is covered with an insulating film 11 made of, for example, silicon oxide, and this insulating film 11 is covered with a barrier insulating film 12 such as a silicon nitride film which becomes a barrier when forming a contact. There is.
In the transistor of the first embodiment, the height h ₁ of the interface 82 between the insulating film 11 on the diffusion layer 9 and the barrier insulating film 12 from the surface of the semiconductor substrate 2 is the gate insulating film 5 The height h ₂ of the interface 84 with the floating gate 6 from the surface of the semiconductor substrate 2 is higher. That is, interface 82 is formed farther from the surface of semiconductor substrate 2 than interface 84.

[0012]
In the present embodiment, as shown in FIG. 15 (a), the semiconductor substrate of the interface 84 the thickness _{d 1} of the insulating film 11 with the height _{h 1} of the interface 82 is higher than the height _{h 2} of the interface 84 The height from the surface of ₂ was larger than h2. However, since the barrier insulating film 12 is formed apart from the gate insulating film 5 as compared with a case alone and greater than the height h ₂ of the distance d ₁ as shown in FIG. 15 (b), the conventional, the The same effect as that of the embodiment can be obtained. Or 15 alone was higher than the height h ₂ of height h ₁ (c), the since the barrier insulating film 12 is formed apart from the gate insulating film 5 as compared with the conventional case, the The same effect as that of the embodiment can be obtained.
The reason is explained. In general, at the time of writing / erasing, carriers exist in the semiconductor substrate 2 and the floating gate 6 with energy sufficient to pass through the tunnel insulating film 5 having a thickness of h ₂ . Therefore, when the height h ₁ and the distance d ₁ is smaller than the thickness h ₂ of the tunnel insulating film 5, in some carriers during writing and erasing the barrier insulating film 12 or the barrier insulating film 12 and the intermediate layer (diffusion It is trapped at the interface between the layer 9 and the film provided between the barrier insulating film 12 (in the present embodiment, the insulating film 11)). By setting the distance d ₁ or the height h ₁ larger than the height h ₂ , part of carriers is trapped in the barrier insulating film 12 or at the interface between the barrier insulating film 12 and the intermediate film 11 at the time of writing and erasing. Can be prevented.

[0013]
With this configuration, it is possible to prevent trapping of part of carriers in the barrier insulating film 12 or at the interface between the barrier insulating film 12 and the intermediate film 11 at the time of writing / erasing, whereby diffusion is achieved. The parasitic resistance of the layer 9 can be prevented from increasing. Therefore, as shown in FIG. 16, the characteristics of the drain current Id with respect to the gate voltage Vg do not change even if writing and erasing are repeated in the nonvolatile semiconductor memory device of this embodiment. However, in the conventional nonvolatile semiconductor memory device, as shown in FIG. 17, Vg-Id characteristics before repeating the writing and erasing a graph g _1, repeated writing and erasing, the carrier at the time of writing and erasing part to be trapped at the interface between the barrier insulating film or the barrier insulating film and the intermediate film, the Vg-Id characteristic deteriorates as the graph g _2.
In the present embodiment, the insulating film 7 is a laminated film including an oxide film, a nitride film, and an oxide film, and an end of the nitride film constituting the insulating film 7 protrudes into the insulating film 11 and (See Figure 1). Therefore, the distance d ₂ between the interface between the insulating film 11 and the barrier insulating film 12 from the end face of the nitride film constituting the insulating film 7 is preferably greater than 3 nm. This is because when the insulating film 7 and the barrier insulating film 12 are in contact with each other, that is, when the distance d ₂ is zero, a leak current is generated between the insulating film 7 and the barrier insulating film 12 and the insulating film 7 is insulated. It is because the sex is deteriorated. If the distance d ₂ greater than 3 nm, the direct tunnel between the insulating film 7 and the barrier insulating film 12 does not occur, insulation property of the insulating film 7 is not lowered.

[0014]
Next, a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIGS. 2 (a) to 2 (d).
First, as shown in FIG. 2A, after forming the gate insulating film 5 in the element region of the semiconductor substrate 2, an insulating film 7 composed of a film 6 of floating gate material, silicon oxide and silicon nitride and silicon oxide, A plurality of gate electrodes are formed in the element region by sequentially forming and patterning a film 8 of control gate material.
Subsequently, implantation of impurities for post-oxidation for recovery of gate processing damage and formation of the diffusion layer 9 is performed (see FIG. 2B). Then, the insulating film 11 is deposited on the entire surface of the semiconductor substrate 2 (see FIG. 2B), and then the barrier insulating film 12 is deposited using the CVD (Chemical Vapor Deposition) method (see FIG. 2C). At this time, the thickness of the insulating film 11, the interface 82 between the insulating film 11 and the barrier insulating film 12 on the diffusion layer 9, the height h ₁ from the surface of the semiconductor substrate 2 is, floating electrode 6 and the gate insulating film Adjustment is made to be higher than the height h ₂ from the surface of the semiconductor substrate 2 at the interface with the element 5.

[0016]
Second Embodiment
Next, the configuration of a second embodiment of the nonvolatile semiconductor memory device according to the present invention is shown in FIG. The nonvolatile semiconductor memory device of the second embodiment is a NAND cell type EEPROM, and an insulating film 11a made of, for example, a silicon oxide film is formed on the side of the gate electrode of the transistor constituting each memory cell. The structure is These memory cells are covered with a barrier insulating film 12 such as a silicon nitride film . Although the barrier insulating film 12 is formed on the diffusion layer 9 of each memory cell of the conventional NAND cell type EEPROM via the silicon oxide film 5a (see FIG. 14), in the present embodiment, the diffusion is The barrier insulating film 12 is directly formed on the layer 9.
And in the present embodiment, as shown in FIG. 4, the thickness t ₁ of the insulating film 11a of the floating gate 6 near it is configured to be thicker than the thickness t ₂ of the gate insulating film 5. By such a configuration, it is possible to carrier during the write and erase operation is prevented as much as possible from reaching the interface between the barrier insulating film 12 and the barrier insulating film 12 and the diffusion layer 9, a diffusion layer The parasitic resistance of 9 can be prevented from increasing. Thus, the reduction of the driving power of the transistor can be prevented as much as possible.

[0017]
Further, since the barrier insulating film 12 is formed apart from the gate insulating film 5 as compared with the conventional case, the gate insulating film 5 can be prevented as much as possible from deteriorating. This can prevent the reliability from being reduced.
Next, a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. 5 (a) to 5 (d).
First, as shown in FIG. 5A, the gate insulating film 5 is formed in the element region of the semiconductor substrate 2, and then the film 6 of floating gate material, the insulating film 7 made of silicon oxide, and the film 8 of control gate material are sequentially By forming and patterning, a plurality of gate electrodes are formed in the element region.
Subsequently, implantation of impurities for post-oxidation for recovery of gate processing damage and formation of the diffusion layer 9 is performed (see FIG. 5B). Then, a silicon oxide film 11 is deposited on the entire surface of the semiconductor substrate 2 (see FIG. 5 (b)) .
Next, as shown in FIG. 5C, anisotropic etching such as RIE (Reactive Ion Etching) is performed to leave the silicon oxide film only on the side surface of the gate electrode and form the insulating film 11a made of the silicon oxide film.
Next, as shown in FIG. 5D, a barrier insulating film 12 is deposited on the entire surface of the substrate using a CVD method. Thereafter, an interlayer insulating film 22 is deposited on the entire surface of the substrate 2, and then various contacts such as contacts 44 are formed in the interlayer insulating film 22, and a wiring BL ₂ is formed on the interlayer insulating film 22 to complete the EEPROM. Do. The diffusion layer 9 may be formed after the formation of the insulating film 11a, or may be an LDD structure.

[0018]
It goes without saying that the non-volatile semiconductor memory device manufactured by this manufacturing method also exhibits the same effect as that of the second embodiment.
Third Embodiment
Next, FIG. 6 shows the configuration of the third embodiment of the nonvolatile semiconductor memory device according to the present invention. The nonvolatile semiconductor memory device of the third embodiment is a NAND cell type EEPROM, and in the NAND cell type EEPROM of the second embodiment, the diffusion layer 9 between the memory cells and the barrier insulating film 12 are formed. and it has a form with the structure of the conductive film 15 to and between the barrier insulating film 12 such as a diffusion layer a diffusion layer SL ₁ and the silicon nitride film of the contact base. The height of the interface between the conductor film 15 and the barrier insulating film 12 from the surface of the semiconductor substrate 2 is adjusted by adjusting the film thickness of the conductor film 15 to the floating gate 6 and the gate insulating film 5. And the height of the interface from the surface of the semiconductor substrate 2.
With this configuration, it is possible to prevent, as much as possible, that carriers passing through the gate insulating film 5 during the write and erase operations are trapped at the interface between the barrier insulating film 12 and the conductor film 15. This makes it possible to prevent the parasitic resistance of the diffusion layer 9 from increasing, and to prevent the reduction of the driving power of the transistor as much as possible.

[0019]
Further, since the barrier insulating film 12 is formed apart from the gate insulating film 5 as compared with the conventional case, deterioration of the gate insulating film 5 can be prevented as much as possible. This can prevent the reliability from being reduced.
When the gate insulating film 5 contains nitrogen, it is generally difficult to form an oxide film on the diffusion layer 9 by post oxidation or the like to increase the thickness of the oxide film. In such a case, if configured as in any of the first to third embodiments of the present invention, the barrier insulating film 12 can be formed apart from the gate insulating film 5, and the transistor can be formed. Thus, it is possible to prevent the reduction of the driving force and the deterioration of the gate insulating film. This can prevent the reliability from being reduced.
Next, a method of manufacturing the nonvolatile semiconductor memory device according to the third embodiment will be described with reference to FIGS. 7 (a) to 7 (d).
First, as shown in FIG. 7A, the gate insulating film 5 is formed in the element region of the semiconductor substrate 2, and then the film 6 of floating gate material, the insulating film 7 made of silicon oxide, and the film 8 of control gate material are sequentially By forming and patterning, a plurality of gate electrodes are formed in the element region.
Subsequently, implantation of impurities for post-oxidation for recovery of gate processing damage and formation of the diffusion layer 9 is performed (see FIG. 7B). Then, the insulating film 11 is deposited on the entire surface of the semiconductor substrate 2 (see FIG. 7B).

[0020]
Next, as shown in FIG. 7C, anisotropic etching such as RIE (Reactive Ion Etching) is performed to form an insulating film 11a made of a silicon oxide film on the side surface of the gate electrode. The insulating film 11 a is preferably thicker than the gate insulating film 5.
Subsequently, silicon is selectively grown on the diffusion layer 9, and an impurity of the same conductivity type as that of the diffusion layer 9 is implanted into the grown silicon to form a conductor film 15 (see FIG. 7C). The film thickness of the conductor film 15 is preferably about the same as the depth of the diffusion layer 9, for example, about 3 nm, and the impurity concentration is also about the same as that of the diffusion layer 9, for example 1.0 × 10 ²⁰ cm ^{− 3} is preferable.
Next, as shown in FIG. 7D, a barrier insulating film 12 is deposited on the entire surface of the substrate using a CVD method. Thereafter, an interlayer insulating film 22 is deposited on the entire surface of the substrate 2, and then various contacts such as contacts 44 are formed in the interlayer insulating film 22 and a wiring BL ₂ is formed on the interlayer insulating film 22 to complete an EPROM. Do. The formation of the diffusion layer 9 may be performed after the formation of the insulating film 11a, or may be an LDD structure.
Similarly to the third embodiment, the non-volatile semiconductor memory device manufactured by this manufacturing method can prevent the reduction of the driving power of the transistor and the deterioration of the gate insulating film 5. Further, since the conductor film 15 is an impurity region of the same conductivity type as the diffusion layer 9, the conductor film 15 becomes a source / drain. Since the source and drain are at a high position with respect to the channel (the surface of the semiconductor substrate 2 below the gate insulating film 5), the short channel effect can be suppressed.

[0021]
In the third embodiment, the silicon film 15 to which the impurity is added is formed not only on the diffusion layer 9 between the memory cells but also on the diffusion layer SL ₁ to which the contact 44 is connected (see FIG. See Figure 6). That is, the same conductivity type impurity as the diffusion layer is added to the silicon formed between the memory cells and on the diffusion layer at the bottom of the contact (see 1 in the table of FIG. 8). However, by adding an impurity to the silicon formed on the diffusion layer SL _1, the silicon formed on the diffusion layer 9 between the memory cells it is not necessary to add an impurity (2 in the table of FIG. 8) reference ). Also in this case, since the barrier insulating film 12 is formed apart from the gate insulating film 5, it is possible to prevent the reduction of the driving force of the transistor and the deterioration of the gate insulating film 5.
Alternatively, the film made of silicon grown on the diffusion layer may be silicided without adding an impurity (see 3 in the table of FIG. 8).
In the third embodiment, the conductive film 15 is thicker than the film thickness of the gate insulating film 5 and the surface of the semiconductor substrate 2 at the interface between the conductive film 15 and the barrier insulating film 12 is The height from the top is higher than the height from the surface of the semiconductor substrate 2 at the interface between the floating gate 6 and the gate insulating film 5. However, when the conductor film 15 is made of metal, the gate insulation is It can be thinner than the film thickness of the film 5. When the conductor film 15 is made of, for example, a semiconductor film made of silicon doped with an impurity, the impurity concentration is increased, and the electric conductor film 15 is trapped at the interface between the conductor film 15 and the barrier insulating film 12 . If the conductor film 15 is formed to such a thickness that the depletion layer formed in the conductor film 15 by the carrier does not reach the diffusion layer 9, the same effect as that of the third embodiment can be obtained. In addition, the film thickness of the conductor film 15 can be made thinner than that of the third embodiment. In this case, the film thickness of the insulating film 11a is preferably thicker than that of the gate insulating film.

Brief Description of the Drawings
FIG. 1 is a cross-sectional view showing a configuration of a first embodiment of a nonvolatile semiconductor memory device according to the present invention.
FIG. 2 is a process sectional view showing the method of manufacturing the nonvolatile semiconductor memory device of the first embodiment.
FIG. 3 is a cross-sectional view showing the configuration of a second embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 4 is a cross-sectional view for explaining the features of the second embodiment.
FIG. 5 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device of the second embodiment.
FIG. 6 is a cross-sectional view showing a configuration of a third embodiment according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device of the third embodiment.
FIG. 8 is a view for explaining a modification of the third embodiment.
FIG. 9 is a cross-sectional view for explaining a modification of the first to third embodiments.
FIG. 10 is an equivalent circuit diagram of a NAND cell type EEPROM.
11 is a layout diagram of the NAND cell type EEPROM shown in FIG.
12 is a cross-sectional view taken along the line A-A 'shown in FIG.
13 is a cross-sectional view taken along the line B-B 'shown in FIG.
FIG. 14 is a diagram for explaining problems of the conventional nonvolatile semiconductor memory device .
FIG. 15 is a view for explaining the features of the present invention.
FIG. 16 is a graph showing the characteristics of the present invention.
FIG. 17 is a graph showing conventional characteristics.
FIG. 18 is a view for explaining the constitution of an intermediate film of the present invention.
[Description of the code]
2 ... Semiconductor substrate,
4 ... element isolation region (insulating film),
5: Gate insulating film,
6 ... floating gate,
7 ... Insulating film,
8: Control gate,
9: Diffusion layer,
11: Insulating film,
12: Barrier insulating film

Claims (14)

A nonvolatile semiconductor memory device comprising a plurality of memory cell transistors formed on a semiconductor substrate,
The plurality of memory cell transistors include a gate insulating film formed on a semiconductor substrate, a floating gate electrode formed thereon, an insulating film formed thereon, and a control gate formed thereon Equipped
The plurality of memory cell transistors are connected in series, sharing a diffusion layer between the source line and the bit line contact,
A barrier insulating film disposed to cover the top and side surfaces of the memory cell transistor;
A nonvolatile semiconductor memory device characterized in that a distance between the insulating film and the barrier insulating film is larger than 3 nm. The nonvolatile semiconductor device according to claim 1, wherein the insulating film has a laminated structure of a silicon oxide film and a silicon nitride film, and a distance between the silicon nitride film and the barrier insulating film is larger than 3 nm. Storage device. 2. The nonvolatile semiconductor memory according to claim 1, wherein said nonvolatile semiconductor memory device has a select transistor, and a diffusion layer of said memory cell is connected to said bit line contact via said select transistor. apparatus. 2. The non-volatile semiconductor storage device according to claim 1, wherein the barrier insulating film is made of a silicon nitride film, and a silicon oxide film is disposed between the insulating film and the barrier insulating film. A nonvolatile semiconductor memory device comprising a plurality of memory cell transistors formed on a semiconductor substrate,
The plurality of memory cell transistors include a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and diffusion layers disposed on both sides of the gate electrode.
The plurality of memory cell transistors are connected in series to share the diffusion layer between a source line and a bit line contact,
A barrier insulating film disposed to cover the top and side surfaces of the memory cell transistor;
The distance between the side surface of the gate electrode of the memory cell transistor and the barrier insulating film is larger than the thickness of the gate insulating film, and the distance from the surface of the semiconductor substrate to the barrier insulating film is the gate insulating film. A nonvolatile semiconductor memory device characterized by having a film thickness smaller than that. 6. The non-volatile semiconductor storage device according to claim 5, wherein an intermediate film is disposed between the gate electrode and the barrier insulating film. 6. The nonvolatile semiconductor memory according to claim 5, wherein the nonvolatile semiconductor memory device has a select transistor, and the diffusion layer of the memory cell is connected to the bit line contact via the select transistor. apparatus. 7. The non-volatile semiconductor storage device according to claim 6, wherein the intermediate film is made of a silicon oxide film, and the barrier insulating film is made of a silicon nitride film. A nonvolatile semiconductor memory device comprising a plurality of memory cell transistors and a selection transistor formed on a semiconductor substrate,
The memory cell transistor and the selection transistor include a gate insulating film formed on a semiconductor substrate, gate electrodes disposed thereon, and diffusion layers disposed on both sides thereof.
The memory cell transistor includes a barrier insulating film connected to a bit line contact via the selection transistor and formed to cover the upper surface and the side surface of the selection transistor, and the side surface of the gate electrode of the selection transistor The distance from the barrier insulating film is greater than the thickness of the gate insulating film of the selection transistor, and the distance from the surface of the semiconductor substrate is A nonvolatile semiconductor memory device characterized in that a distance to a barrier insulating film is smaller than a film thickness of a gate insulating film of the selection transistor. 10. The non-volatile semiconductor storage device according to claim 9, wherein an intermediate film is disposed between the gate electrode of the select transistor and the barrier insulating film. 11. The nonvolatile semiconductor memory device according to claim 10, wherein the intermediate film is made of a silicon oxide film, and the barrier insulating film is made of a silicon nitride film. A plurality of memory cell transistors each having a gate insulating film and a gate electrode formed on a semiconductor substrate; and bit line contacts connected to the semiconductor substrate, and arranged to cover the top and side surfaces of the memory cell transistors. A method of manufacturing a non-volatile semiconductor memory device comprising the
Processing the gate electrode;
Post-oxidation to deposit a silicon oxide film thicker than the gate insulating film over the entire surface of the semiconductor substrate;
Depositing the barrier insulating film;
A method of manufacturing a non-volatile semiconductor memory device, comprising: 13. The method of manufacturing a nonvolatile semiconductor memory device according to claim 12, further comprising the step of depositing an interlayer insulating film over the entire surface of the semiconductor substrate after the step of depositing the barrier insulating film. 13. The method according to claim 12, wherein the barrier insulating film is formed of a silicon nitride film.