JP2002164535A - Insulated gate semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: In an insulated gate semiconductor device and a method of manufacturing the same, an increase in parasitic capacitance accompanying the adoption of the damascene method is suppressed. SOLUTION: A double side wall comprising a first side wall 2 on the outside and a second side wall 3 on the inside, and a side wall facing the second side wall has a shape bulging inward, and a gate is provided. The insulating film 4 also extends at least on the opposing side wall of the second side wall 3, and a gate electrode 5 is provided in the gap between the opposing second side walls 3 via the gate insulating film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly, to a structure for suppressing an increase in parasitic capacitance due to a gate forming process by a damascene method. The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in the field of information communication, with the increase in the amount of data to be communicated, it has become an important issue to improve the processing capability of semiconductor integrated circuit devices used in information communication equipment.

In order to meet such a demand, it is necessary to operate the semiconductor integrated circuit device at high speed. For this purpose, a MOSFET (Met) constituting the semiconductor integrated circuit device is required.
alOxide Semiconductor FE
T) and MISFET (Metal Insulator)
Insulated gate FET (IGFET: Insulated Gate) such as Semiconductor FET
It is indispensable to increase the driving current of the FET and to reduce the parasitic capacitance.

Conventionally, in order to meet the demand for higher speed, IGFETs have been made finer in accordance with a scaling law. However, silicon oxide films conventionally used for gate insulating films and gate electrode materials have been used. With polysilicon, physical limitations have been seen in thinning along with miniaturization due to increased leakage current and depletion of gate electrodes.

In order to solve such a problem, attempts have been made to employ a metal gate and a high dielectric gate insulating film. However, high-temperature processes such as activation annealing of source / drain regions formed by ion implantation are used. There is a problem that is weak.

That is, the high-temperature process causes penetration of the elements constituting the metal gate, thereby increasing the gate leakage. In addition, there is a problem that the interface between the silicon substrate and the high-dielectric gate insulating film has a high dielectric constant. And Si
There is a problem that a transition region made of a mixture with the O ₂ film is formed by a thermal reaction, and the equivalent effective oxide film thickness fluctuates.

In order to solve such a problem associated with the high-temperature process, a so-called damascene method in which a high-dielectric gate insulating film and a metal gate are formed in a self-aligned manner with respect to a source / drain region after high-temperature annealing is performed. IGFETs formed using the conventional damascene method will be described with reference to FIG.

FIG. 7A is a schematic cross-sectional view of a conventional IGFET, in which an element isolation oxide film 32 is formed on an n-type silicon substrate 31 in the same manner as in the conventional manufacturing process. B is implanted into a predetermined region to form a p-type well region 33, and then a channel doped region is formed by ion implantation.

Next, after a dummy gate oxide film 34 is formed on the entire surface by thermal oxidation, the dummy gate oxide film 34 is formed.
A dummy gate electrode (not shown) made of polycrystalline silicon is formed through the gate electrode, As ions are implanted using the dummy gate electrode as a mask to form an n ⁺ -type shallow source / drain region 35, and then the dummy gate electrode is formed. After the sidewalls 36 are formed on the side walls of the electrodes, the n ⁺ -type source / drain regions 37 are formed again by implanting As ions, and then annealing for activating the implanted As is performed.

Then, after an interlayer insulating film 38 such as a TEOS-NSG film is deposited on the entire surface, the interlayer insulating film 38 is polished by CMP (chemical mechanical polishing) until the dummy gate electrode is exposed, and the surface is polished. Is flattened.

Next, the dummy gate electrode is selectively removed by etching. In the subsequent cleaning step, the dummy gate oxide film 34 immediately below the dummy gate electrode was used.
Disappears, and the surface of the p-type well region 33 is exposed.

Next, a Ta ₂ O ₅ film for forming a gate oxide film 39 on the entire surface and a TiN film 4 serving as a barrier metal
0 and a W film 41 are sequentially deposited, and then patterned by a normal photolithography process to form a gate electrode 42 composed of a TiN film 40 and a W film 41 and a gate oxide film 39 composed of a Ta ₂ O ₅ film. Is formed, the basic configuration of the IGFET is completed.

As described above, when the damascene method is used, the n ⁺ type shallow source / drain regions 35 and n ⁺
Since the gate oxide film 39 and the gate electrode 42 are formed after the activation annealing step of the mold source / drain regions 37, the penetration of W and transition regions do not occur.

[0014]

However, in the conventional IGFET using the damascene method, in the step of removing the dummy gate electrode and the subsequent cleaning step, the side wall of the side wall 36 is etched and the opening is formed in the dummy. The overlap between the gate electrode 42 and the n ⁺ -type shallow source / drain region 35 is longer than that of a Si gate IGFET employing a normal process, thereby increasing the parasitic capacitance and increasing the signal capacity. Since there is a problem that the delay becomes large, this situation will be described with reference to FIG.

FIG. 7B is an enlarged view of the circle shown by the broken line in FIG. 7A. As in the conventional case, the parasitic capacitance C ₁ via the side wall 36 is reduced. other parasitic capacitance C ₂ is generated between the projecting portion of the n ⁺ -type shallow source and drain regions 35, parasitic capacitance C ₂ between the overhanging portion of the n ⁺ -type shallow source and drain regions 35 This causes an increase in parasitic capacitance.

The gate oxide film 39 is made of Ta ₂ O.
_Since a high dielectric film such as ₅ is used, the parasitic capacitances C ₁ and C
There is a problem that the increase of ₂ is further emphasized, and the merit of speeding up by increasing the drive current is offset.

Accordingly, it is an object of the present invention to suppress an increase in parasitic capacitance due to the adoption of the damascene method.

[0018]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1 In order to achieve the above object, the present invention relates to an insulated gate semiconductor device,
And a second side wall 3 on the inner side, and a double side wall having a shape in which the opposite side wall of the second side wall 3 swells inward, and the gate insulating film 4 is formed of at least the second side wall 3. And a gate electrode 5 is provided in a gap between the opposing second side walls 3 with a gate insulating film 4 interposed therebetween.

As described above, by providing the double side wall having the shape in which the opposing side wall of the second side wall 3 bulges inward, the gate electrode 5 and the source
The amount of overlap of the drain region with the overhang can be reduced, thereby reducing the parasitic capacitance.

In this case, the parasitic capacitance is the capacitance of a capacitor using the second side wall 3 as a dielectric film. Therefore, in order to reduce the parasitic capacitance, the dielectric constituting the second side wall 3 must be It is preferable to use a dielectric having a relative dielectric constant of 3.9 or less, such as a high-temperature oxide film (HTO) or a low-temperature oxide film (LTO) having a lower dielectric constant than the thermal oxide film.

In order to reduce the equivalent gate insulating film thickness, the dielectric constituting the gate insulating film 4 has a dielectric constant higher than that of a thermal oxide film, such as Ta ₂ O ₅ , having a dielectric constant of 3 or more. Desirably, the dielectric is higher than 0.9.

As a manufacturing method, a source / drain region 6 is formed using a dummy gate insulating film and a dummy gate structure provided on a semiconductor substrate 1, and then an interlayer insulating film 8 is deposited and planarized. Then, after removing the dummy gate structure to form a gate opening, a sidewall 3 is formed in the gate opening, and a gate electrode 5 is formed in the gate opening with a gate insulating film 4 interposed therebetween. And The semiconductor substrate in the present invention means a semiconductor wafer itself, a well region, an epitaxial layer provided on the substrate, and the like. Further, in the drawing, reference numeral 9 denotes a remaining portion of the dummy gate insulating film.

In this case, a first heat treatment is performed between the step of forming the source / drain regions 6 and the step of forming the interlayer insulating film 8, and the first heat treatment is performed after the step of forming the sidewalls 3.
It is desirable to carry out a second heat treatment for activating impurities at a higher temperature than the heat treatment of the above, thereby reducing the damage introduced to the surface of the semiconductor substrate 1 in the step of forming the second sidewall 3. be able to.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of an IGFET according to a first embodiment of the present invention will now be described with reference to FIGS. Each figure is a cross-sectional view along the traveling direction of the carrier. Referring to FIG. 2A, first, an element isolation oxide film 12 is formed on an n-type silicon substrate 11, and then B is implanted into a predetermined region to form a p-type well region 13.
Is formed, and then the B ions 1 are formed through the sacrificial oxide film 14.
5 is ion-implanted to form a channel doped region on the surface of the p-type well region 13.

Next, after the sacrificial oxide film 14 is removed, a dummy gate oxide film 16 having a thickness of, for example, 3 nm is formed on the entire surface by thermal oxidation, and then a polycrystalline silicon film is formed on the entire surface. By depositing and patterning the gate length, for example,
Forming a 0.1 μm dummy gate electrode 17;
As ions 18 are implanted at a low acceleration energy, and the impurity concentration is 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ , for example, an n ⁺ -type shallow source / drain region of 1 × 10 ¹⁹ cm ⁻³ 19 is formed.

Next, as shown in FIG. 2C, a SiO ₂ film is deposited on the entire surface by using the CVD method, and then a side wall 20 is formed by performing reactive ion etching.
1 at a high acceleration energy and the impurity concentration is 1 ×
10 ¹⁸ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ , for example, 1 × 10 ¹⁹
An n ⁺ type source / drain region 22 of cm ⁻³ is formed.

Next, in an N ₂ gas atmosphere, for example, 9
RTA (Rapid Ther) for 1 second at 00 ° C
By performing a first heat treatment by using a thermal annealing method, the concentration profile of the implanted As is adjusted,
Undesired solid phase diffusion in the subsequent thermal process is prevented.

Next, after a TEOS-NSG film is deposited on the entire surface,
The TEOS-NSG film is polished by using the CMP method until the dummy gate electrode 17 is exposed, thereby forming the interlayer insulating film 23 having a planarized surface.

Next, as shown in FIG. 3E, CDE using HBr + O ₂ as a reactive gas
The dummy gate electrode 17 is selectively removed by etching (Chemical Dry Etching). Subsequently, by performing a cleaning step, the dummy gate oxide film 16 immediately below the dummy gate electrode 17 disappears, and the surface of the p-type well region 13 is exposed.

Next, a high-temperature oxide film 24 having a thickness of, for example, 10 nm is formed in order to form a second sidewall on the entire surface by using the CVD method, as shown in FIG.

Next, as shown in FIG. 4G, a sidewall 25 made of a high-temperature oxide (HTO) film is formed by performing reactive ion etching using CHF ₃ + CF ₄ having a selectivity to Si as a reactive gas. At the same time, the surface of the p-type well region 13 is exposed again.

Next, the implanted As is activated again by performing a second heat treatment by RTA for 10 seconds at 1000 ° C. in an N ₂ gas atmosphere, and the sidewall 25 is formed. The damage introduced to the surface of the p-type well region 13 during the process is recovered.

Next, in order to form a gate insulating film by using a sputtering method, a Ta ₂ O ₅ film 2 having a thickness of, for example, 4 nm is formed.
6 is deposited on the entire surface.

Next, referring to FIG. 4 (i), the thickness is
For example, a TiN film 28 having a thickness of 20 nm and a W film 29 having a thickness of, for example, 150 nm are deposited to bury the gate opening, and then patterned by a normal photolithography process, whereby the TiN film 28 and the W film are formed. By forming a gate electrode 30 composed of a gate electrode 29 and a gate oxide film 27 composed of a Ta ₂ O ₅ film, the IGF
The basic configuration of ET is completed.

As described above, in the first embodiment of the present invention, since the gate oxide film 27 and the gate electrode 30 are provided in the gate opening via the second sidewall 25, the gate opening is formed. Can compensate for the reduced amount of the first sidewall 20, whereby
Since the overlap between the n ⁺ -type shallow source / drain region 19 and the gate electrode 30 can be reduced,
This will be described with reference to FIG.

FIG. 5 is an enlarged view of a portion surrounded by a broken line in FIG. 4 (i). As schematically shown in FIG. 5, the n ⁺ -type shallow source / drain region 19 and the gate electrode 30 are separated from each other. The overlap is almost eliminated, so that the parasitic capacitance between the n ⁺ -type shallow source / drain region 19 and the gate electrode 30 is formed as a capacitor using the gate oxide film 27 and the sidewall 25 as a dielectric film.

In this case, since the conventional capacitor using only the gate insulating film as the dielectric film is not effectively formed, the parasitic capacitance can be reduced.
Since 5 has a lower dielectric constant than SiO ₂ formed by thermal oxidation, the parasitic capacitance is further reduced from this point as well. In this case, the gate length can be controlled by adjusting the width of the sidewall 25.

In the second embodiment of the present invention, since the heat treatment step is performed twice before depositing the gate insulating film, the penetration of the metal element constituting the gate electrode and the transition region are suppressed. Without causing the impurity profile, the impurity profile in the source / drain region can be suitably maintained, and the damage introduced in the sidewall forming step can be recovered.

That is, similarly to the conventional case, when the high-temperature annealing at about 1000 ° C. for activating the impurities is performed only immediately after the step of forming the n ⁺ -type source / drain regions 22 in FIG. The damage introduced with the wall forming process cannot be recovered, while FIG. 4 (g)
In the case where heat treatment was performed only immediately after the step of FIG.
Impurities implanted by the heat associated with the film forming step in the steps of (c) to FIG. 3 (f) undergo solid phase diffusion, and the controllability of the impurity profile is reduced.

Next, the IGF according to the second embodiment of the present invention
The manufacturing process of the ET will be described. Since only the heat treatment process is performed once and the other processes are the same as those in the first embodiment, the description will be made with reference to FIGS. To Referring to FIG. 2C, first, as in the first embodiment, FIG.
Through the steps of (a) to FIG. 2 (b), n ⁺
After the mold source / drain regions 22 are formed, the implanted impurities are activated by performing a high-temperature heat treatment for 10 seconds by RTA at 1000 ° C. in an N ₂ gas atmosphere, for example.

Thereafter, FIG. 3D to FIG.
Through these steps, a basic configuration of the IGFET can be obtained. However, in the second embodiment, FIG.
The second heat treatment immediately after the formation of the side wall 25 in (g) is not performed.

In the second embodiment, since the number of heat treatment steps is one, the number of manufacturing steps can be reduced, and thereby the throughput can be improved.

Next, an IGFET according to a third embodiment of the present invention will be described with reference to FIG. 6. In the third embodiment, the gate electrode 30 is formed using a literal damascene method. It is embedded in the gate opening, and the other steps are exactly the same as in the first embodiment. FIG. 6 is a schematic cross-sectional view of an IGFET according to the third embodiment of the present invention. The Ta ₂ O ₅ film 26 shown in FIG.
, A TiN film 28 and a W film 29 are deposited to fill the gate opening, and then the CM is formed again.
The gate electrode 3 is formed by a planarization process using the P method.
0 is completely buried in the gate opening.

In the third embodiment, since the gate electrode 30 is completely buried in the gate opening,
It is possible to eliminate the parasitic capacitance associated with the overhanging portion of the conventional gate electrode 30, thereby enabling higher-speed operation.

The embodiments of the present invention have been described above.
However, according to the present invention, the configurations and conditions described in each embodiment
The present invention is not limited to this, and various changes are possible. An example
For example, in each of the above embodiments, the gate oxide film 2
7 is high dielectric Ta _TwoO_FiveBut ZrO etc.
Other high-dielectric films may be used.
It is not possible to use SiO_TwoFilm or SiN film
May be a dielectric having a relative dielectric constant of 3.9 or more.
Among them, a film having a higher dielectric constant is desirable.

Further, in each of the above embodiments, the second sidewall 25 is formed by the HTO film, but a low temperature oxide (LTO) film may be used. It is sufficient that the dielectric constant is lower than that of the SiO ₂ film formed by thermal oxidation. For example, a dielectric having a relative dielectric constant of 3.9 or less may be used, whereby the parasitic capacitance can be further reduced.

In each of the above embodiments, the TiN / W structure film is used as the gate electrode 30. However, the present invention is not limited to the TiN / W structure film, and polycrystalline Si may be used. Alternatively, Al may be used since no high-temperature heat treatment step is performed after the electrode film deposition step,
Furthermore, when the gate electrode is buried as in the third embodiment, the selective etching step is not required, and therefore Cu, which is difficult to perform the selective etching step, may be used. However, when a CMOS is formed using the same electrode material, W in which the Fermi level is located substantially at the center of the silicon band gap as in the embodiment is preferable.

In each of the above embodiments, the dummy gate electrode is formed of polycrystalline silicon. However, the dummy gate electrode does not need to be formed of a conductor. Any material can be used as long as it can selectively etch SiO ₂ constituting the wall 20 and the like and has a good masking action for impurities.
It may be formed of an insulator such as a SiN film.

Further, in each of the above-described embodiments, in the cleaning step after the step of removing dummy gate electrode 17,
Although it is described that the exposed portion of the dummy gate oxide film 16 disappears, it does not necessarily have to completely disappear.
What is necessary is just to remove so that the mold well region 13 may be exposed.

Further, in each of the above embodiments, 2
N ⁺ type shallow source
Drain region 19 and n ⁺ type source / drain region 22
The source / drain regions may be formed by a single implantation process. For example, the first ion implantation may be performed with high acceleration energy.

In each of the above embodiments, n
Although described as a channel IGFET, it goes without saying that the present invention is also applied to a p-channel IGFET.

Here, the detailed features of the present invention will be described with reference to FIG. 1 again. See FIG. 1 (Supplementary Note 1) A double side wall including an outer first side wall 2 and an inner second side wall 3, and opposed side walls of the second side wall 3 bulging inward. And the gate insulating film 4 also extends at least on the opposing side wall of the second side wall 3, and a gate electrode is provided in the gap between the opposing second side wall 3 via the gate insulating film 4. 5. An insulated gate semiconductor device comprising: (Supplementary Note 2) The insulated gate semiconductor device according to Supplementary Note 1, wherein a relative dielectric constant of an insulator forming the second sidewall 3 is 3.9 or less. (Supplementary Note 3) The insulated gate semiconductor device according to supplementary note 2, wherein the second sidewall 3 is formed of either a high-temperature oxide film or a low-temperature oxide film. (Supplementary Note 4) The insulated gate semiconductor device according to any one of Supplementary notes 1 to 3, wherein a relative dielectric constant of an insulator forming the gate insulating film 4 is 3.9 or more. (Supplementary Note 5) The insulated gate semiconductor device according to any one of Supplementary notes 1 to 4, wherein the gate electrode 5 is made of a metal. (Supplementary Note 6) A step of forming a dummy gate structure on the semiconductor substrate 1 via a dummy gate insulating film, a step of forming source / drain regions 6 by ion implantation using the dummy gate structure as a mask, Flattening the interlayer insulating film 8 so as to have the same height as the dummy gate structure after depositing the insulating film 8;
Forming a gate opening by removing the dummy gate structure, forming a sidewall 3 in the gate opening, and forming a gate electrode 5 in the gate opening with a gate insulating film 4 interposed therebetween. A method for manufacturing an insulated gate semiconductor device, comprising: (Supplementary Note 7) A first heat treatment is performed between the step of forming the source / drain regions 6 and the step of forming the interlayer insulating film 8, and after the step of forming the sidewalls 3, the first heat treatment is performed at a higher temperature than the first heat treatment. 7. The method of manufacturing an insulated gate semiconductor device according to claim 6, wherein a second heat treatment for activating the impurities is performed. (Supplementary note 8) The insulated gate type according to supplementary note 6, wherein a high-temperature heat treatment for activating impurities is performed only between the step of forming the source / drain regions 6 and the step of forming the interlayer insulating film 8. A method for manufacturing a semiconductor device. (Supplementary Note 9) After the source / drain region 6 is formed by ion implantation using the dummy gate structure as a mask, a sidewall 2 is formed on a side wall of the dummy gate structure, and a sidewall of the dummy gate structure is formed. 9. The insulation according to any one of claims 6 to 8, wherein the second source / drain region 7 deeper than the source / drain region 6 is formed by ion-implanting using the side wall 2 formed as a mask. A method for manufacturing a gate type semiconductor device.

[0053]

According to the present invention, since the sidewall is provided in the gate opening after the removal of the dummy gate electrode, the overlap between the gate electrode and the shallow source / drain region can be greatly reduced. With
The gate length can be controlled by adjusting the width of the sidewall, thereby reducing the parasitic capacitance and shortening the channel length, so that the IGFET can operate at a high speed, and as a result, the semiconductor integrated circuit can be controlled. This greatly contributes to speeding up of the circuit device and improvement of the processing capability.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention after FIG. 3;

FIG. 5 is an explanatory diagram of the operation and effect of the IGFET according to the first embodiment of the present invention.

FIG. 6 is a schematic sectional view of an IGFET according to a third embodiment of the present invention.

FIG. 7 is an explanatory diagram of a conventional IGFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Side wall 3 Side wall 4 Gate insulating film 5 Gate electrode 6 Source / drain region 7 Source / drain region 8 Interlayer insulating film 9 Remaining part of dummy insulating film 11 N-type silicon substrate 12 Element isolation oxide film 13 P-type well Region 14 Sacrificial oxide film 15 B ion 16 Dummy gate oxide film 17 Dummy gate electrode 18 As ion 19 n ⁺ type shallow source / drain region 20 Side wall 21 As ion 22 n ⁺ type source / drain region 23 Interlayer insulating film 24 High temperature oxidation Film 25 sidewall 26 Ta ₂ O ₅ film 27 gate oxide film 28 TiN film 29 W film 30 gate electrode 31 n-type silicon substrate 32 element isolation oxide film 33 p-type well region 34 dummy gate oxide film 35 n ⁺ type shallow source / Drain region 36 side Oru 37 n ⁺ -type source and drain regions 38 interlayer insulating film 39 a gate oxide film 40 TiN film 41 W film 42 gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 F term (Reference) 4M104 AA01 BB01 BB02 BB04 BB30 CC05 DD03 DD04 DD37 DD65 EE03 EE09 EE16 FF18 GG09 GG10 GG14 HH20 5F040 DA01 DA12 DB03 DC01 EC01 EC04 EC07 EC08 EC10 EC12 ED03 EK01 EL02 FA01 FA02 FA05 FB02 FC10 FC21 5F048 AC03 BA01 BB09 BG01 BG13 DA25

Claims (5)

[Claims] 1. A double gate comprising an outer first side wall and an inner second side wall, wherein opposing side walls of the second side wall have a shape bulging inward, and a gate. An insulating film extending at least on opposing side walls of the second sidewall, and a gate electrode provided in a gap between the opposing second sidewalls via the gate insulating film. Gate type semiconductor device. 2. The insulated gate semiconductor device according to claim 1, wherein a relative dielectric constant of an insulator forming said second sidewall is 3.9 or less. 3. The insulator constituting the gate insulating film has a relative permittivity of 3.9 or more.
Or the insulated gate semiconductor device according to 2. 4. A step of forming a dummy gate structure on a semiconductor substrate via a dummy gate insulating film, a step of forming source / drain regions by ion implantation using the dummy gate structure as a mask, Depositing a film, flattening the interlayer insulating film so as to have the same height as the dummy gate structure, removing the dummy gate structure to form a gate opening, Forming a sidewall in a portion, and forming a gate electrode in the gate opening via a gate insulating film. 5. A first heat treatment is performed between the step of forming the source / drain region and the step of forming the interlayer insulating film, and after the step of forming the sidewall, impurities having a higher temperature than the first heat treatment are removed. 5. The method for manufacturing an insulated gate semiconductor device according to claim 4, wherein a second heat treatment for activation is performed.