JP2002152173A - Ofdm system receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an AGC control over a receive signal of an OFDM system without having any adverse effect of demodulation characteristics. SOLUTION: A synchronous processing part 20 detects the position, etc., of a guard interval from an in-phase component signal I and a quadrature component signal which are separately generated by an IQ separation part 15 and according to the detection result, a signal level detection part 21 detects the output level (output level in the period of the guard interval) of the IQ separation part 15. Further, an arithmetic part 22 performs in the period of the guard interval gain control over an AGC circuit 16 whose level variation should be suppressed according to the detection result of the signal level detection part 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM receiver, and more particularly, to an OFDM receiver having an automatic gain control means for automatically adjusting a received signal to an appropriate level.

[0002]

2. Description of the Related Art With the development of digital communication technology, attempts have been made to provide high-quality and high-speed data such as audio data, traffic information, weather forecasts and the like with high added value.

[0003] OFDM (Orthogonal Frequency Division Multipl) is a communication method that enables high-quality communication.
ex: orthogonal frequency division multiplexing) method is known.
Digital audio broadcasting using this OFDM method (Digita
l Audio Broadcasting (DAB) systems are being researched and developed.

In the DAB system, convolutional coding is performed for random errors and π / 4DQPSK is performed for burst errors in order to take into account a transmission path environment in which, for example, fading occurs due to multipath interference.
(Differentially Encoded Quadrature Phase Shift Ke
ying) is used for the modulation method, and by taking measures such as performing interleaving on the time axis and frequency, transmission quality is improved.

[0005] When a transmitting side such as a broadcasting station performs OFDM modulation of digital data including digital audio data and transmits it as a transmission radio wave, a conventional receiving apparatus located on the receiving side of a customer or the like transmits a signal to a block shown in FIG. As shown in the figure, the incoming arriving radio wave is received by the antenna ANT, the RF signal from the antenna ANT is converted to an intermediate frequency signal by the RF unit 1, and further converted to a digital signal by the A / D converter 2. After the conversion, the IQ separating section 3 generates the in-phase component signal I and the quadrature component signal Q, and the AGC circuit 4 adjusts the levels of the in-phase component signal I and the quadrature component signal Q, thereby obtaining a Fourier transform (FFT) section. 5 Then, the demodulation information vector data output from the Fourier transform unit 5 is differentially decoded by the differential decoding unit 6 based on the phase information on a predetermined number of carriers, and the decoded data is converted into a serial digital signal by the channel decoding unit 7. Convert to data and output. Then, the data is converted into digital audio data by a source decoder (not shown).

Further, in order to perform synchronous demodulation, a synchronous processing unit 8 is provided.
Detects the synchronization timing from the in-phase component signal I and the quadrature component signal Q, and supplies the detection result to the signal level detector 9. The signal level detection unit 9 sequentially detects a change in the output level of the AGC circuit 4 at a predetermined timing synchronized with the synchronization timing based on the detection result from the synchronization processing unit 8, and outputs the level detection result to the arithmetic unit 10. Supply. The arithmetic unit 10 automatically adjusts the AGC gain of the AGC circuit 4 based on the level detection result in accordance with the command of the control unit 11, and thereby the in-phase component signal I and the quadrature component supplied from the AGC circuit 4 to the Fourier transform unit 5. The fluctuation of the level of the signal Q is suppressed so that an appropriate demodulation characteristic can be obtained.

As shown in FIG. 5A, a transmission signal in the DAB system (hereinafter, referred to as a "DAB signal") includes a plurality of N symbols # 1 to #N as one frame. It is configured in a format in which a guard interval GI is provided at the head of symbols # 1 to #N. Further, a NULL symbol (null symbol) for synchronization detection is provided between each frame. This NULL
The symbol is an unmodulated symbol, and is set to a lower level than the guard interval GI in each frame and the signal levels of the symbols # 1 to #N. Therefore, the synchronization processing unit 8 sets the level of the NULL symbol to By checking, the synchronization timing can be detected.

The signal level detecting section 9 and the arithmetic section 1
AGC of AGC circuit 4 by feedback control with 0
The adjustment timing for adjusting the gain is performed at intervals as short as possible further in synchronization with the synchronization timing detected from the NULL symbol.

That is, as shown in a partially enlarged view in FIG. 5 (b), at a time point ts for each cycle as short as possible, A
The gain control of the GC circuit 2 is performed.

[0010] By shortening the cycle of the gain control of the AGC circuit 2 in this way, a movable receiving apparatus such as a portable radio receiving apparatus can receive a received power along with a change in a transmission path environment while moving. Even if a change is introduced, the company will respond to the change as quickly as possible.

[0011] Then, the Fourier transform unit 5 sets an effective symbol section (FFT window) which is predetermined as a period for selecting a symbol to be demodulated.
The in-phase component signal I and the quadrature component signal Q output from the AGC circuit 4 are Fourier-transformed to generate the demodulated information vector data.

[0012]

However, in the conventional receiver, the cycle of the gain control of the AGC circuit 4 is shortened as much as possible as described above, but the intensity of the arriving radio wave fluctuates rapidly due to fading or the like. In order to obtain an appropriate received power by following it even if
It is necessary to further increase the resolution (time resolution) of the synchronization processing unit 8, the signal level detection unit 9, and the calculation unit 10 for detecting the synchronization timing from the UL symbol, which causes a problem that the circuit scale is increased. there were.

As shown in FIGS. 5A and 5B,
Regardless of the position of each symbol or the length of each (symbol length), the cycle of gain control of the AGC circuit 4 is to be made as short as possible (that is, the resolution is increased). The gain control is performed, and the Fourier transform unit 5 Fourier-transforms the gain-controlled in-phase component signal I and quadrature component signal Q within the range of the FFT window. When differential decoding of demodulation information vector data is performed based on a plurality of carriers, there is a problem that the orthogonality relationship of each carrier is easily broken, and proper decoding cannot be performed.

[0014] It is an object of the present invention to provide a receiving apparatus which can overcome the above-mentioned conventional problems and further improve the demodulation characteristics.

[0015]

In order to achieve the above object, the present invention provides an OFDM that receives and demodulates an OFDM signal.
A DM receiving apparatus, comprising: a detecting means for detecting a guard interval included in the OFDM signal; and an automatic gain control for adjusting a level of the OFDM signal within a guard interval detected by the detecting means. Means, and demodulation means for demodulating the level-adjusted signal output from the automatic gain control means.

In the above-mentioned OFDM receiving apparatus, the automatic gain control means adjusts the level of the OFDM signal within each guard interval detected by the detecting means.

In the above-mentioned OFDM receiver, the automatic gain control means counts the number of guard intervals detected by the detection means and adjusts the level of the OFDM signal as if once every predetermined number. It is characterized by doing.

According to the OFDM receiver having such a configuration, the level of the received OFDM signal is adjusted to a level suitable for demodulation within the guard interval added to the symbol to be demodulated (valid symbol). adjust.

That is, since the above-described level adjustment is not performed within the period of the symbol to be demodulated (valid symbol), the demodulation characteristics are not adversely affected when the valid symbol is demodulated, and the demodulation characteristics are improved.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A receiving apparatus for receiving an OFDM-modulated DAB signal will be described below as an embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of the receiving apparatus of the present embodiment, and FIG. 2 is a diagram for explaining the operation of the receiving apparatus.

In FIG. 1, a receiving apparatus 12 includes a receiving antenna A for receiving a radio wave arriving from a transmitting side such as a broadcasting station.
NT, an RF unit 13 for converting an RF signal SRF from the receiving antenna ANT to an intermediate frequency signal SIF, an A / D converter 14 for converting the intermediate frequency signal SIF to a digital signal,
It comprises an IQ separation unit 15 for generating an in-phase component signal I and a quadrature component signal Q from a digital signal, an AGC circuit 16, a Fourier transform unit 17, a differential decoding unit 18, and a channel decoding unit 19.

The AGC circuit 16 is formed of a variable gain type digital filter, and adjusts the in-phase component signal I and the quadrature component signal Q separated and generated by the IQ separation section 15 to appropriate levels by gain control described later. And output.

The Fourier transform unit 17 generates and outputs demodulation information vector data D by performing a Fourier transform on the in-phase component signal I and the quadrature component signal Q output from the AGC circuit 16 and subjected to gain adjustment. That is, within the FFT window of a predetermined time length, A
By performing a Fourier transform on the stable in-phase component signal I and the quadrature component signal Q having stable levels output from the GC circuit 16,
Generate demodulation information vector data D.

The differential decoding unit 18 performs differential decoding on the demodulated information vector data D based on phase information on a predetermined number of carriers, and outputs the decoded data Dm to the channel decoding unit 19.

The channel decoding section 19 converts the data Dm from the differential decoding section 18 into serial data Ds and outputs it. For example, when digital audio data such as MPEG audio is transmitted as a DAB signal, the serial data Ds is output as MPEG audio data. Then, the data is converted into digital audio data by a source decoder (not shown).

The receiving apparatus 12 further includes a synchronization processing unit 2
0, signal level detection unit 21, arithmetic circuit 22, control unit 23
Is provided.

Here, the synchronization processing unit 20 calculates the length of a NULL symbol from the in-phase component signal I and the quadrature component signal Q, the start position of each frame, the length of each symbol included in each frame, and the number of symbols. Are supplied to the signal level detection unit 21 and the control unit 23.

The signal level detection section 21 detects the output level of the IQ separation section 15 in synchronization with a predetermined timing commanded by the control section 23, and supplies the detection result to the calculation section 22 and the control section 23.

The arithmetic unit 22 checks the variation of the output level of the IQ separation unit 15 based on the detection result from the signal level detection unit 21, and further obtains the parameter for gain control supplied from the control unit 22 and the variation. Are generated to generate a filter coefficient for suppressing the fluctuation of the output level. Then, AG is determined by the generated filter coefficient.
The AGC gain of the C circuit 16 is adjusted. Further, the control unit 23
Is supplied to the arithmetic unit 22 with a control signal for instructing the timing to adjust the AGC gain of the AGC circuit 16, and the arithmetic unit 22 outputs the AG signal at a predetermined timing according to the control signal.
The AGC gain of the C circuit 16 is adjusted, and the level-adjusted in-phase component signal I and quadrature component signal Q are converted by the Fourier transform unit 17.
Output to

The control unit 23 detects the length of the NULL symbol supplied from the synchronization processing unit 20, the head position of each frame, the length of each symbol included in each frame, the number of symbols, and the like. , The timing at which the signal level detection unit 21 should detect the output level and the timing at which the calculation unit 22 should perform gain control of the AGC circuit 16, and instructs the signal level detection unit 21 and the calculation unit 22.

The resolution of the operation unit 22 follows the resolution of the signal level detection unit 21.
Reference numeral 3 indicates that the response speed of the AGC circuit 16 can be changed by changing the detection timing of the signal level detection unit 21.

Next, the present receiving apparatus 12 having such a configuration is described.
Will be described with reference to FIG. In addition, FIG.
FIG. 5A is a diagram showing the format of the DAB signal shown corresponding to FIG. 5A, and FIG. 2B is a diagram for explaining the features of the receiving device 12.

As described above, the synchronization processing unit 20 has the IQ
From the in-phase component signal I and the quadrature component signal Q output from the separation unit 15, the length of the NULL symbol, the head position of each frame, the length of each symbol included in each frame, the number of symbols, and the like are detected. The detection results are supplied to the signal level detection unit 21 and the control unit 23.

Thus, the control unit 23 determines the timing at which the signal level detection unit 21 should perform level detection,
The circuit 16 determines when to perform gain control.

In this embodiment, a plurality of algorithms for determining these timings are prepared.
The plurality of algorithms are preset in the control unit 23 as a so-called system program, and a microprocessor (MPU) in the control unit 23 executes an algorithm specified by a user, a system administrator, or the like.
When the receiving device 12 is shipped from a product, a process such as a predetermined algorithm is determined in advance.

First, one of those algorithms will be described. As shown in FIG.
The start position of each guard interval GI is detected by arithmetically operating information such as the length of a NULL symbol, the start position of each frame, the length of each symbol included in each frame, and the number of symbols. At each detected time point tagc, a command is issued to the signal level detection unit 21 to detect the output level of the IQ separation unit 15.

Further, the control unit 23 performs the above-described time taggc.
After a predetermined delay time Δτ from, the timing at which the gain control of the AGC circuit 16 is to be performed is instructed to the arithmetic unit 22. As a result, the arithmetic unit 22 sets each time point tagc + Δ to suppress the level fluctuation detected by the signal level detecting unit 21.
The AGC circuit 16 adjusts the AGC gain for each τ.

Here, although the delay time Δτ is not shown in FIG. 2A, the signal level detecting section 21
5 is set to the time required for detecting the output level of No. 5 and supplying the detection result to the calculation unit 22. Since this delay time Δτ is an extremely short time, the delay time Δτ is substantially the same as each time point Tagc. It is possible to regard it.

The point at which the AGC circuit 16 actually performs the gain control is a point further after each point in time tagc + Δτ, but the arithmetic unit 22 uses the DPS (Digital Signal Processor).
r) and a high-speed electronic element such as an FPGA (Field Programmable Array), the time point at which the gain control is performed can be regarded as substantially the same time point as each of the above-mentioned time points Tagc.

As a result, as shown in FIG.
The gain control by the C circuit 16 is performed by the guide interval G
This is performed within the period I. Then, the Fourier transform unit 17
Generates the demodulation information data D corresponding to each symbol by Fourier-transforming the in-phase component signal I and the quadrature component signal Q whose gains are controlled to appropriate levels within a predetermined FFT window period. .

As described above, when the gain control of the AGC circuit 16 is performed within the period of the gart interval GI provided at the head of each symbol in one frame, compared with the prior art in which the gain control is performed within one symbol. And the differential decoding unit 18
When differential decoding is performed based on a predetermined number (multiple) of carriers, the orthogonality relationship of each carrier can be appropriately maintained,
The demodulation characteristics can be improved.

Further, even if the above-described gain control is performed between consecutive symbols, even if a power difference occurs for each symbol, accurate phase information can be obtained at the time of decoding by the differential decoding unit 18. Therefore, the problem that the demodulation characteristics are deteriorated does not occur.

Furthermore, since the above-described gain control is performed for each period of the gart interval GI, high resolution unlike the prior art is not required. Therefore, there is no need to increase the circuit scale, and conversely, the circuit scale can be simplified.

Further, the period of the gart interval GI is
Since the position and length of the NULL symbol can be easily detected, the timing for gain control can be easily and accurately determined. Furthermore, the timing for gain control can be determined with high accuracy by an extremely simple algorithm (program).

As a further significant feature, when an incoming radio wave delayed in a multipath environment is received, each symbol is delayed as shown in the second and third stages in FIG. 2B. The time t to be gain-controlled based on the position and length of the NULL symbol obtained by receiving a direct wave (a radio wave arriving directly from a base station or the like).
By simply determining agc, the Fourier transform unit 17 can appropriately perform Fourier transform on symbols received with delay.

That is, when the symbol shown in the first row in FIG. 2B is obtained from a direct wave, it is determined that the gain control is performed at the time point tagc in the guard interval GI. Since the range of the FFT window for the delayed received symbols (the symbols shown in the second and third stages) is set after the time point tagc,
The gain control by the AGC circuit 16 is not performed during the period of the FFT window. As a result, when decoding is performed in the differential decoding unit 18, the orthogonality relationship is not broken, and robustness to a multipath environment (robu
st) A receiving device can be realized.

Next, with reference to FIG. 3, an operation when the gain control of the AGC circuit 4 is performed based on another algorithm will be described.

FIG. 3A shows that the gain control of the AGC circuit 4 is not performed for each symbol, but the AG control is performed for a plurality of symbols.
The case where the gain control of the C circuit 4 is performed is shown.

That is, the guard interval positioned at the head of each of the plurality of symbols included in one frame is counted, and every time the count value reaches a predetermined number, at the time point tagc in the guard interval GI period, The gain control of the AGC circuit 4 is performed.

At these time points tagc, the control unit 23
Based on the length of the UL symbol, the start position of each frame, the length of each symbol included in each frame, and the number of symbols, the positions of all guard intervals GI are detected, and all guard intervals GI are detected. From the positions of the interval GI, the positions of the guard intervals GI having a predetermined arithmetic progression or geometric progression relation obtained by the above-described counting process are selected, and the AGC circuit 4 is selected within the period of the selected guard interval GI. At which the gain control should be performed is determined.

The method of selecting the position of the guard interval GI having a predetermined arithmetic progression or geometric progression relationship is merely a typical example, and may be selected at random.

As described above, when the gain control of the AGC circuit 16 is performed for each of a plurality of symbols, effects such as reduction of the load on the control unit 23 can be obtained.

As shown in FIG. 3B, NULL
The AGC circuit 1 only during the guard interval GI following the symbol, that is, once per frame.
6 may be performed.
The effect of reducing the load on the device can be obtained.

As described above, according to the receiving apparatus 12 of the present embodiment, the gain control of the AGC circuit 16 is performed during the guard interval GI.
Appropriate AGC control can be performed without excessively increasing the resolution, and the circuit scale can be simplified.

Further, after the gain control by the AGC circuit 16 is performed (after the time point tagc), the FFT window set in the Fourier transform unit 17 comes. The problem that the relationship is lost does not occur, and a receiver that is more robust to a multipath environment can be provided.

In the above description of the embodiment, the AGC is performed at the initial point in the guard interval GI.
The case where the gain control of the circuit 16 is performed has been described. As early as possible within the guard interval GI,
It is preferable to control the gain of the AGC circuit 16, but it is not necessarily limited to this. In short, at any point during the guard interval GI, the AGC
By controlling the gain of the circuit 16, it is possible to avoid adverse effects on symbols when controlling the gain of the AGC circuit 16, and it is possible to appropriately adjust the gain according to the actual application.

The timing at which the signal level detecting section 21 should detect the output level of the IQ separating section 15 and the calculating section 22
Has described the case where the control unit 23 determines the timing at which the AGC circuit 16 should perform gain control. However, the signal level detection unit 21 and the calculation unit 22 may determine each timing. That is, when the control unit 23 detects the start time of each frame and instructs the signal level detection unit 21 to perform the AGC control, the signal level detection unit 21 transmits the NULL symbol of the NULL symbol supplied from the synchronization processing unit 20. Based on the length, the head position of each frame, the length of each symbol included in each frame, the number of symbols, and the like, the timing at which the output level of the IQ separation unit 15 should be detected is determined. Detect level. When the signal level detection unit 21 supplies the output level detection result to the calculation unit 22, the calculation unit 22
Calculates the filter coefficient for adjusting the gain of AGC
The control may be performed.

Although the description has been given of the receiving apparatus having the configuration in which the AGC circuit is connected downstream of the IQ separating section, the receiving apparatus can be arranged at another position according to the design specification. For example, the present invention can be applied to a case where an analog AGC circuit is provided after the RF unit 3.

Furthermore, the case where the DAB signal is received has been described. However, even if the receiving apparatus 12 receives an OFDM signal other than the DAB signal and having no NULL symbol at the head of the frame, the receiving apparatus 12 may receive the OFDM signal. By detecting information on synchronization from the signal and detecting the received power by the signal level detection unit 21 based on the detection result,
Since the position and length of each symbol can be detected, AGC control can be performed at a time other than within the period of each symbol. That is, the present receiving device 12
It is versatile not only for B signals but also for OFDM signals.

[0060]

As described above, the OFDM receiver according to the present invention adjusts the level of the received OFDM signal to a level suitable for demodulation within the guard interval included in the OFDM signal. Therefore, when demodulating a symbol to be demodulated (an effective symbol), the demodulation characteristics are not adversely affected, and the demodulation characteristics can be improved.

Further, appropriate AGC control can be performed without excessively increasing the resolution, and the circuit scale can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a receiving device according to an embodiment.

FIG. 2 is a diagram for explaining the operation of the receiving device shown in FIG.

FIG. 3 is a diagram for explaining another operation of the receiving device shown in FIG.

FIG. 4 is a block diagram illustrating a configuration of a conventional receiving device.

FIG. 5 is a diagram for explaining a problem of a conventional receiving apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 ... Receiving apparatus 13 ... RF part 14 ... A / D converter 15 ... IQ separation part 16 ... AGC circuit 17 ... Fourier transformation part 18 ... Differential decoding part 19 ... Channel decoding part 20 ... Synchronization record processing part 21 ... Signal Level detection unit 22 ... Control unit ANT ... Antenna

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuki Kuriki 25-1, Nishimachi, Yamada-ji, Kawagoe-shi, Saitama Pioneer Co., Ltd. (72) Inventor Katsuhiko Toki 25-1, Nishimachi, Yamada-shi, Kawagoe-shi, Saitama Pioneer Inside the Kawagoe Plant Co., Ltd. (72) Inventor Toshito Ichikawa 25-1, Nishimachi, Yamada-shi, Kawagoe-shi, Saitama Prefecture Pioneer Corporation Kawagoe Plant F-term (reference) 5K022 DD01 DD13 DD19 DD33 DD34 5K061 AA11 BB12 CC52 FF11 JJ06

Claims (3)

[Claims] 1. An OFDM receiving apparatus for receiving and demodulating an OFDM signal, comprising: detecting means for detecting a guard interval included in the OFDM signal; and a period of the guard interval detected by the detecting means. And an automatic gain control means for adjusting the level of the OFDM signal within the apparatus, and a demodulation means for demodulating the level-adjusted signal output from the automatic gain control means. Receiver. 2. An OFDM reception system according to claim 1, wherein said automatic gain control means adjusts the level of said OFDM signal within each of a plurality of guard intervals detected by said detection means. apparatus. 3. The automatic gain control means counts the number of guard intervals detected by the detection means, and adjusts the level of the OFDM signal as if once every predetermined number. Item 2. The OFDM receiver according to Item 1.